PRODUCT SPECIFICATIONS (R) Integrated Circuits Group LH28F008SAT-85 Flash Memory 8M (1MB x 8) (Model No.: LHF08S49) Spec No.: EL105017A Issue Date: October 5, 1999 sharp LHF08S49 Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. When using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) The products covered herein are designed and manufactured for the following application areas. When using the products covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph (3). Office electronics Instrumentation and measuring equipment Machine tools Audiovisual equipment Home appliance Communication equipment other than for trunk lines (2) Those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. Control and safety devices for airplanes, trains, automobiles, and other transportation equipment Mainframe computers Traffic control systems Gas leak detectors and automatic cutoff devices Rescue and security equipment Other safety devices and safety equipment,etc. (3) Do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. Aerospace equipment Communications equipment for trunk lines Control equipment for the nuclear power industry Medical equipment related to life support, etc. (4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales representative of the company. Please direct all queries regarding the products covered herein to a sales representative of the company. sharp LHF08S49 1 CONTENTS 1 FEATURES ************************ 2 2 PRODUCT OVERVIEW ************************ 3 3 PRINCIPLES OF OPERATION ************************ 8 4 BUS OPERATION ************************ 9 5 COMMAND DEFINITIONS ************************ 11 6 EXTENDED BLOCK ERASE/BYTE WRITE CYCLING ************************ 13 7 AUTOMATED BYTE WRITE ************************ 13 8 AUTOMATED BLOCK ERASE ************************ 13 9 DESIGN CONSIDERATIONS ************************ 13 10 ABSOLUTE MAXIMUM RATINGS ************************ 18 11 OPERATING CONDITIONS ************************ 18 12 DC CHARACTERISTICS ************************ 18 13 CAPACITANCE ************************ 19 14 AC CHARACTERISTICS ************************ 20 15 BLOCK ERASE AND BYTE WRITE PERFORMANCE ************************ 23 16 ALTERNATIVE CE#-CONTROLLED WRITES ************************ 25 17 PACKAGING AND PACKING SPECIFICATION ************************ 27 sharp LHF08S49 2 LH28F008SAT-85 8M-BIT (1MBit x 8) FLASH MEMORY 1. FEATURES *High-Density Symmetrically Blocked Architecture - Sixteen 64K-Byte Blocks *Extended Cycling Capability - 100,000 Block Erase Cycles - 1.6 Million Block Erase Cycles per Chip * Very High-Performance Read - 85ns Maximum Access Time * Operating Temperature - 0C to +70C * SRAM-Compatible Write Interface *Automated Byte Write and Block Erase - Command User Interface - Status Register * Hardware Data Protection Feature - Erase/Write Lockout during Power Transitions *System Performance Enhancements - RY/BY# Status Output - Erase Suspend Capability * Industry Standard Packaging - 40-Lead TSOP *Deep-Powerdown Mode - 10A ICC Maximum * ETOXTM* Nonvolatile Flash Technology - 12V Byte Write/Block Erase * CMOS Process (P-type silicon substrate) * Not designed or rated as radiation hardened SHARP's LH28F008SAT-85 8M-bit Flash Memory is the highest density nonvolatile read/write solution for solid state storage. The LH28F008SA's extended cycling, symmetrically blocked architecture, fast access time, write automation and low power consumption provide a more reliable, lower power, lighter weight and higher performance alternative to traditional rotating disk technology. The LH28F008SAT-85 brings new capabilities to portable computing. Application and operating system software stored in resident flash memory arrays provide instant-on rapid execute-in-place and protection from obsolescence through in-system software updates. Resident software also extends system battery life and increases reliability by reducing disk drive accesses. For high density data acquisition applications, the LH28F008SAT-85 offers a more cost-effective and reliable alternative to SRAM and battery. Traditional high density embedded applications, such as telecommunications, can take advantage of the LH28F008SA's nonvolatility, blocking and minimal system code requirements for flexible firmware and modular software designs. The LH28F008SAT-85 is offered in 40-lead TSOP (standard) package. Pin assignments simplify board layout when integrating multiple devices in a flash memory array or subsystem. This device uses an integrated Command User Interface and state machine for simplified block erasure and byte write. The LH28F008SAT-85 memory map consists of 16 separately erasable 64K-byte blocks. SHARP's LH28F008SAT-85 employs advanced CMOS circuitry for systems requiring low power consumption and noise immunity. Its 85ns access time provides superior performance when compared with magnetic storage media. A deep powerdown mode lowers power consumption to 50W maximum thru VCC, crucial in portable computing, handheld instrumentation and other low-power applications. The RP# power control input also provides absolute data protection during system powerup/down. * ETOX is a trademark of Intel Corporation. sharp LHF08S49 3 2. PRODUCT OVERVIEW Maximum access time is 85ns (tACC) over the commercial temperature range (0C to +70C) and over VCC supply volt- The LH28F008SAT-85 is a high-performance 8M-bit age range (4.5V to 5.5V and 4.75V to 5.25V). ICC active current (CMOS Read) is 20mA typical, 35mA maximum (8,388,608 bit) memory organized as 1M-byte (1,048,576 bytes) of 8 bits each. Sixteen 64K-Byte (65,536 byte) blocks are included on the LH28F008SAT-85. A memory map is shown in Figure 4 of this specification. A block erase operation erases one of the sixteen blocks of memory in typically 1.6s, independent of the remaining blocks. Each block can be independently erased and written 100,000 cycles. Erase Suspend mode allows system software to suspend block erase to read data or execute code from any other block of the LH28F008SAT-85. The LH28F008SAT-85 is available in the 40-lead TSOP (Thin Small Outline Package, 1.2mm thick) package. Pinouts are shown in Figure 2 of this specification. at 8MHz. When the CE# and RP# pins are at VCC, the ICC CMOS Standby mode is enabled. A Deep Powerdown mode is enabled when the RP# pin is at GND, minimizing power consumption and providing write protection. I CC current in deep powerdown is 10 A maximum. Reset time of 400ns is required from RP# switching high until outputs are valid to read attempts. Equivalently, the device has a wake time of 1s from RP# high until writes to the Command User Interface are recognized by the LH28F008SAT-85. With RP# at GND, the WSM is reset and the Status Register is cleared. The Command User Interface serves as the interface between the microprocessor or microcontroller and the internal operation of the LH28F008SAT-85. Please do not execute reprogramming "0" for the bit which Byte Write and Block Erase Automation allow byte write the data which has been programed "1". *Program "0" for the bit in which you want to change data and block erase operations to be executed using a twowrite command sequence to the Command User Interface. The internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for byte write and block erase operations, including verifications, thereby unburdening the microprocessor or microcontroller. Writing of memory data is performed in byte increments typically within 8s. IPP byte write and block erase currents are 10mA typical, 30mA maximum. V PP byte write and block erase voltage is 11.4V to 12.6V. The Status Register indicates the status of the WSM and when the WSM successfully completes the desired byte write or block erase operation. The RY/BY# output gives an additional indicator of WSM activity, providing capability for both hardware signal of status (versus software polling) and status masking (interrupt masking for background erase, for example). Status polling using RY/BY# minimizes both CPU overhead and system power consumption. When low, RY/BY# indicates that the WSM is performing a block erase or byte write operation. RY/BY# high indicates that the WSM is ready for new commands, block erase is suspended or the device is in deep powerdown mode. has already been programed "0". Overwrite operation may generate unerasable bit. In case of reprogramming "0" to from "1" to "0". *Program "1" for the bit which has already been programmed "0". For example, changing data from "10111101" to "10111100" requires "11111110" programming. A0-A19 Figure 1. Block Diagram X-DECODER ADDRESS LATCH ADDRESS COUNTER Y-DECODER INPUT BUFFER OUTPUT MULTIPLEXER OUTPUT BUFFER 16 64K-BYTE BLOCKS Y-GATING DATA COMPARATOR STATUS REGISTER IDENTIFIER REGISTER INPUT BUFFER DATA REGISTER DQ0-DQ7 WRITE STATE MACHINE COMMAND USER INTERFACE PROGRAM/ERASE VOLTAGE SWITCH I/O LOGIC GND VCC VPP RY/BY# RP# OE# WE# CE# sharp LHF08S49 4 sharp LHF08S49 Table 1. Pin Description Symbol A0-A19 Type INPUT Name and Function ADDRESS INPUTS: for memory addresses. Addresses are internally latched during a write cycle. INPUT/OUTPUT DATA INPUT/OUTPUTS: Inputs data and commands during Command User Interface write cycles; outputs data during memory array, Status Register and Identifier read cycles. The data pins are active high and float to tri-state off when the chip is deselected or the outputs are disabled. Data is internally latched during a write cycle. INPUT CHIP ENABLE: Activates the device's control logic input buffers decoders, and sense amplifiers. CE# is active low; CE# high deselects the memory device and reduces power consumption to standby levels. RP# INPUT RESET/POWERDOWN: Puts the device in deep powerdown mode and resets internal automation. RP# is active low; RP# high gates normal operation. RP# also locks out block erase or byte write operations when active low, providing data protection during power transitions. OE# INPUT OUTPUT ENABLE: Gates the device's outputs through the data buffers during a read cycle. OE# is active low. WE# INPUT WRITE ENABLE: Controls writes to the Command User Interface and array blocks. WE# is active low. Addresses and data are latched on the rising edge of the WE# pulse. DQ0-DQ7 CE# OUTPUT READY/BUSY#: Indicates the status of the internal Write State Machine. When low, it indicates that the WSM is performing a block erase or byte write operation. RY/BY# high indicates that the WSM is ready for new commands, block erase is suspended or the device is in deep powerdown mode. RY/BY# is always active and does NOT float to tri-state off when the chip is deselected or data outputs are disabled. VPP SUPPLY BLOCK ERASE/BYTE WRITE POWER SUPPLY: for erasing blocks of the array or writing bytes of each block. NOTE: With VPP<VPPLMAX, memory contents cannot be altered. VCC SUPPLY DEVICE POWER SUPPLY (5V0.5V, 5V0.25V) GND SUPPLY GROUND RY/BY# NC NO CONNECT: Lead is not internal connected; recommend to be floated. 5 sharp LHF08S49 A19 A18 A17 A16 A15 A14 A13 A12 CE# VCC VPP RP# A11 A10 A9 A8 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 LEAD TSOP STANDARD PINOUT 10mm x 20mm TOP VIEW Figure 2. TSOP Lead Configuration 6 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 NC NC WE# OE# RY/BY# DQ7 DQ6 DQ5 DQ4 VCC GND GND DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3 sharp LHF08S49 7 12V SA1-16, LA17-20 SBHE# SBHE# 80386SL CSL1# CSH1# PSTART# PCMD# CS# TO OTHER PLD WR# PW/R# RD# FLSHDCS# CS1# PRDY# CS2# CS3# VGACS# SD0-15 WE# 82360SL Controller VPP WE# VPP OE# OE# RY/BY# RP# DQ0-7 RY/BY# RP# DQ0-7 CTRL XCVR INT RESET# CE# LH28F008SA's PM/IO# GPIO CE# LH28F008SA LATCH A0-19 A0-19 LH28F008SA SA0, LA21-22 SA0-16, LA17-20 VPP Switch FD0-7 FD8-15 RY/BY# RESET# RD# POWERGOOD WR# RY/BY1# RY/BY2# EPLD(s) RY/BY# FROM OTHER LH28F008SA's RP# RP# TO OTHER LH28F008SA's PAIRS Figure 3. LH28F008SA Array Interface to 386SL Microprocessor Superset through PI Bus (Including RY/BY# Masking and Selective Powerdown), for DRAM Backup during System SUSPEND, Resident O/S and Applications and Motherboard Solid-State Disk. sharp LHF08S49 3. PRINCIPLES OF OPERATION The LH28F008SAT-85 includes on-chip write automation to manage write and erase functions. The Write State Machine allows for: 100% TTL-level control inputs; fixed power supplies during block erasure and byte write; and minimal processor overhead with SRAM-like interface timings. After initial device powerup, or after return from deep powerdown mode (see Bus Operations), the LH28F008SAT-85 functions as a read-only memory. Manipulation of external memory-control pins allow array read, standby and output disable operations. Both Status Register and intelligent identifiers can also be accessed through the Command User Interface when VPP=VPPL. This same subset of operations is also available when high voltage is applied to the VPP pin. In addition, high voltage on VPP enables successful block erasure and byte writing of the device. All functions associated with altering memory contents -- byte write, block erase, status and intelligent identifier -- are accessed via the Command User Interface and verified thru the Status Register. 8 FFFFF F0000 EFFFF E0000 DFFFF D0000 CFFFF C0000 BFFFF B0000 AFFFF A0000 9FFFF 90000 8FFFF 80000 7FFFF 70000 6FFFF 60000 5FFFF 50000 4FFFF 40000 3FFFF 30000 2FFFF 20000 1FFFF 10000 0FFFF 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 00000 Commands are written using standard microprocessor write timings. Command User Interface contents serve as input to the WSM, which controls the block erase and byte write Figure 4. Memory Map circuitry. Write cycles also internally latch addresses and data needed for byte write or block erase operations. With Command User Interface and Write Automation the appropriate command written to the register, standard microprocessor read timings output array data, access the An on-chip state machine controls block erase and byte intelligent identifier codes, or output byte write and block erase status for verification. Interface software to initiate and poll progress of internal byte write and block erase can be stored in any of the LH28F008SAT-85 blocks. This code is copied to, and executed from, system RAM during actual flash memory update. After successful completion of byte write and/or block erase, code/data reads from the LH28F008SAT-85 are again possible via the Read Array command. Erase suspend/resume capability allows system software to suspend block erase to read data and execute code from any other block. write, freeing the system processor for other tasks. After receiving the Erase Setup and Erase Confirm commands, the state machine controls block pre-conditioning and erase, returning progress via the Status Register and RY/BY# output. Byte write is similarly controlled, after destination address and expected data are supplied. The program and erase algorithms of past standard Flash memories are now regulated by the state machine, including pulse repetition where required and internal verification and margining of data. sharp LHF08S49 9 Data Protection The first task is to write the appropriate read mode command to the Command User Interface (array, intelligent Depending on the application, the system designer may choose to make the VPP power supply switchable (available identifier, or Status Register). The LH28F008SAT-85 automatically resets to Read Array mode upon initial device only when memory byte writes/block erases are required) or hardwired to V PPH . When VPP =VPPL , memory contents powerup or after exit from deep powerdown. The LH28F008SAT-85 has four control pins, two of which must cannot be altered. The LH28F008SAT-85 Command User Interface architecture provides protection from unwanted be logically active to obtain data at the outputs. Chip Enable (CE#) is the device selection control, and when active en- byte write or block erase operations even when high voltage is applied to VPP. Additionally, all functions are disabled ables the selected memory device. Output Enable (OE#) is the data input/output (DQ0-DQ 7) direction control, and whenever VCC is below the write lockout voltage VLKO, or when RP# is at VIL. The LH28F008SAT-85 accommodates when active drives data from the selected memory onto the I/O bus. RP# and WE# must also be at VIH. Figure 8 illus- either design practice and encourages optimization of the processor-memory interface. trates read bus cycle waveforms. Output Disable The two-step byte write/block erase Command User InterWith OE# at a logic-high level (VIH), the device outputs are disabled. Output pins (DQ0-DQ7) are placed in a high-im- face write sequence provides additional software write protection. pedance state. 4. BUS OPERATION Standby Flash memory reads, erases and writes in-system via the local CPU. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. CE# at a logic-high level (VIH) places the LH28F008SAT-85 in standby mode. Standby operation disables much of the Read LH28F008SA's circuitry and substantially reduces device power consumption. The outputs (DQ0-DQ7) are placed in a high-impedence state independent of the status of OE#. If the LH28F008SAT-85 is deselected during block erase or The LH28F008SAT-85 has three read modes. The memory can be read from any of its blocks, and information can be byte write, the device will continue functioning and consuming normal active power until the operation completes. read from the intelligent identifier or Status Register. VPP can be at either VPPL or VPPH. Table 2. Bus Operations(1,2) Notes RP# CE# OE# WE# A0 VPP DQ0-7 RY/BY#(3) 6 VIH VIL VIL VIH X X DOUT X Output Disable VIH VIL VIH VIH X X High Z X Standby VIH VIH X X X X High Z X Deep PowerDown VIL X X X X X High Z VOH Mode Read Intelligent Identifier (Mfr) 6 VIH VIL VIL VIH VIL X 89H VOH Intelligent Identifier (Device) 6 VIH VIL VIL VIH VIH X A2H VOH 4,5,6 VIH VIL VIH VIL X X DIN X Write NOTES: 1. Refer to DC Characteristics. When VPP=VPPL, memory contents can be read but not written or erased. 2. X can be VIL or VIH for control pins and addresses, and VPPL or VPPH for VPP. See DC Characteristics for VPPL and VPPH voltages. 3. RY/BY# is VOL when the Write State Machine is executing internal block erase or byte write algorithms. It is VOH when the WSM is not busy, in Erase Suspend mode or deep powerdown mode. 4. Command writes involving block erase or byte write are only successfully executed when VPP=VPPH. 5. Refer to Table 3 for valid DIN during a write operation. 6. Don't use the timing both OE# and WE# are VIL. sharp LHF08S49 10 Deep Power-Down Intelligent Identifier Operation The LH28F008SAT-85 offers a deep powerdown feature, entered when RP# is at VIL. Current draw thru VCC is 10A The intelligent identifier operation outputs the manufacturer code, 89H; and the device code, A2H for the maximum in deep powerdown mode, with current draw through VPP maximal 5A. During read modes, RP#-low LH28F008SAT-85. The system CPU can then automatically match the device with its proper block erase and byte write deselects the memory, places output drivers in a highimpedence state and turns off all internal circuits. The algorithms. LH28F008SAT-85 requires time tPHQV (see AC Characteristics-Read-Only Operations) after return from powerdown The manufacturer- and device-codes are read via the Command User Interface. Following a write of 90H to the Com- until initial memory access outputs are valid. After this wakeup interval, normal operation is restored. The mand User Interface, a read from address location 00000H outputs the manufacturer code (89H). A read from address Command User Interface is reset to Read Array, and the upper 5bits of the Status Register are cleared to value 00001H outputs the device code (A2H). It is not necessary to have high voltage applied to VPP to read the intelligent 10000, upon return to normal operation. identifiers from the Command User Interface. During block erase or byte write modes, RP# low will abort either operation. Memory contents of the block being al- Write tered are no longer valid as the data will be partially written or erased. Time tPHWL after RP# goes to logic-high (VIH) is Writes to the Command User Interface enable reading of device data and intelligent identifiers. They also control in- required before another command can be written. spection and clearing of the Status Register. Additionally, when VPP=VPPH, the Command User Interface controls block erasure and byte write. The contents of the interface register serve as input to the internal state machine. Table 3. Command Definitions(6) Command Bus Second Bus Cycle First Bus Cycle Cycles Notes Req'd Operation(1) Address(2) Data(3) Operation(1) Address(2) Data(3) Read Array/Reset 1 Intelligent Identifier 3 Read Status Register Write X FFH Write X 90H Read IA IID 2 Write X 70H Read X SRD Clear Status Register 1 Write X 50H Erase Setup/Erase Confirm 2 Write BA 20H Write BA D0H Erase Suspend/Erase Resume 2 Write X B0H Write X D0H Byte Write Setup/Write 2 5 Write WA 40H Write WA WD Alternate Byte Write Setup/Write 2 5 Write WA 10H Write WA WD 4 NOTES: 1. Bus operations are defined in Table 2. 2. IA=Identifier Address: 00H for manufacturer code, 01H for device code. BA=Address within the block being erased. WA=Address of memory location to be written. 3. SRD=Data read from Status Register. See Table 4 for a description of the Status Register bits. WD=Data to be written at location WA. Data is latched on the rising edge of WE#. IID=Data read from intelligent identifiers. 4. Following the intelligent identifier command, two read operations access manufacture and device codes. 5. Either 40H or 10H are recognized by the WSM as the Byte Write Setup command. 6. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. sharp LHF08S49 11 The Command User Interface itself does not occupy an addressable memory location. The interface register is a latch Device operations are selected by writing specific commands into the Command User Interface. Table 3 defines used to store the command and address and data information needed to execute the command. Erase Setup and the LH28F008SAT-85 commands. Erase Confirm commands require both appropriate command data and an address within the block to be erased. Read Array Command The Byte Write Setup command requires both appropriate command data and the address of the location to be written, Upon initial device powerup and after exit from deep powerdown mode, the LH28F008SAT-85 defaults to Read while the Byte Write command consists of the data to be written and the address of the location to be written. Array mode. This operation is also initiated by writing FFH into the Command User Interface. Microprocessor read The Command User Interface is written by bringing WE# to cycles retrieve array data. The device remains enabled for reads until the Command User Interface contents are al- a logic-low level (VIL) while CE# is low. Addresses and data are latched on the rising edge of WE#. Standard micropro- tered. Once the internal Write State Machine has started a block erase or byte write operation, the device will not rec- cessor write timings are used. ognize the Read Array command, until the WSM has completed its operation. The Read Array command is functional Refer to AC Write Characteristics and the AC Waveforms for Write Operations, Figure 9, for specific timing param- when VPP=VPPL or VPPH. eters. Intelligent Identifier Command 5. The LH28F008SAT-85 contains an intelligent identifier operation, initiated by writing 90H into the Command User In- COMMAND DEFINITIONS When VPPL is applied to the VPP pin, read operations from the Status Register, intelligent identifiers, or array blocks are enabled. Placing VPPH on VPP enables successful byte write and block erase operations as well. terface. Following the command write, a read cycle from address 00000H retrieves the manufacturer code of 89H. A read cycle from address 00001H returns the device code of A2H. To terminate the operation, it is necessary to write another valid command into the register. Like the Read Array command, the intelligent identifier command is functional when VPP=VPPL or VPPH. Table 4. Status Register Definitions WSMS ESS ES BWS VPPS R R R 7 6 5 4 3 2 1 0 SR. 7=WRITE STATE MACHINE STATUS (WSMS) 1=Ready 0=Busy SR. 6=ERASE SUSPEND STATUS (ESS) 1=Erase Suspended 0=Erase in Progress/Completed SR. 5=ERASE STATUS (ES) 1=Error in Block Erasure 0=Successful Block Erase SR. 4=BYTE WRITE STATUS (BWS) 1=Error in Byte Write 0=Successful Byte Write SR. 3=VPP STATUS (VPPS) 1=VPP Low Detect; Operation Abort 0=VPP OK SR. 2-0=RESERVED FOR FUTURE ENHANCEMENTS (R) These bits are reserved for future use and should be masked out when polling the Status Register. NOTES: RY/BY# or the Write State Machine Status bit must first be checked to determine byte write or block erase completion, before the Byte Write or Erase Status bit are checked for success. If the Byte Write AND Erase Status bits are set to "1"s during a block erase attempt, an improper command sequence was entered. Attempt the operation again. If VPP low status is detected, the Status Register must be cleared before another byte write or block erase operation is attempted. The VPP Status bit, unlike an A/D converter, does not provide continuous indication of VPP level. The WSM interrogates the VPP level only after the byte write or block erase command sequences have been entered and informs the system if VPP has not been switched on. The VPP Status bit is not guaranteed to report accurate feedback between VPPL and VPPH. sharp LHF08S49 12 Read Status Register Command LH28F008SAT-85 automatically outputs Status Register data when read (see Figure 6; Block Erase Flowchart). The The LH28F008SAT-85 contains a Status Register which may be read to determine when a byte write or block erase CPU can detect the completion of the erase event by analyzing the output of the RY/BY# pin, or the WSM Status bit operation is complete, and whether that operation completed successfully. The Status Register may be read at of the Status Register. any time by writing the Read Status Register command (70H) to the Command User Interface. After writing this When erase is completed, the Erase Status bit should be checked. If erase error is detected, the Status Register command, all subsequent read operations output data from the Status Register, until another valid command is written should be cleared. The Command User Interface remains in Read Status Register mode until further commands are is- to the Command User Interface. The contents of the Status Register are latched on the falling edge of OE# or CE#, sued to it. whichever occurs last in the read cycle. OE# or CE# must be toggled to VIH before further reads to update the Status This two-step sequence of set-up followed by execution ensures that memory contents are not accidentally erased. Register latch. The Read Status Register command functions when VPP=VPPL or VPPH. Also, reliable block erasure can only occur when VPP=VPPH. In the absence of this high voltage, memory Clear Status Register Command contents are protected against erasure. If block erase is attempted while VPP=VPPL, the VPP Status bit will be set to The Erase Status and Byte Write Status bits are set to "1"s "1". Erase attempts while V PPL <V PP <V PPH produce spurious results and should not be attempted. by the Write State Machine and can only be reset by the Clear Status Register Command. These bits indicate vari- Erase Suspend/Erase Resume Commands ous failure conditions (see Table 4). By allowing system software to control the resetting of these bits, several opera- The Erase Suspend command allows block erase interrup- tions may be performed (such as cumulatively writing several bytes or erasing multiple blocks in sequence). The Sta- tion in order to read data from another block of memory. Once the erase process starts, writing the Erase Suspend tus Register may then be polled to determine if an error occurred during that sequence. This adds flexibility to the way command (B0H) to the Command User Interface requests that the WSM suspend the erase sequence at a predeter- the device may be used. mined point in the erase algorithm. The LH28F008SAT-85 continues to output Status Register data when read, after Additionally, the VPP Status bit (SR.3) MUST be reset by system software before further byte writes or block erases the Erase Suspend command is written to it. Polling the WSM Status and Erase Suspend Status bits will determine are attempted. To clear the Status Register, the Clear Status Register command (50H) is written to the Command when the erase operation has been suspended (both will be set to "1"). RY/BY# will also transition to VOH. User Interface. The Clear Status Register command is functional when VPP=VPPL or VPPH. At this point, a Read Array command can be written to the Erase Setup/Erase Confirm Commands Command User Interface to read data from blocks other than that which is suspended. The only other valid com- Erase is executed one block at a time, initiated by a two- mands at this time are Read Status Register (70H) and Erase Resume (D0H), at which time the WSM will continue cycle command sequence. An Erase Setup command (20H) is first written to the Command User Interface, fol- with the erase process. The Erase Suspend Status and WSM Status bits of the Status Register will be automatically lowed by the Erase Confirm command (D0H). These commands require both appropriate sequencing and an ad- cleared and RY/BY# will return to VOL. After the Erase Resume command is written to it, the LH28F008SAT-85 auto- dress within the block to be erased to FFH. Block preconditioning, erase and verify are all handled internally by the matically outputs Status Register data when read (see Figure 7; Erase Suspend/Resume Flowchart). VPP must re- Write State Machine, invisible to the system. After the twocommand erase sequence is written to it, the main at VPPH while the LH28F008SAT-85 is in Erase Suspend. sharp LHF08S49 Byte Write Setup/Write Commands Byte write is executed by a two-command sequence. The Byte Write Setup command (40H or 10H) is written to the Command User Interface, followed by a second write specifying the address and data (latched on the rising edge of WE#) to be written. The WSM then takes over, controlling the byte write and write verify algorithms internally. After the two-command byte write sequence is written to it, the LH28F008SAT-85 automatically outputs Status Register data when read (see Figure 5; Byte Write Flowchart). The CPU can detect the completion of the byte write event by analyzing the output of the RY/BY# pin, or the WSM Status bit of the Status Register. Only the Read Status Register command is valid while byte write is active. When byte write is complete, the Byte Write Status bit should be checked. If byte write error is detected, the Status Register should be cleared. The internal WSM verify only detects errors for "1"s that do not successfully write to "0"s. The Command User Interface remains in Read Status Register mode until further commands are issued to it. If byte write is attempted while VPP=VPPL, the VPP Status bit will be set to "1". Byte write attempts while V PPL <V PP <V PPH produce spurious results and should not be attempted. 6. EXTENDED BLOCK ERASE/BYTE WRITE CYCLING The LH28F008SAT-85 is designed for 100,000 byte write/ block erase cycles on each of the sixteen 64K-byte blocks. Low electric fields, advanced oxides and minimal oxide area per cell subjected to the tunneling electric field combine to greatly reduce oxide stress and the probability of failure. A 20M-byte solid-state drive using an array of LH28F008SA's has a MTBF (Mean Time Between Failure) of 33.3 million hours(1), over 600 times more reliable than equivalent rotating disk technology. 7. AUTOMATED BYTE WRITE The LH28F008SAT-85 integrates the Quick-Pulse programming algorithm using the Command User Interface, Status Register and Write State Machine (WSM). On-chip integration dramatically simplifies system software and provides processor interface timings to the Command User Interface and Status Register. WSM operation, internal verify and VPP high voltage presence are monitored and reported via the RY/BY# output and appropriate Status Register bits. Figure 5 shows a system software flowchart for device byte write. The entire sequence is performed with VPP at VPPH. Byte write abort occurs when RP# transitions to VIL, or VPP drops to VPPL. Although the WSM is halted, byte data is partially written at the location where byte write was aborted. Block erasure, or a repeat of byte write, is required to initialize this data to a known value. 8. AUTOMATED BLOCK ERASE As above, the Quick-Erase algorithm is now implemented internally, including all preconditioning of block data. WSM operation, erase success and VPP high voltage presence are monitored and reported through RY/BY# and the Status Register. Additionally, if a command other than Erase Confirm is written to the device following Erase Setup, both the Erase Status and Byte Write Status bits will be set to "1"s. When issuing the Erase Setup and Erase Confirm commands, they should be written to an address within the address range of the block to be erased. Figure 6 shows a system software flowchart for block erase. Erase typically takes 1.6s per block. The Erase Suspend/ Erase Resume command sequence allows suspension of this erase operation to read data from a block other than that in which erase is being performed. A system software flowchart is shown in Figure 7. The entire sequence is performed with VPP at VPPH. Abort occurs when RP# transitions to VILor VPP falls to V PPL, while erase is in progress. Block data is partially erased by this operation, and a repeat of erase is required to obtain a fully erased block. 9. DESIGN CONSIDERATIONS Three-Line Output Control The LH28F008SAT-85 will often be used in large memory arrays. SHARP provides three control inputs to accommodate multiple memory connections. Three-line control provides for: a) lowest possible memory power dissipation b) complete assurance that data bus contention will not occur To efficiently use these control inputs, an address decoder should enable CE#, while OE# should be connected to all memory devices and the system's READ# control line. This assures that only selected memory devices have active outputs while deselected memory devices are in Standby Mode. Finally, RP# should either be tied to the system RESET#, or connected to VCC if unused. (1) Assumptions: 10K-byte file written every 10 minutes. (20M-byte array)/(10K-byte file) = 2,000 file writes before erase required. (2000 files writes/erase) x (100,000 cycles per LH28F008SA block) = 200 million file writes. (200 x 106 file writes) x (10 min/write) x (1 hr/60 min) = 33.3 x 106 MTBF. 13 sharp LHF08S49 14 RY/BY# and Byte Write/Block Erase Polling RY/BY# can be connected to the interrupt input of the system CPU or controller. It is active at all times, not tristated if RY/BY# is a full CMOS output that provides a hardware the LH28F008SAT-85 CE# or OE# inputs are brought to VIH. RY/BY# is also VOH when the device is in Erase Sus- method of detecting byte write and block erase completion. It transitions low time tWHRL after a write or erase command pend or deep powerdown modes. sequence is written to the LH28F008SAT-85, and returns to VOH when the WSM has finished executing the internal algorithm. Bus Operation Start Write 40H (10H), Byte Address Command Comments Write Byte Write Setup Data=40H(10H) Address=Byte to be written Write Byte Write Data to be written Address=Byte to be written Write Byte Address/Data Check RY/BY# VOH=Ready, VOL=Busy or Standby/Read WSM Ready? NO Read Status Register Check SR.7 1=Ready, 0=Busy Toggle OE# or CE# to update Status Register YES Full Status Check if Desired Repeat for subsequent bytes Full status check can be done after each byte or after a sequence of bytes Byte Write Completed Write FFH after the last byte write operation to reset the device to Read Array Mode FULL STATUS CHECK PROCEDURE Status Register Data Read (See Above) SR.3=0 ? NO VPP Range Error YES SR.4=0 ? YES Byte Write Successful NO Byte Write Error Bus Operation Command Comments Optional Read CPU may already have read Status Register data in WSM Ready polling above Standby Check SR.3 1=VPP Low Detect Standby Check SR.4 1=Byte Write Error SR.3 MUST be cleared, if set during a byte write attempt, before further attempts are allowed by the Write State Machine. SR.4 is only cleared by the Clear Status Register Command, in cases where multiple bytes are written before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. Figure 5. Automated Byte Write Flowchart sharp LHF08S49 Bus Operation Start 15 Command Comments Write Erase Setup Data=20H Address=Within block to be erased Write Erase Data=D0H Address=Within block to be erased Write 20H, Block Address Write D0H Block Address Check RY/BY# VOH=Ready, VOL=Busy or Read Status Register Check SR.7 1=Ready, 0=Busy Toggle OE# or CE# to update Status Register Standby/Read NO WSM Ready? NO Suspend Erase? Erase Suspend Loop YES YES Full Status Check if Desired Repeat for subsequent bytes Full status check can be done after each block or after a sequence of blocks Block Erase Completed Write FFH after the last block erase operation to reset the device to Read Array Mode FULL STATUS CHECK PROCEDURE Status Register Data Read (See Above) SR.3=0 ? NO VPP Range Error YES SR.4,5=1 ? YES Command Sequence Error Bus Operation Command Comments Optional Read CPU may already have read Status Register data in WSM Ready polling above Standby Check SR.3 1=VPP Low Detect Standby Check SR.4,5 Both 1=Command Sequence Error Standby Check SR.5 1=Block Erase Error NO SR.5=0 ? YES Block Erase Successful NO Block Erase Error SR.3 MUST be cleared, if set during a block erase attempt, before further attempts are allowed by the Write State Machine. SR.5 is only cleared by the Clear Status Register Command, in cases where multiple blocks are erased before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. Figure 6. Automated Block Erase Flowchart sharp LHF08S49 Start 16 Bus Operation Command Write Erase Suspend Data=B0H Write Read Status Register Data=70H Write B0H Comments Write 70H Standby/ Read Check RY/BY# VOH=Ready, VOL=Busy or Read Status Register Read Status Register SR.7=1 ? Check SR.7 1=Ready, 0=Busy Toggle OE# or CE# to Update Status Register NO YES SR.6=1 ? Check SR.6 1=Suspended Standby NO YES Write Read Array Read Read array data from block other than that being erased. Write FFH Done Reading? Data=FFH Erase Has Completed Write NO Erase Resume Data=D0H YES Write D0H Continue Erase Figure 7. Erase Suspend/Resume Flowchart Power Supply Decoupling ally, for every 8 devices, a 4.7F electrolytic capacitor should be placed at the array's power supply connection Flash memory power switching characteristics require careful device decoupling. System designers are interested in 3 between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances. supply current issues; standby current levels (ISB), active current levels (ICC) and transient peaks produced by falling VPP Trace on Printed Circuit Boards and rising edges of CE#. Transient current magnitudes depend on the device outputs' capacitive and inductive load- Writing flash memories, while they reside in the target sys- ing. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device tem, requires that the printed circuit board designer pay attention to the VPP power supply trace. The VPP pin supplies should have a 0.1F ceramic capacitor connected between each VCC and GND, and between its VPP and GND. These the memory cell current for writing and erasing. Use similar trace widths and layout considerations given to the VCC high frequency, low inherent-inductance capacitors should be placed as close as possible to package leads. Addition- power bus. Adequate VPP Supply traces and decoupling will decrease VPP voltage spikes and overshoots. sharp LHF08S49 VCC, VPP, RP# Transitions and the Command/ Status Registers Byte write and block erase completion are not guaranteed if VPP drops below VPPH. If the VPP Status bit of the Status Register (SR.3) is set to "1", a Clear Status Register command MUST be issued before further byte write/block erase attempts are allowed by the WSM. Otherwise, the Byte Write (SR.4) or Erase (SR.5) Status bits of the Status Register will be set to "1"s if error is detected. RP# transitions to VIL during byte write and block erase also abort the operations. Data is partially altered in either case, and the command sequence must be repeated after normal operation is restored. Device poweroff, or RP# transitions to VIL, clear the Status Register to initial value 10000 for the upper 5 bits. The Command User Interface latches commands as issued by system software and is not altered by V PP or CE# transitions or WSM actions. Its state upon powerup, after exit from deep powerdown or after VCC transitions below VLKO, is Read Array Mode. After byte write or block erase is complete, even after VPP transitions down to V PPL, the Command User Interface must be reset to Read Array mode via the Read Array command if access to the memory array is desired. Power Up/Down Protection The LH28F008SAT-85 is designed to offer protection against accidental block erasure or byte writing during power transitions. Upon power-up, the LH28F008SAT-85 is indifferent as to which power supply, VPP or VCC, powers up first. Power supply sequencing is not required. Internal circuitry in the LH28F008SAT-85 ensures that the Command User Interface is reset to the Read Array mode on power up. 17 A system designer must guard against spurious writes for VCC voltages above VLKO when VPP is active. Since both WE# and CE# must be low for a command write, driving either to VIH will inhibit writes. The Command User Interface architecture provides an added level of protection since alteration of memory contents only occurs after successful completion of the two-step command sequences. Finally, the device is disabled until RP# is brought to VIH, regardless of the state of its control inputs. This provides an additional level of memory protection. Power Dissipation When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash nonvolatility increases usable battery life, because the LH28F008SAT-85 does not consume any power to retain code or data when the system is off. In addition, the LH28F008SA's deep powerdown mode ensures extremely low power dissipation even when system power is applied. For example, portable PCs and other power sensitive applications, using an array of LH28F008SA's for solid-state storage, can lower RP# to VIL in standby or sleep modes, producing negligible power consumption. If access to the LH28F008SAT-85 is again needed, the part can again be read, following the tPHQV and tPHWL wakeup cycles required after RP# is first raised back to VIH. See AC Characteristics -- Read-Only and Write Operations and Figures 8 and 9 for more information. sharp LHF08S49 10. ABSOLUTE MAXIMUM RATINGS* 18 * WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. Operating Temperature During Read .........................................0C to +70C(1) During Block Erase/Byte Write ................0C to +70C Temperature Under Bias .....................-10C to +80C Storage Temperature ........................-65C to +125C Voltage on Any Pin (except VCC and VPP) with Respect to GND .........................-2.0V to +7.0V(2) VPP Program Voltage with Respect to GND during Block Erase/Byte Write .................-2.0V to +14.0V(2,3) VCC Supply Voltage with Respect to GND ..........................-2.0V to +7.0V(2) Output Short Circuit Current ...........................100mA(4) NOTES: 1. Operating temperature is for commercial product defined by this specification. 2. All specified voltages are with respect to GND. Minimum DC voltage is -0.5V on input/output pins and -0.2V on VCC and VPP pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input/output pins, VCC and RP# pin is VCC+0.5V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. 3. Maximum DC voltage on VPP may overshoot to +14.0V for periods <20ns. 4. Output shorted for no more than one second. No more than one output shorted at a time. 11. OPERATING CONDITIONS Symbol TA Parameter Notes Min. Max. Unit 0 +70 C Operating Temperature VCC VCC Supply Voltage (5V0.5V) 1 4.50 5.50 V VCC VCC Supply Voltage (5V0.25V) 1 4.75 5.25 V NOTE: 1. 0.25V VCC specifications reference the LH28F008SA-85 in its High Speed configuration. 0.5V VCC specifications reference the LH28F008SA-85 in its Standard configuration. 12. DC CHARACTERISTICS TA=0 to +70 Symbol Parameter ILI Input Load Current ILO Output Leakage Current ICCS VCC Standby Current Notes Min. Typ. Max. Unit 1 1.0 A VCC=VCC Max. VIN=VCC or GND 1 10 A VCC=VCC Max. VOUT=VCC or GND 1.0 2.0 mA VCC=VCC Max. CE#=RP#=VIH 30 100 A VCC=VCC Max. CE#=RP#=VCC0.2V 0.2 10 A RP#=GND0.2V IOUT(RY/BY#)=0mA 20 35 mA VCC=VCC Max., CE#=GND f=8MHz, IOUT=0mA CMOS Inputs 25 50 mA VCC=VCC Max., CE#=VIL f=8MHz, IOUT=0mA TTL Inputs 1, 3 ICCD VCC Deep PowerDown Current ICCR VCC Read Current 1 1 Test Condition sharp LHF08S49 19 DC CHARACTERISTICS (Continued) Symbol Parameter Notes Min. Typ. Max. Unit Test Condition ICCW VCC Byte Write Current 1 10 30 mA Byte Write In Progress ICCE VCC Block Erase Current 1 10 30 mA Block Erase In Progress ICCES VCC Erase Suspend Current 1,2 5 10 mA Block Erase Suspended CE#=VIH IPPS VPP Standby Current 1 +15/ -300 A VPP=GND IPPD VPP Deep PowerDown Current 1 5.0 A RP#=GND0.2V IPPR VPP Read Current 1 200 A VPP>VCC IPPW VPP Byte Write Current 1 10 30 mA VPP=VPPH Byte Write in Progress IPPE VPP Block Erase Current 1 10 30 mA VPP=VPPH Block Erase in Progress IPPES VPP Erase Suspend Current 1 90 200 A VPP=VPPH Block Erase Suspended VIL Input Low Voltage -0.5 0.8 V VIH Input High Voltage 2.0 VCC+0.5 V VOL Output Low Voltage 0.45 V VCC=VCC Min. IOL=5.8mA VOH1 Output High Voltage (TTL) V VCC=VCC Min. IOH=-2.5mA VOH2 Output High Voltage (CMOS) 0.1 3 3 2.4 0.85VCC V VCC-0.4 VPPL VPP during Normal Operations VPPH VPP during Erase/Write Operations 11.4 VLKO VCC Erase/Write Lock Voltage 2.0 0.0 4 12.0 6.5 V 12.6 V IOH=-2.0mA VCC=VCC Min. IOH=-100A VCC=VCC Min. V NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC=5.0V, VPP=12.0V, TA=+25C. 2. ICCES is specified with the device deselected. If read while in Erase Suspend Mode, current draw is the sum of ICCES and ICCR. 3. 4. Includes RY/BY#. Block Erases/Byte Writes are inhibited when VPP=VPPL and not guaranteed in the range between VPPH and VPPL. 13. CAPACITANCE(1) TA=+25C, f=1MHz Symbol Parameter Typ. Max. Unit Condition CIN Input Capacitance 6 8 pF VIN=0V COUT Output Capacitance 8 12 pF VOUT=0V NOTE: 1. Sampled, not 100% tested. sharp LHF08S49 AC INPUT/OUTPUT REFERENCE WAVEFORM(1) 20 AC TESTING LOAD CIRCUIT(1) 1.3V 2.4 2.0 INPUT 2.0 1N914 OUTPUT TEST POINTS 0.8 0.45 0.8 RL DEVICE UNDER TEST AC test inputs are driven at VOH (2.4V TTL ) for a Logic "1" and VOL (0.45VTTL) for a Logic "0". Input timing begins at VIH (2.0VTTL) and VIL (0.8VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10ns. HIGH SPEED AC INPUT/OUTPUT REFERENCE WAVEFORM(2) OUT CL RL=3.3k CL=100pF (CL Includes Jig Capacitance) HIGH SPEED AC TESTING LOAD CIRCUIT(2) 1.3V 3.0 INPUT 1.5 TEST POINTS 1.5 1N914 OUTPUT RL 0.0 DEVICE UNDER TEST OUT CL AC test inputs are driven at 3.0V for a Logic "1" and 0.0V for a Logic "0". Input timing begins, and output timing ends, at 1.5V. Input rise and fall times (10% to 90%) <10ns. RL=3.3k CL=30pF (CL Includes Jig Capacitance) NOTES: 1. Testing characteristics for LH28F008SA-85 in Standard configuration. 2. Testing characteristics for LH28F008SA-85 in High Speed configuration. 14. AC CHARACTERISTICS -- Read-Only Operations(1) VCC=5V0.25V(4) Versions Symbol Parameter Notes tAVAV tRC Read Cycle Time tAVQV tACC Address to Output Delay tELQV tCE CE# to Output Delay tPHQV tPWH RP# High to Output Delay tGLQV tOE OE# to Output Delay 2 tELQX tLZ CE# to Output Low Z 3 tEHQZ tHZ CE# High to Output High Z 3 tGLQX tOLZ OE# to Output Low Z 3 tGHQZ tDF OE# High to Output High Z 3 tOH Output Hold from Addresses, CE# or OE# Change,Whichever is First 3 Min. Max. 85 2 VCC=5V0.5V(5) Min. Unit Max. ns 90 85 90 ns 85 90 ns 400 400 ns 40 45 ns 0 0 55 0 ns 55 0 30 0 ns 30 0 ns ns ns NOTES: 1. See AC Input/Output Reference Waveform for timing measurements. 2. OE# may be delayed up to tCE-tOE after the falling edge of CE# without impact on tCE. 3. Sampled, not 100% tested. 4. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load circuits for testing characteristics. 5. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics. Figure 8. AC Waveform for Read Operations VOL VOH VIL VIH VIL VIH VIL VIH VIL RP# (P) VIL VIH GND VCC 5.0V DATA (D/Q) WE# (W) OE# (G) CE# (E) ADDRESSES (A) VIH HIGH Z VCC POWER-UP STANDBY tPHQV OUTPUTS ENABLED tAVQV tELQX tGLQX tELQV tGLQV ADDRESSES STABLE DEVICE AND ADDRESS SELECTION tAVAV DATA VALID VALID OUTPUT tOH tGHQZ tEHQZ STANDBY HIGH Z VCC POWER-DOWN sharp LHF08S49 21 sharp LHF08S49 22 AC CHARACTERISTICS - Write Operations(1) Versions Symbol Parameter tAVAV tWC Write Cycle Time tPHWL tPS RP# High Recovery to WE# Going Low Notes 2 VCC=5V0.25V(7) VCC=5V0.5V(8) Min. Min. Max. Max. Unit 85 90 ns 1 1 s tELWL tCS CE# Setup to WE# Going Low 0 0 ns tWLWH tWP WE# Pulse Width 50 50 ns tVPWH tVPS VPP Setup to WE# Going High 2 100 100 ns tAVWH tAS 3 40 40 ns 4 40 40 ns Address Setup to WE# Going High tDVWH tDS Data Setup to WE# Going High tWHDX tDH Data Hold from WE# High 5 5 ns tWHAX tAH Address Hold from WE# High 5 5 ns tWHEH tCH CE# Hold from WE# High 0 0 ns tWHWL tWPH WE# Pulse Width High 25 25 ns tWHRL WE# High to RY/BY# Going Low tWHQV1 Duration of Byte Write Operation tWHQV2 Duration of Block Erase Operation tWHGL 100 6 6 s 5,6 0.3 0.3 s 0 0 ns 0 0 ns Write Recovery before tVPH V Hold from Valid SRD, PP RY/BY# High ns 5,6 Read tQVVL 100 2,6 NOTES: 1. Read timing characteristics during erase and byte write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations. 2. Sampled, not 100% tested. 3. Refer to Table 3 for valid AIN for byte write or block erasure. 4. Refer to Table 3 for valid DIN for byte write or block erasure. 5. The on-chip Write State Machine incorporates all byte write and block erase system functions and overhead of standard SHARP flash memory, including byte program and verify (byte write) and block precondition, precondition verify, erase and erase verify (block erase). 6. Byte write and block erase durations are measure to completion (SR.7=1, RY/ BY#=VOH). VPP should be held at VPPH until determination of byte write/block erase success (SR.3/4/5=0). 7. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics. 8. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics. sharp LHF08S49 23 15. BLOCK ERASE AND BYTE WRITE PERFORMANCE Parameter Notes Min. Typ.(1) Max. Unit Block Erase Time 2 1.6 10 s Block Write Time 2 0.6 2.1 s Byte Write Time s 8 NOTES: 1. TA=+25C, 12.0V VPP. 2. Excludes System-Level Overhead. AC CHARACTERISTICS - Reset Operation RY/BY#(R) RP#(P) VOH VOL tPLPLC VIH VIL tPLPH (A) Reset During Read Array Mode RY/BY#(R) RP#(P) VOH VOL tPLRH VIH VIL tPLPH (B) Reset During Block Erase or Byte Write AC Waveform for Reset Operation RESET AC Specifications Sym. Parameter tPLPH RP# Pulse Low Time (If RP# is tied to VCC, this specification is not applicable) tPLRH RP# Low to Reset during Block Erase or Byte Write (If RP# is tied to VCC, this specification is not applicable) tPLPLC Reset Cycle Time (During Read Array Mode) Notes Min. Max. 100 1,2 NOTES: 1. If RP# is asserted when the WSM is not busy (RY/BY#="1"), the reset will complete within 100ns. 2. A reset time, tPHQV, is required from the latter of RY/BY# or RP# going high until outputs are valid. ns 12 4 Unit s s Figure 9. AC Waveform for Write Operations VPP (V) RP# (P) RY/BY# (R) DATA (D/Q) WE# (W) OE# (G) CE# (E) ADDRESSES (A) WRITE VIL VIH VPPL VPPH VIL VIH VOL VOH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH tPHWL HIGH Z tDVWH tWLWH DIN tAVAV AIN ERASE SETUP COMMAND tELWL & STANDBY tWHDX tWHWL tWHEH tAVWH DIN AIN tVPWH tWHRL tWHAX OR ERASE CONFIRM COMMAND VCC POWER-UP WRITE BYTE WRITE OR VALID ADDRESS & DATA (BYTE WRITE) tWHQV1, 2 tWHGL OR ERASE DELAY AUTOMATED BYTE WRITE READ STATUS VALID SRD REGISTER DATA tQVVL DIN COMMAND WRITE READ ARRAY sharp LHF08S49 24 sharp LHF08S49 25 16. ALTERNATIVE CE#-CONTROLLED WRITES(1) Versions Symbol Parameter tAVAV tWC Write Cycle Time tPHEL tPS RP# High Recovery to CE# Going Low tWLEL tWS Notes tCP Min. Min. Max. Max. Unit 90 ns 1 1 s 0 0 ns 50 50 ns 2 100 100 ns 2 WE# Setup to CE# Going CE# Pulse Width tVPEH tVPS VPP Setup to CE# Going High VCC=5V0.5V(8) 85 Low tELEH VCC=5V0.25V(7) tAVEH tAS Address Setup to CE# Going High 3 40 40 ns tDVEH tDS Data Setup to CE# Going High 4 40 40 ns tEHDX tDH Data Hold from CE# High 5 5 ns tEHAX tAH Address Hold from CE# High 5 5 ns tEHWH tWH WE# Hold from CE# High 0 0 ns 25 25 ns tEHEL tEPH CE# Pulse Width High tEHRL CE# High to RY/BY# Going Low tEHQV1 Duration of Byte Write Operation tEHQV2 Duration of Block Erase Operation tEHGL 100 6 6 s 5 0.3 0.3 s 0 0 ns 0 0 ns Write Recovery before tVPH V Hold from Valid SRD, PP RY/BY# High ns 5 Read tQVVL 100 2,5 NOTES: 1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE# and WE#. In systems where CE# defines the write pulsewidth (within a longer WE# timing waveform), all setup, hold and inactive WE# times should be measured relative to the CE# waveform. 2. Sampled, not 100% tested. 3. Refer to Table 3 for valid AIN for byte write or block erasure. 4. Refer to Table 3 for valid DIN for byte write or block erasure. 5. Byte write and block erase durations are measured to completion (SR.7=1, RY/BY#=VOH). VPP should be held at VPPH until determination of byte write/block erase success (SR.3/4/5=0). 6. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics. 7. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics. Figure 10. AC Waveform for Write Operations VPP (V) RP# (P) RY/BY# (R) DATA (D/Q) CE# (E) OE# (G) WE# (W) ADDRESSES (A) WRITE VIL VPPL VIH VPPH VIL VIH VOL VOH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH tPHEL HIGH Z tDVEH tELEH DIN tAVAV AIN ERASE SETUP COMMAND tWLEL & STANDBY tEHDX tEHEL tEHWH tAVEH DIN AIN tVPEH tEHRL tEHAX OR ERASE CONFIRM COMMAND VCC POWER-UP WRITE BYTE WRITE OR VALID ADDRESS & DATA (BYTE WRITE) tEHQV1, 2 tEHGL OR ERASE DELAY AUTOMATED BYTE WRITE READ STATUS VALID SRD REGISTER DATA tQVVL DIN COMMAND WRITE READ ARRAY sharp LHF08S49 26 sharp i A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly. VCC(min) VCC GND tVR t2VPH *1 tR tPHQV VIH RP# (P) (RST#) VCCW *2 (V) VIL VCCWH1/2 (VPPH1/2) GND (VPP) tR or tF tR or tF tAVQV VIH Valid Address ADDRESS (A) VIL tF tR tELQV VIH CE# (E) VIL VIH WE# (W) VIL tF tR tGLQV VIH OE# (G) VIL VIH WP# (S) VIL VOH DATA (D/Q) VOL High Z Valid Output *1 t5VPH for the device in 5V operations. *2 To prevent the unwanted writes, system designers should consider the VCCW (VPP) switch, which connects VCCW (VPP) to GND during read operations and VCCWH1/2 (VPPH1/2) during write or erase operations. See the application note AP-007-SW-E for details. Figure A-1. AC Timing at Device Power-Up For the AC specifications tVR, tR, tF in the figure, refer to the next page. See the "ELECTRICAL SPECIFICATIONS" described in specifications for the supply voltage range, the operating temperature and the AC specifications not shown in the next page. Rev. 1.10 sharp ii A-1.1.1 Rise and Fall Time Symbol Parameter Notes Min. Max. Unit 1 0.5 30000 s/V tVR VCC Rise Time tR Input Signal Rise Time 1, 2 1 s/V tF Input Signal Fall Time 1, 2 1 s/V NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the device power-up but also the normal operations. tR(Max.) and tF(Max.) for RP# (RST#) are 100s/V. Rev. 1.10 sharp iii A-1.2 Glitch Noises Do not input the glitch noises which are below VIH (Min.) or above VIL (Max.) on address, data, reset, and control signals, as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal Input Signal VIH (Min.) VIH (Min.) VIL (Max.) VIL (Max.) Input Signal Input Signal (a) Acceptable Glitch Noises (b) NOT Acceptable Glitch Noises Figure A-2. Waveform for Glitch Noises See the "DC CHARACTERISTICS" described in specifications for VIH (Min.) and VIL (Max.). Rev. 1.10 sharp iv A-2 RELATED DOCUMENT INFORMATION(1) Document No. Document Name AP-001-SD-E Flash Memory Family Software Drivers AP-006-PT-E Data Protection Method of SHARP Flash Memory AP-007-SW-E RP#, VPP Electric Potential Switching Circuit NOTE: 1. International customers should contact their local SHARP or distribution sales office. Rev. 1.10 SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited Warranty for SHARP's product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible, for any incidental or consequential economic or property damage. NORTH AMERICA EUROPE JAPAN SHARP Microelectronics of the Americas 5700 NW Pacific Rim Blvd. Camas, WA 98607, U.S.A. Phone: (1) 360-834-2500 Fax: (1) 360-834-8903 Fast Info: (1) 800-833-9437 www.sharpsma.com SHARP Microelectronics Europe Division of Sharp Electronics (Europe) GmbH Sonninstrasse 3 20097 Hamburg, Germany Phone: (49) 40-2376-2286 Fax: (49) 40-2376-2232 www.sharpsme.com SHARP Corporation Electronic Components & Devices 22-22 Nagaike-cho, Abeno-Ku Osaka 545-8522, Japan Phone: (81) 6-6621-1221 Fax: (81) 6117-725300/6117-725301 www.sharp-world.com TAIWAN SINGAPORE KOREA SHARP Electronic Components (Taiwan) Corporation 8F-A, No. 16, Sec. 4, Nanking E. Rd. Taipei, Taiwan, Republic of China Phone: (886) 2-2577-7341 Fax: (886) 2-2577-7326/2-2577-7328 SHARP Electronics (Singapore) PTE., Ltd. 438A, Alexandra Road, #05-01/02 Alexandra Technopark, Singapore 119967 Phone: (65) 271-3566 Fax: (65) 271-3855 SHARP Electronic Components (Korea) Corporation RM 501 Geosung B/D, 541 Dohwa-dong, Mapo-ku Seoul 121-701, Korea Phone: (82) 2-711-5813 ~ 8 Fax: (82) 2-711-5819 CHINA HONG KONG SHARP Microelectronics of China (Shanghai) Co., Ltd. 28 Xin Jin Qiao Road King Tower 16F Pudong Shanghai, 201206 P.R. China Phone: (86) 21-5854-7710/21-5834-6056 Fax: (86) 21-5854-4340/21-5834-6057 Head Office: No. 360, Bashen Road, Xin Development Bldg. 22 Waigaoqiao Free Trade Zone Shanghai 200131 P.R. China Email: smc@china.global.sharp.co.jp SHARP-ROXY (Hong Kong) Ltd. 3rd Business Division, 17/F, Admiralty Centre, Tower 1 18 Harcourt Road, Hong Kong Phone: (852) 28229311 Fax: (852) 28660779 www.sharp.com.hk Shenzhen Representative Office: Room 13B1, Tower C, Electronics Science & Technology Building Shen Nan Zhong Road Shenzhen, P.R. China Phone: (86) 755-3273731 Fax: (86) 755-3273735