TQP3M9009
High Linearity LNA Gain Block
Advanced Data Sheet: Rev B 03/29/10 - 1 of 10 -
Disclaimer: Subject to change without notice
e
©
2009 TriQuint Semiconductor, Inc. Connecting the Digital World to the Global Network®
Applications
3-pin SOT-89 Package
Repeaters
Mobile Infrastructure
LTE / WCDMA / EDGE / CDMA
General Purpose Wireless
Product Features
Functional Block Diagram
50-4000 MHz
21.8 dB Gain @ 1.9 GHz
+39.5 dBm Output IP3
1.3 dB Noise Figure @ 1.9 GHz
50 Ohm Cascadable Gain Block
Unconditionally stable
High input power capability
+5V Single Supply, 125 mA Current
SOT-89 Package
RF IN GND RF OU T
GND
12 3
4
General Description
Pin Configuration
The TQP3M9009 is a cascadable, high linearity gain bloc
k
amplifier in a low-cost surface-mount package. At 1.9
GHz, the amplifier is targeted to provide 21.8 dB gain,
+39.5 dBm OIP3, and 1.3 dB Noise Figure while only
drawing 125 mA current. The device is housed in
a
leadfree/green/RoHS-compliant industry-standard SOT-89
p
ackage using a NiPdAu plating to eliminate the
possibility of tin whiskering.
The TQP3M9009 has the benefit of having high gain
across a broad range of frequencies while also providing
very low noise. This allows the device to be used in both
receiver and transmitter chains for high performance
systems. The amplifier is internally matched using a high
performance E-
p
HEMT process and only requires an
external RF choke and blocking/bypass capacitors fo
r
operation from a single +5V supply. The internal active
b
ias circuit also enables stable operation over bias an
d
temperature variations.
The TQP3M9009 covers the 0.05-4 GHz frequency ban
d
and is targeted for wireless infrastructure or othe
r
applications requiring high linearity and/or low noise
figure.
Ordering Information
Part No. Description
TQP3M9009 High Linearity LNA Gain Block
TQP3M9009-PCB_IF TQP3M9009 EVB 0.05-0.5 GHz
TQP3M9009-PCB_RF TQP3M9009 EVB 0.5-4 GHz
Standard T/R size = 1000 pieces on a 7” reel.
Pin # Symbol
1 RF Input
3 RF Output / Vcc
2, 4 Ground
TQP3M9009
High Linearity LNA Gain Block
Advanced Data Sheet: Rev B 03/29/10 - 2 of 10 -
Disclaimer: Subject to change without notice
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©
2009 TriQuint Semiconductor, Inc. Connecting the Digital World to the Global Network®
Specifications
Absolute Maximum Ratings
Parameter Rating
Storage Temperature -65 to +150 oC
RF Input Power,CW,50 Ω, T = 25ºC +23 dBm
Device Voltage,Vd
d
+7 V
Reverse Device Voltage -0.3 V
Thermal Resistance (junction to case) 34 oC/W
Junction Temperature, TJ
For 106 hours MTTF
190 oC
Operation of this device outside the parameter ranges given
above may cause permanent damage.
Recommended Operating Conditions
Parameter Min Typ Max Units
Vd
d
+4.75 +5 +5.25 V
T(case) -40 85
oC
Electrical specifications are measured at specified test conditions.
Specifications are not guaranteed over all recommended operating
conditions.
Electrical Specifications
Test conditions unless otherwise noted: +25ºC, +5V Vsupply, 50 Ω system.
Parameter Conditions Min Typical Max Units
Operational Frequency Range 50 4000 MHz
Test Frequency 1900 MHz
Gain 21.8 dB
Input Return Loss 13 dB
Output Return Loss 14 dB
Output P1dB +22 dBm
Output IP3 See Note 1. +39.5 dBm
Noise Figure 1.3 dB
Vdd +5 V
Current, Idd 125 mA
N
otes
1. OIP3 measured with two tones at an output power of +3 dBm / tone separated by 1 MHz. The suppression on the largest IM3 product is
used to calculate the OIP3 using 2:1 rule.
TQP3M9009
High Linearity LNA Gain Block
Advanced Data Sheet: Rev B 03/29/10 - 3 of 10 -
Disclaimer: Subject to change without notice
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©
2009 TriQuint Semiconductor, Inc. Connecting the Digital World to the Global Network®
Application Circuit Configuration
Bill of Material
Reference Designation Frequency (MHz)
TQP3M9009-PCB_IF TQP3M9009-PCB_RF
50 - 500 500 - 4000
Q1 TQP3M9009
C2, C6 1000 pF 100 pF
C1 0.01 uF 0.01 uF
L2 330 nH 68 nH
L1, D1, C3, C4 Do Not Place
B1 0 Ω
Notes:
1. Performances can be optimized at frequency of interest by using recommended component values shown in the table below.
Reference
Designation Frequency (MHz)
500 2000 2500 3500
C2, C6 100 pF 22 pF 22 pF 22 pF
L2 82 nH 22 nH 18 nH 15 nH
N
otes:
1. See PC Board Layout, page 8 for more information.
2. Components shown on the silkscreen but not on the schematic are not used.
3. B1 (0 Ω jumper) may be replaced with copper trace in the target application layout.
4. The recommended component values are dependent upon the frequency of operation.
5. All components are of 0603 size unless stated on the schematic.
+5Vdd
TQP3M9009
High Linearity LNA Gain Block
Advanced Data Sheet: Rev B 03/29/10 - 4 of 10 -
Disclaimer: Subject to change without notice
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©
2009 TriQuint Semiconductor, Inc. Connecting the Digital World to the Global Network®
Typical Performance 500-4000 MHz
Test conditions unless otherwise noted: +25ºC, +5V, 125 mA, 50 Ω system. The data shown below is measured on TQP3M9009-PCB_RF.
Notes:
1. OIP3 measured with two tones at an output power of +3 dBm / tone separated by 1 MHz. The suppression on the largest IM3 product is
used to calculate the OIP3 using 2:1 rule.
2. Noise figure data shown in the table above is measured on evaluation board which includes board losses of around 0.1 dB @ 2 GHz.
RF Performance Plots
16
20
24
28
500 1000 1500 2000 2500 3000 3500 4000
Gain (dB )
Frequency (MHz)
Gain vs. Frequency over Temp
-40 C
-20 C
+25 C
+85 C
-20
-15
-10
-5
0
500 1000 1500 2000 2500 3000 3500 4000
S11 (dB)
Frequency (MHz)
S11 v s. Fre que ncy over Te mp
+85 C
+25 C
-20 ⁰C
-40 C
-20
-15
-10
-5
0
500 1000 1500 2000 2500 3000 3500 4000
S22 (dB)
Frequency (MHz)
S22 vs. Frequency over Temp
-40 C
-20 ⁰C
+25 C
+85 C
0
1
2
3
4
500 1000 1500 2000 2500 3000 3500 4000
NF (dB)
Frequency (MHz)
Noise Figure vs. Frequency over Temp
+85 C
+25 C
-40 C
Frequency MHz 500 900 1900 2700 3500 4000
Gain dB 25.5 24.7 21.8 20 18.9 17.9
Input Return Loss dB 11.5 12 13 13 8 6
Output Return Loss dB 10.8 13 14 10 10 11.3
Output P1dB dBm +22.5 +21.8 +22 +21.6 +21.8 +20.7
OIP3 [1] dBm +41.4 +40.5 +39.5 +39 +37.9 +35.8
Noise Figure [2] dB 0.9 0.9 1.3 1.7 2.1 2.4
TQP3M9009
High Linearity LNA Gain Block
Advanced Data Sheet: Rev B 03/29/10 - 5 of 10 -
Disclaimer: Subject to change without notice
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©
2009 TriQuint Semiconductor, Inc. Connecting the Digital World to the Global Network®
RF Performance Plots
25
30
35
40
45
024681012
OIP3 (dBm)
Pout / tone (dBm)
OIP3 vs. Pout / tone ove r Temp
Freq = 1900 MHz, 1 MHz Spacing
+25 C
+85 C
-40 C
25
30
35
40
45
500 1000 1500 2000 2500 3000 3500 4000
OIP3 (dBm)
Pout / tone (dBm)
OIP3 vs. Fr equency over Temp
1 MHz Spacing, 3 dBm/tone
+25 C
+85 C
-40 C
25
30
35
40
45
3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25
OIP3 (dBm)
Vdd (V)
OIP3 vs. Vdd
F=1900 MHz, 1 MHz Spacing, T=+25
⁰C
, 3dBm / tone
14
16
18
20
22
24
500 1000 1500 2000 2500 3000 3500 4000
P1dB ( dB)
Frequency (MHz)
P1dB vs. Frequency over Temp
-40 C
+25 C
+85 C
105
110
115
120
125
130
3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25
Idd (mA)
Vdd (V)
Idd vs. Vdd
T=25
⁰
C, CW Signal
105
110
115
120
125
130
-40 -15 10 35 60 85
Idd (mA)
Temperature (
⁰
C)
Idd vs. Temperature
CW Signal
TQP3M9009
High Linearity LNA Gain Block
Advanced Data Sheet: Rev B 03/29/10 - 6 of 10 -
Disclaimer: Subject to change without notice
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©
2009 TriQuint Semiconductor, Inc. Connecting the Digital World to the Global Network®
Typical Performance 50-500 MHz
Test conditions unless otherwise noted: +25ºC, +5V, 125 mA, 50 Ω system. The data shown below is measured on TQP3M9009-PCB_IF.
Notes:
1. OIP3 measured with two tones at an output power of +3 dBm / tone separated by 1 MHz. The suppression on the largest IM3 product is
used to calculate the OIP3 using 2:1 rule.
2. Noise figure data shown in the table above is measured on evaluation board which includes board losses of around 0.1 dB @ 2 GHz.
IF Performance Plots
16
20
24
28
0 100 200 300 400 500
Gain (dB )
Frequency (MHz)
Gain vs. Frequency over Temp
-40 C
-20
⁰
C
+25 C
+85 C
-20
-15
-10
-5
0
0 100 200 300 400 500
S11 (dB)
Frequency (MHz)
S11 v s. Fre que ncy ov e r Te mp
-40 C
-20
⁰
C
+25 C
+85 C
-20
-15
-10
-5
0
0 100 200 300 400 500
S22 (dB)
Frequency (MHz)
S22 vs. Frequency over Temp
-40 C
+20 C
+25 C
+85
⁰
C
0
1
2
3
4
0 100 200 300 400 500
NF (dB)
Frequency (MHz)
Noise Figure vs. Frequency over Temp
+85 C
+25 C
-40 C
Frequency MHz 70 100 200 500
Gain dB 27 26.8 26.4 25.8
Input Return Loss dB 12 13 13 13
Output Return Loss dB 11 12 12 13
Output P1dB dBm +21.6 +21.9 +21.9 +22.2
OIP3 [1] dBm +37.6 +38.8 +39 +41.4
Noise Figure [2] dB 1.4 1.3 0.9 0.9
TQP3M9009
High Linearity LNA Gain Block
Advanced Data Sheet: Rev B 03/29/10 - 7 of 10 -
Disclaimer: Subject to change without notice
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©
2009 TriQuint Semiconductor, Inc. Connecting the Digital World to the Global Network®
IF Performance Plots
25
30
35
40
45
0 100 200 300 400 500
OIP3 (dBm)
Pout / tone (dBm)
OIP3 vs. Fr equency over Temp
1 MHz Spacing, 3 dBm/tone
-40 C
+25 C
+85 C
14
16
18
20
22
24
0 100 200 300 400 500
P1dB ( dB)
Frequency (MHz)
P1dB vs. Frequency over Temp
-40 C
+25 C
+85 C
TQP3M9009
High Linearity LNA Gain Block
Advanced Data Sheet: Rev B 03/29/10 - 8 of 10 -
Disclaimer: Subject to change without notice
e
©
2009 TriQuint Semiconductor, Inc. Connecting the Digital World to the Global Network®
Pin Configuration and Description
RF IN GND RF OU T
GND
123
4
Pin Symbol Description
1 RF IN Input, matched to 50 ohms, External DC block is required.
2, 4 GND Needed for RF and the thermal path
3 RFout / Vdd Output, matched to 50 ohms, External DC Block is required and supply voltage
Applications Information
PC Board Layout
Top RF layer is .014” NELCO N4000-13, єr = 3.9, 4 total
layers (0.062” thick) for mechanical rigidity. Metal
layers are 1-oz copper. 50 ohm Microstrip line details:
width = .029”, spacing = .035”.
The pad pattern shown has been developed and tested for
optimized assembly at TriQuint Semiconductor. The
PCB land pattern has been developed to accommodate
lead and package tolerances. Since surface mount
processes vary from supplier to supplier, careful process
development is recommended.
TQP3M9009
High Linearity LNA Gain Block
Advanced Data Sheet: Rev B 03/29/10 - 9 of 10 -
Disclaimer: Subject to change without notice
e
©
2009 TriQuint Semiconductor, Inc. Connecting the Digital World to the Global Network®
Mechanical Information
Package Information and Dimensions
This package is lead-free/RoHS-
compliant. The plating material on the
leads is NiPdAu. It is compatible with
both lead-free (maximum 260 °C
reflow temperature) and lead
(maximum 245 °C reflow temperature)
soldering processes.
The component will be marked with a
“3M9009” designator with an
alphanumeric lot code on the top
surface of package. The “Y” represents
the last digit of the year the part was
manufactured; the “XXX” is an auto
generated number.
Mounting Configuration
All dimensions are in millimeters (inches). Angles are in degrees.
Notes:
1. Ground / thermal vias are critical for the proper performance of this device. Vias should use a .35mm (#80 / .0135”) diameter drill and
have a final plated thru diameter of .25 mm (.010”).
2. Add as much copper as possible to inner and outer layers near the part to ensure optimal thermal performance.
3. RF trace width depends upon the PC board material and construction.
4. Use 1 oz. Copper minimum.
3M9009
YXXX
TQP3M9009
High Linearity LNA Gain Block
Advanced Data Sheet: Rev B 03/29/10 - 10 of 10
Disclaimer: Subject to change without notice
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©
2009 TriQuint Semiconductor, Inc. Connecting the Digital World to the Global Network®
Product Compliance Information
ESD Information
ESD Rating: Class 1A
Value: Passes ≥ 250 V to < 500 V.
Test: Human Body Model (HBM)
Standard: JEDEC Standard JESD22-A114
ESD Rating: Class IV
Value: Passes ≥ 1000 V
Test: Charged Device Model (CDM)
Standard: JEDEC Standard JESD22-C101
Solderability
Compatible with the latest version of J-STD-020, Lead
free solder, 260°
This part is compliant with EU 2002/95/EC RoHS
directive (Restrictions on the Use of Certain Hazardous
Substances in Electrical and Electronic Equipment).
This product also has the following attributes:
• Lead Free
• Halogen Free (Chlorine, Bromine)
• Antimony Free
• TBBP-A (C15H12Br402) Free
• PFOS Free
• SVHC Free
MSL Rating
Level 3 at +260 °C convection reflow
The part is rated Moisture Sensitivity Level 3 at 260°C per
JEDEC standard IPC/JEDEC J-STD-020.
Contact Information
For the latest specifications, additional product information, worldwide sales and distribution locations, and information about
TriQuint:
Web: www.triquint.com Tel: +1.503.615.9000
Email: info-sales@tqs.com Fax: +1.503.615.8902
For technical questions and application information:
Email: sjcapplications.engineering@tqs.com
Important Notice
The information contained herein is believed to be reliable. TriQuint makes no warranties regarding the information contained
herein. TriQuint assumes no responsibility or liability whatsoever for any of the information contained herein. TriQuint
assumes no responsibility or liability whatsoever for the use of the information contained herein. The information contained
herein is provided "AS IS, WHERE IS" and with all faults, and the entire risk associated with such information is entirely with
the user. All information contained herein is subject to change without notice. Customers should obtain and verify the latest
relevant information before placing orders for TriQuint products. The information contained herein or any use of such
information does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other intellectual property
rights, whether with regard to such information itself or anything described by such information.
TriQuint products are not warranted or authorized for use as critical components in medical, life-saving, or life-sustaining
applications, or other applications where a failure would reasonably be expected to cause severe personal injury or death.
