DuSLIC
Dual Channel Subscriber Line
Interface Circuit
PEB 3264/-2 Version 1.2
PEB 4264/-2 Version 1.1
PEB 3265 Version 1.2
PEB 4265/-2 Version 1.1
PEB 4266 Version 1.1
Never stop thinking.
Wired
Communications
Data Sheet, DS2, July 2000
Edition 2000-07-14
Published by Infineon Technologies A G,
St.-Martin-Strasse 53,
D-81541 München, German y
© Infineon Technologies AG 8/16/00.
All Rights Reserved.
Attention please!
The information herein is given to describe cer ta in components and shall not be considered as warranted
characteristics.
Ter m s of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For fur t her information on technology, deliver y terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address
list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or sys tems with the ex press written
approv al of Infineon Technologies, if a f ailure of such components can reasonably be e xpected to cause the f ailure
of that life-support de vice or system, or to affect the saf ety or effectiveness of that device or system. Life support
de vices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. I f they f ail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Preliminary
Wired
Communications
DuSLIC
Dual Channel Subscriber Line
Interface Circuit
PEB 3264/-2 Version 1.2
PEB 4264/-2 Version 1.1
PEB 3265 Version 1.2
PEB 4265/-2 Version 1.1
PEB 4266 Version 1.1
Data Sheet, DS2, July 2000
Never stop thinking.
For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see our webpage at http://www.infineon.com.
DuSLIC
Preliminary
Revisi on History: 2000-07-14 DS2
Previous Version: Data Sheet D S 1
Page Subjec ts (major c hanges sinc e last revis i on)
Page 15 Usag e of the te rm SLICOFI-2x as synon y m us ed f or all codec v ers ions
SLICOFI-2/-2S/-2S2.
Page 33 Chapter 3.1 "Functional Overview" completely upda ted.
Page 94 Chapter 4.7.2 "Power Dissipation of SLICOFI-2": Power dissipation tables
were replaced by cross-references to Chapter 7.
Page 107 Chapter 4.8 "Int eg r ated Test and Diagnosi s Fun c ti o ns" rep l aces the
former chapter "Test Modes".
Page 132 Chapter 4.9 "Signal P at h and Test L oops": updated figures.
Page 137 Chapter 4.10 "Caller ID Buf fe r Handling of SLIC OF I -2" added.
Page 162 Figure 70 "I nter face SL ICOFI-2 a nd SLIC- P": Pi n IO1A on PE B 3265 was
replace d by pin IO2A.
Page 174 Regi ster XCR: Bit PLL-L OOP r emo ved.
Page 204 Register LMCR2: D es c r ipt ion for bit LM -N OT CH changed.
Page 228 Chapter 6.2.3 "POP C omma nds ": General update and part ially renaming
of POP commands .
Page 317 Chapter 7: Electrical characteristics and AC transmission performance
complet ely updated.
Page 342 Chapter 7.4.6 "Digital Interface": Test condition current I0 for Low-output
voltage VOLDU for PEB 3264/-2 was lowered to I0=–30mA.
Page 367 Chapter 8 "Applicat ion Ci rc uit s " completely ov erwork ed.
DuSLIC
Table of Contents Page
Data Sheet 5 2000-07-14
1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.2 Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.3 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.1 Pin Diagram SLIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2 Pin Diagram SLICOFI-2/-2S/-2S2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.1.1 Basic Functions available for all DuSLIC Chip Sets . . . . . . . . . . . . . . . 33
3.1.2 Additional Functions available for DuSLIC-E/-E2/-P Chip Sets . . . . . . . 34
3.2 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.3 DC Feeding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.3.1 DC Characteristic Feeding Zones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.3.2 Constant Current Zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.3.3 Resistive Zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3.4 Constant Voltage Zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3.5 Programmable Volt age and C urrent Range of DC Ch aracteris tic . . . . . 45
3.3.6 SLIC Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3.7 Necessary Voltage Reserve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.3.8 Extended Battery Feeding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.4 AC Transmission Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.4.1 Transmit Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.4.2 Receive Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.4.3 Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.5 Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.5.1 Ringer Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.5.2 Ring Trip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.5.3 Ringing Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.5.4 DuSLIC Ringing Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.5.5 Internal Balanced Ringing via SLICs . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.5.6 Internal Unbalanced Ringing with SLIC-P . . . . . . . . . . . . . . . . . . . . . . . 58
3.5.7 External Unbalanced Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.6 Signaling (Supervision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.7 Metering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.7.1 Metering by 12/16 kHz Sinusoidal Bursts . . . . . . . . . . . . . . . . . . . . . . . 61
3.7.2 Metering by Polarity Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.7.2.1 Soft Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.8 DuSL IC Enhanced Signal Pr ocessing Capabilities . . . . . . . . . . . . . . . . . . 63
3.8.1 DTMF Generation and Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.8.2 Caller ID Generation (only DuSLIC-E/-E2/-P) . . . . . . . . . . . . . . . . . . . . 66
DuSLIC
Table of Contents Page
Data Sheet 6 2000-07-14
3.8.3 Line Echo Cancelling (LEC) (only DuSLIC-E/-E2/-P) . . . . . . . . . . . . . . 69
3.8.4 Universal Tone Detection (UTD) (only DuSLIC-E/-E2/-P) . . . . . . . . . . . 70
3.8.5 MIPS Requirements for EDSP Capa bilitie s . . . . . . . . . . . . . . . . . . . . . . 71
3.9 Message Waiting Indication (only DuSLIC-E/-E2/-P) . . . . . . . . . . . . . . . . 72
3.10 Three-party Conferencing (only DuSLIC-E/-E2/-P) . . . . . . . . . . . . . . . . . . 74
3.10.1 Conferencing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.11 16 kHz Mode on PCM Highway . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.1 Operating Modes for the DuSLIC Chip Set . . . . . . . . . . . . . . . . . . . . . . . . 78
4.2 Operating Modes for the DuSLIC-S/-S2 Chip Set . . . . . . . . . . . . . . . . . . . 82
4.3 Operating Modes for the DuSLIC-E/-E2 Chip Set . . . . . . . . . . . . . . . . . . . 84
4.4 Operating Modes for the DuSLIC-P Chip Set . . . . . . . . . . . . . . . . . . . . . . 86
4.5 Reset Mode and Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.5.1 Hardware and Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.5.2 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.6 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.7 Operating Modes and Power Management . . . . . . . . . . . . . . . . . . . . . . . . 93
4.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.7.2 Power Dis s i patio n of the SLICOFI-2x . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.7.3 Power Dissipation of the SLIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.7.3.1 P ower Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.7.3.2 Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.7.3.3 S LIC Power Consumption Calculation in Active Mode . . . . . . . . . . . 96
4.7.3.4 Ri nging Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.7.3 . 5 SLIC Pow er Consumption Calculation in R inging Mo de . . . . . . . . . 103
4.8 Integrated Test and Diagnosis Functions (ITDF) . . . . . . . . . . . . . . . . . . . 107
4.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.8.1.1 Conventional Line Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.8.1.2 DuSLIC Line Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.8.2 Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.8.2.1 Line Test Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.8.2.2 Integrated Signal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.8.2.3 Result Register Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
4.8.2.4 Using the Levelmeter Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
4.8.2.5 DC Levelmeter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4.8.2.6 AC Levelmeter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.8.2.7 Levelmeter Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
4.8.2.8 Current Offset Error Compensation . . . . . . . . . . . . . . . . . . . . . . . . . 122
4.8.2.9 L oop Resistance Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.8.2.10 Line Resistance Tip/GND and Ring/GND . . . . . . . . . . . . . . . . . . . . 125
4.8.2.11 Capacitance Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
4.8.2.12 Line Capacitance Measurements Ring and Tip to GND . . . . . . . . . 129
DuSLIC
Table of Contents Page
Data Sheet 7 2000-07-14
4.8.2.13 Foreign- and Ring Voltage Measurements . . . . . . . . . . . . . . . . . . . 129
4.9 Signal Path and Test Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
4.9.1 Test Loops DuSLIC-E/-E2/-P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
4.9.2 Test Loops DuSLIC-S/-S2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
4.10 Caller ID Buffer Handling of SLICOFI-2 . . . . . . . . . . . . . . . . . . . . . . . . . . 137
5 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.1 PCM Interface with a Serial Microcontroller Interface . . . . . . . . . . . . . . . 138
5.1.1 PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.1.2 Control of the Active PCM Channels . . . . . . . . . . . . . . . . . . . . . . . . . . 142
5.1.3 Serial Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
5.2 The IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.2.1 IOM-2 Interface Monitor Transfer Protocol . . . . . . . . . . . . . . . . . . . . . 148
5.2.2 SLICOFI-2x Identification Command (only IOM-2 Interface) . . . . . . . . 152
5.3 TIP/RING Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
5.4 SLICOFI-2S/-2S2 and SLIC-S/-S2 Interface . . . . . . . . . . . . . . . . . . . . . . 153
5.5 SLICOFI-2 and SLIC-E/-E2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
5.6 SLICOFI-2 and SLIC-P Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
6SLICOFI-2x Command Structure and Programming . . . . . . . . . . . . . 163
6.1 Overview of Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
6.2 SLICOFI-2 Command Structure and Programming . . . . . . . . . . . . . . . . . 167
6.2.1 SOP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
6.2.1.1 SOP Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
6.2.1.2 SOP Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
6.2.2 COP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
6.2.2.1 CRAM Programming Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
6.2.3 POP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
6.2.3.1 POP Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
6.2.4 POP Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
6.2.5 IOM-2 Interface Command/Indication Byte . . . . . . . . . . . . . . . . . . . . . 262
6.2.6 Programming Examples of the SLICOFI-2 . . . . . . . . . . . . . . . . . . . . . 264
6.2.6.1 Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
6.2.6.2 IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
6.3 SLICO FI-2S/ -2S2 Com m and Structur e and Programm ing . . . . . . . . . . . 267
6.3.1 SOP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
6.3.1.1 SOP Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
6.3.1.2 SOP Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
6.3.2 COP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
6.3.2.1 CRAM Programming Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
6.3.3 IOM-2 Interface Command/Indication Byte . . . . . . . . . . . . . . . . . . . . . 312
6.3.4 Programming Examples of the SLICOFI-2S/-2S2 . . . . . . . . . . . . . . . . 314
6.3.4.1 Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
DuSLIC
Table of Contents Page
Data Sheet 8 2000-07-14
6.3.4.2 IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
7 Elect rical Charact eristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
7.1 Electrical Characteristics PEB 4264/-2 (SLIC-S/-S2) . . . . . . . . . . . . . . . 317
7.1.1 Absolute Maximum Ratings PEB 4264/-2 (SLIC-S/-S2) . . . . . . . . . . . 317
7.1.2 Operating Range PEB 4264/-2 (SLIC-S/-S2) . . . . . . . . . . . . . . . . . . . 319
7.1.3 Thermal Resistances PEB 4264/-2 (SLIC-S/-S2) . . . . . . . . . . . . . . . . 319
7.1.4 Electrical Parameters PEB 4264/-2 (SLIC-S/-S2) . . . . . . . . . . . . . . . . 320
7.1.5 Power Calculation PEB 4264/-2 (SLIC-S/-S2) . . . . . . . . . . . . . . . . . . . 322
7.1.6 Power Up Sequence PEB 4264/-2 (SLIC-S/-S2) . . . . . . . . . . . . . . . . . 323
7.2 Electrical Characteristics PEB 4265/-2 (SLIC-E/-E2) . . . . . . . . . . . . . . . 324
7.2.1 Absolute Maximum Ratings PEB 4265/-2 (SLIC-E/-E2) . . . . . . . . . . . 324
7.2.2 Operating Range PEB 4265/-2 (SLIC-E/-E2) . . . . . . . . . . . . . . . . . . . 325
7.2.3 Thermal Resistances PEB 4265/-2 (SLIC-E/-E2) . . . . . . . . . . . . . . . . 325
7.2.4 Electrical Parameters PEB 4265/-2 (SLIC-E/-E2) . . . . . . . . . . . . . . . . 326
7.2.5 Power Calculation PEB 4265/-2 (SLIC-E/-E2) . . . . . . . . . . . . . . . . . . . 328
7.2.6 Power Up Sequence PEB 4265/-2 (SLIC-E/-E2) . . . . . . . . . . . . . . . . . 329
7.3 Electrical Characteristics PEB 4266 (SLIC-P) . . . . . . . . . . . . . . . . . . . . . 330
7.3.1 Absolute Maximum Ratings PEB 4266 (SLIC-P) . . . . . . . . . . . . . . . . . 330
7.3.2 Operating Range PEB 4266 (SLIC-P) . . . . . . . . . . . . . . . . . . . . . . . . . 332
7.3.3 Thermal Resistances PEB 4266 (SLIC-P) . . . . . . . . . . . . . . . . . . . . . . 332
7.3.4 Electrical Parameters PEB 4266 (SLIC-P) . . . . . . . . . . . . . . . . . . . . . 333
7.3.5 Power Calculation PEB 4266 (SLIC-P) . . . . . . . . . . . . . . . . . . . . . . . . 336
7.3.6 Power Up Sequence PEB 4266 (SLIC-P) . . . . . . . . . . . . . . . . . . . . . . 337
7.4 Electrical Characteristics PEB 3265/PEB 3264/PEB 3264-2 (SLICOFI-2/-2S/-
2S2) 338
7.4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
7.4.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
7.4.3 Power Dissipation PEB 3265 (SLICOFI-2) . . . . . . . . . . . . . . . . . . . . . 340
7.4.4 Power Dissipation PEB 3264, PEB 3264-2 (SLICOFI-2S/-2S2) . . . . . 341
7.4.5 Power Up Sequence for Supply Voltages . . . . . . . . . . . . . . . . . . . . . . 341
7.4.6 Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
7.5 AC Transmission DuSLIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
7.5.1 Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
7.5.2 Gain Tracking (Receive or Transmit) . . . . . . . . . . . . . . . . . . . . . . . . . . 352
7.5.3 Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
7.5.4 Out-of-Band Signals at Analog Output (Receive) . . . . . . . . . . . . . . . . 354
7.5.5 Out-of-Band Signals at Analog Input (Transmit) . . . . . . . . . . . . . . . . . 355
7.5.6 Total Distortion Measured with Sine Wave . . . . . . . . . . . . . . . . . . . . . 356
7.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
7.7 DuSLIC Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
7.7.1 MCLK/FSC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
7.7.2 PCM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
DuSLIC
Table of Contents Page
Data Sheet 9 2000-07-14
7.7.2.1 Single-Clocking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
7.7.2.2 Double-Clocking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
7.7.3 Microcontroller Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
7.7.4 IOM-2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
7.7.4.1 Single-Clocking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
7.7.4.2 Double-Clocking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
8 Application Cir cuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
8.1 Internal Ringing (Balanced/Unbalanced) . . . . . . . . . . . . . . . . . . . . . . . . . 367
8.1.1 Circuit Diagram Internal Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
8.1.2 Protection Circuit for SLIC-E/-E2 and SLIC-S . . . . . . . . . . . . . . . . . . . 369
8.1.3 Protection Circuit for SLIC-P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
8.1.4 Bill of Materi als (Including Protection) . . . . . . . . . . . . . . . . . . . . . . . . . 371
8.2 External Unbalanced Ringing with DuSLIC-E/-E2/-S/-S2/-P . . . . . . . . . . 372
8.3 DuSLIC Layout Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
9 Packa ge Outline s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
10 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
10.1 List of Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
11 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
DuSLIC
List of Figures Page
Data Sheet 10 2000-07-14
Figure 1 DuSLIC Chip Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 2 Logic Symbol SLIC-S / SLIC-S2 / SLIC-E / SLIC-E2. . . . . . . . . . . . . . 20
Figure 3 Logic Symbol SLIC-P. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 4 Logic Symbol SLICOFI-2/-2S/-2S2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 5 Pin Configuration SLIC-S/-S2, SLIC-E/-E2, SLIC-P (top view) . . . . . . 23
Figure 6 Pin Configuration SLICOFI-2/-2S/-2S2 (top view) . . . . . . . . . . . . . . . . 28
Figure 7 Line Circuit Functions included in the DuSLIC-S/-S2 . . . . . . . . . . . . . 35
Figure 8 Line Circuit Functions included in the DuSLIC-E/-E2/-P . . . . . . . . . . . 35
Figure 9 Block Diagram SLIC-S/-S2 (PEB 4264/-2). . . . . . . . . . . . . . . . . . . . . . 36
Figure 10 Block Diagram SLIC-E/-E2 (PEB 4265/-2). . . . . . . . . . . . . . . . . . . . . . 37
Figure 11 Block Diagram SLIC-P (PEB 4266) . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 12 Block Diagram SLICOFI-2/-2S/-2S2 (PEB 3265, PEB 3264/-2) . . . . . 39
Figur e 13 S igna l Pa th s – DC Feeding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 14 DC Feeding Characteristic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 15 Constant Current Zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 16 Resistive Zone. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 17 Constant Voltage Zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 18 DC Characteristic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 19 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 20 TTX Voltage Reserve Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 21 DC Feeding Characteristics (ACTH, ACTR) . . . . . . . . . . . . . . . . . . . . 48
Figure 22 Signal Paths - AC Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 23 Signal Flow in Voice Channel (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 24 Nyquist Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 25 Typical Ringer Loads of 1 and 5 REN Used in US . . . . . . . . . . . . . . . 52
Figure 26 External Ringing Zero Crossing Synchronization . . . . . . . . . . . . . . . . 56
Figure 27 Balanced Ringing via SLIC-E/-E2, SLIC-S and SLIC-P. . . . . . . . . . . . 57
Figure 28 Unbalanced Ringing Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 29 Teletax Injection and Metering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 30 Soft Reversal (Example for Open Loop) . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 31 DuSLIC AC Signal Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 32 DuSLIC EDSP Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 33 Bellcore On-hook Caller ID Physical Layer Transmission . . . . . . . . . . 68
Figure 34 Line Echo Cancelling Unit - Block Diagram. . . . . . . . . . . . . . . . . . . . . 69
Figure 35 UTD Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 36 MWI Circuitry with Glow Lamp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 37 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 38 Conference Block for One DuSLIC Channel . . . . . . . . . . . . . . . . . . . . 74
Figure 39 DuSLIC Reset Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 40 Circuit Diagram for Power Consumption . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 41 SLIC-E/-E2 Power Dissipation with Switched Battery Voltage. . . . . . . 98
Figure 42 SLIC-P Power Dissipation (Switched Battery Voltage, Long Loops) . . 99
DuSLIC
List of Figures Page
Data Sheet 11 2000-07-14
Figure 43 SLIC-P Power Dissip at ion (Swit ched Bat t ery Voltage, Sh ort Loops). 101
Figure 44 Circuit Diagram for Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 45 Blockdiagram Levelmeter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 46 Single Me asurem ent Sequence (A C &DC Le velmeter) . . . . . . . . . . . 110
Figure 47 C ontinuous Meas urement Sequence (DC Levelmeter) . . . . . . . . . . . 111
Figure 48 C ontinuous Meas urement Sequence (AC Leve lm e t er) . . . . . . . . . . . 111
Figure 49 Example Resistance Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 50 Differential Resistance Measurement . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 51 Capacitance Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 52 Foreign Voltage Measurement Principle . . . . . . . . . . . . . . . . . . . . . . 130
Figure 53 AC Test Loops DuSLIC-E/-E2/-P. . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 54 DC Test Loops DuSLIC-E/-E2/-P. . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 55 AC Test Loops DuSLIC-S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 56 AC Test Loops DuSLIC-S2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 57 DC Test Loops DuSLIC-S/-S2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 58 General PCM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 59 Setting of Slopes in Register PCMC1 . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 60 Serial Microcontroller Interface Write Access . . . . . . . . . . . . . . . . . . 143
Figure 61 Serial Microcontroller Interface Read Access . . . . . . . . . . . . . . . . . . 144
Figure 62 IOM-2 I nt . Timin g f or up to 16 Voice Channels (Per 8-k Hz Frame). . 145
Figure 63 IOM-2 Interface Timing (DCL = 4096 kHz, Per 8-kHz Frame). . . . . . 146
Figure 64 IOM-2 Interface Timing (DCL = 2048 kHz, Per 8-kHz Frame). . . . . . 147
Figure 65 IOM-2 Interface Monitor Transfer Protocol . . . . . . . . . . . . . . . . . . . . 148
Figure 66 State Diagram of the SLICOFI-2x Monitor Transmitter . . . . . . . . . . . 150
Figure 67 State Diagram of the SLICOFI-2x Monitor Receiver . . . . . . . . . . . . . 151
Figure 68 Interface SLICOFI-2S/-2S2 and SLIC-S/-S2 . . . . . . . . . . . . . . . . . . . 155
Figure 69 Interface SLICOFI-2 and SLIC-E/-E2. . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 70 Interface SLICOFI-2 and SLIC-P . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 71 Ex am ple for Switchin g Betwe en Different Ring Of f s et V olt ages . . . . 208
Figure 72 Example for UTD Recognition Timing . . . . . . . . . . . . . . . . . . . . . . . . 259
Figure 73 Example for UTD Tone End Detection Timing. . . . . . . . . . . . . . . . . . 261
Figure 74 W av e f orm of P rogrammi ng Example SOP-Writ e to Chan nel 0 . . . . . 264
Figure 75 Wavefor m of P rogramm ing Example SOP R ead from Channe l 0 . . . 264
Figure 76 Waveform of Programming Example SOP Write to Channel 0 . . . . . 314
Figure 77 Wavefor m of P rogramm ing Example SOP R ead from Channe l 0 . . . 314
Figure 78 Hysteresis for Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Figure 79 Signal Definitions Transmit, Receive . . . . . . . . . . . . . . . . . . . . . . . . . 343
Figure 80 Overload Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Figure 81 Frequency Response Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Figure 82 Frequency Response Receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Figure 83 Gain Tracking Receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Figure 84 Gain Tracking Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
DuSLIC
List of Figures Page
Data Sheet 12 2000-07-14
Figure 85 Group Delay Distortion Receive and Transmit. . . . . . . . . . . . . . . . . . 353
Figure 86 Out-of-Band Signals at Analog Output (Receive) . . . . . . . . . . . . . . . 354
Figure 87 Out-of-Band Signals at Analog Input (Transmit) . . . . . . . . . . . . . . . . 355
Figure 88 Total Distortion Transmit (LX = 0 d Br) . . . . . . . . . . . . . . . . . . . . . . . . 356
Figure 89 Total Distortion Rece ive (LR = –7 dBr). . . . . . . . . . . . . . . . . . . . . . . 356
Figure 90 Total Distortion Receive (LR = 0 dBr) . . . . . . . . . . . . . . . . . . . . . . . . 357
Figure 91 MCLK / FSC-Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Figure 92 PCM Interface Timing - Single- Clocking Mode . . . . . . . . . . . . . . . . . 361
Figure 93 PCM Interface Timing – Double-Clocking Mode . . . . . . . . . . . . . . . . 362
Figure 94 Microcontroller Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Figure 95 IOM-2 Interface Ti ming – Single-Clocking Mode. . . . . . . . . . . . . . . . 365
Figure 96 IOM-2 Interface Timing – Double-Clocking Mode . . . . . . . . . . . . . . . 366
Figure 97 Ap plic ation Ci rc uit , Internal Ringing (Balanced & Unb alanced ). . . . . 368
Figure 98 Typical Overvoltage Protection for SLIC-E/-E2 and SLIC-S . . . . . . . 369
Figure 99 Typical Overvoltage Protection for SLIC-P . . . . . . . . . . . . . . . . . . . . 370
Figure 100 Application Circuit, External Unbalanced Ringing . . . . . . . . . . . . . . . 372
Figure 101 Applicat ion Circuit , E x ternal Un balance d Ringing f or Long Loops. . . 373
Figure 102 DuSLIC Layout Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
Figure 103 PEB426x (SLIC-S/-S2, SLIC-E/-E2, SLIC-P). . . . . . . . . . . . . . . . . . . 376
Figure 104 PEB 3264, PEB 3264-2, PEB 3265 (SLICOFI-2x). . . . . . . . . . . . . . . 377
DuSLIC
List of Tables Page
Data Sheet 13 2000-07-14
Table 1 DuSLIC Chip Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 2 Pin Definitions and Functions SLIC-S/-S2 and SLIC-E/-E2. . . . . . . . . 24
Table 3 Pin Definitions and Functions SLIC-P . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 4 Pin Definitions and Functions SLICOFI-2/- 2S/-2S2. . . . . . . . . . . . . . . 29
Table 5 DC Characteristic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 6 Ringing Options with SLIC-S, SLIC-E/-E2 and SLIC-P . . . . . . . . . . . . 54
Table 7 Performance Characteristic s of t he DTMF Decode r Algorithm . . . . . . 65
Table 8 FSK Modulation Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 9 MIPS Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 10 Conference Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 11 Possible Modes in PCM/µC Interface Mode . . . . . . . . . . . . . . . . . . . . 76
Table 12 Overview of DuSLIC Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 13 DuSLIC-S/-S2 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 14 DuSLIC-E/-E2 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 15 DuSLIC P Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 16 Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 17 Typical Buffer Voltage Drops (Sum) for ITRANS (ITor IR) . . . . . . . . . . 95
Table 18 Line Feed Conditions for Power Calculation of SLIC-E/-E2. . . . . . . . . 97
Table 19 SLIC-E/-E2 Typical Total Power Dissipation . . . . . . . . . . . . . . . . . . . . 97
Table 20 Line Feed Conditions for Power Calculation for SLIC-P . . . . . . . . . . . 98
Table 21 SLIC-P PEB 4266 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 22 Line Feed Conditions for Power Calculation for SLIC-P . . . . . . . . . . 100
Table 23 SLIC-P PEB 4266 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 24 SLIC-E /-E2 Balanced Ringing Power Dissipatio n (typical) . . . . . . . . 104
Table 25 SLIC-P Balanced Ringing Power Dissipation (typical). . . . . . . . . . . . 105
Table 26 SLIC-P Unbalanced Ringing Power Dissipation (typical). . . . . . . . . . 106
Table 27 Levelmeter Result Value Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 28 Selecting DC Levelmeter Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 29 KINTDC Setting Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 30 NSamples Setting Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 31 Levelmeter Results with and without Integrator Function . . . . . . . . . 115
Table 32 Selecting AC Levelmeter Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 33 KINTAC Setting Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 34 KTG Setting Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 35 Threshold Setting Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 36 Measurement Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 37 SLICOFI-2x PCM Interface Configuration . . . . . . . . . . . . . . . . . . . . . 140
Table 38 Active PCM Channel Configuration Bits . . . . . . . . . . . . . . . . . . . . . . 142
Table 39 IOM-2 Time Slot Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 40 SLIC-S/-S2 Interface Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 41 SLIC-S/-S2 Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 42 SLIC-E/-E2 Interface Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
DuSLIC
List of Tables Page
Data Sheet 14 2000-07-14
Table 43 SLIC-E/-E2 Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 44 SLIC-P Interface Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 45 SLIC-P Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 46 SLIC-P Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 47 M2, M1, M0: General Operating Mode . . . . . . . . . . . . . . . . . . . . . . . 164
Table 48 Valid DTMF Keys (Bit DTMF-KEY4 = 1) . . . . . . . . . . . . . . . . . . . . . . 178
Table 49 DTMF Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Table 50 Typical Usage for the three Ring Offsets. . . . . . . . . . . . . . . . . . . . . . 208
Table 51 CRAM Coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Table 52 CRAM Programming Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Table 53 Ranges of GDTMF [d B] dependent on “e” . . . . . . . . . . . . . . . . . . . . . 237
Table 54 Example for DTMF-GAIN Calculation . . . . . . . . . . . . . . . . . . . . . . . . 237
Table 55 Characteristic Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Table 56 Characteristic Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Table 57 Characteristic Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Table 58 Ranges of GLEC-XI [ dB] Dependent on “e” . . . . . . . . . . . . . . . . . . . . 243
Table 59 Example for LEC-GAIN-XI Calculation . . . . . . . . . . . . . . . . . . . . . . . 243
Table 60 Ranges of GLEC-RI [dB] Dependent on “e” . . . . . . . . . . . . . . . . . . . . 244
Table 61 Example for LEC-GAIN-RI Calculation . . . . . . . . . . . . . . . . . . . . . . . 244
Table 62 Ranges of GLE C-X0[dB] D ependent on “e”. . . . . . . . . . . . . . . . . . . . 245
Table 63 Example for LEC-GAIN-X0 Calculation . . . . . . . . . . . . . . . . . . . . . . . 245
Table 64 Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Table 65 UTD Inband/Outband Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Table 66 M2, M1, M0: General Operating Mode . . . . . . . . . . . . . . . . . . . . . . . 262
Table 67 DTMF Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Table 68 CRAM Coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Table 69 CRAM Programming Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Table 70 M2, M1, M0: General Operating Mode . . . . . . . . . . . . . . . . . . . . . . . 312
Table 71 PI Calculation PEB 4264/-2 (SLIC-S/-S2) . . . . . . . . . . . . . . . . . . . . . 322
Table 72 PG Calculation PEB 4264/-2 (SLIC-S/-S2) . . . . . . . . . . . . . . . . . . . . . 323
Table 73 PO Calculation PEB 4264/-2 (SLIC-S/-S2) . . . . . . . . . . . . . . . . . . . . . 323
Table 74 PI Calculation PEB 4265/-2 (SLIC-E/-E2) . . . . . . . . . . . . . . . . . . . . . 328
Table 75 PG Calculation PEB 4265/-2 (SLIC-E/-E2) . . . . . . . . . . . . . . . . . . . . . 329
Table 76 PO Calculation PEB 4265/-2 (SLIC-E/-E2) . . . . . . . . . . . . . . . . . . . . . 329
Table 77 PI Calculation PEB 4266 (SLIC-P). . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Table 78 PG Calculation PEB 4266 (SLIC-P) . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Table 79 PO Calculation PEB 4266 (SLIC-P) . . . . . . . . . . . . . . . . . . . . . . . . . 337
Table 80 AC Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Table 81 Group Delay Absolute Values: Signal level 0 dBm0 . . . . . . . . . . . . . 353
Table 82 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
Table 83 Ext ernal Component s in Application Circ uit for DuSLIC-E/- E2/-S/ -P. 371
DuSLIC
Data Sheet 15 2000-07-14
Preliminary
Preface
This document describes the DuSLIC chip set comprising a programmable dual channel
SLICOFI-2x codec and two single channel high-voltage SLIC chips. For more DuSLIC
related documents please se e our webp age at http://w w w.infineon.com / dus lic .
To sim plify m at ters, the following s ynony m s are used:
SLICOFI-2x: Synonym used f or all codec v ers ions SLIC OFI-2/-2S/ -2S2
SLIC: Synonym used for all SLIC versions SLIC-S /-S2 , SL IC-E/-E2 and
SLIC-P
Organization of this Document
This D at a Shee t is div ided into eleve n chapters. It is org anized as f ollows:
•Chapter 1, Overview
A general description of the product, its key features, and some typical applications.
•Chapter 2, Pin Descriptions
•Chapter 3, Functional Description
The ma in f unctio ns are presen ted following a functional block diagram.
•Chapter 4, Opera t ional Descript ion
A brief description of the three operating modes: power down, active and ringing (plus
signal m onitoring tec hniques ) .
•Chapter 5, Interfaces
Connection information including standard IOM-2 and PCM interface timing frames
and pins .
•Chapter 6, SLICOFI-2x co mma nd st ructu r e
A general brief about the SLICOFI-2x command structure.
•Chapt er 7, Electrical Characteris t ics
Parameters, symbols and limit values.
•Chapter 8, Application Circuits
Exter nal comp onents and layout recom mendation s. Illustratio ns of balanced ringin g,
unba lanced rin ging and pr ot ec t i on circ uit s.
•Chapter 9, Package Outlines
Illustrations and dimensions of th e package outlines.
•Chapter 10, Glossary
List of abbrev iation s and descrip tion of symbols.
•Chapter 11, Index
DuSLIC
Overview
Data Sheet 16 2000-07-14
Preliminary
1 Overview
DuSLIC is a chip set, comprising one dual channel SLICOFI-2x codec and two single
chann el SLIC chips. It is a highly flexible codec/SLIC solution for a n analog line circuit
and is widely programmable via software. Users can now serve different markets with a
single hardware design that meets all different standards worldwide.
The interconnections between the single channel high-voltage SLIC and the dual
channel SLICOFI-2x codec (advanced CMOS process) ensure a seamless fit. This
guarantees maximum transmission performance with minimum line circuit component
count.
DuSLIC family chip sets:
Table 1 DuSLIC Chip Sets
Chip Set DuSLIC-S DuSLIC-S2 DuSLIC-E DuSLIC-E2 DuSLIC-P
Marketing Name SLICOFI-2S/
SLIC-S SLICOFI-2S2/
SLIC-S2 SLICOFI-2/
SLIC-E SLICOFI-2/
SLIC-E2 SLICOFI-2/
SLIC-P
Product ID PEB 3264/
PEB 4264 PEB 3264-2/
PEB 4264-21)
1) Nevertheless marked on the chip as PEB 4264
PEB 3265/
PEB 4265 PEB 3265/
PEB 4265-22)
2) Nevertheless marked on the chip as PEB 4265
PEB 3265/
PEB 4266
Longitudinal
Balance 53 dB 60 dB 53 dB 60 dB 53 dB
Maxim u m D C
feeding 32 mA 50 mA 32 mA 50 mA 32 mA
Neg. Battery
Voltages 22222/3
Add. positive
Voltages 11110
Internal Ringing 45 Vrms no 85 Vrms 85 Vrms 85 Vrms bal.,
50 Vrms unbal.
ITDF3)
3) Integrated Test and Diagnosis Functions
no no yes yes yes
TTX 1.2 Vrms no 2.5 Vrms 2.5 Vrms 2.5 Vrms
Add-Ons4)
4) The add-on functions are DTMF detection, Caller I D generation, Message Waiting lamp support, Three Party
Conferencing, Universal Tone Detection (UTD), Line Echo Cancellation (LEC) and Sleep Mode.
no no yes yes yes
DuSLIC
Overview
Data Sheet 17 2000-07-14
Preliminary
The DuSLIC family comprises five different chip sets (see Table 1):
–Three basic DuSLIC c hip sets optimize d for different appl ications:
DuSLIC-S (Standard),
DuSLIC-E (Enhanced),
DuSLIC-P (Power Management).
–Two differ ent perfo rm ance version s of the b as i c DuSLIC -E and DuSLIC -S ch ip s ets:
DuSLI C -E2 (usin g SLIC-E 2 PEB 4265-2 c om pared to D uSLIC-E)
DuSLI C-S2 (us ing SLIC -S2 PEB 4264- 2 and codec PEB 3264 -2)
The co dec dev ices SLIC OFI-2, SL ICOFI- 2S and SLIC OFI-2S2 are manuf actured in an
advanced 0.35 µm 3.3 V CMOS proc ess.
The SLIC-E, SLIC-E2 and SLIC-P devices are manufactured in Infineon Technologies
robu st and well proven 170 V Smart Powe r techno logy.
The SLIC-S and SLIC-S2 devices are manufactured in Infineon Technologies 90 V
Smart Power techno logy and off er further cost reduction.
Usag e o f C odec´s and SLIC´s:
DuSLIC-E, DuSLIC-E2 and DuSLIC-P comprise the same SLICOFI-2 codec with full
EDSP (Enhanced Digital Signal Processor) features like DTMF detection, Caller ID
generation , Uni v e r sal Tone Dete cti on (UTD ) an d Line Echo Cancel lation.
DuSLIC-S comprise s the SLICOFI-2S cod e c without EDSP features.
DuSLIC-S2 comprises the SLICOFI-2S2 codec based on the SLICOFI-2S but without
Telet ax m etering (T T X) and internal ringing capability.
The respective SLIC variant for each chip set featured in Table 1 has been selected
acco rding to per forman ce and application requirem ents:
SLIC-S/-S2 (PEB 4264 / PEB 4264-2) and SLIC-E/-E2 (PEB 4265 / PEB 4265-2) are
optimized for access network requirements, while the power management SLIC-P
(PEB 4266) is an enhanced version for extremely power-sensitive applications or for
appl ications w here inte rnal unbalanced rin ging is requ ired.
DuSLIC Architecture
Unlike traditional designs, DuSLIC splits the SLIC function into high-voltage SLIC
functions and low-voltage SLIC functions.
The low-voltage functions are handled in the SLICOFI-2x device. The partitioning of the
functions is shown in Figure 1.
For further information see Chapter 3.1.
DuSLIC
Overview
Data Sheet 18 2000-07-14
Preliminary
Figure 1 DuSLIC Chip Set
SLICOFI-2x
HV SLIC Functions LV SLIC Functions Codec Filter Functions
Vol t age feed ing Programmable DC fe eding Filtering
Transversal curre nt Ri ng gene rat io n PCM compression /e xpansion
sensing Supe rv i sion Programmable gain
Longi t udina l current Teletax generat i on Programmable frequency
sensing Teletax not ch filt er Impedance matching
Overload protection Ring trip detection Hy brid balance
Battery switching Ground key detection DTMF generation
Ring amplificati on Hook switch detecti on DTMF detecti on
On-hoo k transmission FSK generation (Call er I D)
Polarity reversal Linear mode support
(16-bit uncompressed voice data)
IOM-2 and PCM/µC interface
Integrat ed Test and Diagnosis Funct ions (IDTF)
Line Echo Cancelling (LEC)
Universal Tone D etecti on (UTD)
Three-party conferencing
Message waiting lamp support
SLIC
SLIC IOM
®
-2
PCM
µC
ezm14034.wmf
P-MQFP-64-1,-2
P-DSO-20-5
Dual Channel Subscriber Line Interface Circuit
DuSLIC PEB 3264/-2
PEB 3265
PEB 4264/-2
PEB 4265/-2
PEB 4266
Data Sheet 19 2000-07-14
Version 1.2
Type Package
PEB 3264/-2 P-MQFP-64-1
PEB 4264/-2 P-DSO-20-5
PEB 3265 P-MQFP-64-1
PEB 4265/-2 P-DSO-20-5
PEB 4266 P-DSO-20-5
1.1 Features
•Internal unbalanced/ba lanced ringing capability up
to 85 Vrms
•Program mable Teletax (TTX) genera t ion
•Programm ab le battery feeding with capa bility for
driving longer loops
•Fully program m able dual-chann el codec
•Grou nd/ loop start signaling
•Polarity re versal
•Integ rat ed Test and Diag nosis Func t ions (IDT F)
•On-h ook t r ansmiss i on
•Integrated DTMF generator
•Integrated DTMF decoder
•Integrated Calle r ID (FSK) generator
•Integ r at ed fax/modem detec tion (Universal Tone
Detection (UTD))
•Integrated Line Echo Cancellation unit (LEC)
•Optimized filter structure for modem transmission
•Three-party confer encing (in PCM/µC mode)
•Message waiting lamp su pport (PBX )
•Power o pt im iz ed architec t ure
•Power management capability (integrated battery switches)
•8 and 16 kHz PC M T r ansmiss i on
•Specification in accord ance with
ITU-T Recom m endatio n Q. 552 for int erface Z and applic able LSSGR
DuSLIC
Overview
Data Sheet 20 2000-07-14
Preliminary
1.2 Logic Symbols
Figure 2 Logic Symbol SLIC-S / SLIC-S2 / SLIC-E / SLIC-E2
Figure 3 Logic Symbol SLIC-P
TIP
RING
VDD
AGND
VHR
BGND
VBATL
VBATH
VCMS
CEXT
IT
IL
ACP
ACN
DCP
DCN
C1
C2
PEB 4264
PEB 4264-2
PEB 4265
PEB 4265-2
Tip/Ring
interface
Power
supply Logic
control
AC & DC
feeding
Line
current
ezm14094.emf
TIP
RING
VCMS
CEXT
IT
IL
ACP
ACN
DCP
DCN
C1
C2
C3
PEB 4266
Tip/Ring
interface
Logic
control
AC & DC
feeding
Line
current
VDD
AGND
BGND
VBATL
VBATH
VBATR
Power
supply
ezm14095.emf
DuSLIC
Overview
Data Sheet 21 2000-07-14
Preliminary
Figure 4 Logic Symbol SLICOFI-2/-2S/-2S2
ITA
ITB
ITACA
ITACB
ILA
ILB
VCMITA
VCMITB
DCPA
DCPB
DCNA
DCNB
CDCPA
CDCNA
CDCPB
CDCNB
VCM
VCMS
ACPA
ACPB
ACNA
ACNB
C1A
C1B
C2A
C2B
IO1A
IO2A
IO3A
IO4A
IO1B
IO2B
IO3B
IO4B
PEB 3265
PEB 3264
PEB 3264-2
PCM/IOM-2
FSC
DCL/PCLK
DD/DRB
DU/DOUT
TS0/DIN
TS1/DCLK
TS2/CS
INT
MCLK
SEL24/DRA
DXA
DXB
TCA
TCB
RSYNC
RESET
TEST
CREF
SELCLK
VDDA
VDDB
GNDA
GNDB
VDDR
GNDR
VDDD
GNDD
VDDPLL
GNDPLL
Power
supply
Logic
control
IOM-2 interf ace
µC-interface
PCM
interface
Line
current
DC
loop
AC
loop
I/O
feeding
ezm14096.emf
DuSLIC
Overview
Data Sheet 22 2000-07-14
Preliminary
1.3 Typical Applications
•Digital Loop C arrier (DLC)
•Wireless Local Loop
•Fiber in the Loop
•Private Branch E xchange
•Intelligent NT (Network Termination) for ISDN
•ISDN T erminal Adapte r
•Central Office
•Cable Modem
•XDSL NT
•Router
DuSLIC
Pin Descriptions
Data Sheet 23 2000-07-14
Preliminary
2 Pin Descriptions
2.1 Pin Diagram SLIC
Figure 5 Pin Configuration SLIC-S/-S2, SLIC-E/-E2, SLIC-P (top view)
Note: The SLIC is only available in a P-DSO-20-5 package with heatsink on top. Please
note th at the p in countin g for the P-DS O-20-5 pa ckage is clock wise (top view) in
contrast to similar type packages which mostly count counterclockwise.
PEB 4264/-2
PEB 4265/-2
PEB 4266
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
IT
IL
C2
C3
DCN
ACP
VCMS VCMS
ACP
DCN
N.C.
C2
IL
IT
ACP
DCN
N.C.
C2
IL TIP
VDD
AGND AGND
VDD
TIP
AGND
VBATR
VDD
N.C.
TIP
SLIC-S/-S2 PEB 4264/-2
SLIC-E/-E2 PEB 4265/-2
SLIC -P P EB 4266
IT
C1 C1 C1
DCP DCP DCP
ACN ACN ACN
VCMS
RING RING RING
BGND BGND BGND
VHR VHR
VBATL VBATL
VBATH VBATHVBATH
N.C. N.C.
CEXT CEXT CEXT
VBATL
ezm29017.emf
DuSLIC
Pin Descriptions
Data Sheet 24 2000-07-14
Preliminary
Table 2 Pin Definitions and Functio ns SLIC-S/-S2 and SLI C-E/-E 2
Pin
No. Symbol Input (I)
Output (O) Function
1 RING I/O Subsc riber loop c onnection RING
2 TIP I/O Subs criber loop conn ec tion TIP
3 BGND Power Battery ground: TIP, RING, VBATH, VBATL and VHR refer to
this pin
4 VHR Power Aux iliary positive battery supply voltage used in rin ging
mode
5 VDD Power Positive suppl y voltage (+ 5 V), referred to AGND
6 VBA T L Power Negat iv e batter y s upply v olt age (–15 V ≥ VBATL ≥ VBATH)
7 VBA T H Power Negat iv e batter y s upply v olt age:
SLIC-S / SLIC-S2: – 20 V ≥ VBATH ≥ – 65 V
SLIC-E / SLIC-E2: – 20 V ≥ VBATH ≥ – 85 V
8N.C. –Not connected
9 AGND Power Analog ground: VDD, and all signal and control pins with the
exception of TIP and RI NG refer to AGND
10 CEXT O Out put of voltage div ider defin ing DC line potentials; an
external capacitance allows supply voltage filtering (output
resist ance abo ut 30 kΩ)
11 VCMS I Reference voltage for differential two-wire interface, typical
1.5 V
12,
13 ACN,
ACP I Differential two-wire AC input voltage; multiplied by –6 and
related to (VHI +VBI)/2, ACN appears at T IP and ACP at
RIN G output, respecti v e ly ( VHI &VBI are internal voltages)
14,
15 DCN
DCP I Differential two-wire DC input voltage; multiplied by a factor
(–30 in ACTH and ACTL mode, –60 in ACTR mode) and
related to (VHI +VBI)/2, DCN appears at TIP and DCP at
RIN G output, respecti v e ly
16 N.C. –Not connected
17 C2 I Ternary logic inpu t, contro lling the operation mode
18 C1 I/O Ternary logic input, controlling the operation mode; in case
of therm al overl oad (chip te m peratu re excee ding 165 °C)
this pin sinks a curr ent of typi cally 150 µA
DuSLIC
Pin Descriptions
Data Sheet 25 2000-07-14
Preliminary
Note: The SLIC is only available in a P-DSO-20-5 package with heatsink on top. Please
note th at the p in countin g for the P-DS O-20-5 pa ckage is clock wise (top view) in
contrast to similar type packages which mostly count counterclockwise.
19 IL O Current output : longitudinal line current sc aled dow n by a
factor of 100
20 IT O Current output representing the transversal current scaled
down by a fac to r of 5 0
Table 2 Pin Definitions and Functio ns SLIC-S/-S2 and SLI C-E/-E 2 (cont’d)
Pin
No. Symbol Input (I)
Output (O) Function
DuSLIC
Pin Descriptions
Data Sheet 26 2000-07-14
Preliminary
Table 3 Pin Definitions and Functions SLIC-P
Pin
No. Symbol Input (I)
Output (O) Function
1 RING I/O Subsc riber loop c onnection RING
2 TIP I/O Subs criber loop conn ec tion TIP
3 BGND Power Battery ground: TIP, RING, VBATH, VBATL and VBATR refer
to this pin
4N.C. –Not connected
5 VDD Power Po sitive supply v olt age (3 .1 V ≤ VDD ≤ 5.5 V),
referred to AGND
6 VBATL Power Negative battery supply voltage (– 15 V ≥ VBATL ≥ – 140 V)
7 VBA T H Power Negat iv e batter y s upply v olt age
(– 20 V ≥ VBATH ≥ – 145 V, VBATL ≥ VBATH)
8 VBATR Power Negative battery supply voltage used as on-hook voltage in
power sensitive applications with external ringing or for the
extended battery f eeding opt ion.
(– 25 V ≥ VBATR ≥ – 150 V, VBATL ≥ VBATH ≥ VBATR)
9 AGND Power Analog ground: VDD, and all signal and control pins with the
exception of TIP and RI NG refer to AGND
10 CEXT O Out put of voltage div ider defin ing DC line potentials; an
external capacitance allows supply voltage filtering (output
resist ance abo ut 30 kΩ)
11 VCMS I Reference voltage for differential two-wire interface, typical
1.5 V
12,
13 ACN,
ACP I Differential two-wire AC input voltage; multiplied by –6 and
related to VBI/2, ACN appears at TIP and AC P at RING
output, respectively (VBI is an internal voltage)
14,
15 DCN,
DCP I Differential two-wire DC input voltage; multiplied by a factor
(–30 in ACT H & AC TL mode, –60 in AC TR mode) and
related to VBI/2, DCN appea r s at TIP an d DCP at RING
output, respectively
16 C3 I Binar y logic input, controllin g the operation m ode
17 C2 I Ternary logic inpu t, contro lling the operation mode
18 C1 I/O Ternary logic input, controlling the operation mode; in case
of therm al overl oad (chip te m peratu re excee ding 165 °C)
this pin sinks a curr ent of typi cally 150 µA
DuSLIC
Pin Descriptions
Data Sheet 27 2000-07-14
Preliminary
Note: The SLIC is only available in a P-DSO-20-5 package with heatsink on top. Please
note th at the p in countin g for the P-DS O-20-5 pa ckage is clock wise (top view) in
contrast to similar type packages which mostly count counterclockwise.
19 IL O Current output : longitudinal line current sc aled dow n by a
factor of 100
20 IT O Current output representing the transversal current scaled
down by a fac to r of 5 0
Table 3 Pin Definitions and Functions SLIC-P (cont’d)
Pin
No. Symbol Input (I)
Output (O) Function
DuSLIC
Pin Descriptions
Data Sheet 28 2000-07-14
Preliminary
2.2 Pin Diagram SLICOFI-2/-2S/-2S2
Figure 6 Pin Configuration SLICOFI-2/ -2 S /-2S 2 (top view)
ezm22005.emf
PEB 3265
PEB 3264
PEB 3264-2
PCM/IOM-2
VDDPLL
GNDPLL
TCB
DXB
VDDD
DXA
TCA
GNDD
MCLK
FSC
SEL24 / DRA
DCL / PC LK
DD / DRB
DU / DOUT
INT
TS2 / CS
TS1 / DCLK
TS0 / DI N
IO4B
IO3B
IO2B
IO1B
GNDB
VDDB
ACNB
ACPB
DCNB
CDCNB
CDCPB
DCPB
C2B
C1A
ILA
ITACA
VCMITA
ITA
GNDR
VCMS
CREF
VCM
SELCLK
VCMITB
ITB
ILB
ITACB
C1B
RSYNC
RESET
TEST
IO4A
IO3A
IO2A
IO1A
GNDA
VDDA
ACNA
ACPA
DCNA
CDCNA
CDCPA
DCPA
C2A
VDDR
1
17
33
49
DuSLIC
Pin Descriptions
Data Sheet 29 2000-07-14
Preliminary
Table 4 Pin Definitions and Functions SLICOFI-2/-2S/-2S2
Pin
No. Symbol Input (I)
Output (O) Function
1 C2B O Ternary logic output for controlling the SLIC operation mode
(chann el B)
2 DCPB O Two- wire output voltage (DCP) (cha nnel B)
3 CDCPB I/O External capacitance for filtering (channel B)
4 CDCNB I/O External capacitance for filtering (channel B)
5 DCNB O Two-wire outpu t vol ta g e (DCN) (cha n nel B)
6 ACPB O Differential two-wire AC output voltage controlling the RING
pin (cha nnel B)
7 ACNB O Differe ntial tw o-w ire AC output voltage controllin g the TIP
pin (cha nnel B)
8 VDDB Pow er + 3.3 V analog sup ply voltag e (c hannel B)
9 GNDB Power Analog gr ound (cha nnel B)
10 IO1B I /O User- programmable I/O pin (cha nnel B) with relay-driving
capability. In externa l ring ing mode IO1 is used to
automatically control and drive the ring relay.
11 IO2B I /O User- programmable I/O pin (cha nnel B) with relay-driving
capability. SLICO F I-2 and SLIC-P: connected to pin C3 of
SLIC -P, w hen two supply volt ages fo r vo ic e transmi s s ion
and in ternal ringing are us ed.1)
12 IO3B I /O User-progra mmable I/ O pin (cha nnel B) with analog input
functionality
13 IO4B I /O User-progra mmable I/ O pin (cha nnel B) with analog input
functionality
14 TS0
DIN I
IPCM/IOM-2 = 0 (IOM-2 in te rface): Time slo t sel ection pin 0
PCM/IOM-2 =1 (µC interface): Data in
15 TS1
DCLK I
IPCM/IOM-2 = 0 (IOM-2 interface): Time slot selection pin 1
PCM/IOM-2 =1 (µC interface): Data clock
16 TS2
CS
I
IPCM/IOM-2 = 0 (IOM-2 interface):
Time slot selection Pin 2
PCM/IOM-2 =1 (µC interface): Chip select, low active
17 INT OPCM/IOM-2= 0 (I OM -2 interface) : not connected
PCM/IOM-2 =1 (µC interface): Interrupt pin, low active
DuSLIC
Pin Descriptions
Data Sheet 30 2000-07-14
Preliminary
18 DU
DOUT
O
O
PCM/IOM-2 = 0 (IOM-2 interface):
Data u ps tream , open drain
PCM/IOM-2 =1 (µC interface): Data out, push/pull
19 DCL
PCLK I
IPCM/IOM-2 = 0 (IOM-2 interface): Data clock
PCM/IOM-2 = 1 (PCM interface): 128 kHz to 8192 kHz
PCM clock
20 DD
DRB I
IPCM/IOM-2 = 0 (IOM-2 interface): Data downstream
PCM/IOM-2 = 1 (PCM interface): Receive data input for
PCM highw ay B
21 SEL24
DRA
I
I
PCM/IOM-2 =0 (IOM-2 interface):
SEL24 = 0: DCL = 2048 kHz selected
SEL24 = 1: DCL = 4096 kHz selected
PCM/IOM-2 =1 (PCM-interface): Receive Data input for
PCM-highway A
22 MCLK I PCM/IOM-2 = 0 (IOM -2 inte rf ac e): no t c onnect ed
PCM/IOM-2 = 1 (PCM interface): master clock when PCM/
µC interface is used, c loc k rates are 512 kHz, 1536 kHz ,
2048 kHz, 4096 kHz, 716 8 kHz, 81 92 kHz
23 FSC I Frame synchronization clock for PCM/µC or IOM-2
inte rf ac e, 8 k Hz , ident ifies th e beginni ng of the frame,
individual time s lot s are referenced to t his input signal.
24 GNDD Power Digital ground
25 VDDD Power + 3.3 V digital su pp l y volt a ge
26 TCA O Transm i t control ou tput fo r PC M highw ay A, active low
during transmission, open drain
27 DXA O Transmit data output fo r P C M highw ay A
(goes tristate when inactive)
28 DXB O Transmit data output fo r P C M highw ay B
(goes tristate when inactive)
29 TCB O Transm i t control ou tput fo r PC M highw ay B, active low
during transmission, open drain
30 GN DPLL Power D igital ground PLL
31 VD D PLL Power + 3.3 V supply v olt age PLL
Table 4 Pin Definitions and Functions SLICOFI-2/-2S/-2S2 (cont’d)
Pin
No. Symbol Input (I)
Output (O) Function
DuSLIC
Pin Descriptions
Data Sheet 31 2000-07-14
Preliminary
32 PCM/
IOM-2 IPCM/IOM-2=1: PCM/µC interface selected
PCM/IOM-2 = 0: IOM-2 interface selected
33 R SYNC I Exter nal ringing s ynchroniz at i on pin
34 RESET I Rese t pin, low active
35 TEST I Testpin for production test, has to be conne cte d to GNDD
36 I O4A I/O User- program m able I/O P in (channel A) with analog input
functionality
37 I O3A I/O User- program m able I/O P in (channel A) with analog input
functionality
38 I O2A I/O U s er-programmable I/O Pin (c hannel A) w it h relay-driving
capability. SLICO F I-2 and SLIC-P: connected to pin C3 of
SLIC -P, w hen two supply volt ages fo r vo ic e transmi s s ion
and in ternal ringing are us ed.1)
39 I O1A I/O U s er-programmable I/O Pin (c hannel A) w it h relay-driving
capability. In externa l ring ing mode IO1 is used to
automatically control and drive the ring relay.
40 GN D A Pow er Analog ground (c hannel A)
41 VD D A Power + 3.3 V analog supply voltag e (channe l A)
42 ACN A O Differential two-wire AC output voltage con tr ollin g the TIP
pin (cha nnel A)
43 ACPA O Differential two-wire AC output voltage controlling the RING
pin (cha nnel A)
44 DCNA O Two-wire output vol t a g e (DCN) (cha n nel A)
45 CDCNA I/O External capacitance for filtering (channel A)
46 CDCPA I/O External capacitance for filtering (channel A)
47 DCPA O Two- wire output volt age (DCP ) (channe l A)
48 C2A O Ternary logic output for controlling the SLIC operation mode
(chann el A)
49 C1A I/O Ter nary logic output, contro lling the SLIC op eration mode
(channel A); indicating thermal overload of SLIC if a current
of typically 150 µA is drawn ou t
50 I LA I Longitudin al c urrent inp ut (ch annel A)
51 I TA CA I T ransvers al current input (AC) (cha nnel A)
Table 4 Pin Definitions and Functions SLICOFI-2/-2S/-2S2 (cont’d)
Pin
No. Symbol Input (I)
Output (O) Function
DuSLIC
Pin Descriptions
Data Sheet 32 2000-07-14
Preliminary
52 ITA I Transversal current input (AC + DC) (channel A)
53 VCMIT A I Reference pin for t rans./l ong. cu rrent sensing (ch annel A)
54 VD D R Power + 3. 3 V analog s upply volt age (bias )
55 GN D R Power Analog ground (bi as )
56 VCMS O Refer ence vol tage f or differ entia l two-wi re inte rface, typica l
1.5 V
57 VCM O Reference voltage for inp ut pins IT, IL, ITAC
58 CREF I/O An external c apacitor of 68 nF has to be connecte d t o
GNDR
59 SELCLK I Master clock select. Should be set to GND (internal master
clock generation). For test purposes, external master clock
gene rat i on can be selec t ed (SELCLK = 1). In this ca se a
clock of nom inal 32. 768 Mhz wit h a jitter time of less than
1 n s has to b e applied to the MCLK pin.
60 VCMITB I Reference pi n for tra nsversa l/lo ngitu di n al current sensing
(chann el B)
61 ITB I Transversal current input (AC + DC) (channel B)
62 I TA CB I T ransvers al current input (AC) (cha nnel B)
63 I LB I Longitudin al c urrent inp ut (ch annel B)
64 C1B I/O Ter nary logic output, contro lling the SLIC op eration mode
(channel B);
indicat ing therm al overlo ad of SLIC if a current of typically
150 µA is drawn out
1) If SLIC-P is selected, IO2 cannot be controlled by the user, but is utilized by the SLICOFI-2 to control the C3
pin of SLIC-P.
Table 4 Pin Definitions and Functions SLICOFI-2/-2S/-2S2 (cont’d)
Pin
No. Symbol Input (I)
Output (O) Function
DuSLIC
Functional Description
Data Sheet 33 2000-07-14
Preliminary
3 Functional Description
3.1 Functional Overview
3.1.1 Basic Functions available for all DuSLIC Chip Sets
The functions described in this chapter are integrated in all DuSLIC chip sets (see
Figure 7 for DuSLIC-S/-S2 and Figure 8 for DuSLIC-E/-E2/-P).
All BO R SC HT func tions are i nt egrated :
•Battery fee d
•Overv oltage protection
(realized by the robust high-voltage SLIC technology and additional circuitry)
•Ringing1)
•Signaling (supervision )
•Coding
•Hybri d for 2/4-w ire conv ersio n
•Testing
An important feature of the DuSLIC design is the fact that all the SLIC and codec
functions are programmable via the IOM-2 or PCM/µC-interface of the dual channel
SLICOFI-2x device :
•DC (battery) feed characteristics
•AC imp edance matching
•Transmi t gain
•Receiv e gain
•Hybri d balance
•Frequency res ponse in tr ansmit and receive direction
•Ring frequency an d am plitude1)
•Hook thre sh ol ds
•TTX modes2)
Because signal processing within the SLICOFI-2x is completely digital, it is possible to
adapt to the requirements listed above by simply updating the coefficients that control
DSP processing of all data. This means, for example, that changing impedance
matching or hybrid balance requires no hardware modifications. A single hardware is
now capa ble of me eting the requirements fo r differe n t ma rkets. The digi tal nature of the
filters an d gain stages also assu res high reliability, no drifts (over temperature o r time)
and minimal variations between different lines.
1) For DuSLIC-S2 chip set external ringing is supported
2) Not available with DuSLIC-S2 chip set
DuSLIC
Functional Description
Data Sheet 34 2000-07-14
Preliminary
The characteristics for the two voice channels within SLICOFI-2x can be programmed
independently of each other. The DuSLICOS software is provided to automate
calculation of coefficients to match different requirements. DuSLICOS also verifies the
calculated coefficients.
3.1.2 Additional Functions available for DuSLIC-E/-E2/-P Chip Sets
The f ollow ing lin e circ uit f unctio ns a re integ rated on ly in the DuS LIC -E/-E 2/-P ch ip s ets
(see Figure 8):
•Teletax metering
For pulse metering, a 12/16 kHz sinusoidal metering burst has to be transmitted. The
DuSLIC chip set generates the metering signal internally and has an integrated notch
filter.
•DTMF
DuSLIC has an integrated DTMF generator comprising two tone generators and a DTMF
decode r . The decode r is able to monitor the tra nsmit or re ceive path for valid ton e pairs
and o ut puts th e c orresponding digital code for each D T MF tone pair.
•Caller I D Fre quency Shift Keyin g (F SK) Modu lat or
DuSLIC has an integrated FSK modulator capable of sending Caller ID information. The
Caller I D modula tor c omplies w ith all re quireme nts of ITU -T reco mmend ation V. 23 and
Bell 202.
•LEC (Line Echo Cancellation)
DuSLIC co nt ain s an ad apt iv e li ne e cho ca nc ell ati on un it for the ca ncel la tio n of ne a r end
echos (up to 8 ms c anc elable echo dela y time).
•UTD (Universal Tone Detection)
DuSLIC has an integrate d Universal Tone Detection unit to detect specia l tones in the
receive or transmit path (e.g. fax or modem tones).
DuSLIC
Functional Description
Data Sheet 35 2000-07-14
Preliminary
Figure 7 Line Circuit Functions included in the DuSLIC-S/-S2
Figure 8 Line Circuit Functions included in the DuSLIC-E/-E2/-P
ezm22020.emf
V
BAT
/V
H
switch Control
Logic
TIP
RING
Current
Sensor &
Offhook
Detection
Gain
SLIC-S/-S2
V
BAT
/V
H
switch Control
Logic
TIP
RING
Current
Sensor &
Offhook
Detection
Gain
ADC
DAC Hardware
Filters Programmable
Filters and Gain A-Law
or µ-Law
PCM /
IOM-2
Inte rfa c e
ADC
DAC Hardware
Filters Programmable
Filters and Gain A-Law
or µ-Law
Prefilter
Postfilter
Prefilter
Postfilter
Controller
PCM
Interface
IOM-2
Interface
Serial µC
Interface
SLICOFI-2S/-2S2
Channel A
Channel B
SLIC-S/-S2
Interface
Control
both
SLICOFI-2S/-2S2
channels
one
SLICOFI-2S/-2S2
channel
Ringing*
TTX
Metering*
Supervision
Digital Signal
Processing (DSP) Compander
DCCTL
* not available with SLICOFI-2S2
SLIC-S/-S2
ezm22007.emf
V
BAT
/V
H
switch Control
Logic
TIP
RING
Current
Sensor &
Offhook
Detection
Gain
SLIC-E/-E2/-P
V
BAT
/V
H
switch Control
Logic
TIP
RING
Current
Sensor &
Offhook
Detection
Gain
ADC
DAC Hardware
Filters Programmable
Filters and Gain A-Law
or µ-Law
PCM /
IOM-2
Interface
ADC
DAC Hardware
Filters Programmable
Filters and Gain A-Law
or µ-Law
Prefilter
Postfilter
Prefilter
Postfilter
Controller
PCM
Interface
IOM-2
Interface
Serial µC
Interface
SLICOFI-2
Channel A
Channel B
SLIC-E/-E2/-P
Interface
Control
both
SLICOFI-2
channels
one
SLICOFI-2
channel
Ringing
Level
Metering TTX
Metering CID
Generation DTMFSupervision
Digital Signal
Processing (DSP) Compander
DCCTL
UTD
LEC
SLIC-E/-E2/-P
DuSLIC
Functional Description
Data Sheet 36 2000-07-14
Preliminary
3.2 Block Diagra ms
Figure 9, Figure 10 and Figure 11 show t he basic func tional blocks a nd ci rcuits for al l
SLIC versions of the DuSLIC chip set.
Figure 9 Block Diagram SLIC-S/-S2 (PEB 4264/-2)
TIP
RING
I
T
I
R
BIAS Logic
Current
Sensor
(I
R
+ I
T
) / 100
60k
60k
CEXT
ACP
C1
VHR
VBATH
(Sub)
PEB 4264/-2
(I
R
- I
T
) / 200
VHI
VHI
VHI
DCP
DCN
ACN
Off-hook VH
Switch
+
+
-
-
SymFi
VDD (+5V)
VBI
VBAT
Switch
VBATL
VBI
C2
IT
BGND
IL
10k
2k
2k
10k
2k
2k
2k
VCMS
(I
RO
+ I
TO
) / 10
5k
BGND
PDRHL
PDRH
PDRHL
PDRH
5k
I
TO
I
RO
AGND
S1, S2 closed:
ACTR, HIT,
HIR
S1
S2
ezm29012.emf
DuSLIC
Functional Description
Data Sheet 37 2000-07-14
Preliminary
Figure 10 Block Diagram SLIC-E /-E2 (PEB 4265/-2)
ezm20002.emf
TIP
RING
I
T
I
R
BIAS Logic
Current
Sensor
(I
R
+ I
T
) / 100
60k
60k
CEXT
ACP
C1
VHR
VBATH
(Sub)
PEB 4265/-2
(I
R
- I
T
) / 200
VHI
VHI
VHI
DCP
DCN
ACN
Off-
hook
VH
Switch
+
+
-
-
SymFi
VDD (+5V)
VBI
VBAT
Switch
VBATL
VBI
C2
IT
BGND
IL
10k
2k
2k
10k
2k
2k
2k
VCMS
(I
RO
+ I
TO
) / 10
5k
BGND
PDRHL
PDRH
PDRHL
PDRH
5k
I
TO
I
RO
AGND
S1, S2 c lo sed:
ACTR, HIT,
HIR, HIRT
S1
S2
DuSLIC
Functional Description
Data Sheet 38 2000-07-14
Preliminary
Figure 11 Block Diagram SLIC-P (PEB 4266)
RING
I
T
I
R
BIAS
Current
sensor
(I
R
+ I
T
) / 100 IT
60k
60k
CEXT
ACP
C1
(I
R
- I
T
) / 200
BGND
DCP
DCN
ACN
Off-hook
IL
+
+
-
-
SymFi
AGND VDD(+5V)
Battery
switch VBI
VBI
BGND
PEB 4266
C3
VCMS
TIP
10k
2k
2k
10k
2k
2k
2k
C2
5k
BGND
PDRR
PDRRL
PDRH
PDRHL
PDRR
PDRRL
5k
(I
R0
+ I
T0
) / 10
VBATR
(SUB)
VBATH
VBATL
Logic
PDRH
PDRHL
I
T0
I
R0
S1, S2 closed:
ACTR, ROT,
ROR, HIT,
HIR, HIRT
S1
S2
ezm21002.emf
DuSLIC
Functional Description
Data Sheet 39 2000-07-14
Preliminary
Figure 12 shows the internal block structure of all SLICOFI-2x codec versions available.
The Enhanced Digital Signal Processor (EDSP) realizing the add-on funtions1) is only
inte grated in the SLIC OF I - 2 (PEB 3265) device.
Figu re 12 Block Dia g ram SLIC OF I-2/-2 S/ -2S2 (PEB 3265, PEB 3 264/-2)
1) The add-on functions are DTMF detection, Caller I D generation, Message Waiting lamp support, Three Party
Conferencing, Universal Tone Detection (UTD), Line Echo Cancellation (LEC) and Sleep Mode.
ezm22021.emf
DBUS
GNDA GNDD GNDRGNDPLLVDDA VDDD VDDRVDDPLL CREF
PCM/IOM-2
RESET
Super-
vision
Prefi
Pofi
ADC
DAC
+
ILA
ITA
ITACA
VCMITA
ACNA
ACPA
DCNA
DCPA
CDCNA CDCPA
C1A
C2A
HW-Fi
HW-Fi
IMa
DSP
CRAM
CONTR
µC
PCM
IOM-2
COMPAND
ILB
ITB
ITACB
VCMITB
ACNB
ACPB
DCNB
DCPB
C1B
C2B
CDCNB CDCPB
PCM / µC
Interface
Channel A
HV
Interf.
Super-
vision
Prefi
Pofi
ADC
DAC
+
HW-Fi
HW-Fi
IMa
Channel B
HV
Interf.
EDSP
IO1A IO2A IO3A IO4A IO1B IO2B IO3B IO4B
VCM VCMS
PEB 3265 / PEB 3264 / PEB 3264-2
PEB 3265 only
IOM-2
Interface
or
DuSLIC
Functional Description
Data Sheet 40 2000-07-14
Preliminary
3.3 DC Feeding
DC feeding with the DuSLIC is fully programmable by using the software coefficients
depi ct ed in Table 5 on Page 45.
Figure 13 shows the signal pat hs for DC feeding bet ween th e SLIC and SLICOFI-2x:
Figure 13 Signal Pa ths – DC Feeding
ACP
DCPB
DCNB
DCP
DCN
SLIC
Channel A
SLICOFI-2x
PCM out
(data upstream)
PCM in
(dat a dow nstream)
DCPA
IT
IL
ITACA
ILA
ITA
VCM
VCMITA
DCNA
DCP
DCN
SLIC
Channel B
IT
IL ITACB
ILB
ITB
VCM
VCMITB
RING
TIP
RING
TIP
ACPB
ACNB
ACN
ACPA
ACNA
ACP
ACN
PCM or
IOM-2
Interface
R
ILB
R
IT1B
R
IT2B
C
ITB
R
ILA
R
IT1A
R
IT2A
C
ITA
Transmit path
Receive path
C
VCMITA
C
VCMITB
Transmit
Receive
ezm140374.emf
DuSLIC
Functional Description
Data Sheet 41 2000-07-14
Preliminary
3.3.1 DC Characteristic Feeding Zones
The DuSLIC DC feeding characteristic has three different zones: the constant current
zone, the resistive zone and the constant voltage zone. A voltage reserve VRES (see
Chapter 3.3.7) can be selected to avoid clipping the high level AC signals (e.g. TTX) and
to take into account the voltage drop of the SLIC. The DC feeding characteristic is shown
in Figure 14.
Figure 14 DC Feeding Characteris t ic
The simplified diagram shows the constant current zone as an ideal current source with
an infinite internal resistance, while the constant voltage zone is shown as an ideal
voltage source with an internal resistance of 0 Ω. For the specification of the internal
resistances see Chapter 3.3.5.
ezm14017.emf
I
TIP/RING
I
0
Constant
voltage zone
Necessary
voltage reserve V
RES
|V
BAT
|V
TIP/RING
Resistive zone
Constant
current zone
DuSLIC
Functional Description
Data Sheet 42 2000-07-14
Preliminary
3.3.2 Constant Current Zone
In the off-hook state, the feed current must usually be kept at a constant value
independent of load (see Figure 15). The SLIC senses the DC current and supplies this
information to SLICOFI-2x via the IT pin (input pin for DC control). SLICOFI-2x
compares the actual current with the programmed value and adjusts the SLIC drivers as
necessary. ITIP/RING in the con stant cur rent zone is pr ogr ammab le fro m 0 to 32 mA or 0
to 50 mA depending on the use d SLIC ver sio n.
Figure 15 Constant Current Zone
Depending on the load, the operating point is determined by the voltage VTIP/RING
betw een the T i p and Ring p ins .
The operating point is calc ulated from :
VTIP/RING =RLOAD ×ITIP/RING
where
RLOAD =RPRE +RLINE +RPHONE,OFF-HOOK
RPRE =RPROT +RSTAB (see Figure 99 on Page 370).
The lower the load resistance RLOAD, the lower the voltage between the Tip and Ring
pins. A typical value for the programmable feeding resistance in the constant current
zone is about RI=10kΩ (see Table 5).
ezm14016.emf
I
TIP/RING
I
0
V
RES
|V
BAT
|V
TIP/RING
R
LOAD
R
K12
R
I
DuSLIC
Functional Description
Data Sheet 43 2000-07-14
Preliminary
3.3.3 Resistive Zone
The pro grammable res istive zone RK12 of D uSLIC provides extra flexibility over a wide
range of applicat ions. The resis t iv e z one is used f or very long lines w here the bat t ery is
incapa ble of feeding a const ant current int o t he line.
The operating point in this case crosses from the constant current zone for
low a nd medium impedance loops to the r esistive zon e for high impeda nce loops (see
Figure 16). The resi stanc e of the zone RK12 is pro gr a mmable from RV to 1000 Ω.
Figure 16 Resistive Zone
ezm14035.emf
I
TIP/RING
I
0
V
RES
|V
BAT
|V
TIP/RING
R
LOAD
R
K12
R
I
DuSLIC
Functional Description
Data Sheet 44 2000-07-14
Preliminary
3.3.4 Constant Voltage Zone
The constant voltage zone (see Figure 17) is used in some applications to supply a
constant voltage to the line. In this case VTIP/RING is const ant and the cur rent depends
on the load between the Tip and Ring pin.
In the constant voltage zone the external resistors RPRE =RStab +RProt necessary for
stability and pro tection define the resistance RV seen at the RING and TIP wires of the
application.
The programmable range of the parameters RI, I0, IK1, VK1, RK12 and VLIM is given in
Table 5.
Figure 17 Constant Voltage Zone
ezm14036.emf
I
TIP/RING
I
0
V
RES
|V
BAT
|V
TIP/RING
R
LOAD
R
K12
V
LIM
DuSLIC
Functional Description
Data Sheet 45 2000-07-14
Preliminary
3.3.5 Programmable Voltage and Current Range of DC Characteristic
The D C charact eristic and all symb ols are shown in Figure 18.
Figure 18 DC Characteristi c
Table 5 DC Characteristi c
Symbol Programmable Range Condition
RI1.8 kΩ…40 kΩ–
I00…32 mA only for DuSLIC-S, DuSLIC-E, DuSLIC-P
0…50 mA only for DuSLIC-S2, DuSLIC-E2
IK1 0…32 mA only for DuSLIC-S, DuSLIC-E, DuSLIC-P
0…50 mA only for DuSLIC-S2, DuSLIC-E2
VK1 0…50 V –
VK1 <VLIM –IK1 ×RK12 only (VK1, IK1)
VK1 <VLIM –IK1 ×RV
VK1 >VLIM –IK1 ×RK12
(VK1, IK1) and (VK2, IK2)
RK12 RV…1000 Ω–
VLIM 0…50 V –
VLIM >VK1 +IK1 ×RK12 only (VK1, IK1)
I
TIP/RING
I
0
V
LIM
V
TIP/RING
V
K2
V
K1
I
K1
I
K2
R
I
R
K12
R
V
= R
PRE
= R
PROT
+ R
STAB
1
2
ezm22009.wmf
DuSLIC
Functional Description
Data Sheet 46 2000-07-14
Preliminary
3.3.6 SLIC Power Dissipation
The major portion of the power dissipation in the SLIC can be estimate d by the power
dissipation in the output stages. The power dissipation can be c alc ulated from:
PSLIC ≈(VBAT –VTIP/RING)×ITIP/RING
Figure 19 Power Dis si pation
For further information see Chapter 4.7.3 on Page 95.
ezm14021.emf
I
TIP/RING
I
0
|V
BAT
|V
TIP/RING
SLIC output stage
power dissipation
constant current zone
SLIC output stage
power dissipation
constant voltage zone
DuSLIC
Functional Description
Data Sheet 47 2000-07-14
Preliminary
3.3.7 Necessary Voltage Reserve
To avoid clipping AC speech signals as well as AC mete ring pulses, a voltage reserve
VRES (see Figure 14) has to be provide d.
VRES =|VBAT|–VLIM
VBAT is the selected battery voltage, which can be depending on the mode either VBATH,
VBATL, (VHR –VBATH) for SLIC-S/-S2/-E/-E2 or VBATH, VBATL, –VBATR for SLIC-P.
VRES consists of:
•Voltag e reserve of the SL IC output b uffers: this voltage drop depends on the ou tput
current through the Tip and Ring pins. For a standard output current of 25 mA, this
volta ge reserv e is a few volts (see Table 17 on Page 95).
•Volta ge re serve for AC speec h si gnals : max. si gn al amplitude (ex amp le 2 V)
•Voltage rese rv e f or AC meterin g pulses: The TT X s ignal am plitude VTTX depen ds on
loca l specification s and vari es from 0.1 Vrms to se veral Vrms at a load of 200 Ω. To
obtain VTTX = 2 Vrms at a load of 200 Ω and RPRE =50Ω=(RPRE =RPROT +RSTAB,
see Figure 99 on Page 370), 3 Vrms = 4.24 Vpeak are needed at the SLIC output .
Therefore a VRES v alue of 10.24 V must be sel ected (= 4 V (SLI C drop for pe ak curren t
of DC and speech and TTX) + 2 V (AC speech signals) + 4.24 V (TTX-signal)).
Figure 20 TTX Voltage Reserve Schematic
R
PRE
SLIC
R
PRE
200
Ω
V
TTX
ezm14032.wmf
DuSLIC
Functional Description
Data Sheet 48 2000-07-14
Preliminary
3.3.8 Extended Batte ry Feeding
If the battery voltag e is not sufficient to supply the minimu m required current through the
line even in the resistive zone, the auxiliary positive battery voltage can be used to
expand the voltage swing between Tip and Ring. With this extended supply voltage
VHR (DuSLIC -S /E) r espe ctivel y VBATR (D uSLIC-P), it is possible to supply the constant
current for long lines. Figure 21 shows the DC feeding impedances RMAX,ACTH in ACTH
mode and RMAX,ACTR in ACTR mode (for ACTH and ACTR modes see Chapter 4.1).
Figure 21 DC Feeding Chara cteris t ic s (AC TH, ACTR)
The extended feeding characteristic is determined by the feeding characteristic in normal
mode (ACTH) and an additional gain factor KB (DuSLICOS DC Control Para meter 1/3:
Addi tional Gain in active Ring) :
VLIM,ACTR = VLIM × KB
VK1,ACTR = VK1 × KB + RV × IK1 × (KB – 1) ≈= VK1 × KB
RK12,ACTR = KB × (RK12 – RV) + RV ≈ RK12 ×=KB
RI,ACTR = RI × KB/2
IK2,ACTR = IK2 × KB × (RK12 – RV)/(KB × RK12 – RV)
VK2,ACTR = VLIM,ACTR – IK2,ACTR × RV
|V
HR
– V
BATH
|
1)
|V
BATH
|
V
TIP/RING
R
MAX
I
K1
I
TIP/RING
ACTH
Normal Mode
ACTR
Extended Battery
Feeding Mode
R
MAX, ACTR
V
K1, ACT R
V
K1
R
K12, ACTR
R
K12
|V
BATR
|
2)
1)
DuSLIC-S/-E,
2)
DuSLIC-P
V
LIM
V
LIM, ACTR
ezm23019.emf
DuSLIC
Functional Description
Data Sheet 49 2000-07-14
Preliminary
3.4 AC Transmission Characteristics
SLICOFI-2x uses either an IOM-2 or a PCM digital interface. In receive direction,
SLICOFI-2x converts PCM data from the network and outputs a differential analog signal
(ACP and ACN) to the SLIC, that amplifies the signal and applies it to the subscriber line.
In transmit direction, the transversal (IT) and longitudinal (IL) currents on the line are
sensed by the SLIC and fed to the SLICOFI-2x. A capacitor separates the transversal
line current into DC (IT) and AC (ITAC) components. As ITAC is the sensed transversal
(also called metallic) current on the line, it includes both the receive and transmit
components. SLICOFI-2x separate s the receive and transmit components d igitally, via
a tra nshy brid circ uit. Figure 22 shows the signal paths for AC transmission between the
SLICs and SLICOFI-2x:
Figure 22 Signal Pa ths - AC Trans mi ssi on
The signal flow within the SLICOFI-2x for one voice channel is shown in Figure 23 by
the following schematic circuitry. With the exception of a few analog filter functions,
signal processi ng is perform ed digit ally in t he SLICOFI-2x.
ACP
DCPB
DCNB
DCP
DCN
SLIC
Channel A
SLICOFI-2x
DCPA
IT
IL
ITACA
ILA
ITA
VCM
VCMITA
DCNA
DCP
DCN
SLIC
Channel B
IT
IL
ITACB
ILB
ITB
VCM
VCMITB
RING
TIP
RING
TIP
ACPB
ACNB
ACN
ACPA
ACNA
ACP
ACN
PCM or
IOM-2
Interface
R
ILB
R
IT1B
R
IT2B
C
ITB
R
ILA
R
IT1A
R
IT2A
C
ITA
Transmit path
Receive path
C
VCMITA
C
VCMITB
PCM out
(data upstream)
PCM in
(data downstream)
Transmit
Receive
ezm140373.emf
DuSLIC
Functional Description
Data Sheet 50 2000-07-14
Preliminary
Figure 23 Signal Flow in Voice Channel (A)
3.4.1 Transmit Path
The current s ense signal (ITAC) is co nverted to a voltag e by an externa l resistor. This
voltage is first filtered by an anti-aliasing filter (pre-filter), that stops producing noise in
the voiceband from signals near the A/D sampling frequency. A/D conversion is done by
a 1-bit sigma-delta converter. The digital signal is down-sampled further and routed
through programmable gain and filter stages. The coefficients for the filter and gain
stag es can be programmed to m eet sp ecific requirem ent s . The process ed digi tal signal
goes through a compander (CMP) that converts the voice data into A-law or µ-law codes.
A time slot assignment unit outputs the voice data to the programmed time slot.
SLICOFI-2x can also operate in 16-bit linear mode for processing uncompressed voice
data. In thi s c as e , t wo time slots ar e us ed for one v o ic e channel.
3.4.2 Receive Path
The digital input signal is received via the IOM-2 or PCM interface. Expansion (EXP),
PCM low-pass filtering, frequency response correction and gain correction are
performed by the DSP. The digital data stream is up-sampled and converted to a
corres pond ing analo g sig nal. Af ter sm oothin g by po st-filter s in the SLICOFI-2x, the AC
signal is fed to the SLIC, where it is superimposed on the DC signal. The DC signal has
been processed in a separate DC path. A TTX signal, generated digitally within
SLICOFI-2x, can also be added.
ezm14026.emf
Pre-
filter
Post-
filter
+
Teletax
generator
ITAC
ACP
ACN
+Amplify
receive
Frequency
response
receive
D/A
TTX
filter A/D Amplify
transmit +Frequency
response
transmit CMP
Impedance
matching Transhybrid
filter
EXP
PCM out
PCM in
Channel A
Cha n ne l B
TG 1 TG 2
Impedance
matching
SLICOFI-2x
+
CID generation
DTMF detection
Transmit
Receive
DuSLIC
Functional Description
Data Sheet 51 2000-07-14
Preliminary
3.4.3 Impedance Matching
The SLIC outputs the voice signal to the line (receive direction) and also senses the
voice signal coming from the subscriber. The AC impedance of the SLIC and the load
imped ance nee d to be ma tch ed in orde r t o ma xi mize pow er tra ns fer a nd m inimiz e two -
wire return loss. The two-wire return loss is a measure of the impedance matching
betw een a transmiss i on line and the AC termination of Du SLIC.
Impeda nce m atchin g is d one digit ally wit hin SLICOFI-2x by providing t hree impedan ce
matching feedback loops. The loops feed the transmit signal back to the receive signal
simulating the programmed impedance through the SLIC. When calculating the
feedback filter coefficients, the external resistors between the protection network and
SLIC (RPRE =RPROT +RSTAB, see Figure 100, Page 372) have to be taken into
account. The impedance can be programmed to any appropriate real and complex
values shown in the Nyquist diagram Figure 24. This means that the device can be
adapted to requirements anywhere in the world without requiring the hardware changes
that a r e neces sary wi th convention al line card desig ns .
Figure 24 Nyquist Diagram
0
-200
-400
-600
200 400 600 800 1000 1200 1400
Re Z
L
Im Z
L
Poss ible Values
for Line Impedance
ezm22019.emf
DuSLIC
Functional Description
Data Sheet 52 2000-07-14
Preliminary
3.5 Ringing
With the 170 V technology used for the SLIC, a ringing voltage of up to 85 Vrms can be
generated on -chip without th e need for an e xternal ringing generator. The SLICOFI-2x
generates a sinusoidal ringing signal that causes less noise and cross-talk in
neighboring lines than a trapezoidal ringing signal. The ringing frequency is
programmable f rom 3 to 300 Hz.
SLIC-E/-E2, SLIC-S/-S2 and SLIC-P support different ringing methods (see
Chapter 3.5.3).
3.5.1 Ringer Load
A typical ringer load can be thought of as a resistor in series with a capacitor. Ringer
loads are usually described as a REN (Ringer Equivalence Number) value. REN is used
to describe the on-hook impedance of the terminal equipment, and is actually a
dimensionless ratio that reflects a certain load. REN definitions vary from country to
count ry. A com monly used R EN is d escrib ed in F CC pa rt 68 tha t defin es a sin gle RE N
as ei the r 5 kΩ, 7 kΩ or 8 kΩ of AC impedance at 20 Hz. The impedance of an n-multiple
REN is equivalent to parallel connection of n single RENs. In this manual, all references
to REN as sume the 7 k Ω model.
For example, a 1 REN an d 5 REN load wou l d be:
Figure 25 Typical Ringer Loads of 1 and 5 REN Used in US
3.5.2 Ring Trip
Once the subscriber has gone off-hook, the ringing signal must be removed within a
specified time, and power must start feeding to the subscriber's phone. There are two
ring trip m et hods:
DC Ring Trip Detection
Most applications with DuSLIC are using DC ring trip detection. By applying a DC offset
together with the ringing signal, a transversal DC loop current starts to flow when the
subscribe r goes off-hoo k. This DC curre nt is sensed by the SLIC and in this way used
as an off-ho ok crite rion. The SL IC supp lies this information to the SLICOFI-2x at the IT
pin. The SLICOFI-2x continuously integrates the sensed line current ITRANS over one
1 REN 5 REN
8 µF 40 µF1386
Ω
6930
Ω
ezm14024.wmf
DuSLIC
Functional Description
Data Sheet 53 2000-07-14
Preliminary
ringer period. This causes the integration result to represen t the DC component of the
ring current . If the DC c urrent ex ceeds t he programmed ring t r ip thre s hold, SLICOFI-2x
generat es an interr upt. Ring trip is reliably detec ted and rep orted within t wo ring signa l
periods. The ringing signal is switched off automatically at zero crossing by the
SLICOFI-2x. The threshold for the ring trip DC current is set internally in SLICOFI-2x,
programmed via the digital interface. The DC offset for ring trip detection can be
generated by the DuSLIC chip set and the internal ring trip function can be used, even if
an external ringing generator is used.
AC Ring Trip Detection
For short lines (< 1 kΩ loop length) and for low-power applications, the DC offset can be
avoided to reduce the battery voltage for a given ring amplitude. Ring trip detection is
done by rectifying the ring current ITRANS, integrating it over one ringer period and
comparing it to a programmable AC ring trip threshold. If the ring current exceeds the
programmed threshold the HOOK bit in register INTREG1 is set accordingly.
Most applications with DuSLIC are using DC ring trip detection, which is more reliable
than AC ring trip detection.
3.5.3 Ringing Methods
There a re two methods of ringing:
•Balanc ed ringing (bridged rin ging)
•Unbala nced ringi ng (divided ringing)
Internal balanced ringing generally offers more benefits compared to unbalanced
ringing:
•Balanced ringing produces much less longitudinal voltage, which results in a lower
amount of nois e coupled into adjacent c able pairs
•By using a dif f erential ringing sign al, low er supply v olt ages become poss ible
The phone itself cannot distinguish between balanced and unbalanced ringing. Where
unbalan ced ringing is still used , it is often simp ly a hi storical l eftover. Fo r a comparison
betw een balanc ed and unbalanced ringin g see also ANSI docum ent T1.401-1993.
Additionally, integrated ringing with the DuSLIC offers the following advantages:
•Internal ringing (no need for external ringing generator and relays)
•Reduction of board space because of much higher integration and fewer external
components
•Programmab le ringing amp litude, frequency and ringing D C offset with out hardware
changes
•Programmable ring trip thresholds
•Switching off the ringing signal at zero-crossing
DuSLIC
Functional Description
Data Sheet 54 2000-07-14
Preliminary
3.5. 4 D uSLI C Ringin g O ptions
Application requirements differ with regard to ringing amplitudes, power requirements,
loop length and loads. The DuSLIC options include three different SLICs to select the
most appropriate ringing me thods (see Table 6):
SLIC-S allows balanced ringing up to 45 Vrms and is dedicated for short loop or PBX
applications.
For SLIC -S2 only ext ernal ringing is provided.
SLIC-E/-E2 allows balanced ringing up to 85 Vrms and can therefore be used in systems
with hi gher loop impedanc e.
Table 6 Ringing Opti ons with SLIC-S, SLIC-E/-E 2 an d SLIC-P
SLIC Version/
Ringing Facility,
Battery Voltages
SLIC-S
PEB 4264 SLIC-E/-E2
PEB 4265
PEB 426 5-2
SLIC-P
PEB 4266
Internal balanced ringing
max. voltage in Vrms (sinusoidal)
with 20 VDC used for ring trip
detection
45 Vrms 85 Vrms 85 Vrms
DC voltage for balanced ringing1)
1) In most applications 20 VDC are sufficient for reliable ring trip detection. A higher DC voltage
will reduce the achievable maximum ringing voltage. For short loops 10 VDC may be sufficient.
programmable
typ. 0 …50 V programmable
typ. 0 …50 V programmable
typ. 0 …50 V
Intern al unbalanced ringing
max. voltage in Vrms (sinusoidal) NO NO 50 Vrms
DC volt age for unbalanc ed
ringing NO NO VBATR/2
Required SLI C su pply v oltages
for maximum ringing amplitude
(typically)
VDD =5V,
VBATH =–54 V,
VHR =36V
VDD =5V,
VBATH =–70 V,
VHR =80V
VDD =5V or
3.3 V,
VBATH =–70 V,
VBATR =–150 V
Number of battery voltages for
power saving 2 (VBATL &
VBATH)2 (VBATL &
VBATH)2 (when internal
ringing is used)
3 (when external
ringing is used)
DuSLIC
Functional Description
Data Sheet 55 2000-07-14
Preliminary
The low-power SLIC-P is optimized for power-critical applications (e.g. intelligent ISDN
network termination). Internal ringing can be used up to 85 Vrms balanced or 50 Vrms
unbalanced. For lowest power applications where external ringing is preferred, three
different battery voltages (VBATR, VBATH, VBATL) can be used for optimizing the power
cons um pt ion of th e application.1)
SLIC-E/-E2 and SLIC-P differ in supply voltage configuration and the ring voltages at Tip
and Ring VT and VR. External ringing is supported by both SLIC’s.
Both internal and external ringing is activated by switching the DuSLIC to ringing mode
by setting the CIDD/CIOP bits M2, M1, M0 to 101.
External Ringing Support by DuSLIC
The following settings have to be m ade:
•Enabling the use of an external ring signal generator by setting bit REXT-EN in
Register BCR2 to 1.
•A TTL compatible zero crossing signal has to be applied to the RSYNC pin of the
SLICOFI-2x (see Figure 26).
•Acti vating th e r i nging mode by settin g th e C IDD/ C IOP b i ts M2, M1, M0 to 1 01.
•Setting the DuSLIC internal ring frequency to a value according a factor of about 0.75
of the external ring f requenc y.
The ring relay is controlled by the IO1 pin (see Figure 100). Due to the high current drive
capability of the IO1 ouput, no additional relay driver is necessary.
The relay is switched:
•Synchronous to the zero crossing of the external ringing frequency
(bit ASYNCH-R in register XCR set to 0)
A ring generator delay TRING,DELAY (see DuSLICOS control parameters 2/3) can be
programmed to consider the ring relay delay TRING-RELAY,DELAY as shown in Figure 26.
•Asynchronous
(bit ASYNCH-R in register XCR set to 1)
The ring relay is switched imme diately w i t h the ring c o m m and.
1) In this case VBATR is typically used for the on-hook state, while VBATH and VBATL are used for optimized feeding
of different loop length in the off-hook state.
DuSLIC
Functional Description
Data Sheet 56 2000-07-14
Preliminary
Figure 26 External Ringing Zero Crossing Synchronization
External
Ringing Voltage
t
t
t
V
RSYNC
V
IO1
T
RING,DELAY
T
RING-RELAY,DELAY
t
V
RING
duslic_0015_zero_crossing.emf
DuSLIC
Functional Description
Data Sheet 57 2000-07-14
Preliminary
3.5.5 Internal Balanced Ringing via SLICs
SLIC-E/-E2 and SLIC-P support internal balanced ringing up toVRING,RMS =85Vrms,
SLIC -S s upport balanc ed ringing up t o VRING,RMS =45Vrms
1).
The ring ing signal is ge nerated d igit ally within SLICOFI-2x2).
Figure 27 Balanced Ringing via SLIC-E/-E2, SLIC-S and SLIC-P
In ringing m ode, th e DC feeding regulat ion lo op is no t acti ve. A program mable DC ring
offset voltage is applied to the line instead. During ring bursts, the ringing DC offset and
the ringing signal are summed digitally within SLICOFI-2x in accordance with the
programmed values. This signal is then converted to an analog signal and applied to the
SLIC. The SLIC amplifies the signal and supplies the line with ringing voltages up to
85 Vrms. In balanced ringing mode , the SLIC uses an additional su pply volta ge VHR for
SLIC-E/-E2/-S and VBATR for SLIC-P. The total supply span is now VHR –VBATH for
SLIC-E/-E2/-S and VBATR for SLIC-P.
The m aximum ringing voltage that ca n be achiev ed is:
for SLIC-E/-E2/-S : VRING,RMS =(VHR –VBATH –VDROP, RT –VDC,RING)/1.41
for SLIC-P: VRING,RMS =(–VBATR –VDROP,RT –VDC,RING)/1.41
where: VDROP,RT =VDROP,T +VDROP,R
1) In this case VRING,RMS =VRT,RMS =VRT0,RMS because of the low impedance of the SLIC output (< 1 Ω).
VRT,RMS is t he open-circuit rms voltage measured directly at pins RING and TIP at the SLIC output with ringer
load. VRT0,RMS is the rms voltage measured directly at pins RING and TIP at the SLIC output without any ringer
load. For calculation of the ringing voltage at the ringer load see the Voltage and Power Application Note and
the accompanying MS Excel Sheet for calculation.
2) SLICOFI-2S2 supports only external ringing
ezm140315.emf
V
DC,RING
v
R
v
T
V
DROP,T
V
DROP,R
V
RING,pp
= V
Tp
- V
Rp
V
BATR
BGND
SLIC-E
SLIC-E2
SLIC-S SLIC-P
V
BATH
V
HR
V
Tp
V
Rp
DuSLIC
Functional Description
Data Sheet 58 2000-07-14
Preliminary
With the DuSLIC ringing voltages up to 85 Vrms sinusoidal can be applied, but also
trapezoidal ringing can be programmed.
For a detailed application diagram of internal balanced ringing refer to the chapter on
“Application Circuits” (see Figure 97, Page 368).
3.5.6 Internal Unbalanced Ringing with SLIC-P
The internal unbalanc ed ringing together with SLIC-P can be used for ringing volt ages
up to 50 Vrms. The SLICOFI-2 integrated ringing generator is used and the ringing signal
is applied to either the Tip or Ring line. Ringing signal generation is the same as
described above for balanced ringing. Since only one line is used for ringing, technology
limits the ringing amplitude to about half the value of balanced ringing, to maximum
50 Vrms.
Figure 28 Unbalanced Ringing Signal
The above diagram shows an example with the ring line used for ringing and the Tip line
fixed at –VDROP,T which is the drop in the output buffer of the Tip line of SLIC-P (typ.
< 1 V). The ring li ne has a fixed D C volt age of VBATR/2 used for ring trip detect ion.
The m ax i m um ringing voltage is:
VRING,RMS =(–VBATR –VDROP,R,VBATR –VDROP,T)/2.82
When the called subscriber goes off-hook, a DC path is established from the Ring to the
Tip line. The DC current is recognized by the SLICOFI-2 because it monitors the IT pin.
An interrupt indicates ring trip if t he line curr ent excee ds th e program med thre shold.
The same hardware can be used for integrated balanced or unbalanced ringing. The
balanced or unbalanced modes are configured by software. The maximum achievable
amplit udes dep end on the values selected for VBATR.
V
BATR
/ 2
V
T
v
R
V
RING,p
V
DC,RING
V
DROP,R,VBATR
V
DROP,R,BGND
≈=
V
DROP,T
V
DROP,T
V
BATR
BGND
v
RING
= v
R
ezm140316.wmf
DuSLIC
Functional Description
Data Sheet 59 2000-07-14
Preliminary
In both balanced and unbalanced ringing modes, SLICOFI-2 automatically applies and
removes the ringing signal during zero-crossing. This reduces noise and cross-talk to
adjacent lines.
3.5.7 External Unbalanced Ringing
SLICOFI-2x supports external ringing for higher unbalanced ringing voltage
requirements above 85 Vrms with all SLICs. For a detailed application diagram of
unbalanced rin ging see Figure 100 and Figure 101 on Page 372 and Page 373.
Since hig h voltage s are involved, an ext ernal relay should be used to switch the RING
line off and to switch the external ringing signal together with a DC voltage to the line.
The DC voltage has to be applied for the internal ring trip detection mechanism which
oper at es for exte rnal ring ing in the s am e way as for intern al ringing.
The SLICOFI-2x has to be set to the external ringing mode by the REXT-EN bit in
register BCR2. A synchronization signal of the external ringer is applied to the
SLICOFI-2x via the RSYNC pin . The ex ternal relay is switched on or off sync hronous ly
to this signal via the IO1 pin of the SLICOFI-2x according to the actual mode of the
DuSLIC. An interrupt is generated if the DC current exceeds the programmed ring trip
threshold.
3.6 Signal ing (Supe r vis ion)
Sign aling in the subscriber loop is moni tored int ernally by the DuSLIC ch ip s e t .
Supervision is performed by sensing the longitudinal and transversal line currents on the
Ring an d Tip w ir es. Th e sc aled v alu es of th ese c ur rents ar e gener ated in t he SLI C and
fed to the SLICOFI-2x via the IT and IL pins.
Transversal line current: ITRANS =(IR+IT)/2
Longit udinal line c urrent: ILONG =(IR–IT)/2
where IR, IT are t he loop currents on the Ri ng and Tip w ires.
Off-hook Detection
Loop start signaling is the most common type of signaling. The subscriber loop is closed
by the hook switch inside the subscriber equipment.
•In Acti ve mode, the r esulting transver sal loop cur rent is sensed by th e intern al current
sensor in th e SL IC. The IT pi n of th e SL IC in dic ates the s ubscr ib er l oop cur rent t o the
SLICOFI-2x. External resistors (RIT1, RIT2, see Figure 97, Page 368) convert the
current inf ormat ion to a volta ge on the IT A (or ITB ) pin.
The analog information is first converted to a digital value. It is then filtered and
processed further which effectively suppresses line disturbances. If the result exceeds
a prog ram mable t hreshold, an interrupt is generated to indicat e of f-hook detection.
DuSLIC
Functional Description
Data Sheet 60 2000-07-14
Preliminary
•In Sleep/Power Down mode (PDRx) a similar mechanism is used. In this mode, the
internal current sensor of the SLIC is switched off to minimize power consumption.
The loop cu rrent is ther efore fed and se nsed throu gh 5 kΩ resistors integrated in the
SLIC (se e Figure 9, Figure 10, Figure 11). The information is made available on the
IT pin and inter prete d by the SLICOFI-2x.
–In Sleep mode, the analog information is fed to an analog comparator integrated in the
SLICOFI-2x who directly in dicat es off-hook.
–In Power Down mode, the SLICOFI-2x converts the analog information to a digital
value. It is then filtered and processed further which effectively suppresses line
disturbances. If the result exceeds a programmable threshold, an interrupt is
generated to indicate off-hook detection.
In applications using ground start signaling, DuSLIC can be set in the ground start mode.
In this mode, the Tip wire is switched to high impedance mode. Ring ground detection is
perform ed by t he internal cu rrent s ensor in the SL IC and tran sf erred to the SLICOFI-2x
via the IT pin.
Ground Key Detection
The scaled longitudinal current information is transferred from the SLIC via the IL pin and
the ext ernal res is t or RIL to SLICOFI-2x. This voltage is compared with a fixed threshold
value. For the specified RIL (1.6 kΩ, see application circuit Figure 97, Page 368) this
threshold corresponds to 17 mA (positive and negative). After further post-processing,
this informa tion gen erate s an inter rup t (G NDK bit in the INT RE G1 regis ter) a nd ground
key de tectio n is indicat ed.
The polarity of the longitudinal current is indicated by the GNKP bit in the INTREG1
register. Each change of the GNKP bit generates an interrupt. Both bits (GNDK, GNKP)
can be m as k e d in the M ASK regis t er.
The post-processing is performed to guarantee ground key detection, even if longitudinal
AC currents with frequencies of 162/3, 50 or 60 Hz are superimposed. The time delay
betw een t rigg eri ng th e g round ke y f unct ion an d re gist ering th e g round ke y int err upt wi ll
in most cases (f= 50 Hz, 60 H z) be les s than 40 ms.
For lon gitudinal DC sig nals, t he block ing period can be p rogram med by the DUP value
in register IOCT L3. DC signals with le ss du ration will not b e detected . The DUP time is
equi valent t o the ha lf of the cy cle time for the low est fre quency for AC su ppres sion (fo r
values s ee Page 189).
In Power Down mode, the SLIC’s interna l current sens ors are switche d off and ground
key detection is disabled.
DuSLIC
Functional Description
Data Sheet 61 2000-07-14
Preliminary
3.7 Metering
There are two dif ferent me tering method s :
•Mete ring by sinusoid al bursts w ith eithe r 12 or 16 kHz or
•Polar ity reversal of Tip and Ring.
3.7.1 Metering by 12/16 kHz Sinusoidal Bur sts
To satisfy worldwide application requirements, SLICOFI-2/-2S1) offers integrated
metering injection of either 12 or 16 kHz signals with programmable amplitudes.
SLICOFI-2/-2S also has an integrated adaptive TTX notch filter and can switch the TTX
signal to the lin e in a smooth wa y. When swit ching the signal to the line, the switching
noise is less than 1 mV. Figure 29 shows TTX bursts at certain points of the signal flow
within SLICOFI-2/-2S.
Figure 29 Teletax Injection and Metering
The integrated, adaptive TTX notch filter guarantees an attenuation of > 40 dB. No
external components for filtering TTX bursts are required.
1) Metering is not available with SLICOFI-2S2
ezm14027.emf
SLICOFI-2/-2S
A/D
D/A
D / A
TTX
Adaptive
Filter
TTX
Gen.
IM
Filter
+
SLIC-E/-E2
SLIC-S
SLIC-P
x1
-
y
ε
Receive Path
Tran smit Path
Z
L
/2
Z
L
/2
+
+
DuSLIC
Functional Description
Data Sheet 62 2000-07-14
Preliminary
3.7.2 Metering by Polarity Reversal
SLICOFI-2/-2S also supports metering by polarity reversal by changing the actual
polarity of the voltages on the TIP/RING lines. Polarity reversal is activated by switching
the REVP OL b it in r egi s ter B CR1 to one o r swit chi ng to the “Activ e with Metering” mode
by the CIDD or CIOP command (see “Operating Modes for the DuSLIC Chip Set” on
Page 78).
3.7.2 .1 Soft Re versal
Some applications require a smooth polarity reversal (soft reversal), as shown in
Figure 30. Soft reversal helps to prevent negative effects like non-required ringing. Soft
revers al is deact ivated by t he SOFT-DIS bit in register BC R 2.
Figure 30 Soft Reversal (Example for Open Loop)
STAR T: T he soft ram p start s by s etti ng t he R EVPO L bit i n r egi ster BC R1 t o 1. T he D C
characteristic is switched off.
SR-END1: At the soft reversal end one point, the DC characteristic is switched on again.
Programmable by the DuSLICOS software, e.g. ∆U/8.
SR-END2: At the soft reversal end two point, the soft ramp is switched off.
Programmable by the Du SLI C OS software, e.g. 1/ 16 ×SR-END1.
From START to SR-END2 the READY bit in register INTREG2 is set to 0 (see register
description in Chapter 6.3.1.2 for further information).
SOFT -D IS = 1 Immediate re versal is performed (hard rever sa l )
SOFT-DIS = 0 Soft reversal is performed. Transition time (time from START to SR-
END1, see Figure 30) is programm able by C R A M c oefficients,
default value 80 ms.
050 100 150 200 250
-25
-20
-15
-10
-5
0
5
10
15
20
25
t [ms]
V
TIP/RING
[V]
SR-END1
∆
U
∆
U/8 SR-END2
= 1/16*SR-END1
START
ezm14038.wmf
DuSLIC
Functional Description
Data Sheet 63 2000-07-14
Preliminary
3.8 DuSLIC Enhanced Signal Processing Capabilities
The signal processing capabilities described in this chapter are realized by an Enhanced
Digital Signal Processor (EDSP) except for DTMF generation. Each function can be
individually enabled or disabled for each DuSLIC channel. Therefore power
consumption can be reduced according to the needs of the application. For the MIPS
requirements of the different EDSP algorithms see Chapter 3.8.5.
Figure 31 shows the A C sign al path for D uSLIC with t he A DCs an d DA Cs, im pedance
matc hing loop, trans-hybrid filt er, gain s t ages and t he connectio n to the ED SP.
Figure 31 DuSLIC AC Signal Path
Figure 32 shows a closeup on the EDSP signal path shown in Figure 31 outlining signal
names and SOP commands.
Figure 32 DuSLIC EDSP Signal Path
EDSP
CMP
EXP
DTMF
LEC
AX1
HPX1
ε
CID
+
AR1
HPR1
TG
LPX
FRX
LPR
FRR
TH
AX2
HPX2
AR2
HPR2
IM3
TTXA
+
DAC
DAC
ADC
IM2
++
IM1
+
XOUT
RIN
VIN
VOUT
TTXG
ε
UTD
UTD
Switch
DuSLIC_0005_ACsignal_path.emf
CMP
UTDX
DTMF
UTDR
EXP
G
LEC
G
G
AR1
LPR
FRR
+
+
CID
TG
AX1
HPX1
LPX
FRX
TH
LEC-EN
UTDX-SUM
UTDX-SRC
UTDX-EN
DTMF-SRC
UTDR
-SUM
UTDR-EN
RIN
XOUT
S
LEC,TIN
S
SLEC,R
S
LEC,TOUT
S
SUM
G
G
DTMF
G
LEC-X0
G
LEC-XI
G
LEC-RI
S
x
S
R
LEC-OUT
LEC-EN
DTMF-EN
DuSLIC_0006_EDSPsignal_path.emf
Switch position
shown for control
bit set to 0
DuSLIC
Functional Description
Data Sheet 64 2000-07-14
Preliminary
The enh anced Sig nal Processin g Capabilitie s are availabl e only for the DuS LIC-E/-E2/
-P versions, with an exception of DTMF generation.
The D TMF generat ion is available for all D uSLIC version s .
The f unctio ns of the EDSP ar e con figure d a nd co ntrol led by PO P r egister se ttings (see
Chapter 6.2.3).
3.8.1 DTMF Generation and Detection1)
Dual T one Mult i-Fre qu ency (D TMF ) is a s ign aling sch eme us ing v oice fr eque ncy ton es
to signal dialing information. A DTMF signal is the sum of two tones, one from a low
group (697 - 941 Hz) and one from a high group (1209 - 1633 Hz), with each group
containing four individual tones. This scheme allows 16 unique combinations. Ten of
these codes represent the numbers from zero through nine on the telephone keypad, the
remaining six codes (*, #, A, B, C, D) are reserved for special signaling. The buttons are
arranged in a matrix, with the rows determining the low group tones, and the columns
determ ining the high group t one for each button.
In all SLICOFI-2x codec versions the 16 standard DTMF tone pairs can be generated
independently in each channel via two integrated tone generators. Alternatively the
frequency and the amplitude of the tone generators can be programmed individually via
the digital interface. Each tone generator can be switched on and off. The generated
DTMF tone signals meet the frequency variation tolerances specified in the ITU-T Q.23
recommendation.
Both channels (A and B) of SLICOFI-21) have a powerful built-in DTMF decoder that will
meet most national requirements. The receiver algorithm performance meets the quality
criteria for central office/exchange applications. It complies with the requirements of ITU-
T Q.24, Bellcore GR-30-CORE (TR-NWT-000506) and Deutsche Telekom network
(BAPT 223 ZV 5, Approval Specification of the Federal Office for Post and
Telecommunications, Germany).
The performance of the algorithm can be adapted according to the needs of the
application via the digital interface (detection level, twist, bandwidth and center
frequ ency of the notch fil ter).
1) DTMF Detection only available for DuSLIC-E/-E2/-P
DuSLIC
Functional Description
Data Sheet 65 2000-07-14
Preliminary
Table 7 shows the performance characteristics of the DTMF decoder algorithm:
Table 7 Performance Characteristics of the DTMF Decoder Algorithm
Characteristic Value Notes
1 Valid in put signal det ection lev el –48 to 0 dBm0 Programmable
2 Inpu t s ignal rejec t ion level –5 dB of va lid s ignal
detec tion level –
3 Positive twist accept < 8 dB Programmable
4 Neg at iv e tw is t accept < 8 dB Programma ble
5 Frequency deviation accept < ± (1.5% + 4 Hz) and
<±1.8% Related to center
frequency
6 Frequency deviation reject > ± 3% Related to center
frequency
7 DTMF noise toleranc e
(could be the sa me as 14) –12 dB dB referenced to
lowest amplitude
tone
8 Minimum tone accept duration 40 ms –
9 Maximum tone reject duration 25 ms –
10 Signaling vel o city ≥93 ms/digit –
11 Minimum int er-digit pause du rat ion 40 ms –
12 Maximum tone drop-out duration 20 ms –
13 Interference rejection
30 Hz to 480 Hz for valid DTMF
recognition
Level in frequenc y
range 30 Hz …480 Hz
≤ level of DTMF
frequency + 22 dB
dB referenced to
lowest amplitude
tone
14 Gaussian no i s e i nflue nce
Signal le vel –22 dBm0,
SNR = 23 dB
Error rate better than
1 in 10000 –
15 Pulse noise influe nc e
Impulse noise tape 201 according
to Bellcore TR-TSY-000762
Error rate better than
14 in 10000 measured with
DTMF level
–22 dBm0
Impuls e Noise
–10 dBm0 an d
–12 dBm0
DuSLIC
Functional Description
Data Sheet 66 2000-07-14
Preliminary
In the event of pauses < 20 ms:
•If the pause is followed by a tone pair with the same frequencies as before, this is
interpreted as drop-out .
•If the pause is followed by a tone pair with different frequencies and if all other
condit ions are valid, this is int e rpreted as two differ ent numbers.
DTMF decod ers can be s wi tc hed on or off indiv idually to reduce power c ons umpt ion. In
normal operation, the decoder monitors the Tip and Ring wires via the ITAC pins
(transmit path). Alternatively the decoder can be switched al so in the rece ive path. On
detec ting a valid DTMF tone pair, SLICO F I-2 generates an int e rrupt vi a the approp riate
INT pin and indic ates a ch ange o f status. T he DTMF c ode inf ormation is provide d by a
regist er w hich is read v ia t he digital in terface.
The DTMF decoder also has excellent speech-rejection capabilities and complies with
Bellco re TR-TSY-000763. The algorithm has been fully test ed with the spee ch sample
sequences in the Series-1 Digit Simulation Test Tapes for DTMF decoders from
Bellcore. The characteristics of DTMF detection can be controlled by POP registers 30h
to 39h.
3.8.2 Caller ID Generation (only DuSLIC-E/-E2/-P)
A generator to send calling line identification (Caller ID, CID) is integrated in the DuSLIC
chip s et. Caller ID is a gene ric name fo r the servic e provided by telephone utilities that
supply information like the telephone number or the name of the calling party to the
called subscriber at the start of a call. In call waiting, the Caller ID service supplies
information about a second incoming caller to a subscriber already busy with a phone
call.
In typical Caller ID (CID) systems, the coded calling number information is sent from the
central exchange to the called phone. This information can be shown on a display on the
subscriber telephone set. In this case, the Caller ID information is usually displayed
before the s ubscriber decide s to ans wer the incom ing cal l. If th e line is connec ted to a
computer, caller information can be used to search in databases and additional services
can be off ered.
There a re two me thods use d for send ing CID inform ation de pendi ng on the app lication
and country-specific requirements:
•Caller I D generatio n us ing DTMF s ignaling (s ee Chapter 3.8.1)
•Caller I D generatio n us ing FSK
DuSLIC contains D TMF gener ation units and FSK g eneration u nits which ca n be used
for bot h c hannels s i m ultaneously.
The characteristics of the Caller ID generation circuitry can be controlled by POP
registers 00h, 43h to 4Ah.
DuSLIC
Functional Description
Data Sheet 67 2000-07-14
Preliminary
DuSLIC FSK Generation
Different countries use different standards to send Caller ID information. The DuSLIC
chip set is compatible with the widely used standards Bellcore GR-30-CORE, British
Telecom (BT) SIN227, SIN242 or the UK Cable Communications Association (CCA)
specification TW/P&E/312. Continuous phase binary frequency shift keying (FSK)
modulation is used for coding which is compatible with BELL 202 (see Table 8) and
ITU-T V.23, the most common standards. SLICOFI-2 can be easily adapted to these
requirements by programming via the microcontroller interface. Coefficient sets are
provided for the m ost com m o n standards.
The Caller ID data of the calling party can be tra nsferr ed via the microc ontroller interf ace
into a SL ICO F I-2 buffer register. The SLICOFI-2 w ill start sen ding the FSK signal when
the CIS-EN bit is set and the CID-data buffer is filled up to CIS-BRS plus 1 byte. The data
transf er i nt o the buf fe r re gist er i s ha ndl ed b y a SLICO FI-2 inte rrup t sign al . Call er d at a is
transferred fr om the buf f er vi a the inte rface pi n s to th e SLIC-E /- E2/-P and fed to the Ti p
and Ring wires . The Calle r ID data byte s from CID -data buf f er are sent LSB first.
DuSLIC offers two different levels of framing:
•A basic low-level framing mode
All the data necessary to implement the FSK data stream – including channel
seizure, mark sequence and framing for the data packet or checksum – has to be
config ured by firm ware. S LICOFI-2 transmi ts the dat a stream in the s ame orde r in
which the data is written to the buffer register.
•A high level framing mode
The number of channel seizure and mark bits can be programmed and are
automatically sent by the DuSLIC. Only the data packet information has to be written
into the CID buffer. Start and Stop bits are automatically inserted by the SLICOFI-2.
The example below shows signaling of CID on-hook data transmission in accordance
with Bellcore specifications. The Caller ID information applied on Tip and Ring is sent
during the period bet ween the f irst and sec ond ring bu rst.
Table 8 FSK Modulation Characteristics
Characte ri stic ITU- T V.23 Bell 202
Mark (Logic 1) 1300 ± 3 Hz 1 200 ± 3 Hz
Space (Logic 0) 2100 ± 3 Hz 2200 ± 3 Hz
Modulation FSK
Transmi ssion rate 1200 ± 6 ba ud
Data format Seria l binary asynchro nous
DuSLIC
Functional Description
Data Sheet 68 2000-07-14
Preliminary
Figure 33 Bellcore On-hook Caller ID Physical Layer Transmission
Bellcor e On-hook Cal ler ID Physical Layer Transmi ssi on
First Ring Burst Channel Seizure Mark Da ta Packet Second Ring
Burst
ABC D EFG
More
Parameter
Messages
More
Parameter
Bytes
Message
Type Message
Length
1
Parameter
Type Parameter
Length Parameter
Byte Checksum
Parameter Messag e
Parameter Header Parameter Body
Message He ade r Message Body
Message
1 Message length equals the number of bytes to follow in the message body, excluding the checksum.
A: 0.2 - 3 second ring burst
B: 0.5 - 1.5 seconds between first ring burst and start of data transmission
C: 300 alternating mark and space bits
D: 180 mark bits
C + D + E = 2.9 to 3.7 seconds
F:
≥
200ms
G: 1.8 - 3 secon d ring burst
ezm14014.wmf
DuSLIC
Functional Description
Data Sheet 69 2000-07-14
Preliminary
3.8.3 Line Echo Cancelling (LEC) (only DuSLIC-E/-E2/-P)
The DuSLIC contains an adaptive line echo cancellation unit for the cancellation of near
end ec hoes. With the adaptive balancing o f the LEC unit th e Transhyb rid Loss can be
improved up to a value of about 50 dB. The maximum echo cancellation time selectable
is 8 ms. The line echo cancellation unit is especially useful in combination with the DTMF
detection unit. In critical situations the performance of the DTMF detection can be
improved.
If 8 ms line echo cancellation length (LEC Length) is used, please take care about the
MIPS requirem ent s des c r ibed in Chapter 3.8.5.
The DuSLIC line echo canceller is compatible with applicable standards ITU-T G.165
and G .1 68. An echo canc ellation delay time of up to 8 ms can be program med.
The LEC unit consists basically of an FIR filter, a shadow FIR filter, and a coefficient
adap t ion mech anism between thes e tw o filters as shown in Figure 34.
Figure 34 Line Ec ho C ancelling Unit - Block Diagra m
The adaption proc ess i s controlled by t he three param eters PowLECR (Power Detection
Level Receive), DeltaPLEC (Delta Power) and DeltaQ (Delta Quality) (“POP Command”
on Page 228). Adaptation tak es place only if bo th of the following cond itions ho ld:
1. SLEC,R >Pow
LECR
2. SLEC,R –SLEC,TIN >DeltaP
LEC
With the first condition, adaptation to small signals can be avoided. The second condition
avoids adaptation during double talk. The parameter DeltaPLEC represents the echo loss
provid ed by external c irc uit ry .
Shadow
FIR
Filter
Copy
Coeff. FIR
Filter
Adapt
Coeff.
S
LEC,R
S
LEC, TIN
S
LEC, TOUT
DuSLIC_0004_LECunit.emf
DuSLIC
Functional Description
Data Sheet 70 2000-07-14
Preliminary
If the ada ptation o f th e sha do w fi lte r is p erfor med bett er than th e ada ption of the act ual
filter by a value of more than D eltaQ then the shado w filter coefficients w ill be copie d to
the actua l fil te r.
At the start of an adaption process the coefficients of the LEC unit can be reset to default
initial v alues or set to t he old coe ff ic ient values. Th e c oef f i c ients may also b e frozen .
3.8.4 Universal Tone Detection (UTD) (only DuSLIC-E/-E2/-P)
Each channel of the DuSLIC has two Universal Tone Detection units which can be used
to detect special tones in the receive and transmit paths, especially fax or modem tones
(e.g. , se e the modem start up sequence de s c ribed in re commendatio n ITU-T V. 8).
This allows the use of modem-optimized filter for V.34 and V.90 connections. If the
DuSLIC UTD detects that a modem connection is about to be established, the optimized
filter coefficients for the modem connection can be downloaded before the modem
connection is set up. With this mechanism implemented in the DuSLIC chip set, the
optim um mod em transmi s s ion rate c an always be achi ev ed.
Figure 35 shows the functio nal block d iagram of the UTD unit:
Figure 35 UTD Functional Block Diagram
Initially, the input signal is filtered by a programmable band-pass (center frequency fC
and bandwidth fBW). Both the in-band signal (upper path) and the out-of-band signal
(lower path) are determined, and the absolute value is calculated. Both signals are
furthermore filtered by a limiter and a low-pass. All signal samples (absolute values)
below a programmable limit LevN (Noise Level) are set to zero and all other signal
samples are diminished by LevN. The purpose of this limiter is to increase noise
robu st ness . Aft e r t he limite r st ages both signals are filtered by a fixe d low-pass.
The evaluation logic block determines whether a tone interval or silence interval is
detec ted and an interrupt is generated for the recei ve or trans mit pa th.
EZM14061
S
UTD
Programmable
Band-pass
|x|
|x|
+
+
Limit
Limit
LP
LP
Evaluation
Logic
DuSLIC
Functional Description
Data Sheet 71 2000-07-14
Preliminary
The UTDR-OK respectively UTDX-OK bit (register INTREG3) will be set if both of the
following conditions hold for a time span of at least RTIME without breaks longer than
RBRKTime occurring:
1. T h e in-band signal exceeds a progr am mable level LevS.
2. T he difference of the in-band and the out-of-band sign al lev els exceeds Delt aUTD.
The UTDR-OK respectively UTDX-OK bit will be reset if at least one of these conditions
is violated for a timespan of at least ETime during which the violation does not cease for
at least EBRKTime.
The times ETIME a nd EBRKTim e help to r educe the effects o f s poradi c dropo ut s.
If the bandwidth parameter is programmed to a negative value, the UTD unit can be used
for the detection of silenc e int ervals in the who le frequency ra nge.
The D uSLIC U T D unit is com pat ible wit h ITU-T G. 164.
The UTD is resistant to a modulation with 15 Hz sinusoidal signals and a phase reversal
but is not able to detect the 15 Hz modulation and the phase reversal.
3.8.5 MIPS Requirements for EDSP Capabilities
Table 9 show s the MIPS requirements fo r each al gorithm us ing the EDSP:
The m aximum capability of the EDS P is 32 MIPS .
Example:
•All devic es enabled and LE C Lengt h = 8 ms (LEN = 64):
→ 33.32 MIPS tot al comput ing load ex c eeding th e 32 MIPS limit!
•All devic es enabled and LEC Length = 4 ms (LEN = 32):
→ 31.272 MIP S total c om puting load with in the 32 MIPS limit.
•4 x UTD, 2 x DTMF Receiver and 2 x LEC (8 ms) enabled:
→ 29.85 MIPS total computing load within the 32 MIPS limit.
Table 9 MIPS Requirements
Algorithm / Device Used MIPS Conditions
Caller ID Sen der
(CIS) 1.736*nCIS nCIS = 0...2
Universal Tone
Detection (UTD) 1.208*nUTD nUTD= 0...4, transmit and
rece iv e f or two ch annels
DTMF R ec eiv er 6.296*nDTMF nDTMF= 0...2
Line Echo Canceller
(LEC) (3.448 + 0.032*LEN)*nLEC nLEC= 0...2
LEN - see Page 239
Operati n g System 1.432 –
DuSLIC
Functional Description
Data Sheet 72 2000-07-14
Preliminary
3.9 Message Waiting Indication (only DuSLIC-E/-E2/-P)
Message Waiting Indication (MWI) is usually performed using a glow lamp at the
subs criber phone. Curren t doe s not f low th rough a g low lamp un til the voltag e reach es
a threshold value above approximately 80 V. At this threshold, the neon gas in the lamp
will start to glow. When the voltage is reduced, the current falls under a certain threshold
and the lamp glow is extinguished. DuSLIC has high-voltage SLIC technology (170 V)
whic h is able to activ at e t he glow lamp witho ut any ex t ernal com ponents.
The hardware circuitry is shown in Figure 36 below. The figure shows a typical
telephone circuit with the hook switch in the on-hook mode, together with the
imped anc es for the o n-hook (ZR) and off-h ook (Z L) m od es.
Figure 36 MWI Circui try with Glow Lamp
The glow lamp circuit also requires a resistor (RMW) and a lamp (MW La mp) built into the
phon e. When ac tivated, the lamp must be a ble to either blink or rema in on constantly .
In non -DuSLIC s olutions the telephone ringer may respond b riefly if the s ignal slope is
too steep, which is not desirable. DuSLIC’s integrated ramp generator can be
programmed to increase the voltage slowly, to ensure activating the lamp and not the
ringer.
ezm14066.wmf
Z
L
R
MW
Z
R
Z
L
AC Impedance
Z
R
Ringer Impedance
R
MW
Pre Resistor Message Waiting
MW
Lamp
DuSLIC
Functional Description
Data Sheet 73 2000-07-14
Preliminary
To activate the Message Waiting function of DuSLIC the following steps should be
performed:
•Activating Ring Pau se mod e by setting the M0-M2 bits
•Select Ring Offset RO2 by set t ing the bit s in register LMCR3
•Enable t he ramp ge nerator by s et tin g bit R AM P-EN in re gis t er LM C R2
•Switching between the Ring Offsets RO3 and RO2 in register LMCR3 will flash the
lamp on a nd of f (see Figure 37).
The values for RO2 and RO3 have to be programmed in the CRAM to the according
values before so that the lamp will flash on and of f .
Figure 37 Timing Diagram
ezm14067.emf
V
TR
RNG-O FF SET Bi ts
V
HIGH
V
LOW
Power Down
State Ring Pause
State t
t
Lamp On
Lamp Off
10
11
RO 3
RO 2
DuSLIC
Functional Description
Data Sheet 74 2000-07-14
Preliminary
3.10 Three-party Conferencing (only DuSLIC-E/-E2/-P)
Each DuSLIC channel has a three-party conferencing facility implemented which consist
of four PCM registers, adders and gain stages in the microprogram and the
corres ponding control reg is te rs (s ee Figure 38).
This facility is available in PCM/µC mode only. The PCM control registers PCMR1
through PCMR4 and PCMX1 through PCMX4 control the timeslot assignment and PCM
highway selection, while the bits PCMX-EN, CONF-EN and CONFX-EN in the BCR3
register control the behavior of the conferencing facility and the PCM line drivers (see
Figure 38). A programmable gain stage G is able to adjust the gain of the conferencing
voice data (B, C, D, S) in a range of –6 dB to + 3 dB to prevent an overload of the sum
signals.
Figure 38 Confe re nc e Bloc k fo r One DuSLIC Channel
Note: G … Gain Stage (Gain Factor) set in CRAM coefficients,
X1 - X4 … PCM transmit channe ls,
R1 - R4 … PCM rece iv e chan nels,
A, B, C, D, S … e x amples for voice dat a on PCM channels X1 - X4, R1 - R4
ezm14069.emf
+
+
+
Subscriber S
PCM Highways
G
G
G
CONF_EN = 0
10
CONF_EN = 0
0
1
Subscribers
PCM channel X4 X1 X3 X2 A
R1
B
R2 C
R3
D
R4
-
--
X2 = (R3 –R4)*G
X3 = (R2 –R4)*G
X4 = (R2 –R3)*G
DuSLIC
Functional Description
Data Sheet 75 2000-07-14
Preliminary
3.10.1 Conferencing Modes
(see also “Control of the Active PCM Channels” on Page 142)
•PCM Off
After a reset, or in power down there is no communication via the PCM highways. Also
when selecting new timeslots it is recommended to switch off the PCM line drivers by
setting the control bits to zero.
•PCM Active
This is the normal operating mode without conferencing. Only the channels R1 and
X1 ar e in us e, an d voice d ata a re t rans ferre d from s ub scr iber A t o anal og s ubs cribe r
S and vice versa.
•Exte rn al Con f er en ce
In this mode the SLICOFI-2 acts as a server for a three-party conference of
subscribers B, C and D which may be controlled by any device connected to the PCM
highways. The SLICOFI-2 channel itself can remain in power down mode to lower
power consumption.
•External Co n fer en ce + PCM A ctive
Like in Exte rnal Co nferen ce mod e any extern al three- party c onfer ence is suppor ted.
At the same time an internal phone call is active using the channels R1 an d X1.
•Intern al C onference
If the ana log subscr iber S is one of th e conference partners, t he internal con ference
mode will be selected. The partners ( B, C) d o n ot ne ed any confere nce facility, since
the SLI C OFI-2 pe rf orm s all required func tions fo r them as w ell.
Table 10 Conferenc e Modes
Configuration
Registers Receive Channels Transmit Channels
Mode PCMX
-EN CONF
-EN CONFX
-EN R1 R2 R3 R4 X1 X2 X3 X4 Subscriber
S
PCM Off 000 ––––off off off off off
PCM Active 100 A–––Soff off off A
External
Conference 001 –B C D off G (C+ D ) G (B+ D ) G (B+C ) off
External
Conference +
PCM Active
1 0 1 A B C D S G (C+D) G (B+D) G (B+C) A
Internal
Conference 010 –BC–off G (C+S) G (B+S) off G (B+C)
DuSLIC
Functional Description
Data Sheet 76 2000-07-14
Preliminary
3.11 16 kHz Mode on PCM Highway
In addition to the standard 8 kHz transmission PCM interface modes, there are also two
16 kHz modes for high dat a t ransm is sion perf orm ance.
Table 11 shows the configuration of PCM channels for the different PCM interface
modes.
The configuration bits PCM16K and LIN (in the BCR3 register) are used to select the
following PCM interface modes:
•PCM Mode
Normal mode used for voice transmission via channels R1 and X1 (receive and
transmit). The PCM input channels R2, R3 and R4 are always available for use in
different conference configurations. The status of the PCM output channels depends on
the conf erence mode config uration.
Table 11 Possible Modes in PCM/µC Interface Mode 1)
1) see “Control of the Active PCM Channels” on Page 142
Config. Bits Receive PCM Channels Transmit PCM Channels
PCM16K LIN R1 R1L2)
2) Time slot R 1 + 1
R2 R3 R4 X1 X1L3)
3) Time slot X 1 + 1
X2 X3 X4
PCM Mode
00A
4)
4) Empty cells in the table mark unused data in the PCM receive channels and switched-off line drivers in the PCM
transmit channels
BCDS–depends on
conference mode
LIN Mode
0 1 A-HB A-LB B C D S-HB S-LB depends on
conference mode
PCM 16 M o d e
10DS1––DS2 –DS1 ––DS2 –
LIN16 Mode
11DS1-
HB –DS1-
LB DS2-
HB DS2-
LB DS1-
HB –DS1-
LB DS2-
HB DS2-
LB
DuSLIC
Functional Description
Data Sheet 77 2000-07-14
Preliminary
•LIN Mode
Similar to the PCM mode, but for 16 bit linear data at 8 kHz sample rate via the PCM
channels R1 , R1 L (receiv e) and X1, X1L (transmit).
•PCM16 Mode
Mode for higher data transmission rate of PCM encoded data using a 16 kHz sample
rate (onl y in PCM/ µC Interface mode with the PCMX-EN bit in the BCR3 register set to
one). In this mode the channels R1, R3 (X1, X3) are used to receive (transmit) two
samp les of data (DS 1, DS2) in eac h 8 kHz fra me.
•LIN16 Mode
Like the PCM16 mode for 16 kHz sample rate but for linear data. Channels R1 to R4 (X1
to X4) are used for receiv ing (tran s mittin g) t he high a nd low bytes of th e two line a r data
sample s DS1 an d DS2 .
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 78 2000-07-14
Preliminary
4 Operational Description
4.1 Operating Modes for the DuSLIC Chip Set
Table 12 Overview of DuSLIC Operating Modes
SLICOFI-2x
Mode SLIC Type CIDD/
CIOP1) Additional Bits used
(Note 2))
SLIC-S/
SLIC-S2 SLIC-E/
SLIC-E2 SLIC-P M2 M1 M0
Sleep (SL) –PDRHPDRH111SLEEP-EN=1
PDRR111SLEEP-EN=1, ACTR=1
Power Down
Resistive (PDR) PDRHPDRHPDRH111SLEEP-EN=0
PDRR111SLEEP-EN=0, ACTR=1
Power Down
High Impedance
(PDH)
PDH PDH PDH 000–
Active High
(ACTH) ACTH ACTH ACTH 0 1 0 –
Active Low
(ACTL) ACTLACTLACTL010ACTL=1
Active Ring
(ACTR) ACTRACTRACTR010ACTR=1
Ringing (R ing) ACTR3) ACTR ACTR 1 0 1 –
––ROT 101HIT=1
––ROR 101HIR=1
Active wi th HIT HIT HIT HIT 0
01
10
0HIT = 1
HIT = 1, ACTR = 0
Active wi th HIR HIR HIR HIR 0
01
10
0HIR = 0
HIR = 0, ACTR = 0
Active with Ring
to Ground ROT 010HIT=1, ACTR=1
Active with Tip
to Ground ROR 010HIR=1, ACTR=1
HIRT –HIRT HIRT 010HIR=1, HIT=1
Active with
Metering ACTx3)
4) ACTx4) ACTx4) 1 1 0 TTX-DIS to select Reverse
Polarity or TTX Metering
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 79 2000-07-14
Preliminary
Sleep (SL) (only available with DuSLIC-E/-E2/-P)
The SLICOFI-2 is able to go into a sleep mode with minimal power dissipation. In this
mode off-hook detection is performed without any checks on spikes or glitches. The
sleep mode can be used for either channel, but for the most effective power saving, both
channels should be set to this mode. Note that this requires the following:
•Due to the lac k of persis tence checki ng only non-nois y lines should us e t his feat ure.
•If both channe ls are se t to th e sleep mode, w aki n g up t ake s abou t 1.25 ms, since th e
on-ch i p PLL is also switch ed off. Therefore it is also po ssi ble to switch off al l exter n al
clocks. In this time no programming or other functionality is available. The off-hook
event is indicated either by setting the interrupt pin to active mode if the PCM/µC
interface mod e is selected or by pullin g down the DU pin if IOM -2 interface is used.
•If only one channel is set to sleep mode, persistence checking and off-hook indication
is performed as in any other mode, but the off-hook level is fixed to 2 mA at the
subscriber line. No special wake-up is needed if only one channel is in sleep mode. A
simpl e m ode chang e ends th e sleep m ode.
•A sleeping SLI C OF I-2 is wok en up if th e C S pin is drawn to low level when the PCM /
µC interface is used or the MX bit is set to zero when the IOM-2 interface is used. Note
that no programming is possible until the SLICOFI-2 wakes up. In IOM-2 mode the
identification request can be used as a wake-up signal since this command is
indep endent of the internal cl ock. In the PCM/µC mo de it is reco mmend ed to s et the
CS to 0 for only one clock cycle.
•After a wake up from Sleep mode the SLICOFI-2 enters the PDRH or PDRR mode.
To re-e nter the Sl eep mod e it is neces sary to perform a mo de chan ge to any Active
mode at least at one channel f irst.
Ground Start HIT HIT HIT 1
10
00
0–
ACTR = 0
Ring Pause ACTR3) ACTR ACTR
ROR
ROT
001HIR = 1
HIT = 1
1) CIDD = Data Downstream Command/Indication Channel Byte (IOM-2 interface)
CIOP = Command/Indication Operation
For further information see “SLICOFI-2x Command Structure and Programming” on Page 163.
2) if not otherwise stated in the table, the bits ACTL, ACTR, HIT, HIR have to be set to 0.
3) only for SLIC-S
4) ACTx means ACTH, ACTL or ACTR.
Table 12 Overview of DuSLIC Operating Modes (cont’d)
SLICOFI-2x
Mode SLIC Type CIDD/
CIOP1) Additional Bits used
(Note 2))
SLIC-S/
SLIC-S2 SLIC-E/
SLIC-E2 SLIC-P M2 M1 M0
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 80 2000-07-14
Preliminary
Power Down Resistive (PDRH for SLIC-E/-E2/-S/-S2 and PDRR for SLIC-P)
The P ower Do wn Res istive mo de is the standard mode for none-act ive lines . Off-ho ok
is detected by a current value fed to the DSP, compared with a programmable threshold,
and filtered by a data upstream persistence checker. The power management SLIC-P
can be switched to a Power Down Resistive High or a Power Down Resistive Ring mode.
HIRT
The line drivers in the SLIC-E/-E2/-P are shut down and no resistors are switched to the
line. Off-hook de tection is not possible. In HIRT mode the S LICOFI-2 is able to measure
the inp ut of fse t of th e cur r ent sensors.
Power Down High Impedance (PDH)
In Pow er Down High Im pedance mode , the SLIC is tot ally powered dow n. No off-ho ok
sens ing can be pe rf orm ed. This mode can be use d for emer gency shu tdown o f a lin e.
Active High (ACTH)
A regular call can be performed, voice and metering pulses can be transferred via the
telep ho n e li n e and the DC loop is opera tiona l in th e Active Hi gh mode .
Active Low (ACTL)
The Active Low mode is similar to the Active High mode. The only difference is that the
SLIC uses a lower battery voltage, VBATL (bit ACTL = 1 ).
Active Ring (ACTR)
The Active Ring mode is different for the SLIC-E/- E2 and the SLIC-P. The SLIC-E/-E2
uses the additional positive voltage VHR for extended feeding and the SLIC-P will switch
to the negative battery voltage VBATR.
Ringing
If the SLICOFI-2x is switch ed t o Ringing mo de, t he SLIC is s w itc hed to ACTR mode.
With the SLIC-P connected to the SLICOFI-2, the Ring on Ring (ROR) mode allows
unba lanc ed inte rna l rin ging on th e Ring wire. The T ip w ire is s et t o batt er y grou nd . The
Ring signal w ill be superimposed by VBATR/2.
The R ing on Ti p (R OT ) mode is the equiv a lent to the ROR mode.
Active with HIT
This is a testing mode where the Tip wire is set to a high impedance mode. It is used for
special line testing. It is only available in an active mode of the SLICOFI-2x to enable all
necessary test features.
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 81 2000-07-14
Preliminary
Active with HIR
HIR is similar to HIT but with th e R i ng wire set to hig h im pedance.
Active with Metering
Any available active mode can be used for metering either with Reverse Polarity or with
TTX Signals.
Ground Start
The T ip wire is s et to h igh imped ance in Groun d Start mo de. An y curre nt drawn on the
Ring w ire leads t o a s ignal on IT, indicati ng off- hook.
Ring Pause
The Ring burst is switched off in Ring Pause, but the SLIC remains in the specified mode
and the off-hook recognition behave s like in ring ing mode (Ring Trip) .
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 82 2000-07-14
Preliminary
4.2 Operating Modes for the DuSLIC-S/-S2 Chip Set
Table 13 DuSLIC-S/-S2 Oper a ti ng Modes
SL ICO FI-2S /
SLICOFI-2S2
Mode
SLIC-S /
SLIC-S2
Mode
SLIC-S/-S2
Internal
Supply
Voltages
(+/–)[
VHI/VBI]
System
Functionality Active
Circuits Tip/Ring
Output
Voltage
PDH PDH Open/VBATH None None High
Impedance
Power Down
Resistive PDRH Open/VBATH Off-hook
detect as i n
active mode
(DSP)
Off-hook,
DC transmit
path
VBGND/VBATH
(via 5 kΩ)
–PDRHL
1) Open/VBATH Off-hook
detect as i n
active mode
(DSP)
Off-hook,
DC transmit
path
VBGND/VBATH
(via 5 kΩ)
Active Low
(ACTL) ACTL VBGND/VBATL Voice an d/or
TTX
transmission
Buffer,
Sensor,
DC + AC
loop, TTX
generator
(optional)
Tip: (VBATL +
VAC +VDC)/2
Ring: ( VBATL –
VAC –VDC)/2
Active High
(ACTH) ACTH VBGND/VBATH Voic e and/or
TTX
transmission
Buffer,
Sensor,
DC + AC
loop, TTX
generator
(optional)
Tip: (VBATH +
VAC +VDC)/2
Ring: (VBATH –
VAC –VDC)/2
Active Ring
(ACTR) ACTR VHR/VBATH Voice and/or
TTX
transmission
Buffer,
Sensor,
DC + AC
loop, TTX-
generator
(optional)
Tip: (+ VBATH
+VHR +VAC
+VDC)/2
Ring: (+ VBATH
+VHR –VAC
–VDC)/2
Ringing
(Ring) ACTR VHR/VBATH Balanced ring
signal fe ed
(incl. DC
offset)
Buffer,
Sensor, DC
loop, Ring
generator
Tip: (VBATH +
VHR +VDC)/2
Ring: (VBATH +
VHR –VDC)/2
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 83 2000-07-14
Preliminary
Ring Pause ACTR VHR/VBATH DC offset
feed Buffer,
Sensor, DC
loop, Ramp
generator
Tip: (VBATH +
VHR +VDC)/2
Ring: (VBATH +
VHR –VDC)/2
Active with
HIR HIR VHR/VBATH E.g. line test
(Tip) Tip Buffer,
Sensor,
DC + AC loop
Tip: (VBATH +
VHR +VAC +
VDC)/2
Ring: High
impedance
Active with
HIT HIT VHR/VBATH E.g. line test
(Ring) Ring Buffer,
Sensor,
DC + AC loop
Ring: (VBATH +
VHR –VAC –
VDC)/2
Tip: High
impedance
1) load ext. C for switching from PDRH to ACTH in on-hook mode
VAC …Tip/Ring AC Voltage
VDC …Tip/Ring DC Voltage
Table 13 DuSLIC-S/-S2 Oper a ti ng Modes (cont’d)
SL ICO FI-2S /
SLICOFI-2S2
Mode
SLIC-S /
SLIC-S2
Mode
SLIC-S/-S2
Internal
Supply
Voltages
(+/–)[
VHI/VBI]
System
Functionality Active
Circuits Tip/Ring
Output
Voltage
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 84 2000-07-14
Preliminary
4.3 Operating Modes for the DuSLIC-E/-E2 Chip Set
Table 14 DuSLIC-E/-E2 Oper a ti ng Modes
SLICOFI-2
Mode SLIC-E /
SLIC-E2
Mode
SLIC-E/-E2
Internal
Supply
Voltages
(+/–)[
VHI/VBI]
System
Functionality Active
Circuits Tip/Ring
Output
Voltage
PDH PDH Open/VBATH None None High
Impedance
Sleep PDRH Open/VBATH Off-hook
dete c t v ia off-
hook
comparator
Off-hook,
Analog
comparator
VBGND/VBATH
(via 5 kΩ)
Power
Down
Resistive
PDRH Open/VBATH Off-hook
dete c t as in
active mode
(DSP)
Off-hook, DC
transmit path VBGND/VBATH
(via 5 kΩ)
–PDRHL1) Open/VBATH Off-hook
dete c t as in
active mode
(DSP)
Off-hook, DC
transmit path VBGND/VBATH
(via 5 kΩ)
Active Low
(ACTL) ACTL VBGND/VBATL Voice an d/ or
TTX
transmission
Buffer, Sensor,
DC + AC loop,
TTX generator
(optional)
Tip: (VBATL +
VAC +VDC)/2
Ring: (VBATL –
VAC –VDC)/2
Active
High
(ACTH)
ACTH VBGND/VBATH Voice and/ or
TTX
transmission
Buffer, Sensor,
DC + AC loop,
TTX generator
(optional)
Tip: (VBATH +
VAC +VDC)/2
Ring: (VBATH –
VAC –VDC)/2
Active
Ring
(ACTR)
ACTR VHR/VBATH Voice and/or
TTX
transmission
Buffer, Sensor,
DC + AC loop,
TTX generator
(optional)
Tip:
(+ VBATH + VHR
+VAC + VDC)/2
Ring:
(+ VBATH + VHR
–VAC –VDC)/2
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 85 2000-07-14
Preliminary
Ringing
(Ring) ACTR VHR/VBATH Balanced
Ring signal
feed (inc l. DC
offset)
Buffer, Sensor,
DC loop, Ring
generator
Tip: (VBATH +
VHR +VDC)/2
Ring: (VBATH +
VHR –VDC)/2
Ring
Pause ACTR VHR/VBATH DC offset feed Buffer, Senso r,
DC loop, ramp
generator
Tip: (VBATH +
VHR +VDC)/2
Ring: (VBATH +
VHR –VDC)/2
HIRT HIRT VHR/VBATH E.g. sens or
offset
calibration
Sensor, DC
transmit path High
Impedance
Active with
HIR HIR VHR/VBATH E.g. line test
(Tip) Tip-Buffer,
Sensor,
DC + AC loop
Tip: (VBATH +
VHR +VAC +
VDC)/2
Ring: High
impedance
Active with
HIT HIT VHR/VBATH E.g. line test
(Ring) Ring-Buffer,
Sensor,
DC + AC loop
Ring: (VBATH +
VHR –VAC –
VDC)/2
Tip: High
impedance
1) load ext. C for switching from PDRH to ACTH in on-hook mode
VAC …Tip/Ring AC Voltage
VDC …Tip/Ring DC Voltage
Table 14 DuSLIC-E/-E2 Oper a ti ng Modes (cont’d)
SLICOFI-2
Mode SLIC-E /
SLIC-E2
Mode
SLIC-E/-E2
Internal
Supply
Voltages
(+/–)[
VHI/VBI]
System
Functionality Active
Circuits Tip/Ring
Output
Voltage
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 86 2000-07-14
Preliminary
4.4 Operating Modes for the DuSLIC-P Chip Set
Table 15 DuSLIC P Operating Modes
SLICOFI-2
Mode SLIC-P
Mode SLIC-P
Internal
Supply
Voltages
[VBI]
System
Functionality Active Circuits Tip/Ring
Output
Voltage
PDH PDH VBATR None None High
impedance
Sleep PDRH VBATH Off-hook detect
via off-hoo k
comparator
Off-hook,
Analog
comparator
VBGND/VBATH
(via 5 kΩ)
Sleep PDRR VBATR Off-hook detect
via off-hoo k
comparator
Off-hook,
Analog
comparator
VBGND/VBATR
(via 5 kΩ)
Power
Down
Resistive
PDRH VBATH Off-hook detect
as in active
mode (DSP)
Off-hook, DC
transmit pa th VBGND/VBATH
(via 5 kΩ)
–PDRHL1) VBATH Off-hook detect
as in active
mode (DSP)
Off-hook, DC
transmit pa th VBGND/VBATH
(via 5 kΩ)
–PDRR VBATR Off-hook detect
as in active
mode (DSP)
Off-hook,
Analog
comparator
VBGND/VBATR
(via 5 kΩ)
–PDRRL2) VBATR Off-hook detect
as in active
mode (DSP)
Off-hook, DC
transmit pa th VBGND/VBATR
(via 5 kΩ)
Active Low
(ACTL) ACTL VBATL V oic e and/or
TTX
transmission
Buffer, Se nsor,
DC + AC loop,
TTX generator
(optional)
Tip: (VBATL +
VAC +VDC)/2
Ring: ( VBATL –
VAC –VDC)/2
Active
High
(ACTH)
ACTH VBATH Voice and/or
TTX
transmission
Buffer, Se nsor,
DC + AC loop,
TTX generator
(optional)
Tip: (VBATH +
VAC +VDC)/2
Ring: ( VBATH –
VAC –VDC)/2
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 87 2000-07-14
Preliminary
Active
Ring
(ACTR)
ACTR VBATR Voice and/or
TTX
transmission
Buffer, Se nsor,
DC + AC loop,
TTX generator
(optional)
Tip: (VBATR +
VAC +VDC)/2
Ring: ( VBATR –
VAC –VDC)/2
Ringing
(Ring) ACTR VBATR Balanced ring
signal feed
(incl. DC
offset)
Buffer, Se nsor,
DC loop, ring
generator
Tip: (VBATR +
VDC)/2
Ring: ( VBATR –
VDC)/2
Ringing
(Ring) ROR VBATR Ring signal on
ring, Tip on
BGND
Buffer, Se nsor,
DC loop, ring
generator
Ring: (VBATR –
VDC)/2
Tip: 0 V
Ringing
(Ring) ROT VBATR Ring signal on
ring, Tip on
BGND
Buffer, Se nsor,
DC loop, ring
generator
Tip: (VBATR +
VDC)/2
Ring: 0 V
Ring
Pause ACTR,
ROR,
ROT
VBATR DC offset feed Buffer, Sensor,
DC loop, ramp
generator
Tip: (VBATR +
VDC)/2
Ring: (VBATR –
VDC)/2
HIRT HIRT VBATR E.g. sensor
offset
calibration
Sensor, DC
transmit pa th High
impedance
Active with
HIR HIR VBATR E.g. line test
(Tip) Tip-Buffer,
Sensor,
DC + AC loop
Tip: (VBATR +
VAC +VDC)/2
Ring: High
impedance
Active with
HIT HIT VBATR E.g. line test
(Ring) Ring-B uffer,
Sensor,
DC + AC loop
Ring: ( VBATR –
VAC –VDC)/2
Tip: High
impedance
1) load ext. C for switching from PDRH to ACTH in on-hook mode
2) load ext. C for switching from PDRR to ACTR in on-hook mode
Table 15 DuSLIC P Operating Modes (cont’d)
SLICOFI-2
Mode SLIC-P
Mode SLIC-P
Internal
Supply
Voltages
[VBI]
System
Functionality Active Circuits Tip/Ring
Output
Voltage
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 88 2000-07-14
Preliminary
4.5 Reset Mo de and Rese t Behav i or
4.5.1 Hardware and Power On Reset
A reset of the DuSLIC is initiated by a power-on reset or a hardware reset by setting the
signal at RESET input pin to low level for at least 4 µs1). The reset input pin has a spike
rejection which will safely suppress spikes with an duration of less than 1 µs2).
By setting the reset signal to low, the chip will be reset (see Figure 39):
•all I/O pins deactivated
•all outputs in active (e .g . DXA/DXB)
•internal PLL stopped
•internal clocks deactivated
•chip in power dow n high im pedance (PDH )
With the high going reset s ignal, the follow ing act ions take place:
•Clock detection
•PLL synchronization
•Running the re set routine
The internal reset routine will then initialize the whole chip to default condition as
described in the SOP default register setting (see Chapter 6). To run through the internal
reset routine it is necessary that all external clocks are supplied:
•µC/P C M m ode: FSC , MC LK, PCLK
•IOM-2 mode : F S C and DC L.
Without valid and stable external clock signals, the DuSLIC will not finish the reset
sequence properly.
The internal reset routine requires 12 frames (125 µs) to be finished (including PLL start
up and clock synchronization) and is setting the default values given in Table 16. The
first register access to the SLICOFI-2x may be done after the internal reset routine is
finished.
1) Maximum spike re jec tion ti me trej, max
2) Minimum spike rejection time trej,min
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 89 2000-07-14
Preliminary
Figure 39 DuSLIC Reset Sequence
t
RESET signal
t
re j
(1 to 4 µs)
S LICOF I- 2 x in te r n a l res e t r o u tine
m in. 12*125 µs = 1.5 m s
First access
to SLICOF I- 2 x
possible
Ch ip re s e t:
- all I/O pins deactivated
- a ll o utp uts in a c tiv e ( e .g . D XA/DXB)
- internal PLL stopped
- internal clocks deactivated
- chip in power down high im pedance (PDH)
duslic_0016_reset_sequence.emf
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 90 2000-07-14
Preliminary
4.5.2 Software Reset
When performing a software reset, the DuSLIC is running the reset routine and sets the
default settings of the configuration registers. The software reset can be performed
individ ually for eac h c hannel.
Table 16 Default Values
DC
IK1 20 mA Limit for Constant Current
VK1 34 V Voltag e of limit betw een Const ant Current and
Re sisti v e Zon e
KB1–Additional gai n wi th extended battery feed ing
RI10 kΩOutpu t Resistance in c ons t ant current zone
RK12 100 ΩProgrammable resistance in resistive zone
fRING 2 5.4 H z Ring fr equen cy
ARING 62 Vrms Ring amplitude at Ring/Tip wire
RO1 23 V Ring offset voltage RO1
RO2 0 V Ring offse t voltage RO2
RO3 50 V Ring offset voltage RO3
fRINGLP 75 Hz Corner frequency of Ring low-pass filter
Off-h ookPD 2 mA Current t hreshol d for Off- hook De tection in Power
Down mode
Off-hookAct 8 mA O ff-hook Detection in Active with 2 mA hysteresis
Off-h o okRing 5 mA DC-C urrent t hreshol d for Off-hook De tectio n in
Ringin g mode
Off-h o okMW 5 mA DC-Curren t threshold for Of f-hook Detec tio n in
Message W aiti ng
Off-h ookA C 22 mArms Current thre s hold for AC Ring- T rip detec tion
LineSup 5 mA Curren t threshol d Line-Supervision for g round start
Ring/Tip 30 V Voltage threshold at Ring/Tip wire for VRTLIM bit
DC-Lowpass 1 .2/2 0 Hz DC low- pass set to 1.2 and 20 Hz resp ec tively
Cons tRam p 300 V/ s Slope of the ramp generator
delayRING 0 ms Delay of Ring burs t
SRend1 1/128 –Soft-reversal threshold 1
(referred to th e input of the ram p generat o r)
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 91 2000-07-14
Preliminary
SRend2 1/512 –Soft-reversal threshold 2
(referred to th e input of the ram p generat o r)
DUP 10 ms Data Upstream Persistence Counter is set to 10 ms
DUP-IO 16.5 ms Da ta Upstream Pe rsistence Counter for I/O pins,
VRTLIM and ICON bits (register INTREG1) is set to
16.5 ms
SR-Time 80 ms Time for soft-reversal
AC
IM-Filter 900 ΩApproximately 900 Ω real input im pedanc e
TH-Filter THBRD –App rox imatel y BRD imp edance for balanc ed network
LX 0 dB Re lative leve l in transmit
LR 7 dB Relative level in receive
ATTX 2.5 Vrms Teletax generator amplitude at the resistance of 200 Ω
fTTX 1 6 kHz Telet ax generator fr equen cy
TG1 940 Hz Tone generat or 1 (–12 dBm)
TG2 1633 Hz T one generator 2 (–10 dBm)
AC-LM- BP 1004 Hz AC leve l mete r band pass
Table 16 Default Values (cont’d)
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 92 2000-07-14
Preliminary
4.6 Interrupt Handling
SLICOFI-2x provides much interrupt data for the host system. Interrupt handling is
performed by the on chip microprogram which handles the interrupts in a fixed 2 kHz
(500 µs) frame. Therefore, some delays up to 500 µs can occur in the reactions of
SLICOFI-2x depending on when the host reads the interrupt registers.
Independent of the selected interface mode (PCM/µC or IOM-2), the general behavio r of
the interrupt is as follows:
•Any change (at some bits only transitions from 0 to 1) in one of the four interrupt
registers leads to an interrupt. The interrupt channel bit INT-CH in INTREG1 is set to
one and all interrupt registers of one DuSLIC channel are locked at the end of the
interrupt procedure (500 µs period). Therefore all changes within one 2 kHz frame are
stored in the interrupt registers. The lock remains until the interrupt channel bit is
cleared (Release Interrupt by reading all four interrupt registers INTREG1 to
INTREG4 wit h one command).
•In IOM- 2 inte rfa ce mod e, the in terru pt chan ne l bits are fe d to t he C IDU cha nn el (see
IOM-CIDU). In PCM mode, the INT pin is set to active (low).
•The interrupt is released (INT-CH bit reset to zero) by reading all four interrupt
registers by one command. Reading the interrupt registers one by one using a series
of comm ands do es not release the interrupt even if all f our registers are read.
•A hard ware or pow er- on rese t of th e c hip cle ars all pe ndin g inter rup ts and res ets the
INT line to inactive (PCM/µC mode) or resets the INT-CH bit in CIDU (IOM-2 mode).
The behavior after a software reset of both channels is similar, the interrupt signal
switches to non-active within 500 µs. A software reset of one DuSLIC channel
deactivates the interrupt signal if there is no active interrupt on the other DuSLIC
channel.
If the reset line is deactivated, a reset interrupt is generated for each channel (bit
RSTAT in register INTREG2).
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 93 2000-07-14
Preliminary
4.7 Operating Modes and Power Management
In many applications, the power dissipated on the line card is a critical parameter. In
larger systems, the mean power value (taking into account traffic statistics and line
length distribution) determines cooling requirements. Particularly in remotely fed
systems, the maximum power for a line must not exceed a given limit.
4.7.1 Introduction
Generally, system power dissipation is determined mainly by the high-voltage part. The
most effective power-saving method is to limit SLIC functionality and reduce supply
volta ge in line wit h requirements . This is a chieved us ing diffe rent operating m odes.
The three main modes – Power Down, Active and Ringing – correspond to the main
system states: on-hook, signal transmission (voice and/or TTX) and ring signal feed.
For power critical applications the Sleep mode can be used for even lower power
cons umptio n than in Pow er Down mod e.
–Power Down
Off-h ook detect ion is the only function av ailable. It is realiz ed by 5 k Ω resistors applied
by the SLIC from Tip to VBGND and Ring to VBAT, respectively. A simple sensing circuit
superv is es the DC cur rent thro ugh thes e resis to rs (zero in on-hook and non-z ero in off-
hook state). This scaled transversal line current is transferred to the IT pin and compared
with a programmable current threshold in the SLICOFI-2x. Only the DC loop in the
SLICOFI-2x is active.
In Sleep mode, all functions of the SLICOFI-2x are switched off except for off-hook
detection which is still available via an analog comparator. Both AC and DC loops are
inactive. To achieve the lowest power consumption of the DuSLIC chip set, the clock
cycles fed to the MCLK and PCLK pins have to be shut off.
For changing into another state the DuSLIC has to be woken up according to the
procedure described in Chapter 4.1.
–Active
Both AC and DC loops are operative. The SLIC provides low-impedance voltage feed to
the line. The SL IC senses, scales and separates transve rsal (metallic) and lon gitudinal
line currents. The voltages at Tip and Ring are always symmetrical with reference to half
the battery voltage (no ground reference!). An integrated switch makes it possible to
choose between two (SLIC-S/-S2, SLIC-E/-E2) or even three (SLIC-P) different battery
voltages. With these voltages selected according to certain loop lengths, power
optimized solutions can be achieved.
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 94 2000-07-14
Preliminary
–Ringing
For SLIC-E/-E2 and SLIC-S, an auxiliary positive supply volta ge VHR is used to give a
total supply range of up to 150 V. For SLIC-P the whole supply range is provided by
VBATR. The low-impedance line feed (RSTAB (2x30 Ω)=+ RFUSE (2x20 Ω)= + appr. 1 Ω
≈101 Ω output impedance) with a balanced sinusoidal Ring signal of up to 85 Vrms, plus
a DC o ffset of 20 V, is su fficie nt to su pply ve ry long line s at any k ind of rin ger load and
to reliable detect Rin g t r ip. U nbalanc ed ringing is s upported by apply ing the Ring signal
to only one line, while Ground is applied t o the othe r line.
For an overview of all DuSLIC operating modes see Table 13 for PEB 4264/-2, Table 14
for PEB 4265/-2 and Table 15 for PEB 4266.
4.7.2 Power Di ssipation of the SLICOFI-2x
For an optimized power cons umption unu se d EDSP functions hav e t o be s w it ched of f.
Typical power dissipation values for different operating modes of the SLICOFI-2x are
shown in Chapter 7.4.3 and Chapter 7.4.4.
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 95 2000-07-14
Preliminary
4.7.3 Power Dissipation of the SLIC
The SLIC power dissipation mainly comes from internal bias currents and the buffers
output stage (to a lesser extent from the sensor) where additional power is dissipated
whenever current is fed to the line.
4.7.3.1 Power Down Modes
In Power Down modes, the internal bias currents are reduced to a minimum and no
current is fed to the line (see Table 19, Table 21 and Table 23). Even with active off-
hook detectio n, the power di ssipation of 5 mW (6 mW for SLIC-P) is negli gible. Note that
this is the dominant factor for a low mean power value in large systems, as a large
percen tage of lines are always inactive.
4.7.3.2 Active Mode
In Active mode, the selected battery voltage VBATx1) has the strongest influence on
power dissipation. The power dissipation in the output stage PO (see Chapter 7.1.5 and
Chapter 7.2.5) is determined by the difference between VBATx and the T ip-Ri ng voltag e
VTIP/RING. At constant DC line current ITrans, the shortest lines (lowest RL) cause lowest
VTIP/RING, and acco rdingly exhibi t the highe st on-chip power diss ipation. Ho wever, the
minimum battery voltage required is determined by the longest line and therefore the
maximum line resistance RL,MAX and in addit ion RPROT and RSTAB.
VBATx,min =ITrans ×(RL,MAX +RPROT +RSTAB)+VAC,P +VDROP
VAC,P.......... ...........Peak value of AC signal
VDROP...................Sum of voltage drop in the SLIC buffers (Table 17)
1) VBATx = VBATL, VBATH or VBATR
Table 17 Typical Buffer Voltage Drops (Sum) for ITRANS (ITor IR)
Mode Total Voltage drop VDROP [V]
SLIC-E/-E2/-S/-S2 SLIC-P
ACTL ITRANS ×96 ΩITRANS ×88 Ω
ACTH ITRANS ×100 ΩITRANS ×100 Ω
ACTR (ITRANS ×100 Ω) + 1 V ITRANS ×92 Ω
ROR, ROT –ITRANS ×92 Ω
HIR, HIT (ITorR×48 Ω) + 1 V ITorR×52 Ω
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 96 2000-07-14
Preliminary
The m ost ef ficient wa y to re duce sho rt-loop power di ssipation is to use a lower b attery
supply voltage (VBATL) whenever line resistance is small enough. This method is
supported on the SLIC-E/-E2 by integrating a battery switch. With a standard battery
volta ge of –48 V, long lines up to 2 kΩ=can be driven at 20 mA line cu rrent.
The SLIC-P PEB 4266 “low-power” version even allows three battery voltages (typically
the most negative one, e.g. –4 8 V, is used in Ac t iv e mode (On - hook) and Power Dow n
mode).
DuSLIC contains two mechanism which can be used as indication for the battery
switching:
1. A thres hold fo r the volt age at Ti p/ Ring can be set for gen erating an interrupt
2. The change between constant current and resistive feeding will generate an interrupt
4.7.3.3 SLIC Power Consumption Calculation in Active Mode
A scheme for a typical calculation is shown in Figure 40.
Figure 40 Circuit Diagram for Power Consumption
RPROT =40Ω, RSTAB =60Ω, RPHONE =150Ω, VPHONE =7V, ILINE =20mA
Conditions: VVoice peak =2V, IVoice peak =2mA, VTTX,rms (see example below)
Typical Powe r Consumption Calcula t ion with SLIC-E/-E2
Assuming a typical application where the following battery voltages are used:
VDD =5V, VBATL =–43 V, VBATH =–62 V, VHR = 80 V an d lin e fee ding is guara nteed
up to RL=1900Ω. For longer lines (RL> 1900 Ω) the extended battery feeding option
can be used (Mod e ACTR).
Requirement for TTX: VTTX =2.5Vrms
at a lo ad of 200 Ω.
SLIC
OFF-HOOK
R
PROT
+ R
STAB
R
LINE
R
PHONE
V
PHONE
I
LINE
V
SUBSCRIBER
V
TR
Circuit Diagram
ezm14049.emf
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 97 2000-07-14
Preliminary
Table 18 shows line currents an d output voltage s for differ ent operating mod es .
With the line feed conditions given in the above table the total power consumption PTOT
and its shares at different o perating m odes are sho wn in Table 19. The outpu t voltage
at Tip and Ring is calculated for the longest line (RL=1900Ω in ACTH, RL=996Ω in
ACTL).
Figure 41 shows the total power dissipation PTOT of the SLIC-E/-E2 in Active Mode
(ACT H and AC TL) with switch ed batter y voltag e (VBATH, VBATL) as a function o f RLine.
The power dissipation in the SLIC is strongly reduced for short lines.
Table 18 Line Feed Conditio ns fo r Powe r Calcula t ion of SLIC-E/-E2
Operating Mode Line Currents Output Voltages
PDRH, PDRHL ITRANS =0mA –
ACTL ITRANS =20mA VTIP/RING =32V
ACTH ITRANS =20mA VTIP/RING =50V
ACTR
exte nded battery f eeding at
higher loop length
(RL> 1900 Ω)
ITRANS =20mA VTIP/RING =130V
Table 19 SLIC-E/-E2 Typical Total Power Dissipation
PQ1)
1) The formulas for the calculation of the power shares PQ, PI, PG and PO can be found in Chapter 7.2.5.
PIPGPOPTOT
Operating
Mode [mW] [mW] [mW] [mW] [mW]
PDH4.60004.6
PDRH 5.6 0 0 0 5.6
ACTL 127 51.3 27.1 220 425.4
ACTH 222 72.2 32.8 240 567
ACTR 379 96.2 412 240 1127.3
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 98 2000-07-14
Preliminary
Figu re 41 SLIC - E/ -E2 Pow er Dissipa t i on with Swi t ch ed Battery Voltage
Typical Powe r Consumption Calcula t ion with SLIC-P (Internal Ringi ng)
Assuming a typical application where the following battery voltages are used:
VDD =5V, VBATL =–36 V, VBATH =–48 V, VBATR =–108 V and line feeding is
guar ant eed up to RL=1200Ω.
Requirement for TTX: VTTX = 2.5 Vrms at a load of 200 Ω.
Table 20 shows line currents an d output voltage s for differ ent operating mod es .
With the line feed conditions given in the above table, the total power consumption PTOT
and its shares at different o perating m odes are sho wn in Table 21. The outpu t voltage
at Tip and Ring is calculated for the longest line (RL=1200Ω in ACTH, RL=662Ω in
ACTL).
.
Table 20 Line Feed Conditions fo r Power Calcula t ion for SLIC-P
Operating Mode Line Currents Output Voltages
PDRH, PDRHL ITRANS =0mA –
ACTL ITRANS =20mA VTIP/RING =25.2V
ACTH ITRANS =20mA VTIP/RING =36V
ACTR ITRANS =20mA VTIP/RING =96V
0
100
200
300
400
500
600
700
800
900
1000
100
190
279
369
458
548
638
727
817
906
996
1086
1177
1267
1358
1448
1538
1629
1719
1810
1900
R
Line
[
Ω
ΩΩ
Ω
]
P
TOT
[mW]
duslic_0002_powerdiss.emf
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 99 2000-07-14
Preliminary
Figure 43 shows the total power dissipation PTOT of the SLIC-P in Active mode (ACTH
and A C TL) with switc hed ba tt ery voltage (VBATH, VBATL) as a f unction of RLine.
Figure 42 SLIC-P Power Dissipation (Switched Battery Voltage, Long Loops)
Tabl e 21 SLIC - P PEB 4266 Power Dissi pa t i o n
PQPIPGPOPTOT
Opera ti ng Mode [mW] [mW] [mW] [mW] [mW]
PDH 8.8 0 0 0 8.8
PDRH 7.7 0 0 0 7.7
PDRR 10.4 0 0 0 10.4
ACTL 81.7 43.6 15.3 216 357
ACTH 135 56.8 0 240 432
ACTR (Extended
Battery Feeding) 383 123 112 240 857
ROR, ROT
(Ring Pa us e) 263 0 102 0 365
0
100
200
300
400
500
600
700
100
156
212
269
325
381
437
493
550
606
662
716
770
823
877
931
985
1039
1092
1146
1200
R
Line
[
Ω
ΩΩ
Ω
]
P
TOT
[m W]
duslic_0001_powerdiss.emf
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 100 2000-07-14
Preliminary
Typical Power Consumption Calculation with SLIC -P (External Ringing)
Assuming a typical application where the following battery voltages are used:
VDD =5V, VBATL =–25 V, VBATH =–31 V, VBATR =–48 V and line feeding is guaran-
teed up to RL=600Ω.
Requirement for TTX: VTTX,rms =0.7V.
This is a typical lowest-power application, where VBATR is used just in the On- hook stat e
and VBATH and VBATL is used in the active m odes with batter y switchin g.
Table 22 shows line currents an d output voltage s for differ ent operating mod es .
With the line feed conditions given in the above table, the total power consumption PTOT
and its shares at different o perating m odes are sho wn in Table 23. The outpu t voltage
at Tip and Ring is calculated for the longest line (RL=600Ω in ACTH, RL=358Ω in
ACTL).
Figure 43 shows the total power dissipation PTOT of the SLIC-P in Active mode (ACTH
and AC TL) with s witche d batte ry volt age (VBATH, VBATL) as a function of RLine (Lowest
Power Applications).
Table 22 Line Feed Conditions fo r Power Calcula t ion for SLIC-P
Operating Mode Line Currents Output Voltages
PDRH, PDRHL ITRANS =0mA –
ACTL ITRANS =20mA VTIP/RING =19.2V
ACTH ITRANS =20mA VTIP/RING =24V
ACTR ITRANS =20mA VTIP/RING =41V
Tabl e 23 SLIC - P PEB 4266 Power Dissi pa t i o n
PQPIPGPOPTOT
Operating
Mode [mW] [mW] [mW] [mW] [mW]
PDH 4.3 0 0 0 4.3
PDRH 4.5 0 0 0 4.5
PDRR 5.0 0 0 0 5.0
ACTL 57.8 31.5 1.0 116 206
ACTH 88.7 38.1 -28.6 140 238
ACTR 172.5 56.8 -87.2 140 282
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 101 2000-07-14
Preliminary
Figure 43 SLIC-P Power Dissipation (Switched Battery Voltage, Short Loops)
4.7.3.4 Ringing Modes
Internal Balanced Ringing (SLIC-E/-E2 and SLIC-P)
The SLIC-E/-E2/-P internal balanced ringing facility requires a higher supply voltage
(auxiliary voltag e VHR). The highes t share of t he tota l power is d issipated in t he outp ut
stage of the SLIC-E/-E2/-P. The output stage power dissipation PO (see Table 24,
Table 25) depends on the ring amplitude (VRNG,PEAK), the equi v ale nt r in ger l oa d (RRNG
and CRNG), the rin g f requency (via c osφL) and the li ne length (RL).
The minimum auxiliary voltage VHR necessary for a required ring amplitude can be
calc ul ated using:
VHR –VBATH =VRNG,PEAK +VRNG,DC +VDROP =VRNG,RMS ×crest factor + VRNG,DC +VDROP
The crest factor is defined as peak value divided by RMS value (here always 1.41
because sinusoidal ringing is assumed).
VRNG,DC Superimp os ed DC volt age for Ring trip dete c t ion (10 to 20 V)
VDROP Sum of voltag e drops in SLIC bu ff ers (Table 17)
VRNG,PEAK P eak ring volt age at Tip/Ring
duslic_0003_powerdiss.emf
0
50
100
150
200
250
300
350
100
126
152
177
203
229
255
281
306
332
358
382
406
431
455
479
503
527
552
576
600
R
Line
[
Ω
ΩΩ
Ω
]
P
TOT
[mW]
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 102 2000-07-14
Preliminary
The strong influence of the ringer load impedance ZLD and the number of ringers
is demonstrated by the formula for the current sensor power dissipation (PI+PO) in
Table 24 and Table 25.
The ring er load impe dance ZLD can be calculated as follows:
ZLD =|ZLD|×e jφLD =RL+RRNG +1/jωCRNG with
ZLD Load im pedanc e
RRNG Ringer resistance
CRNG Ringer capacitance
RLLine resistance
Internal Unbalanced Ringing with SLIC-P
The ring signal is present just on one line (modes ROR, ROT), while the other line is
conn ected to a potential of GND.
The minimum battery voltage VBATR necessary for a required ring amplitude can be
calc ul ated using:
–VBATR –VDROP =2×VRNG, PEAK =2×VRNG,RMS ×cres t fact or
External Ringing (SLIC-E/-E2 and SLIC-P)
When an exte rnal ring generator and ring relays are use d, t he SLI C can be sw itched to
Power Down mod e.
The “low-power” SLIC-P is optimized for extremely power-sensitive applications (see
Table 23). SLIC-P has th ree diff erent batter y volt ages. VBATR can be used f or on-hook,
while VBATH and VBATL are normally used for off-hook mode.
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 103 2000-07-14
Preliminary
4.7.3.5 SLIC Power Consumption Calculation in Ringing Mode
The average power consumption for a ringing cadence of 1 second on and 4 seconds
off is given by
PTOT, average =k×PTOT, Ringing +(1–k) ×PTOT, RingPause
with k = 0.20
The ty pical circuit fo r ringing is s how n in Figure 44.
Figure 44 Circuit Diagram for Ringing
ezm35004.emf
Z
RNG
R
RNG
C
RNG
R
LINE
v
RNG
R
PROT
+ R
STAB
SLIC
v
TR
i
Circuit Diagram for Ringing
ON HOOK
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 104 2000-07-14
Preliminary
–Power Consumption Calculation for SLIC-E/-E2 in Balanced Ringing Mode
With the example of the abo ve calculatio n for SLIC-E/- E2 (see Chapter 4.7.3.3) and a
typical ringer load.
RRNG =450Ω,=CRNG =3.4µF, required ringing voltage VRNG =58Vrms and ringing
frequency fRNG = 20 Hz. DC Of f set Voltage for ring trip detec t ion VDC =20V.
Table 24 shows the power calculation for the total power dissipation PTOT of the SLIC-E/
-E2 in balanced ringing mode consisting of the quiescent power dissipation PQ, the
current sensor power dissipation PI, the gain stage power dissipation PG and the output
stag e pow er dissipation PO.
Table 24 SLIC-E/-E2 Balanced Ringing Power Dissipation (typical)
PTOT, RingPause =PQ+PI+PG+PO (ITrans =0mA) 710mW
PTOT, Ringing =PQ+PI+PG+PO2481 mW1)
1) Values for VDD =5V, VBATL =–43 V, VBATH =–62 V, VHR =80V, TJ=25°C
PQ=VDD ×IDD +IVBATHI×IBATH +IVBATLI×IBATL +VHR ×IHR 390 mW
PI=0.015×ITrans,rms ×VHR +0.055×ITrans,rms ×|VBATH|
+0.04×ITrans,rms ×VDD with ITrans,rms =VTIP/RING, rms/|ZLD|118 mW
PG=(VHR +|VBATH|) ×(SQRT((VHR +VBATH +VDC-offset)2+(VTIP/
RING2)/2) –IVHR +VBATHI)/60k + (VHR2 –322 + VBATH2–482)×
(1/60k + 1/216k)
320 mW
PO=(VHR +IVBATHI) ×ITrans,rms ×2×SQRT(2)/π–VTIP/RING, rms ×
ITrans,rms ×cos(φLoad)1653 mW
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 105 2000-07-14
Preliminary
–Power Consumption Calculation for SLIC-P in Balanced Ringing Mode
With the exa mple of th e abo ve ca lculat ion wi th RL=1200Ω line length for SLIC-P (see
Chapter 4.7.3.3) when the internal ringing feature will be used.
Typical ringer load: RRNG = 1000 Ω,=CRNG =3.7µF. Required ringing voltage
VRNGr = 45 Vrms and ringing frequency fRNG = 20 Hz. DC Offset voltage for ring trip
detection VDC =20V.
Table 25 shows the power calculation for the total power dissipation PTOT of the SLIC-P
in bala nced rin ging mo de c onsistin g of the quiesc ent po wer diss ipation PQ, t he current
sensor power dissipation PI, the gain sta ge power dissipatio n PG and the output stage
power di ssipation PO.
Table 25 SLIC-P Balanced Ringing Power Dissipation (typical)
PTOT, RingPause =PQ+PI+PG+PO (ITrans = 0 mA) 482 mW
PTOT, Ringing =PQ+PI+PG+PO1618 mW1)
1) Values for VDD =5V, VBATL =–36 V, VBATH =–48 V, VBATR =–108 V, TJ=25°C
PQ=VDD ×IDD +IVBATRI×IBATR +IVBATHI×IBATH +IVBATLI×IBATL 370 mW
PI=0.055×ITrans,rms ×IVBATRI + 0.04 ×ITrans,rms ×VDD
with ITrans,rms =VTIP /RING, rms/IZLDI117 mW
PG=(VBATR2–802)×(1/60k + 1/216k) 112 mW
PO=IVBATRI×ITrans,rms ×2×SQRT(2)/π–
VTIP/RING, rms ×ITrans,rms ×cos(φLoad)1019 mW
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 106 2000-07-14
Preliminary
–Power Consumption Calculation for SLIC-P in Unbalanced Ringing Mode
A similar power calculation is valid for in ternal unbalanced rin ging mode, which is only
available for the SLIC-P.
With the following example:
VDD =5V, VBATL =–30 V, VBATH =–36 V, VBATR =–150 V and line feeding is
guar an-te ed up to 600 Ω.
Typical ringer load RRNG =1000Ω,=CRNG =3.7µF, required ringing voltage
VRNG = 45 Vrms and ringing frequency fRNG =20Hz.
Table 26 shows the power calculation for the total power dissipation PTOT of the SLIC-P
in unba lanced ringing mode.
Table 26 SLIC-P Unbalanced Ringing Power Dissipation (typical)
PTOT, RingPause =PQ+PI+PG+PO (ITrans = 0 mA) 644 mW
PTOT, Ringing =PQ+PI+PG+PO2756 mW1)
1) Values for VDD =5V, VBATL =–30 V, VBATH =–36 V, VBATR =–150 V, TJ=25°C
PQ=VDD ×IDD +IVBATRI×IBATR +IVBATHI×IBATH +IVBATLI×IBATL 349 mW
PI=0.055×ITrans,rms ×IVBATRI + 0.04 ×ITrans,rms ×VDD
with ITrans,rms =VTIP /RING, rms/IZLDI160 mW
PG=(0.5×VTIP/RING2–(VBATR/2)2)/60k + (VBATR2–802)×
(1/60k + 1/216k) 295 mW
PO=IVBATRI×ITrans,rms ×2×SQRT(2)/π–
VTIP/RING, rms ×ITrans,rms ×cos(φLoad)1952 mW
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 107 2000-07-14
Preliminary
4.8 Integrated Test and Diagnosis Functions (ITDF)1)
4.8.1 Introduction
Subscriber loops are affected by a variety of failures which have to be monitored.
Monitoring the loop supposes the access to the subscriber loop and to have test
equipment in place which are capable to perform certain measurements. The
measurements or tests involve resistance, capacitance, leakage, and measurements of
inter f eri ng cur rents an d voltages.
4.8.1.1 Conventional Line Testing
Conventional linecards in Central Office (CO) applications usually need two test relays
per channel to access the subscriber loop with the appropriate test equipment. One relay
(test-out) connects the actual test unit to the local loop. All required line tests can be
accomplished that way. The second relay (test-in) separates the local loop from the
SLIC-E/-E2/-P and connects a termination impedance to it. Hence, by sending a tone
signal the entire loop can be checked , in clu ding the SLICOFI-2 and SLIC-E /-E2 /-P .
4.8.1.2 DuSLIC Line Testing
The DuSLIC with its Integrated Test and Diagnosis Functions (ITDF) is capable to
perform all tests necessary to monitor the local loop without an external test unit and test
relays. The fact, that measurements can be accomplished much faster as with
conventional test capabilities makes it even more a compelling argument for the DuSLIC.
With the DuSLIC both channels are able to perform line tests conc urrently, whic h also
has a tremendous impact on the test time. All in all, the DuSLIC increases the quality of
servi ce and reduc es the costs in vari ous applications.
1) only available with DuSLIC-E/-E2/-P
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 108 2000-07-14
Preliminary
4.8.2 Diagnostics
The two-channel chip set has a set of signal generators and features implemented to
accomplish a variety of diagnostic functions. The SLICOFI-2 device generates all test
signals, processes the information that comes back from the SLIC-E/-E2/-P and provides
the data to a higher level master device, e.g. a microprocessor. All the tests can be
initiated by the micropocessor and the results can be read back very easily. The
Integrated Test and Diagnosis Functions (ITDF) might prevent any problem which
affects service caused by the subscriber line or line equipment before the customer
complains. IDTF has been integrated to facilitate the monitoring of the subscriber loop.
4.8.2.1 Line Test Capabilities
The line test comprises the following functions:
•Loop resistan ce
•Leakag e current T ip/Ring
•Leakag e current T ip/GND
•Leakage curr ent R i ng/GN D
•Ringe r capacitance
•Line capacitanc e
•Line capacitanc e Tip/GN D
•Line capacitanc e Ring/GN D
•Foreign vo lt age meas uremen t Tip/G ND
•Foreign vo lt age meas uremen t Ring/ G N D
•Foreign vo lt age meas uremen t Tip/R ing
•Measurement of ringing vol ta ge
•Measurement of line feed curre nt
•Meas urement of supply volta ge VDD of the SLICOFI-2
•Measurement of transvers al- and longitudi nal c urrent
Two main trans fer paths (levelmeter) ar e implemen ted to accomp lish all the d ifferent l ine
meas uremen t f unc tions (ref er to Figure 45).
4.8.2. 2 Integra ted Sign al Sour ces
The signal sources ava ilable on the DuSLIC ch ip set are:
•Cons tant DC voltag e (t hree programmable ringing DC off s et volta ges)
Please refer to the CRAM coefficient set and register LMCR3 (bits RNG-
OFFSET[1:0]) on Page 206.
•2 independent ton e generat ors T G1 and TG2 :
Please refer to the CRAM coefficient set and register DSCR (bits PTG, TG2-EN, TG1-
EN) on Page 200.
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 109 2000-07-14
Preliminary
•TTX metering signal generator (12/16 kHz)
Please refer to the CRAM coefficient set and register BCR2 (bits TTX-DIS, TTX-12k)
on Page 192.
•Ramp generato r (us ed for capac it ance measureme nt s)
Please refer to the CRAM coefficient set and register LMCR2 (bit RAMP-EN) on
Page 204.
•Ring gen erator (5 Hz - 300 Hz )
Please refer to the C RAM coef ficient Table 51 "CRAM Coefficients" on Page 226.
Figure 45 shows the e nt ire lev elmeter block for AC an d DC:
Figure 45 Bl ockdiagra m Lev e l me ter
duslic_0010_level_meter_block.emf
TTX
ADAPTIVE
FILTER
RESULT
REG
MUX
MUX
VOICE PATH
SHIFT
FACTOR
K
INTDC
OFFSET
REGISTER
RECTIFIER
ON / OFF
+
2 kHz
+/- 19 Bit
PROGR GAIN STAG E
DECI-
MATION
A / D
1 Bit
SIGMA
DELTA
1 MHz
DC
PREFI
IO4 - IO3
Offset
VDD
MUX
IT
IL
IO3
IO4
DC Outp ut Volt a ge
V
DC
on DCN – DCP
A-B
A-B
INTEGRATOR
1x16ms
...
16x16ms
SHIFT
FACTOR
K
INTAC
AC
PREFI
A / D
SIGMA
DELTA
4 MHz
DECIMATION
BANDPASS
NOTCH
FILTER
VOICE PATH
PCM IN:
Recei ve Dat a fr om PC M
or IOM-2 Interface
+
RECTIFIER
MUX
AC LEVELMETER
ITAC
a
b
a
b
c
Programmable
Not Programmable
LMCR2:
LM-SEL[3:0]
LMCR1: DC-AD16 LMCR2: LM-RECT
LMCR3:
LM-ITIME[3:0]
LMCR2:
LM-SEL[3:0] CRAM
LMCR2:
LM-NOTCH
LM-FILT
OFR1/2
LMCR2:
LM-SEL[3:0]
LMRES1/2
LMCR1: LM2PCM
LMCR1: LM-EN
CRAM
CRAM CRAM
16 / 1
DC LEVE L MET ER
INTEGRATOR
(Ri ng Period)
PCM OUT:
Transmit Data to PCM
or IOM-2 Interface
TTX
REAL
TTX
IMG.
c
LMCR2:
LM-SEL[3:0]
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 110 2000-07-14
Preliminary
4.8.2. 3 Result Register Data For m at
The result of any measurement can be read via the result registers LMRES1/2. This
gives a 16 bit value with LMRES1 being the high and LMRES2 being the low byte.
The res ult is co ded in 16 bit two´s complement:
4.8.2.4 Using the Levelmeter Integrator
Both AC and DC levelmeter allow to use a programmable integrator. The integrator may
be conf igured to run con tin uously or s ingle.
Singl e M easur ement Se q ue nce (AC & DC L evelmeter)
Figure 46 Single Measur em ent Sequence (AC&DC Leve lm ete r )
Tabl e 27 Levelmeter Re sult Value Range
Negative Val ue Range Po sitive Valu e R an ge
–Fullscale + Fullscale
0x8000 0xFFFF 0 0x7FFF
–32768 –1 0 + 32767
duslic_0019_LM_single.emf
LM C R 1: LM -EN
INTRE G 2: LM -OK
In t. P e rio d In t. P e rio d
Start New
Measurement
Read Result
LMRES1/2
LM CR 1: LM -O NC E = 1
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 111 2000-07-14
Preliminary
Continuous Measuremen t Se que nce (DC Levelmeter)
Figure 47 Continuous Measurement Sequence (DC Levelmeter)
Continuous Measuremen t Se que nce (AC Levelmeter)
Figure 48 Continuous Measurement Sequence (AC Levelmeter)
duslic_0020_LM_contDC.emf
LM CR 1: LM -EN
IN TR EG 2: LM-OK
In t. P e rio d In t. P e rio d
Read Res ult
LMRES1/2
LM CR 1: LM -O NC E = 0
In t. P e rio d In t. P erio d
Read Result
LMRES1/2 Read Result
LMRES1/2
500 µs 500 µs 500 µs
duslic_0021_LM_contAC.emf
LM CR 1: LM -EN
INTRE G 2: LM -O K
In t. P e rio d In t. P e rio d
Read Result
LMRES1/2
LM CR 1: LM -O NC E = 0
500 µs 500 µs 500 µs
In t. P e rio d
Read Result
LMRES1/2 Read Resul t
LMRES1/2
1 m s 1 ms
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 112 2000-07-14
Preliminary
4.8.2.5 DC Levelmeter
The path of the DC levelmeter is shown in Figure 45. Hereby, the DC levelmeter results
will be determined and prepared depending on certain configuration settings. The
selected input signal becomes digitized after pre-filtering and analog-to-digital
conv ers ion. The D C lev elm et er is selected and enabled as s how n in Table 28:
The effectiv e sampling rate a fter the dec imation stages is 2 k Hz. The dec imated value
has a re so lution of 19 bits. T he o ffset c ompe nsa tio n valu e (see Chapter 4.8.2.8) within
the offset re gisters OFR1 (bits OFFSET-H [7:0] ) and OFR2 (bits OFFSET-L[7 :0]) can b e
set to eliminate the offset caused by the SLIC-E/-E2/-P current sensor, pre-filter, and
analog-to-digital converter. After the summation point the signal passes a programmable
digital gain filter. The additional gain factor is either 1 or 16 depending on register LMCR1
(bit DC-AD16):
–LMCR1 (bit DC-AD16) = 0: No additional gain factor
–LMCR1 (bit DC-AD16) = 1: Additional gain factor of 16
The rectifier after the gain filter can be turned on/off with:
–LMCR 2 (bit LM-R ECT) = 0: Rec t ifier disabled
–LMCR 2 (bit LM-R ECT) = 1: Rec t ifier enabl ed
A shift-factor KINTDC in front of the integrator prevents the levelmeter during an
integration op eration to create an over flow. If an overf low in the levelmeter oc curs, the
output result will be ± fullscale (see Table 27).
If the shift factor KINTDC is se t to e .g . 1/8 , the conten t of the lev e lm eter result register is
the integration res ult div ided by 8.
The shift f actor KINTDC is s et in t he C RAM (o ff s et address 0x76 ):
Table 28 Selecting DC Levelmeter Path
LM-SEL[3:0] in
register LMCR2 DC Levelmeter Path
0100 DC out voltag e on DCP-DCN
0101 DC current on IT
1001 DC current on IL
1010 Voltage on IO3
1011 Voltage on IO4
1101 VDD
1110 Offset of DC-pre-filter (short circuit on DC-pre-filter input)
1111 Voltage on IO4 –IO3
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 113 2000-07-14
Preliminary
CRAM:
Addr es s 0x76: LM DC2/LM DC1
Addr es s 0x77: 0/ LM D C3
LMDC1, LMDC2 and LMDC3 are 4 bit nibbles which contain KINTDC.
DuSLICOS allows to automatically calculate the coefficients for KINTDC for ITRANS
measurement. The expected "Current for Ring Off-hook Detection" (see DuSLICOS DC
Control Parameter 2/3) of e.g. 20 mA is entered in to the program and then KINTDC is
autom atically c alculated to achieve 5 0 % fu ll scale if t he current of 20 m A is integrat ed
over the set r inger period.
The integration function accumulates and sums up the levelmeter values over a set time
period. The time period is determined by the programmed ring frequency. A ring
frequency fRING of 20 Hz results in 100 samples (NSamples), because of the 2 kHz
effective DC sampling rate fS,DC.
The number of integration samples NSamples may also be programmed directly by
accessin g dedicat ed bytes in th e Coeffic i ent RAM (C RAM ) .
CRAM:
Addr es s 0x73: R GF2/RGF 1
Addr es s 0x74: R GA1/RG F 3
RGF1, RGF2 and R GF 3 are 4 bit nib bles w hic h control t he ring freq uency fRING.
RGA1 is a 4 bit nibble which is calculated by DuSLICOS and controls the ringer
amplitude (see DuSLICOS byte file). To ensure that RGA1 is not changed please
perf o rm a read/ m odify/write operation.
Table 29 KINTDC Setting Table
LMDC1 LMDC2 LMDC3 KINTDC
8801
881½
88::
8861/64
8871/128
NSamples fSDC,
fRING
-------------- 2000Hz
fRING
---------------------==
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 114 2000-07-14
Preliminary
The int egration function can be turned on and off by bit LM-EN in register LM C R1.
The levelme ter result of the selected signal source will be sto red in the resu lt registers
LMRES1 (bits LM-VAL-H[7:0]) and LMRES2 (bits LM-VAL-L[7:0]) depending on the
LM-SEL[3:0] bits in register LMCR2. The result registers get frequently updated every
500 µs if bit L M -EN in register LMCR 1 = 0, or af t er an integr at ion period, if bit LM-EN in
register LMCR1 = 1. If the bit LM-ONCE in register LMCR1 is set to 1 then the integration
is executed only once. To start again bit LM-EN has to be set from 0 to 1.
The levelmeter source/result can be transferred to the PCM/IOM-2 interface, depending
on the bit LM2PCM in register LMCR1.
Table 31 shows the levelmeter results without and with integrator function. The
integrator is enabled if bit LM-EN in register LMCR1 = 1.
The level meter result L M Value is a 16 bit two´s complement value of LM-VAL-H[7:0] and
LM-VAL-L[7:0].
The factor LMResult used in Table 31 is defined:
•Example for po si ti ve value of LM Result:
LM-VAL-H = "0010 01 00" = 0x24
LM-VA L-L = " 1010 0101" = 0x A5
LMValue = 0x24A5 = 9381
LMResult = 0.2863
•Examp l e for neg ati ve v al ue of LMResult:
LM-VAL-H = "1001 10 01" = 0x99
LM-VA L-L = " 0110 0010" = 0x 62
LMValue = 0x9962 = –26270
LMResult = –0.8017
Table 30 NSamples Setting Table
RGF1 RGF2 RGF3 fRING NSamples
8 805004
8 812508
88:::
8 867.81256
8 873.91512
LMResult LMValue
32768
----------------------=
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 115 2000-07-14
Preliminary
Table 31 Levelmeter Results with and without Integrator Function
LM-EN = 0 (without Integrator) LM-EN = 1 (with Integrator)
ITRANS1):
Power
Down
Resistive
1) DC current on pin IT (bits LM-SEL[3:0] = 0101)
ITRANS1):
any other
mode
ILONG2)
2) DC current on pin IL (bits LM-SEL[3:0] = 1001)
Voltage:
IO33),
IO44),
IO4-IO35)
3) Voltage on IO3 referenced to VVCM (typical 1.5 V) (bits LM-SEL[3:0] = 1010)
4) Voltage on IO4 referenced to VVCM (typical 1.5 V) (bits LM-SEL[3:0] = 1011)
5) Voltage on IO4 –IO3 referenced to VVCM (typical 1.5 V) (bits LM-SEL[3:0] = 1111)
VDD
VDC6)
with
ACTL,
ACTH
6) DC output voltage at SLIC measured via DCN –DCP (bits LM-SEL[3:0] = 0100)
VDC6)
with
ACTR,
ringing
mode
ITRANS LMResult KIT PDR
,
RIT2
--------------------------
×VAD
×=
ITRANS LMResult 7.966 mA
×=
ITRANS LMResult KIT PDR
,VAD
×
RIT2 NSamples KINTDC
××
---------------------------------------------------------------------------------
×=
ITRANS LMResult 7.966 mA
NSamples KINTDC
×
-------------------------------------------------------------×=
ITRANS LMResult KIT
RIT2
------------VAD
××=
ITRANS LMResult 79.66 mA
×=
ITRANS LMResult KIT VAD
×
RIT2 NSamples KINTDC
××
---------------------------------------------------------------------------------
×=
ITRANS LMResult 79.66 mA
NSamples KINTDC
×
------------------------------------------------------------
×=
ILONG LMResult
–KIL
RIL
----------VAD
××=
ILONG LMResult 67.7 mA
×–=
ILONG LMResult KIL VAD
×
RIL NSamples KINTDC
××
-----------------------------------------------------------------------------×–=
ILONG LMResult 67.7 mA
NSamples KINTDC
×
------------------------------------------------------------
×–=
VINPUT LMResult VAD
×–= VINPUT LMResult
V
AD
NSamples KINTDC
×
------------------------------------------------------------×–=
VDD LMResult 3.9 V
×–= VDD LMResult 3.9 V
NSamples KINTDC
×
------------------------------------------------------------
×–=
VDC LMResult 76.35 V
×–= VDC LMResult 76.35 V
NSamples KINTDC
×
------------------------------------------------------------×–=
VDC LMResult 152.7 V
×–= VDC LMResult 152.7 V
NSamples KINTDC
×
------------------------------------------------------------×–=
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 116 2000-07-14
Preliminary
Note: Measurement of pins IL, IO3, IO4, IO4-IO3 and VDD can cause problems in the
DC loop. The measured value is always interpreted as ITRANS current. This can
disturb the DC regulation and the off-hook indication. In active mode you can
freeze the output of the DC loop by setting the bit LM-HOLD to '1'. In ringburst
mode it is possible that DuSLIC automatically switches back to ringpause mode
because the measurement result was interpreted as off-hook. This can be avoided
by program m ing the off-hook c urrent to the ma ximum v alue (79.6 6 m A ).
Measurement of AC signals via DC levelmeter
This method is applicable for a single frequency sinusoidal AC signal which is
superi mposed on a D C signal.
1. S et th e rin g freq ue ncy fRING to the freq uen cy of th e sign al to b e m eas ured. Mult iples
of the expected s ignal period may also be used.
2. Set the offset registers OFR1 and OFR2 to 0x00.
3. Measure the DC content with disabled rectifier (bit LM-RECT = 0).
The DC conten t can be calc ul ated as de scr i bed in Table 31.
Note : If there was an overflow in side the int egrator durin g the inte gration period , the
result will be ± fullscale. Reduce the shift factor KINTDC or the number of samples
NSamples and st art the measurement again.
4. The offset registers OFR1 and OFR2 have to be programmed to the va lue
where OFR1 is the high by te and OFR2 is the l ow byte of the 16 bit word OFFSET.
5. R epeatin g the mea s urement of the DC content s hould result in a LMValue of zero.
6. Perform a new measurement with the rectifier enabled (bit LM-RECT = 1). The result
is the rectified mean value of the measured signal an can be calculated with the
formulas of Table 31.
7. From this result the peak value and the RMS value can be calculated:
KINTDC Shift Factor (see Table 29)
KIT,PDR Value of the curr e nt divid e r i n po w er do w n re sistive mode 5
KIT Valu e of th e c ur r ent divider for tr ansver sal curre nt 50
KIL Value of the current divider for longitudinal current 100
RIT2 Sense resi stor for tr an sversal cur rent 680 Ω
RIL Sense resistor for longitudinal current 1600 Ω
VAD Voltage at A/D c onverter refered to digit al f ulls cale 1.0834
VDC DC output voltage at SLIC measured via DCN –DCP
OFFSET LMValue
NSamples KINTDC
×
------------------------------------------------------------–=
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 117 2000-07-14
Preliminary
4.8.2.6 AC Levelmeter
The AC lev elmeter is se lected and enabled as show n in Table 32:
Figure 45 on Page 109 shows the path of the AC/TTX levelmeter functions. The AC
levelmeter allows access to the voice signal while the active voice signal is being
processed. The input signal for the AC levelmeter might get processed with a
programmable filter characteristic, i.e. bandpass- or notch filter. Depending on the
following set tings, the band p ass or notch filt er is turned on or off:
–Register LMC R 2 bit LM-FILT = 0: No fi lter enabled (nor m al oper at ion)
–Regis ter LMCR 2 bit LM-FILT = 1: Bandpas s /notch filter char acteris t ic s enabled
–Regis t er LM C R2 bit LM -NOTC H = 0: Not ch filter enab led, bandpas s filt er disabl ed
–Regis t er LMCR2 bit LM- NOTCH = 1: B andpass f ilter enabled, notch f ilt er dis abled
The rectifier cannot be turned off, it is always active in the AC path. A shift-factor in front
of the integrator prevents the levelmeter during an integration operation to create an
overflow. The shift-factor can be set by the coefficient LM-AC gain (see CRAM
coeffi cien t set Table 51 "CRAM Coefficients" on Page 226).
KINTAC can be set v i a c oef ficien t LM-AC :
CRAM:
Addr es s 0x34: C G1/LM- AC
LM-AC is a 4 bit nibble w hich cont ains KINTAC.
CG1 is a 4 bit nibble which is calculated by DuSLICOS and controls the conference gain
(see DuSLICOS byte file). To ensure that CG1 is not changed please perform a read/
modify/write opera t ion.
Table 32 Selecting AC Levelmeter Path
LM-SEL[3:0] in
register LMCR2 AC Levelmeter Path
0000 AC levelmeter in transmit
0110 AC levelmeter in receive
0111 AC leve lm et er receiv e + transmit
VPeak VMean π×
2
-----------------------------=
VRMS VPeak
2
---------------=
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 118 2000-07-14
Preliminary
The integration function accumulates and sums up the levelmeter values over a set time
period. The time period from 1*16 ms to 16*16 ms is set by the bits LM-ITIME[3:0] in
register LMCR3. The integration function can be turned on and off by bit LM-EN in
register LM CR1.
The number of sam ples NSamples for the integrator is def ined by:
NSamples = LM-I T IME * 8000
The level c an be calculated b y:
The result registers get frequently updated after an integration period, if bit LM-EN in
register LMCR1 = 1. If the bit LM-ONCE in register LMCR1 is set to 1 then the integration
is executed only once. To start again bit LM-EN has to be set from 0 to 1.
The lev elmeter resul t can be transf erred to the PC M/IOM-2 int erface, de pending on bit
LM2PC M in regist er LMCR1.
Measu r ement of cu r r ents via ITAC
In order to do current measurements via pin ITAC, all feedback loops (IM-filters and TH-
filters) should be disabled. To simplify the formulas, the programmable receive and
transmit gain is disabled.
This is done by set t ing t he following bits:
Register BCR4: AR-DIS = 1, AX-DIS = 1, TH-DIS = 1,
IM-DIS = 1, FRR-DIS = 1, FRX-DIS = 1
Regis t er T ST R 4: OPIM-AN = 1, OPI M -4M = 1
Register LMCR1: TEST-EN = 1
Table 33 KINTAC S et ti ng T able
LM-AC KINTAC
01
1½
::
61/64
71/128
UdBm0 20 LMResult π
2K
INT
×NSamples
×
-------------------------------------------------------------
×
è
æö
log×3.14+=
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 119 2000-07-14
Preliminary
This setting results in a receive gain of 11.88 dB caused by the internal filters. Based on
this a factor KAD (analo g to digital) can be defined:
Transversal current IRMS me asured at SLIC:
In order no t to ov erloa d th e ana log inpu t, th e m aximu m A C tran sver sal curre nt may no t
be hig her than 9 mA rms.
Usage of Tone Generator as Signal Source
To simplify the f ormulas , the programmable receive and transmit gain is disabled.
This is done by set t ing t he following bits:
Register BCR4: AR-DIS = 1, AX-DIS = 1, TH-DIS = 1,
IM-DIS = 1, FRR-DIS = 1, FRX-DIS = 1
Regis t er T ST R 4: OPIM-AN = 1, OPI M -4M = 1
Register LMCR1: TEST-EN = 1
The tone generator level is influenced by a factor KTG which is set in the tone generator
coef ficient s. The internal filter attenuation is 2.87 dB.
RITAC Sense resistor for AC transversal current (RIT1 +R
IT2)1150Ω
KAD Constant factor from Analo g to Digital 3.272 V–1
VADC Voltage at A/D c onverte r refered to digital f u lls c ale 1.2 V
KIT Valu e of th e c ur r ent divider for tr ansver sal curre nt 50
KAD 10
filterAD
20
--------------------
VADC
---------------------- 1011.88 V
20
--------------------
1.2
-----------------------3.272 V1–
===
IRMS LMResult KIT π××
KAD RITAC KINTAC NSamples 22×××××
------------------------------------------------------------------------------------------------------------------LMResult
KINTAC NSamples
×
-------------------------------------------------- 14.76 mA×==
KDA VDAC 10– 2.87
20
---------------- Trapez
2
--------------------KAC SLIC,
××× 1.2 10– 2.87
20
---------------- 1.05
2
----------6
×××==
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 120 2000-07-14
Preliminary
Output voltage between Tip and Ring:
VOUT =K
DA *K
TG
The by t es below are valid for to ne generat or T G1 an a freq uency of 1 000 Hz.
CRAM:
Addr es s 0x38: 0x 08
Addr ess 0x39: T1 1G/0
Addr ess 0x40: T1 3G/T12G
Addr es s 0x41: 0x 05
Addr es s 0x42: 0x B3
Addr es s 0x43: 0x 01
T11G, T12G and T13G are 4 bit nibbles which control the amplitude of the tone
generator TG1.
KDA Constant factor from Digital to Analog 3.84 Vrms
KAC,SLIC Amplification factor of the SLIC 6
VDAC Voltage at D/A converter refered to digital f ulls cale 1.2 V
Trapez Crestfactor of the trapazoidal signal 1.05
Table 34 KTG Setting Table
T11G T12G T13G KTG
8917/8
808½
818¼
8:8:
8581/64
8681/128
8781/256
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 121 2000-07-14
Preliminary
4.8.2.7 Levelmeter Threshold
For the levelmeter res ult a thres hold can be set. Wh en the resul t exc eeds the thre s hold
then bit LM-THRES in register INTREG 2 is set to '1'. It is also possible to activate an
interrupt when the LM-THRES bit changes by setting the bit LM-THM (levelmeter
threshold mask bit) in register LMCR2 to '0'.
The lev elm eter th res hold can be c a lc ulated with DuSLI C OS or taken f rom Table 35.
CRAM:
Addr es s 0x32: LMTH2/ LM TH1
Addr es s 0x33: 0/ LM T H3
(LMTH1, LMTH 2 and LMTH 3 are 4 bit nibb les )
Table 35 Threshold Setting Table
LMTH1 LMTH2 LMTH3 Threshold
1 0075.0%
0 1062.5%
8 8050.0%
8 9037.5%
9 0025.0%
8 1012.5%
8 000.0%
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 122 2000-07-14
Preliminary
4.8.2.8 Cu rrent Offset Error Compensation
The current offset error caused by the current sensor inside the SLIC-E/-E2/-P can be
compensated by programming the compensation registers OFR1 and OFR2
accordingly. The current offset error can be measured with the DC levelmeter. The
following settings are necessary to accomplish this:
•The DuSLIC has to be set into the HIRT mode by setting the bits HIR and HIT in
regist er BC R 1 to 1.
In HIRT mode the line-drivers of the SLIC-E/-E2/-P are shut down and no resistors are
switched to the line. As a matter of fact, no current is present in that mode, but the
current s ens or wrongly indic ates a cu rrent flowin g (current offset e rror).
•The DC path for ITRANS current levelmeter must be selected by setting the LM-
SEL[3:0] bits in reg is te r LM CR2 to 01 01 (s ee Table 28).
•The of fset reg is ters OFR1 and OF R 2 m ust be set t o 0000h.
•IOff-Err can be calculated like shown for "ITRANS: any other mode" in Table 31 (see also
example bel ow) .
The current offset error can be eliminated by programming the offset registers OFR1 and
OFR 2 ac c ording to the inverse v alue of th e m easured cu rrent offset error.
Example:
KINTDC =1, N
Samples = 256, LMValue = 0x0605 = 1541
Shor t f o rm :
OFR1=OFFSET-H=0xFF
OFR2=OFFSET-L=0xFA
LMResult LMValue
32768
----------------------1541
32768
---------------- 0.047===
Ioff Err–LMResult 79.66 mA
NSamples KINTDC
×
------------------------------------------------------------×0.047 79.66 mA
256 1
×
-------------------------×0.0146 mA===
OFFSET IOff Err–
79.6 6 mA
------------------------- 32768
×–0.0146 mA
79.6 6 mA
-----------------------------32768×–6–≈0xFFFA== =
OFFSET LMValue
NSamples KINTDC
×
------------------------------------------------------------–=
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 123 2000-07-14
Preliminary
4.8.2.9 Loop Resistance Measurements
The D C loop re sist an ce can b e det erm ine d by su pp lying a cons tant DC v oltag e VTR,DC
to the Ring- and Tip line and measuring the DC loop current via IT pin. The following
step s are necessa ry to accomplish this :
•Program a certain ring offset voltage RO1, RO2, RO3 (see DuSLICOS DC Control
Parameter 2/3).
•Select ring offset voltage RNG-OFFSET[1:0] in register LMCR3 either to 01, 10 or 11.
If 00 is selected, the DC regulation would be still active and would not allow resistance
measurement.
•Choose an operation mode, either Active High (ACTH) or Ring Pause.
•Select the DC path for levelmeter by setting the bits LM-SEL[3:0] in register LMCR2
to 0101 (DC c urrent on IT ).
•The t rans versal c urrent can be d eterm ined by read ing the leve lmet er res u lt reg iste rs
LMRE S1, LMR ES2.
•Based on the known constant output voltage VTR,DC (DC voltage according to
RNG-OFFSET[1:0]) and the measured ITRANS current, the resistance can be
calculated. It should be noted, that the calculated resistance includes also the onboard
resist ors RPROT a nd RSTAB.
In order to increase the accuracy of the result, either the current offset can be
comp ensated o r the meas urement can b e done dif ferentially . The latter o ne eliminat es
the curr ent- and voltage of fse t s.
Figure 49 shows an ex am ple circuit for res is tance measure m ent :
Figure 49 Example Resistance Measurement
duslic_0011_measurement_tip_ring.emf
SLIC-E/-E2/-P SLICOFI-2
IT
IL
DCP
DCN
LINECARD
R
PROT
+ R
STAB
V
TR,DC*
line current sense signal to
be measured
I
LINE
R
PROT
+ R
STAB
R
LINE
* DC Offset Voltage
according to
RNG-OFFSET[1:0]
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 124 2000-07-14
Preliminary
Assumption:
•Loop resistan ce Rloop = 1000 Ω; Rloop =R
LINE +2*R
PROT +2*R
STAB
•Ring offset RO2 = 60 V (CRAM coefficient set accordingly). Ring offset RO2 is
selected by setting bits RNG-OFFSET[1:0] in register LMCR3 to 10.
The exact value for the Ri ng offse t volta ge can be dete rmined from the *.r es result file
gene rat ed by Du SLI C OS du ring the ca lc ulation of the appropriate coeffi cients.
•Select Active High (ACTH) mode by setting the line mode command CIDD/CIOP bits
M2, M1, M0 to 010 . I n ACTH mode hal f of th e r ing offs et vol tage RO2 of e.g. 6 0 V wil l
be present and applied to Ring and Tip.
Sequ ence to determ ine the loop res ist ance Rloop differ ent ially:
•Select DC levelmeter by setting bits LM-SEL[3:0] in register LMCR2 to 0101.
•Read lev elmet er result register s LM R ES1, LMRE S2.
•Switch into reverse polarity mode by setting bit REVPOL in register BCR1 to 1.
•Read lev elmet er result register s LM R ES1, LMRE S2.
If the loop resistor connected between Ring and Tip is 1000 Ω (RLINE +R
PROT +R
STAB),
the expected curren t will be 30 mA, because the actual voltage ap plie d to Ring and Tip
is 30 V. Considering the fact, that the current measurement in reverse polarity mode will
also become inverted, the read results have to be added. The sum of both levelmeter
result s ( norm al- and rev erse polarity ) should therefore be 60 mA cur rent diff erence.
Figure 50 shows the differential measurement method and the elimination of the offsets.
Figure 5 0 Differ ential Resis tance Me asure ment
The following calculation shows the elimination of the voltage and current offset caused
by output stage and current sensor. This differential measurement method both
duslic_0008_differentially.emf
Offsets
V
TIP/RING
dU
dI
expected values measured
values
No rmal P o lari ty
Reverse Polarity
U
offset
I
offset
I
TIP/RING
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 125 2000-07-14
Preliminary
eliminates the offsets caused by the SLIC-E/-E2/-P current sensor and the offset caused
by the DC v olt age output (R ing offset voltage).
Differential Resistance Calculation:
4.8.2. 10 Line Resistance Tip/GND and Ring/GND
The DuSLIC offers the modes of setting either the Tip- or the Ring line to high impedance
or eve n both by se t tin g the bits HIR and HIT in register BC R1 accordingly. While one of
both lines is set to high impedance, the other line is still active and able to supply a known
voltage. The transversal and/or longitudinal current can be measured and the line
imped anc e can be calc ulated .
Becau se of one line (Tip or Ring) being high im pedance, th ere is only current flo w ing in
either Tip or Ring line. This causes the calculated current (according Table 31) to be half
the actual v alue. Therefore in either HIR o r HIT mode the calculat ed current ha s to be
multiplied by a fac to r of 2.
Imeasure normal()
VTR prog,Voffset
+
R
-----------------------------------------------Ioffset
+=
Imeasure reverse()
V–TR prog,Voffset
+
R
-------------------------------------------------- Ioffset
+=
Imeasure normal()
Imeasure reverse()
–2V
×TR prog,
R
---------------------------------=
R2V
×TR prog,
Imeasure normal()
Imeasure reverse()
–
-------------------------------------------------------------------------------------------- RLINE RPROT RSTAB
++==
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 126 2000-07-14
Preliminary
4.8.2.11 Cap ac i tance Measu r em ents
Capac it ance m easurem ents with the DuSLIC are accomplished by using the integ rated
ramp g enerator func tion. The ra mp generator is capable of ap plying a volta ge ramp to
the Rin g- and Tip lin e with th e f lex ibility of :
–Prog ram m able slopes fr om 30 V/s to 2000 V/ s
–Prog ram m able start - and sto p D C voltage of f s et s via ring offs et s
–Prog ram mable start time of the voltage ramp aft er enabling the lev elm eter function
Figure 51 shows the volt age ram p and the v olt age levels at the Ring and Tip li ne.
The slope of the ramp can be programm ed (refer to CRAM c oef f i c ients). The ring offset
voltages RO1, RO2 and RO3 might be used as start and stop voltages. The ramp starts
for instance at RO1 and stops at RO2. The current can be calculated as
i(t) = CMeasure*dU/dt, where dU/dt is the slope and i(t) is the current which will be
measured by the levelmeter. In order to measure accurate values, the integration has to
start after the current has settled to a constant value. This can be calculated by the time
constant of the ringer load. It is recommended to set the programmable ring generator
dela y higher tha n 3 times the time constant of t he ringer lo ad. When the re is a resis tor
in parallel to the cap acitor (e.g. leakage), it is recommended to measur e symmetrically
around the voltage zero crossing. This can be achieved by programming the ring
generator delay appropriately (see DuSLICOS DC Control Parameter 2/3). The
integration time for the current measurement is determinded by the ring frequency (refer
to CRAM coefficients, see Table 30). After the integration time the measurement
automat icall y stops only wh en the bit LM- ONCE in registe r LMCR1 i s set . Other wise the
levelmeter would continuously measure the current even if the ramp is finished and
turned into its constant voltage position, i.e., that because of the constant voltage no
current will flow .
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 127 2000-07-14
Preliminary
Figure 51 Capacitance Measurement
ezm14053.emf
f
SLIC-PSLIC-E/-E2
V
HR
V
BATH
GND
(
V
HR
+
V
BATH
)/2
TIP
RING
RING
TIP
P rogram m able Voltage S lope
V
DC,Start
V
DC,Stop
LM CR 1: LM -EN
IN TREG 2: LM -O K
IN TREG2 : RE ADY
In t. Pe r io d
T
RING,DELAY
Line C urrent i
S ettlin g o f lin e cur rent i:
Se t ringer de lay T
RING,DELAY
high enough to do the
actual current measurem ent in the settled current
range.
GND
V
BATR
/2
V
BATR
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 128 2000-07-14
Preliminary
Example:
•Assumptions:
–Capacitance as object to be determined: CMeasure =9.8µF
–Resistor RMeasure in series to CMeasure: RMeasure = 6930 Ω
–τ = RMeasure*CMeasure = 67.9 ms
•Calcu lat ing parameter values:
–Choose Ring Offset voltage 1: RO1 = 70 V (Start voltage on Ring/Tip where the
ramp s hould star t ; p rogramm ed by ring offset voltage RO1)
–Choose Ring Offset voltage 2: RO2 = –30 V (End voltage on Ring/Tip where the
ramp s hould stop; program m ed by ring offset voltag e R O2)
–Choos e s lope of ramp while tes t ing: dU / d t = 200 V/s
–Time from start to stop of the ramp from RO1 to RO2 is 100 V/200 V/s = 500 ms
–Time from start to zero cross is 70 V/200 V/s = 350 ms
–Choose Integration time: TI=1/f
RING = 1/100 Hz = 10 ms
–Meas ure arou nd z ero cr os s →=from 345 ms to 355 ms
–TRING,DELAY is programmed to 345 ms
–Chec k ring generator de lay : TRING,DELAY > 3*τ = 204 ms →=OK!
–Expec t ed c urrent i = CMeasure*dU/dt = 1.96 mA
–Choos e c urrent for LM off-hook th res hold ILM,DC =2mA
Note: A current of 2 m A w ill result in LMResult = 0.5 (half of th e fullsca le v alue)
Program Sequence:
•Set the fo llowing parameter values:
•Integration time TI=1/f
RING = 1/100 Hz = 10 ms
•Select the DC l ev elmete r by settin g bit s LM-SEL[ 3: 0] in regist er LM C R2 to 01 01
•Exec ute the lev elmeter only onc e by sett i ng bit LM -ON CE in register LMCR1 to 1.
•Apply Ring Offset voltage RO1 to Ring and Tip line by setting bits RNG-OFFSET[1:0]
in regi ster LMCR3 to 01.
•Enable t he ramp ge nerator by s et tin g bit R AMP-EN in register LM C R2 to 1.
Parameter Symbol & Value DuSLICOS
Slop e of ram p while testing dU/dt = 200 V/s DC C ontrol Pa ram eter 3/3
Rin g frequ ency fRING = 100 Hz DC Control Parameter 2/3
Ring generator delay T RING,DELAY = 345 ms DC Control Pa rameter 2/3
Ring offset voltage 1 RO1 = 70 V DC Control Parameter 2/3
Ring offset voltage 2 RO2 = –30 V DC Control Parameter 2/3
Current for LM off-hook
threshold ILM,DC = 2 mA DC Control Parameter 2/3
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 129 2000-07-14
Preliminary
•Apply Ring Offset voltage RO2 to Ring and Tip line by setting bits RNG-OFFSET[1:0]
in regi ster LMCR3 to 10.
•Enab le t he levelm et er by sett ing bit LM -EN in regist er LM C R1 to 1 .
–Comment: The voltage ramp starts at RO1 and ramps up/down until RO2 is
achieved. After the integration time, the result will be stored within LMRES1 and
LMRES2 registers.
•Read the result regist ers LMR ES1 an d LMRES2
The act ual current I CMeasure amounts to:
The capa citance CMeasure calc ulates as :
Example:
LMValue = 0x3AF2 = 15090
LMResult =0.4605
ICMeasure = 2*2 mA*0.4605 = 1.842 mA
CMeasure = 1,842 mA/200 V/s = 9.21 µF
4.8.2.12 Line Capacitance Measurements Ring and Tip to GND
The voltage ramp can be applied to either line, whereas the other line is set to high
impedance by setting bits HIR and HIT in register BCR1 accordingly. That way
capac i t ance measurem ents from R i ng and Tip to GND ma y be accom plished.
Because of one line being high impedance, the actual line current will be twice the
calcu lat ed one (m ultiplication by a fac t or of 2 nec essa ry ).
4.8.2.13 Foreign- and Ring Voltage Measurements
The DuSLIC supports two user-programmable input/output pins (IO3, IO4) which can be
used f or m easurin g external volta ges . If t he pins IO3 and/or IO4 are led properly over a
voltage divider to the Ring- and Tip wire, foreign voltages from external voltage sources
supplied to the lines can be measured on either pin, even a differential measurement will
be supported (IO4-IO3). The selection of which input information shall be taken for the
meas uremen t is done v ia bit s LM-SEL[ 3:0] in configuration re gis t er LMCR2 (Table 36).
ICMeasure 2I
LM DC,
×LMResult
×=
CMeasure ICMeasure
dU
dt
--------
-------------------------=
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 130 2000-07-14
Preliminary
The m eas urement is accom plishe d by the D C lev elmete r fu nc tion.
Figure 52 Foreign Voltage Measurement Principle
Figure 52 shows the connection and external resistors used for supporting foreign
volta ge m easure m ent s at th e Ring and T ip lines.
Since the pins IO3 and IO4 support analog input functionality and are limited to a certain
volt age ra nge of VVCM ± 1.0 V (typ. 1.5 V ± 1.0 V), the values for the voltage divider has
to be determined ac c ording to following conditions :
•Maximum lev el of the exp ec ted foreign volta ges
•Voltag e range of IO3 and IO4 = VVCM ± 1.0 V
The voltage on IO3 or IO4 is measured with a reference to VCM. Hence an input voltage
of VVCM on either input pin would result into zero output value. Whereas a voltage of
VVCM + 1 V wo uld re sult in to the ne gative full scale value, V VCM –1 V would re sult into
the positive full scale value respectively. For that reason the voltage divider has to be
referen c ed t o VC M. The un k nown foreign voltage VFOREIGN can be calculated as :
Table 36 Measurement Input Selection
LM-SEL[3:0] in
register LMCR2 Measurement Input
1010 Voltage on IO3
1011 Voltage on IO4
1111 Vol tage IO4 –IO3
duslic_0009_foreign_voltage.emf
SLIC-E/-E2/-P SLICOFI-2
IT
IL
ACN / P
DCN / P
LINECARD
AC
DC
FOREIGN
VOLTAGE
SOURCE
VCM
R3
R4
VCM
R2
R1 IO4
IO3
R
PROT
+ R
STAB
R
PROT
+ R
STAB
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 131 2000-07-14
Preliminary
VINPUT =V
IOx –VVCM (refer to Table 31)
VIOx = Voltage on pins IOx (e.g. pins IO3, IO4)
The res is tor direc t ly connec te d t o either R ing or Tip (R 1, R3) sh ould be hi gh enough so
that the loop im pedance will not be affected by them . Several MΩs, e.g. 10 MΩ would
be a reasonable value. The following example illustrates the potential voltage range that
can be measured by ch osing the values as:
•R1 = R3 = 10 MΩ
•R2 = R4 = 47 kΩ
The values given for the m aximum and mi nimum volt age levels are:
•VVCM =1.5V
•VINPUT,max =1V →=VIOX,max =2.5V
•VINPUT,min =–1V →=VIOX,min =0.5V
The voltage r ange wou l d s pan from 215 V to –212 V.
In order to measure small input voltages on IO3/IO4 more accurately the user might
consider to enable the integration function (see Figure 45) by setting bit LM-EN in
register LMCR1 to 1.
In case of measuring the ring voltage supplied to either Ring or Tip or even both
(balanced ringing) pins via IO3 and IO4, the rectifier can be enabled by setting bit
LM-RECT in register LMCR2 to 1.
VFOREIGN VINPUT R1 R2+
R2
----------------------
×VVCM
+=
VFOREIGN max,VINPUT max,R1 R2+
R2
----------------------
×VVCM
+215 V==
VFOREIGN min,VINPUT min,R1 R2+
R2
----------------------
×VVCM
+– 212 V==
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 132 2000-07-14
Preliminary
4.9 Signal Path and Test Loops
The f ollowing figu res show the ma in AC and DC signal path and t he integra ted analog
and d igit al loops of D uSLIC- E/ - E2/-P, Du SLIC-S and Du SLIC-S 2.
Please note the interconnections between the AC and DC pictures of the respective
chip set.
4.9.1 Test Loops DuSLIC -E/-E2/ -P
Figure 53 AC Test Loops DuSLIC-E/-E2 /-P
TG
MU-LAW
LIN
HPX1AX1FRXLPX
EXP
+AR1
TG
HPRFRRLPR
TH
HPX2AX2
AR2
COR8
PCM16K
COX16
AC-DLB-32K
COR-64
AC-DLB-128K
DAC
ADC
IM2
OPIM_4M
POFI
PREFI
OPIM_AN
AC-DLB-4M
PCM16K
16K
AX-DIS
AR-DIS
TH-DIS
LPRX-CR AX-DIS
FRX-DIS HPX-DIS
PD-AC-GN PD-AC-AD
HIM-AN
PD-AC-PO PD-AC-DA
IM-DIS
PTG,
TG1-EN,
TG2-EN
AR-DIS
HPR-DIS
FRR-DISLPX-CR
MU-LAW
LIN
LM-AC
AC-DLB-8K
LM-VAL*
CMP
LM-DC
LM2PCM
LM-SEL[3:0]
LM-NOTCH
LM-FILT
LM-EN
PCM2DC
HPX-DIS
TTX
Gen.
TTX-12K
TTX-DIS
+
IM3
+
TTX
Adapt.
TTX-12K
TTX-DIS
PD-TTX-A
+
+
PD-AC-PR
AC-XGAIN
ITAC
ACN/ACP
a
b
a
b
c
Programmable via CRAM
Not Programmable
SWITCH
SWITCH
Always available
Available only when bit
TEST-EN = 1
*LM-VAL-H[7:0]
LM-VAL-L[7:0]
d
IM1
PCM IN:
Receive Data
from PCM or
IOM-2 Interfa ce
PCM OUT:
Transmit Data
to PCM or
IOM-2 Interface
duslic_0022_intstru_slicofi2_a.wmf
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 133 2000-07-14
Preliminary
Figure 54 DC Test Loops DuSLIC-E/-E2 /-P
duslic_0022_intstru_slicofi2_b.wmf
PD-DC-AD
DC
PREFI
DC
ADC
PD-DC-PR
IT
IL
IO3
IO4
IO4 – IO3
VDD
Offset
LP
DC-HOLD
RAMP-EN
RAMP +
Hook
LM-DC
RO1
RO1
DC
Char. RG RO1
+
+
LM-EN
LM-RECT
RTR-SEL
RNG-OFFSET[1:0]
PCM2DC
DCN/DCP
c
Programmabl e via CRAM
Not Programm abl e
PD-DC-DA
PD-DCBUF PC-POFI-HI
DC
POFI
DC
BUF DC
DAC
LM-SEL[3:0]
SWITCH
SWITCH
Always available
Available onl y when bit
TEST-EN = 1
IT PD-OFHK
OFFHOOK
COMP
IL PD-GNKC
GNK
COMP
C1
PD-HVI
HV-INT.
C2
OVERT.
COMP
PD-OVTC
d
*OFFSET-H[7:0]
OFFSET-L[7:0]
OFFSET*
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 134 2000-07-14
Preliminary
4.9.2 Test Loops DuSLIC -S/-S2
The AC test loops for DuSLIC-S (Figure 55) and DuSLIC-S2 (Figure 56) are different
since Teletax (TTX) is not available with SLICOFI-2S2. The DC test loops are identical.
Figure 55 AC Test Loops DuSLIC-S
duslic_0023_intstru_slicofi2S_c.wmf
TG
MU-LAW
LIN
HPX1AX1FRXLPX
EXP
+AR1
TG
HPRFRRLPR
TH
HPX2AX2
AR2
COR8
COX16
AC-DLB-32K
COR-64
16K
AX-DIS
AR-DIS
TH-DIS
LPRX-CR AX-DIS
FRX-DIS HPX-DIS
PTG,
TG1-EN,
TG2-EN
AR-DIS
HPR-DIS
FRR-DISLPX-CR
MU-LAW
LIN
AC-DLB-8K
CMP
PCM2DC
HPX-DIS
a
b
c
PCM IN:
Receive Data
from PCM
or IOM-2 Interface
PCM OUT:
Transmit Data
to PCM
or IOM-2 Interface
AC-DLB-128K
DAC
ADC
IM2
OPIM_4M
POFI
PREFI
OPIM_AN
AC-DLB-4M
PD-AC-GN PD-AC-AD
HIM-AN
PD-AC-PO PD-AC-DA
IM-DIS
TTX
Gen.
TTX-12K
TTX-DIS
+
IM3
+
TTX
Adapt.
TTX-12K
TTX-DIS
PD-TTX-A
+
+
PD-AC-PR
AC-XGAIN
ITAC
ACN/ACP
a
b
Programmable via CRAM
Not Pr ogramma b l e
SWITCH
SWITCH
Always available
Available only w hen bit
TEST-EN = 1
IM1
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 135 2000-07-14
Preliminary
Figure 56 AC Test Loops DuSLIC-S2
TG
MU-LAW
LIN
HPX1AX1FRXLPX
EXP
+AR1
TG
HPRFRRLPR
TH
HPX2AX2
AR2
COR8
COX16
AC-DLB-32K
COR-64
AC-DLB-128K
DAC
ADC
IM2
OPIM_4M
POFI
PREFI
OPIM_AN
AC-DLB-4M
16K
AX-DIS
AR-DIS
TH-DIS
LPRX-CR AX-DIS
FRX-DIS HPX-DIS
PD-AC-GN PD-AC-AD
HIM-AN
PD-AC-PO PD-AC-DA
IM-DIS
PTG,
TG1-EN,
TG2-EN
AR-DIS
HPR-DIS
FRR-DISLPX-CR
MU-LAW
LIN
AC-DLB-8K
CMP
PCM2DC
HPX-DIS
IM3
+
+
PD-AC-PR
AC-XGAIN
ITAC
ACN/ACP
a
b
a
b
IM1
c
Programmable via CRAM
No t P r o grammab le
SWITCH
SWITCH
Always available
Available only when bit
TEST-EN = 1
PCM IN:
Receive Data
from PCM
or IO M-2 Inte r face
PCM OUT:
Transmit Data
to PC M
or IOM-2 Interface
duslic_0023_intstru_slicofi2S_a.wmf
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 136 2000-07-14
Preliminary
Figure 57 DC Test Loops DuSLIC-S/-S 2
duslic_0023_intstru_slicofi2S_b.wmf
PD-DC-AD
DC
PREFI
DC
ADC
PD-DC-PR
LP
+
Hook
RO1
RO1
DC
Char. RG RO1
+
+
RTR-SEL
RNG-OFFSET[1:0]
PCM2DC
DCN/DCP
c
Programmable via CRAM
Not Programmabl e
PD-DC-DA
PD-DCBUF PC-POFI-HI
DC
POFI
DC
BUF DC
DAC
SWITCH
SWITCH
Always available
Available only when bit
TEST-EN = 1
IT PD-OFHK
OFFHOOK
COMP
IL PD-GNKC
GNK
COMP
C1
PD-HVI
HV-INT.
C2
OVERT.
COMP
PD-OVTC
OFFSET*
*OFFSET-H[7:0]
OFFSET-L[7:0]
IT
DuSLIC
Oper ational Desc r ipt i o n
Data Sheet 137 2000-07-14
Preliminary
4.10 Caller ID Buffer Handling of SLICOFI-2
This chapter intends to describe the handling of the caller ID buffer and the
corresponding handshake bits in th e interru pt r egister s.
Programming Sequence
In orde r to send a call er ID inform ation over the telephone li ne the following sequence
should be programmed between the first and the second ring burst. The initialization part
of the c oeffici en ts i n the POP r egi ster s 43h to 4Ah mu st be do ne pr ior to that sequ ence .
1. Enable the exten ded feat ure DSP in register XCR (ED SP-EN = 1)
2. Enable t he c aller ID sender fea t ure in regist er BCR 5 (C I S -EN = 1)
3. Wait for an interrupt.
4. R ead out all 4 interru pt register s to serv e the int errupt and check th e C IS - R EQ bit.
5. I f this bi t is se t, se nd at least BR S + 2 b ytes (see PO P regis ter C IS-BR S) of caller I D
data but not m ore th an 48 byt e s to the caller ID send er buffer re gis ter CIS-D AT.
6. W ait for t he next in terrupt and chec k again the CIS -R E Q bit.
7. If this bit is set, send the next data to the caller ID-data buffer but not more than (48 –
BRS) bytes. CIS-REQ bit gets reset to zero, if the data buffer is filled again above the
Caller ID sender buffer request size (BRS).
8. R epeat s t eps 6 and 7 as long as th ere is dat a to be sent.
9. Right after sending the last data byte to the caller ID sender buffer, set the bit CIS-
AUTO to 1 and the bit CIS-EN t o 0. After pro cessing t he last bit the c aller ID sen der
will stop automatically and set the CIS-ACT bit in INTREG4 to zero. No more CIS
interrupt will be generated until the caller ID sender will be enabled again (interrupt
bits: CI S-BO F , C I S-BUF a nd C I S-REQ).
The end of the CID transmission can also be controlled by not setting CIS-AUTO and
leaving CIS-EN at one. If the caller ID buffer gets empty, an interrupt is generated to
indicate bu ffe r under flo w (CIS-BUF). If CIS-BUF is set, se t CIS - EN to ze ro with at least
1 ms delay, in order to allow to send th e last bit of caller ID data.
In case of errors in th e handl ing of the CI D data buff er CIS-B UF (buff er under flow) and
CIS-BOF (buffer overflow) indicate these errors. Please stop CID transmission in any of
these cases since unpredictable results may occur.
Note: CID data will be sent out LSB first
If CIS-FRM is set to one: seizure and mark bits are generated automatically (according
to the settings of CIS-SEIZ-H/L and CIS-MARK-H/L) as well as start and stop bits for
every byte
DuSLIC
Interfaces
Data Sheet 138 2000-07-14
Preliminary
5 Interfaces
The DuSLIC connects the analog subscriber to the digital switching network by two
different types of digital interfaces to allow for the highest degree of flexibility in different
applications:
•PCM interf ac e c o m bined with a se rial microcontr oller interfac e
•IOM-2 interface.
The PCM/IOM-2 pin selects th e int erf ace mode.
PCM/IOM-2 = 0: The IO M - 2 interf ace is se lec ted.
PCM/IOM-2 =1: The PCM/µC interface is sel ec t ed.
The analog TIP/RIN G interfa ce connects th e DuSLIC to the subs c r iber.
5.1 PCM Interface with a Serial Microcontroller Interface
In PCM/µC interface mode, voice and control data are separated and handled by
dif ferent pi ns of the SLICOFI-2x. Voice data are transferred via the PCM highways while
cont rol data are using t he m icroco nt r oller interfac e.
5.1.1 PCM Interface
The serial PC M interface is used to transfer A-law or µ-law-compressed voice data. In
test mode, the PCM interface can also transfer linear data. The eight pins of the PCM
interface are used as follows (two PCM highways):
The FSC pulse identifies the beginning of a receive and transmit frame for both
channe ls. Th e PCLK cloc k sign al sync hro nize s the da ta tran sfer on the DXA (DXB) an d
DRA (DRB) lines. On all channels, bytes are serialized with MSB first. As a default
setting, the rising edge indicates the start of the bit, while the falling edge is used to buffer
the content s o f th e received data on DR A (DRB). If double clock rate is sele ct ed (PC LK
PCLK: PCM Clock, 128 kHz to 8192 kHz
FSC : Frame Sy nc hronization C loc k, 8 kH z
DRA: Receive Data Input for PCM Highway A
DRB: Receive Data Input for PCM Highway B
DXA: Transmit Data Output for PCM Highway A
DXB: Transmit Data Output for PCM Highway B
TCA: Tra nsm i t Control Output for PC M High way A, A ctive low du ri ng
transmission
TCB: Tra nsm i t Control Output for PC M High way B, A ctive low du ri ng
transmission
DuSLIC
Interfaces
Data Sheet 139 2000-07-14
Preliminary
clock rate is twice the data rate), the first rising edge indicates the start of a bit, while, by
default, the second falling edge is used to buffer the contents of the data line DRA (DRB).
Figure 58 Gen eral PCM Interfa c e Timi ng
The data rate of the interface ca n vary from 2* 128 kbit/s to 2*8192 kbit/ s (two high ways).
A frame may consist of up to 128 time slots of 8 bits each. The time slot and PCM
ezm14046.wmf
FSC
PCLK
DRA
DXA
125 µs
TCA
Detail A
012 31
3
High 'Z' High 'Z'
FSC
PCLK
DRA
DXA
TCA
High 'Z'High 'Z'
Voice
Data
Voice
Data
01723456
01 723456
Bit
Clock
Time Slot Time Slot
DETAIL A:
DuSLIC
Interfaces
Data Sheet 140 2000-07-14
Preliminary
highway assignment for each DuSLIC channel can be programmed. Receive and
trans mit time sl ot s can also be programmed indiv i dually.
When DuSLIC is transmitting data on DXA (DXB), pin TCA (TCB) is activated to control
an ext ernal drivin g device .
The DRA/B and DXA/B pins may be connected to form a bidirectional data pin for special
purposes, e.g., for the Serial Interface Port (SIP) with the Subscriber Line Data (SLD)
bus. The SLD approach provides a common interface for analog or digital per-line
components. For more details, please see the “ICs for Communications”1) User’s
Manual availa ble from Infi neon Technologies on reques t .
Table 37 shows PCM interface examples; other frequencies (e.g., 1536 kHz) are also
possible.
1) Ordering No. B115-H6377-X-X-7600, published by Infineon Technologies.
Table 37 SLICOFI-2x PCM Interface Configuration
Clock Rate PCLK
[kHz] Single/Double
Clock [1/2] Time Slots
[per highway] Data Rate
[kbit/s per hi gh way]
1281 2128
2562 2128
2561 4256
5122 4256
5121 8512
7682 6384
768 1 12 768
1024 2 8 512
1024 1 16 1024
2048 2 16 1024
2048 1 32 2048
4096 2 32 2048
4096 1 64 4096
8192 2 64 4096
8192 1 128 8192
f1f/64f
f2 f/128 f/2
Valid PCLK clock rates are: f=n×64 kHz (2 ≤n≤128)
DuSLIC
Interfaces
Data Sheet 141 2000-07-14
Preliminary
Figure 59 Setting of Slopes in Register PCMC1
FSC
PCLK
PCLK
Bit 7
Time - Sl ot 0
receive slope
transmit slope
00 00 00 00
00 01 00 00
10 00 00 00
10 01 00 00
01 00 00 00
01 01 00 00
11 00 00 00
11 01 00 00
DBL-
CLK X-
SLOPE R-
SLOPE NO-
DRIVE SHIFT PCMO[2:0]
DBL-
CLK X-
SLOPE R-
SLOPE NO-
DRIVE SHIFT PCMO[2:0]
DBL-
CLK X-
SLOPE R-
SLOPE NO-
DRIVE SHIFT PCMO[2:0]
DBL-
CLK X-
SLOPE R-
SLOPE NO-
DRIVE SHIFT PCMO[2:0]
DBL-
CLK X-
SLOPE R-
SLOPE NO-
DRIVE SHIFT PCMO[2:0]
DBL-
CLK X-
SLOPE R-
SLOPE NO-
DRIVE SHIFT PCMO[2:0]
DBL-
CLK X-
SLOPE R-
SLOPE NO-
DRIVE SHIFT PCMO[2:0]
DBL-
CLK X-
SLOPE R-
SLOPE NO-
DRIVE SHIFT PCMO[2:0]
Single Clock Mode
Double Clock Mode
PCMC1:
PCMC1:
ezm22011.wmf
DuSLIC
Interfaces
Data Sheet 142 2000-07-14
Preliminary
5.1.2 Control of the Active PCM Channels
The SLICOFI-2x offers additional functionality on the PCM interface including three-
party conferencing and a 16 kHz sample rate. Five configuration bits control, together
with the PCM conf iguration registers, the act ivation of the PCM transmit cha nnels. For
details of the different fu nctions s ee Chapter 6.2.
Table 38 gives an overview of the data transmission configuration of the PCM channels.
X1L is used only when linear data are transmitted. In this case the time slot for X1 is
defined by the number X1-TS from the PCMX1 register. The time slot for X1L is defined
by the number X1-TS + 1.
Note: PCM means PCM-coded data (A-law / µ-law)
HB1, HB2, LB1, LB2 indicate the high byte, low byte of linearly transmitted data
for an 8 kHz (16 kHz) sample rate.
Mode s in ro w s with gray back groun d ar e for test ing pu rposes only.
Table 38 Active PCM Channel Configuration Bits
Control Bits Transmit PCM Channel
PCMX-
EN CONF-
EN CONFX-
EN PCM16K LIN X1 X1L X2 X3 X4
000– – –––––
1000 0PCM––––
1000 1HBLB–––
010––––PCM PCM –
1 1 0 0 0 PCM –PCM PCM –
1 1 0 0 1 HB LB PCM PCM –
001––––PCM PCM PCM
1010 0PCM–PCM PCM PCM
1 0 1 0 1 HB LB PCM PCM PCM
0 1 1 – – – – PCM PCM PCM
1 1 1 0 0 PCM –PCM PCM PCM
1 1 1 0 1 HB LB PCM PCM PCM
1–– 10DS1––DS2 –
1–– 11HB1–LB1 HB2 LB2
DuSLIC
Interfaces
Data Sheet 143 2000-07-14
Preliminary
5.1.3 Serial Microcontroller Interface
The m icrocon troller i nt erface con sists of four lines : CS, DCLK, DIN and DOUT.
There are two different command types. Reset commands have just one byte. Read/
write commands ha ve two comma nd bytes with the address off set in formatio n located in
the secon d byte.
A write command consists of two command bytes and the following data bytes. The first
command byte determines whether the command is read or write, how the command
field is to be used, and which DuSLIC channel (A or B) is written. The second command
byte con t ains the addre ss offset .
A read command consists of two command bytes written to DIN. After the second
command byte is applied to DIN, a dump-byte consisting of ‘1’s is writ ten to DOUT. Dat a
transfer starts with the first byte following the ‘dump-byte’.
Figure 60 Serial Microcontroller Interface Write Access1)
CS A sync hronization signal s t arting a read or writ e access to SLICOFI-2x.
DCLK A clock signal (up to 8.192 MHz) supplied to SLICOFI-2x.
DIN Data input carries data f rom the master device to the SLICOFI-2x.
DOUT Da ta ou tp ut carries data from SLICOFI-2x to a master device.
1) for n data bytes and single byte command
ezm14057.emf
Comm 1st
DCLK
DIN
CS
Comm 2nd Data Data Data
Data Byte 1 Data Byte n
Comm 1st
DIN
CS
n Data Bytes
write command
Singl e Byte
write command
DuSLIC
Interfaces
Data Sheet 144 2000-07-14
Preliminary
Figure 6 1 Serial M icroc o ntroll er Inter face Read A c cess
Programming the Microcontroller Interface Without Clocks at FSC, MCLK, PCLK
The SLICOFI-2x can also be programmed via the µC interface without any clocks
connected to the FSC, MCLK, PCLK pins. This can be useful in Power Down modes
when further power saving on system level is necessary. In this case a data clock of up
to 1.0 24 M Hz can be used on p in D CLK.
Since t he SLICOFI-2x will leave the basic reset routine only if clocks at the FSC, MCLK
and PCLK pins are applied, it is not possible to program the SLICOFI-2x without any
clocks at thes e pins directly after the hardwar e res et or pow er on reset.
Comm 1st
DCLK
DIN
DOUT
CS
Comm 2nd
'Dump
Byte' Data Data Data
Data Byte 1 Data Byte n
*
high i mpe dance
**
ezm14058.wmf
DuSLIC
Interfaces
Data Sheet 145 2000-07-14
Preliminary
5.2 The IOM-2 Interface
IOM-2 defines an industry-standard serial bus for interconnecting telecommunication
ICs for a broad range of a pplicati ons - ty pically ISDN- based applica tio ns .
The IOM-2 bus provides a symmetrical full-duplex communication link containing data,
control/programming and status channels. Providing data, control and status information
via a serial channel reduces pin count and cost by simplifying the line card layout.
The IOM-2 I nt e rf ace co ns ists of tw o data lines and tw o c l oc k lines as follows:
SLICOFI-2x handles data as descr ibed in the I OM -2 spec if ic at ion 1) for an alog de vices .
Figure 62 IOM-2 Int. Timing for up to 16 Voice Channels (Per 8-kHz Frame)
DU: Data Upstream carries data from the SLICOFI-2x to a master device.
DD: Data Downstream carries data from the master device to th e SLICOFI-2x.
FSC : A F r ame Sync hronization S i gnal (8 kHz ) su pplied to SLICOFI-2x.
DCL : A Data Clock Si gnal (2048 k Hz or 409 6 kHz) supplied t o SLICOFI-2x.
1) Available on request from Infineon Technologies.
125 µs
Voice Channel A
Voice Channel A
Voice Channel B
Voice Channel B
FSC
DCL
DD
DU
Detail A
TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7
TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7
Detail A
DD
DU
Monitor Channel
Monitor Channel C/I Channel
C/I Channel
MR MX
MR MX
ezm04104.emf
DuSLIC
Interfaces
Data Sheet 146 2000-07-14
Preliminary
The inf ormation is multiplex ed into f rames, wh ich are tra nsmitte d at an 8-kHz rate. The
frames are subdivided into 8 sub-frames, with one sub-frame dedicated to each
transceiver or pair of codecs (in this case, two SLICOFI-2x channels). The sub-frames
provid e channels for data, programm ing and sta tus informatio n for a single transceive r
or codec pair.
Figu re 63 IOM-2 I nterfa ce T i mi n g (DCL = 4096 kHz, Pe r 8-kHz Frame)
FSC
DCL
DD
DU
4096 kHz
Detail B
Detail B
FSC
DCL
Bit N Bit 0 Bit 1
DD/DU
125 µs
TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7
TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7
ezm04105.emf
DuSLIC
Interfaces
Data Sheet 147 2000-07-14
Preliminary
Figu re 64 IOM-2 I nterfa ce T i mi n g (DCL = 2048 kHz, Pe r 8-kHz Frame)
Both DuS LIC channe ls (see Figure 62) can be assi gned to one of the eight time slots.
Set the IOM-2 time slot selection as shown in Table 39 below by pin-strapping. In this
way, up to 16 channels can be handled with on e IOM-2 interface on the l ine card.
2 MHz or 4 MH z DCL is s electe d by the SEL24 pin:
SEL24 = 0: D C L = 2048 kH z
SEL24 = 1: D C L = 4096 kH z
Table 39 IOM-2 Time Slot Assignment
TS2 TS1 TS0 IOM-2 Operating Mode
0
0
0
0
0
0
1
1
0
1
0
1
Time slo t 0; D C L = 2048, 409 6 k H z
Time slo t 1; D C L = 2048, 409 6 k H z
Time slo t 2; D C L = 2048, 409 6 k H z
Time slo t 3; D C L = 2048, 409 6 k H z
1
1
1
1
0
0
1
1
0
1
0
1
Time slo t 4; D C L = 2048, 409 6 k H z
Time slo t 5; D C L = 2048, 409 6 k H z
Time slo t 6; D C L = 2048, 409 6 k H z
Time slo t 7; D C L = 2048, 409 6 k H z
FSC
DCL
DD
DU
2048 kHz
Detail C
Detail C
FSC
DCL
Bit N Bit 0 Bit 1
DD/DU
125 µs
TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7
TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7
ezm04106.emf
DuSLIC
Interfaces
Data Sheet 148 2000-07-14
Preliminary
5.2.1 IOM-2 Interface Monitor Transfer Protocol
Monitor Channel Operation
The monitor channel is used for the transfer of maintenance information between two
functional blocks. Using two monitor control bits (MR and MX) per direction, the data are
trans fe rred in a comp lete handsh ak e proce dure. T he MR and MX bit s in the fourt h byte
(C/ I channel) of the IOM- 2 frame are used for t he handshake procedu re of the moni tor
channel.
The m onit or chann el t ransmiss ion operates on a ps eudo-as y nc hronous bas is:
Data trans f er (bits) on the bus is sy nc hronized to Frame Sy nc FSC .
Data flow (bytes ) i s asyn chr onou sly contr ol led by th e ha ndshake proc ed ure.
For exa m ple: Data is placed on to the DD-M onitor-C hannel by the monitor transmi t t er of
the master device (DD-MX-Bit is activated, i.e., set to zero). This data transfer will be
repeated within each frame (125 µs rate) until it is acknowledged by the SLICOFI-2x
monitor receiver by setting the DU-MR-bit to zero, which is checked by the monitor
transmitter of the master device. The data rate on IOM-2 monitor channels is 4 kb/s.
Figure 65 IOM-2 Inter f ace Monitor Transfer Pr otoc o l
ezm04125.emf
Monitor
Transmitter
Monitor
Receiver
Monitor
Receiver
Monitor
Transmitter
Master Device SLICOFI-2x
MX
MR
MX
MXMX
MR MR
MR
DD
DU
DuSLIC
Interfaces
Data Sheet 149 2000-07-14
Preliminary
Monitor Handshake Procedure
The monit or chann el w orks in thre e s ta te s
–idle state: A pair of inactive (set to ‘1’) MR and MX bits during two or more
consec utive frames: End of Messag e (EOM)
–sendi ng state: MX bit is acti vate d ( set t o zero ) by the moni tor tr ansmi tt er, toge ther
with data bytes (can b e changed) on the monitor c hannel
–acknowledg ing: MR bit is set to active (set to zero) by the monit or receiver, togeth er
with a data byte remaining in the monitor channel.
A start of a transmission is initiated by a monitor transmitter in sending out an active MX
bit together with the first byte of data (the address of the receiver) to be transmitted in
the monitor channel.
The monitor channel remains in this state until the addressed monitor receiver
ackn owledges the received data by send ing out an acti v e MR bit, wh ic h means that the
data transmission is repeated each 125 µs frame (minimum is one repetition). During this
time the monitor transmitter evaluates the MR bit.
Flow control can only take place when the transmitter’s MX and the receiver’s MR bit are
in active state.
Since the receiver is capable to receive the monitor data at least twice (in two
consecutive frames), it is able to check for data errors. If two different bytes are received,
the receiver will wait for the receipt of two identical successive bytes (last look function).
A collision resolution mechanism (checking whether another device is trying to send data
during the same time) is implemented in the transmitter. This is done by looking for the
inactive (‘1’) phase of the MX bit and making a per-bit collision check on the transmitted
monitor data (check if transmitted ‘1’s are on DU/DD line; DU/DD line are open-drain
lines).
Any abort leads to a reset of the SLICOFI-2x command stack, the device is ready to
receive new com m ands.
To maximum speed during data transfers the transmitter anticipates the fallin g edge of
the rece ivers acknowledg men t .
Due to the prog ramm ing s truc ture, dup lex op eratio n is not poss ible. It is not allowed to
send any data to the SLICOFI-2x, while tr ansmis s i on is act i v e .
Da ta tra n s fer to the SLICOFI-2x starts with a SLICOFI-2x-specific add ress byte (81H).
Attention: Each b yte on the moni to r cha nne l has to be sent tw ice a t lea st acc ord ing to
the IO M -2 Monitor hands hake pro c edure.
DuSLIC
Interfaces
Data Sheet 150 2000-07-14
Preliminary
Figure 66 State Diagram of the SLICOFI-2x Monitor Transmitter
MR … MR bit received on DD line
MX … MX bit calculated an d expecte d on DU line
MXR … MX bit sampled on DU line
CLS … Collision withi n the monitor data byte on DU line
RQT … Request for transmission form internal source
ABT … Abort request/indication
ezm04126.emf
Idle
MX = 1 abort
MX = 1
wait
MX = 1
1
st
byte
MX = 0 EOM
MX = 1
n
th
byte
ack
MX = 1
wait for
ack
MX = 0
MR ° RQT
MR ° MXR
MR + MXR MXR
MR ° MXR
initial
state
MR ° RQT
MR
MR
MR ° RQT
MR
MR ° RQT
MR ° RQT
MR
CLS/ABT
any st at e
DuSLIC
Interfaces
Data Sheet 151 2000-07-14
Preliminary
Figure 67 State Diagram of the SLICOFI-2x Monitor Receiver
MR … MR bit calc ulated an d t rans m it t ed on DU line
MX … MX bit received data downstr eam (DD line)
LL … Last lock of monitor byte received on DD line
ABT … Abort indicat ion to int e rnal source
ezm04127.emf
Idle
MR = 1
1
st
byte
rec.
MR = 0
abort
MR = 1
byte
valid
MR = 0
new byte
MR = 1
n
th
byte
rec.
MR = 1
wait
for LL
MR = 0
initial
state
MX
MX ABT
any
state
MX
MX ° LL
MX
MX ° LL
MX ° LL
MX
MX
MX MX ° LL
MX ° LL wait
for LL
MR = 0
MX
MX
MX ° LL
DuSLIC
Interfaces
Data Sheet 152 2000-07-14
Preliminary
Address Byte
Messages t o and from the SLICOFI-2x start with the following byte:
5.2.2 SLICOFI-2x Identification Command (only IOM-2 Interface)
In order to unambiguously identify different devices by software, a two-byte identification
command is defined for analog line IOM-2 devices. A device requesting the identification
of the SLICOFI-2x will send the followin g two byte co de :
Each device will then respond with its specific identification code. For the SLICOFI-2x
this two byte identification code is:
5.3 TIP/RING Interface
The TIP/RING interface is the interface that connects the subscriber to the DuSLIC. It
meets the ITU-T recommendation Q.552 for a Z interface and applicable LSSGR.
For the performance of the TIP/RING interface see Chapter 7.5 and Chapter 7.6, for
appl ication circuits s ee Chapter 8.
Bit 76543210
10000001
10000000
00000000
10000000
10000101
DuSLIC
Interfaces
Data Sheet 153 2000-07-14
Preliminary
5.4 SLICOFI-2S/-2S2 and SLIC-S/-S2 Interface
The SLIC-S/-S2 PEB 4264/-2 operates in the following modes controlled by a ternary
logic s ignal at the C 1 and C2 input:
Tabl e 40 SLI C - S/ -S2 Inte rface C od e
C2 (Pin 17)
LMH
C1 (Pin 18) L1)
1) no “Overtemp” signaling possible via pin C1 if C1 is low.
PDH PDRHL PDRH
MACTL ACTH ACTR
Hunused HIT HIR
Table 41 SLIC-S/-S2 Modes
SLIC Mode Mode Description Used SLIC-S/-S2 Battery
Voltage
PDH Power Down High Impedance VBATH
PDRH Power Dow n Resistive High VBATH
PDRHL Powe r Down Resistive High Loa d VBATH
ACTL Active Low VBATL
ACTH Active High VBATH
ACTR Active Ring VBATH, VHR
HIT High Impedance on TIP VBATH, VHR
HIR High Impedance on RING VBATH, VHR
DuSLIC
Interfaces
Data Sheet 154 2000-07-14
Preliminary
Active (ACTL, ACTH): These are the regular transmit and receive modes for voice
band. Th e li ne dri v i ng sect i on is oper ated be tween VBATL, VBATH and VBGND.
Active Ring (ACTR): In order to p rovide a balanced ring signal of up to 45 Vrms or to
drive longer telephone lines, an auxiliary positive battery voltage VHR is used, making
possible a higher voltage across the line. Transmission performance remains
unc hange d c o m p ared with Active modes.
The Power Down mode PDRH is intended to reduce the power consumption of the
linecard to a minimum: the SLIC-S/-S2 is switched off completely, no operation is
available except off-hook detection.
With respe ct to the out put impe dance of TI P and RING, two Power D own mod es have
to be dist inguishe d:
PDRH provides a connection of 5 kΩ each from TIP to VBGND and RING to VBATH,
respectively, while the outputs of the buffers show high impedance. The current through
thes e resistors is sensed and transferred to the IT pin to a llow off-hook su pervision.
PDRHL is used as a transition state at a mode change from PDRH or PDH to ACTH
mode (automatically initiated by SLICOFI-2S/-2S2 at a mode change).
High Impedance (HIR/HIT): In this mo de each of the lin e output s can b e program med
to sh ow high imp edance. HI T switche s off the T IP buffer, whi le the cu rrent throu gh the
RING output still can be measured by IT or IL. Programming HIR switches off the RING
buffer.
DuSLIC
Interfaces
Data Sheet 155 2000-07-14
Preliminary
Figure 68 Interface SLICOFI-2S/-2S2 and SLIC-S/-S2
Capac it or and resisto r values ar e specified in Chapter 8.
ACNA
DCNA
ACPA
DCPA
AGND
VDD(3.3 V)
C1A
C
EXT
ACP
C1
VHR
PEB 4264/-2
DCP
DCN
ACN
PEB 3264/-2
C2A
C2
BGND
VCMS
TIP
RING
VBATH
(Sub)
AGND
VDD (+5 V)
VBATL
VCMS
VCMITA
ITACA
ITA
ILA
IT
IL
VCM
I
T
I
R
BIAS Logik
Current
Sensor
(I
R
+ I
T
) / 100
60k
60k
(I
R
- I
T
) / 200
VHI
VHI
VHI
Off-hook
VH
Switch
+
+
-
-
SymFi
VBI
VBAT
Switch
VBI
10k
2k
2k
10k
2k
2k
2k
(I
RO
+ I
TO
) / 10
5k
BGND
PDRHL
PDRH
PDRHL
PDRH
5k
I
TO
I
RO
R
ILA
R
IT1A
R
IT2A
S1, S2 closed:
ACTR, HIT,
HIR
S1
S1
S2
C
ITA
C
VCMITA
ezm29204.emf
DuSLIC
Interfaces
Data Sheet 156 2000-07-14
Preliminary
5.5 SLICOFI-2 and SLIC-E/-E2 Interface
The SLIC-E/-E2 PEB 4265/-2 operates in the following modes controlled by a ternary
logic s ignal at the C 1 and C2 input:
Tabl e 42 SLI C - E/ -E2 Inte rface C od e
C2
LMH
C1 L1)
1) no “Overtemp” signaling possible via pin C1 if C1 is low.
PDH PDRHL PDRH
MACTL ACTH ACTR
HHIRT HIT HIR
Table 43 SLIC-E/-E2 Modes
SLIC Mode Mode Description Used SLIC-E/-E2 Battery
Voltage
PDH Power Down High Impedance VBATH
PDRH Power Dow n Resistive High VBATH
PDRHL Powe r Down Resistive High Loa d VBATH
ACTL Active Low VBATL
ACTH Active High VBATH
ACTR Active Ring VBATH, VHR
HIRT High Impedance on RING and TIP VBATH, VHR
HIT High Impedance on TIP VBATH, VHR
HIR High Impedance on RING VBATH, VHR
DuSLIC
Interfaces
Data Sheet 157 2000-07-14
Preliminary
High Impedance (HIR/HIT/HIRT): In this mode each of the line outputs can be
programmed to show high impedance. HIT switches off the TIP buffer, while the current
through the R ING output still can be measured by IT or IL. Programming HIR switch es
off th e RING buf fer. In the mod e H IR T both buf fers sh ow high im peda nc e.
Active (ACTL, ACTH): These are the regular transmit and receive modes for voice
band. Th e li ne dri v i ng sect i on is oper ated be tween VBATL, VBATH and VBGND.
Active Ring (ACTR): In order to p rovide a balanced ring signal of up to 85 Vrms or to
drive longer telephone lines, an auxiliary positive battery voltage VHR is used, making
possible a higher voltage across the line. Transmission performance remains
unc hange d c o m p ared with Active modes.
The Power Down modes are intended to reduce the power consumption of the linecard
to a minimum : the SL IC -E/-E2 is switched of f completely, no operatio n is available.
With respect to the output impedance of TIP and RING, three Power Down modes have
to be dist inguishe d:
A resistive one (PDRH) provides a connection of 5 kΩ each from TIP to VBGND and RING
to VBATH, respectively, while the outputs of the buffers show high impedance. The
curr ent throu gh these resist ors is sen sed an d transferre d to the IT pin to allow off -hook
supervision.
PDRHL is used as a transition mode at a mode change from PDRH mode to ACTH mode
(automatical l y in i t i a ted by SLICOFI-2 at a mode change from PDRH to ACTH).
The other mode (PDH) offers high impedance at TIP and RING.
DuSLIC
Interfaces
Data Sheet 158 2000-07-14
Preliminary
Figure 69 Interface SLICOFI-2 and SLIC-E/-E2
Capac it or and resisto r values ar e specified in Chapter 8.
ACNA
DCNA
ACPA
DCPA
AGND
VDD(3.3 V)
C1A
C
EXT
ACP
C1
VHR
PEB 4265/-2
DCP
DCN
ACN
PEB 3265
C2A
C2
BGND
VCMS
TIP
RING
VBATH
(Sub)
AGND
VDD (+5 V)
VBATL
VCMS
VCMITA
ITACA
ITA
ILA
IT
IL
VCM
I
T
I
R
BIAS Logik
Current
Sensor
(I
R
+ I
T
) / 10 0
60k
60k
(I
R
- I
T
) / 200
VHI
VHI
VHI
Off-hook
VH
Switch
+
+
-
-
SymFi
VBI
VBAT
Switch
VBI
10k
2k
2k
10k
2k
2k
2k
(I
RO
+ I
TO
) / 10
5k
BGND
PDRHL
PDRH
PDRHL
PDRH
5k
I
TO
I
RO
R
ILA
R
IT1A
R
IT2A
S1, S2 closed:
ACTR, HIT,
HIR, HIRT
S1
S2
C
ITA
C
VCMITA
ezm20204.emf
DuSLIC
Interfaces
Data Sheet 159 2000-07-14
Preliminary
5.6 SLICOFI-2 and SLIC-P Interface
The SLIC-P PEB 4266 operates in the following modes controlled by a ternary logic
signal at the C1, C 2 inputs and a binary logic signal at C 3 input:
Operati n g Modes fo r S LIC-P with Two Battery Voltages (VBATH, VBATL) for Voice
and an Additional Voltage (VBATR) for Ringing:
Table 44 SLIC-P Interface Code
C2
LMH
L1)
1) no “Overtemp” signaling possible via pin C1 if C1 is low.
PDH PDRR PDRRL
PDRHL PDRH
C1 M ACTL ACTH ACTR
HHIRT HIT HIR
ROT ROR
C3 = H or L C3 = H2) C3 = L2)
2) C3 pin of SLIC-P is typically connected to IO2 pin of SLICOFI-2. For extremely power-sensitive applications
using external ringing the C3 pin can be connected to GND. In this case, SEL-SLIC[1:0] in register BCR1 has
to be set to 10.
Table 45 SLIC-P Modes
SLIC Mode Mode Description Used SLIC-P Battery Voltage
PDH Power Down High Impedance VBATR
PDRH Power Dow n Resistive High VBATH
PDRHL Powe r Do wn Loa d Resi st ive Hig h
Load VBATH
ACTL Active Low VBATL
ACTH Active High VBATH
ACTR Active Ring VBATR
HIRT High Impedance on RING and TIP VBATR
ROR Ring on RING VBATR
ROT Ring on TIP VBATR
DuSLIC
Interfaces
Data Sheet 160 2000-07-14
Preliminary
Active (ACTL, ACTH): These are the regular transmit and receive modes for voice
band. Th e li ne dri v i ng sect i on is oper ated be tween VBATL, VBATH and VBGND.
Ringing:
Active Ring (ACTR): In order to p rovide a balanced ring signal of up to 85 Vrms or to
drive longer telephone lines, an additional negative battery voltage VBATR is used,
making possible a higher voltage across the line. Transmission performance remains
unch anged c o m p ared with ACT mo de.
Ring on Tip (ROT): An unbalanced ring signal up to 50 Vrms can be fed to the Tip line.
The R ing line is fixed to a potenti al near VBGND.
Ring on Ring (ROR): An unbalanced ring signal up to 50 Vrms can be fed to the Ring
line. T he T ip line is fixed to a pot ential near VBGND.
PDRH is a power down mode providin g a connecti on of 5 kΩ each from TIP to VBGND
and RING t o VBATH, respectively, while the outputs of the buffers show high impedance.
The c urrent throu gh thes e resi stor s is s ensed and tra nsferre d to the IT pin t o allow off-
hook supervision.
PDRHL is used as a transition mode at a mode change from PDRH mode to ACTH mode
(automatical l y in i t i a ted by SLICOFI-2 at a mode change from PDRH to ACTH).
Operating Modes for SLIC-P with Three Battery Voltages (VBATH, VBATL, VBATR) for
voice and External Ringing
Table 46 SLIC-P Modes
SLIC Mode Mode Description Used SLIC-P Battery Voltage
PDH Power Down High Impedance VBATR
PDRR Power Dow n Resistive Ring VBATR
PDRRL Powe r Do wn Loa d Resi st ive Rin g
Load VBATR
ACTL Active Low VBATL
ACTH Active High VBATH
ACTR Active Ring VBATR
HIRT High Impedance on RING and TIP VBATR
HIT High Impedance on TIP VBATR
HIR High Impedance on RING VBATR
DuSLIC
Interfaces
Data Sheet 161 2000-07-14
Preliminary
Active (ACTL, ACTH, ACTR): These are the regular transmit and receive modes for
voice band. The line driving section is operated between VBATL, VBATH, VBATR and
VBGND.
PDRR is a power down mode providin g a connecti on of 5 kΩ each from TIP to VBGND
and RING t o VBATR, respectively, while the outputs of the buffers show high impedance.
The c urrent throu gh thes e resi stor s is s ensed and tra nsferre d to the IT pin t o allow off-
hook supervision.
PDRRL is used as a transition mode at a mode change from PDRR mode to ACTR mode
(automatical l y in i t i a ted by SLICOFI-2 at a mode change from PDRR to ACTR).
High Impedance (HIR/HIT): In this mo de each of the lin e output s can b e program med
to sh ow high imp edance. HI T switche s off the T IP buffer, whi le the cu rrent throu gh the
RING output still can be measured by IT or IL. Programming HIR switches off the RING
buffer.
For Both Operating Modes of SLIC-P (Ringing and Non Ringing):
The Power Down modes are intended to reduce the power consumption of the linecard
to a min i m um : the PE B 4266 is sw itche d of f completely, no operation i s available.
With respect to the output impedance of TIP and RING, the following Power Down
modes hav e to be dist inguished:
The PDH mode offers high impedance at TIP and RING.
High Impedance (HIRT): The output buffers of the Tip and Ring line show high
impedance.
DuSLIC
Interfaces
Data Sheet 162 2000-07-14
Preliminary
Figure 70 Interface SLICOFI-2 and SLIC-P
Capac it or and resisto r values ar e specified in Chapter 8.
ACNA
DCNA
ACPA
DCPA
AGND
VDD(+3.3 V)
C1A
C
EXT
ACP
C1
DCP
DCN
ACN
PEB3265
IO2A
C3
VCMS
C2A
C2
RING
AGND VDD(+5 V)
TIP
VBATR
(SUB)
VBATH
VBATL
PEB 4266
BGND
VCMS
C
VCMITA
C
ITA
ITA
ILA
IT
IL
VCM
I
T
I
R
BIAS
Current
sensor
(I
R
+ I
T
) / 100
60k
60k
(I
R
- I
T
) / 200
Off-hook
+
+
-
-
SymFi
Battery
switch VBI
VBI
BGND
10k
2k
2k
10k
2k
2k
2k
5k
BGND
PDRR
PDRRL
PDRH
PDRHL
PDRR
PDRRL
5k
(I
R0
+ I
T0
) / 10
Logic
PDRH
PDRHL
I
T0
I
R0
R
IT1A
R
ILA
R
IT2A
S1, S2 clos ed:
ACTR, ROT,
ROR, HIT,
HIR, HIRT
S1
S2
VCMITA
ITACA
ezm14041.emf
DuSLIC
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 163 2000-07-14
Preliminary
6SLICOFI-2x Command Structure and Programming
With the commands described in this chapter, the SLICOFI-2x can be programmed,
configured and tested very flexibly via the microcontroller interface or via the IOM-2
interface monitor channel.
The command structure uses one and two-byte commands in order to ensure a high
flexib le an d quick pr ogramm i ng procedure for the most comm on commands.
Structure of the First Command Byte
The first command byte includes the R/W bit, the addresses of the different channels and
the command type.
Bit 76543210
RD OP ADR[2:0] CMD[2:0]
RD Read Data
RD = 0 Write dat a t o chip.
RD = 1 Read data from chip.
OP Selects the usage of the C M D field
OP = 0 The CMD field works as a CIOP (Command/Indication Operation)
command and acts like the M[2:0] bits located in the CIDD byte of
the IOM Interface (µC in te rfac e mod e on ly). See Table 47.
OP = 1 The CMD fie ld acts as the SOP, COP or POP command descr ibed
below.
.
Bit 76543210
0 0 ADR[2:0] M2 M1 M0
DuSLIC
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 164 2000-07-14
Preliminary
Table 47 M2, M1, M0: General Ope ra t ing Mode
Command/Indication
Operation (CIOP) SLICOFI-2x Operating Mode
(for details see “Operating Mode s fo r the DuSLIC
Chip Set” on Page 78)
M2 M1 M0
1 1 1 Sleep, Power Down (PDRx)
0 0 0 Power Dow n High Impedance (PD H )
0 1 0 Any Active mode
1 0 1 Ringing (ACT R Burst On)
1 1 0 Active with Metering
1 0 0 Ground Sta rt
001Ring Pause
ADR[2:0] Chann e l address for the s ubsequent data
ADR[2: 0] = 0 0 0 Channel A
ADR[2: 0] = 0 0 1 Channel B
(other c odes r e s e r ved for futur e use)
CMD[2:0] Command for programming the SLICOFI-2x (OP = 1) or c om m and
equivalent to the CIDD channel bits M[2:0] in microcontroller interface mode
(OP = 0)
The first four c omma nds have no second co m m and byte follow ing.
All necessary in f orm at ion is pres ent in the firs t c omma nd by t e.
CMD[2:0] = 0 0 0 Soft reset of the chip (Reset routine for all channels will
reset all configur at ion registers , C RA M data is no t
affected).
CMD[ 2: 0] = 0 0 1 So ft res et for the s pecified c hannel A or B in ADR field
CMD[ 2: 0] = 0 1 0 Res y ch ronization of the PC M int erf ac e
(only available when pin PCM/IOM-2 =1)
CMD[ 2: 0] = 0 1 1 res erved f or f ut ure use
The second four commands are followed by a second command byte which
defines additional information, e.g., specifying sub-adresses of the CRAM.
CMD[ 2: 0] = 1 0 0 SOP comman d (s t at us operation , programming and
monitoring of all status-relevant data).
CMD[ 2: 0] = 1 0 1 COP comm and ( co ef f i cient op erat ion, prog rammin g
and monit oring o f al l coeffi cients in the CRA M ).
DuSLIC
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 165 2000-07-14
Preliminary
Structure of the Second Command Byte
The second command byte specifies a particular SOP, COP or POP command,
depending on the CMD[2:0] bits of the first command byte. In the following sections, the
cont ent of this regist er is described for each comm and group.
The second command byte specifies the initial offset for the subsequent data bytes. After
each dat a byte transf erred the int ernal offset is inc remente d automatic ally. Ther efore it
is possible to send a various number of data bytes with one SOP, COP or POP
command . Writin g over read-onl y re gisters w ill not de stroy their contents.
Register De scription Example
At the beginning of each register descript i on a singl e line gives inf orm ation about
•Offs et : O f fs et of reg ister address (hex)
•Name: Shor t name of the regi s ter
•Detailed name: Detailed name of the register
•Rese t v alue: Value of the regist er af t er res et (hex)
“hw” – value depends on specific hardware fuses
•Test status: “T” – the register ha s no ef f ec t unless the TEST-EN bit in
register LMCR1 is set to 1
•Channel selection: “N” – the register effects both SLICOFI-2x channels,
“Y” – the regis ter effe c ts a s pecific SLICOFI-2x channel
The line is or ganized a s follows (with example ) :
CMD[ 2: 0] = 1 1 0 PO P c omman d (PI N E access operati on program m i ng
the EDSP).
CMD[ 2: 0] = 1 1 1 reserved for pro ductio n tests
Offset Name Detailed Name Reset
Value Test Per
Channel
27HTSTR1 Test Regis t er 1 00HTY
DuSLIC
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 166 2000-07-14
Preliminary
6.1 Overview of Commands
SOP STATUS OPERATI ON
COP COEFFICIENT OPERATION
POP POP OPERATION (only SLICOFI-2 PEB 3265 used for DuSLIC-E/-E2 /-P)
Bit76543210
Byte 1 RD 1ADR[2:0] 100
Byte 2 OFFSET[7:0]
Bit76543210
Byte 1 RD 1ADR[2:0] 101
Byte 2 OFFSET[7:0]
Bit76543210
Byte 1 RD 1ADR[2:0] 110
Byte 2 OFFSET[7:0]
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 167 2000-07-14
Preliminary
6.2 SLICOFI-2 Command Structure and Programming
This chapter comprises only the SLICOFI-2 PEB 3265 and therefore the DuSLIC-E,
DuSLIC-E2 and DuSLIC-P chip sets.
6.2.1 SOP Command
The SO P “Status Operation” command prov id es acc ess to the conf igura tion an d st atus
registe rs of the SLICOFI- 2. Common regist ers change the mo de of the entire SLICOFI-2
chip, all other registers are channel-specific. It is possible to access single or multiple
registers. Multiple register access is realized by an automatic offset increment. Write
access to read-only registers is ignored and does not abort the command sequence.
Offset s may ch ange in ne w er v e rsions of the SLICO F I-2.
(All empty register bits have to be filled with zeros.)
6.2.1.1 SOP Register Overview
00HREVISION Revision Number (read-only)
REV[7:0]
01HCHIPID 1 Chip Identification 1 (read-only)
for internal use only
02HCHIPID 2 Chip Identification 2 (read-only)
for internal use only
03HCHIPID 3 Chip Identification 3 (read-only)
for internal use only
04HF USE1 Fuse Register 1
for internal use only
05HPCMC1 PCM Configuration Register 1
DBL-CLK X-SLOPE R-SLOPE NO-DRIVE-0 SHIFT PCMO[2:0]
06HXCR Extended Configuration Register
EDSP-EN ASYNCH-R 0 0 0 0
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 168 2000-07-14
Preliminary
07HINT REG1 Interrupt Register 1 (read-only)
INT-CH HOOK GNDK GNKP ICON VRTLIM OTEMP SYNC-FAIL
08HINTR EG2 Interrupt Register 2 (read-only)
LM-THRES READY RSTAT LM-OK IO[4:1]-DU
09HINTR EG3 Interrupt Register 3 (read-only)
DTMF-OK DTMF-KEY[4:0] UTDR-OK UTDX-OK
0AHINTREG 4 Interrupt Register 4 (read-only)
EDSP-FAIL 0 0 0 CIS-BOF CIS-BUF CIS-REQ CIS-ACT
0BHCHKR1 Checksum Register 1 (High Byte) (read-only)
SUM-OK CHKSUM-H[6:0]
0CHCHKR2 Checksum Register 2 (Low Byte) (read-only)
CHKSUM-L[7:0]
0DHLMRES1 Level Metering Result 1 (High Byte) (read-only)
LM-VAL-H[7:0]
0EHLMRE S2 Level Metering Result 2 (Low Byte) (read-only)
LM-VAL-L[7:0]
0FHFUSE2 Fuse Register 2
for internal use only
10HF USE3 Fuse Register 3
for internal use only
11HMASK Mask Register
READY-M HOOK-M GNDK-M GNKP-M ICON-M VRTLIM-M OTEMP-M SYNC-M
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 169 2000-07-14
Preliminary
12HIOCT L1 I O Control Register 1
IO[4:1]-INEN IO[4:1]-M
13HIOCT L2 I O Control Register 2
IO[4:1]-OEN IO[4:1]-DD
14HIOCT L3 I O Control Register 3
DUP[3:0] DUP-IO[3:0]
15HBCR1 Basic Configuration Register 1
HIR HIT SLEEP-EN REVPOL ACTR ACTL SEL-SLIC[1:0]
16HBCR2 Basic Configuration Register 2
REXT-EN SOFT-DIS TTX-DIS TTX-12K HIM-AN AC-XGAIN UTDX-SRC PDOT-DIS
17HBCR3 Basic Configuration Register 3
MU-LAW LIN PCM16K PCMX-EN CONFX-EN CONF-EN LPRX-CR CRAM-EN
18HBCR4 Basic Configuration Register 4
TH-DIS IM-DIS AX-DIS AR-DIS FRX-DIS FRR-DIS HPX-DIS HPR-DIS
19HBCR5 Basic Configuration Register 5
UTDR-EN UTDX-EN CIS-AUTO CIS-EN LEC-OUT LEC-EN DTMF-SRC DTMF-EN
1AHDSCR DTMF Sender Configuration Register
DG-KEY[3:0] COR8 PTG TG2-EN TG1-EN
1BHreserved
00000000
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 170 2000-07-14
Preliminary
1CHLMCR1 Level Metering Configuration Register 1
TEST-EN LM-EN LM-THM PCM2DC LM2
PCM LM-ONCE LM-MASK DC-AD16
1DHLMCR2 Level Metering Configuration Register 2
LM-NOTCH LM-FILT LM-RECT RAMP-EN LM-SEL[3:0]
1EHLMCR3 Level Metering Configuration Register 3
AC-SHORT-
EN RTR-SEL LM-ITIME[3:0] RNG-OFFSET[1:0]
1FHOFR1 Offset Register 1 (High Byte)
OFFSET-H[7:0]
20HOFR2 Offset Register 2 (Low Byte)
OFFSET-L[7:0]
21HPCMR1 PCM Receive Register 1
R1-HW R1-TS[6:0]
22HPCMR2 PCM Receive Register 2
R2-HW R2-TS[6:0]
23HPCMR3 PCM Receive Register 3
R3-HW R3-TS[6:0]
24HPCMR4 PCM Receive Register 4
R4-HW R4-TS[6:0]
25HPCMX1 PCM Transmit Register 1
X1-HW X1-TS[6:0]
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 171 2000-07-14
Preliminary
26HPCMX2 PCM Transmit Register 2
X2-HW X2-TS[6:0]
27HPCMX3 PCM Transmit Register 3
X3-HW X3-TS[6:0]
28HPCMX4 PCM Transmit Register 4
X4-HW X4-TS[6:0]
29HTSTR1 Test Register 1
PD-AC-PR PD-AC-PO PD-AC-AD PD-AC-DA PD-AC-GN PD-GNKC PD-OFHC PD-OVTC
2AHTSTR2 Test Register 2
PD-DC-PR 0 PD-DC-AD PD-DC-DA PD-DCBUF 0 PD-TTX-A PD-HVI
2BHTSTR3 Test Register 3
0 0 AC-DLB-4M AC-DLB-
128K AC-DLB-
32K AC-DLB-
8K 00
2CHTSTR4 Test Register 4
OPIM-ANOPIM-4MCOR-64COX-160000
2DHTSTR5 Test Register 5
000DC-POFI-
HI DC-HOLD 0 0 0
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 172 2000-07-14
Preliminary
6.2.1.2 SOP Register Description
00HREVISION Revision Number (read-only) curr.
rev. N
Bit76543210
REV[7:0]
REV[7:0] Current revisi on numb er of the SLICOF I-2.
01HCHIPID 1 Chip Identification 1 (read-only) hw N
Bit765 4 3210
for internal use on ly
02HCHIPID 2 Chip Identification 2 (read-only) hw N
Bit765 4 3210
for internal use on ly
03HCHIPID 3 Chip Identification 3 (read-only) hw N
Bit765 4 3210
for internal use on ly
04HFUSE1 Fuse Register 1 hw N
Bit765 4 3210
for internal use on ly
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 173 2000-07-14
Preliminary
05HPCMC1 PCM Configuration Register 1 00HN
Bit765 4 3210
DBL-CLK X-SLOPE R-SLOPE NO-DRIVE-0 SHIFT PCMO[2:0]
DBL-CLK Clock mode for the PCM interface (see Figure 59 on Page 141)
DBL-CLK = 0 Single-clocking is used.
DBL-CLK = 1 Double-clocking is used.
X-SLOPE Transm it s lope (see Figure 59 on Page 141)
X-SLOPE = 0 Transmission starts with rising edge of the clock.
X-SLOPE = 1 Transmission starts with falling edge of the clock.
R-SLOPE Receive slo pe (s ee Figure 59 on Page 141)
R-SLOPE = 0 Data is samp l ed with fallin g ed ge of the cl ock.
R-SLOPE =1 Data is sampled with rising edge of the clock.
NO-
DRIVE-0 Driving mode for bit 0 (only available in s ingle-clock i ng mode).
NO-DRIV E = 0 B i t 0 is dr i ven the en t i re clock peri od.
NO-DRIVE = 1 Bit 0 is driven during the first half of the clock period
only.
SHIFT Shifts the ac cess edges by one cloc k c ycle in do uble-cloc k ing mode.
SHIFT = 0 No shift takes place.
SHIFT = 1 Shift takes place.
PCMO[2:0] The whole PCM timing is moved by PCMO data periods against the FSC
signal.
PCMO[2:0 ] = 0 0 0 No offset is adde d.
PCMO[2:0] =0 0 1 One data period is added.
…
PCMO[2:0] =1 1 1 Sev en data pe riods are a dded.
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 174 2000-07-14
Preliminary
06HXCR Extended Configuration Register 00HN
Bit7 6 5 4 3 210
EDSP-
EN ASYNC
H-R 000 0
EDSP-EN Enables th e Enhanced Digit al Signal Proc essor ED SP.
EDSP-EN = 0 En hanced Digital Signal Proc es s or is switc hed off.
EDSP-EN = 1 En hanced Digital Signal Proc es s or is switc hed on.
ASYNCH-R Enables as y n c hronous ringing in case of ex ternal r inging.
ASYNCH-R = 0 External ringing with zero crossing selected.
ASYNCH-R = 1 Asy nchronous rin ging selec ted.
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 175 2000-07-14
Preliminary
07HINTREG1 Interrupt Register 1 (read-only) 80HY
Bit76543210
INT-CH HOOK GNDK GNKP ICON VRTLIM OTEMP SYNC-
FAIL
INT-CH Interrupt channel bit . This b it indicates t hat the corr es ponding c hannel
caused the last interrupt. Will be automatically set to zero after all interrupt
regist ers were read.
INT-CH = 0 No interrupt in corresponding channel.
INT-CH = 1 Interrupt caused by corresp onding ch annel.
HOOK On/off-hook inform at ion for th e loop in all operating modes, fil tered by t h e
DUP (Data Upstream Persistence) counter and interrupt generation masked
by the H OOK-M bit. A change o f this bit ge nerates an interrupt.
HOOK = 0 On-hook .
HOOK = 1 Off-hook.
GNDK Grou nd-Key or Ground Sta r t inf orm at ion via the IL pin in all active m odes,
filtere d f or AC s uppression by th e DUP counter an d int e rrupt ge neration
mask ed by the GNDK-M bit. A cha nge of th is bit generates an interrupt.
GNDK = 0 No longitudinal current detected.
GND K = 1 Longitudinal current det ected (Ground Key or Ground
Start).
GNKP Grou nd Key pola rity. Indicating the acti v e Ground Key level (p os it iv e/
negative) interrupt generation masked by the GNKP-M bit. A change of this
bit ge nerates an interrupt. This bit c an be used to get inform ation about
interference voltage inf l uence .
GNKP = 0 Negative Gro und Key thre shold lev el active.
GNKP = 1 Positive Ground K ey thresh old level active.
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 176 2000-07-14
Preliminary
ICON Cons tan t cur rent infor matio n. Filte red by DUP-IO coun t er and int er rupt
generation masked by the ICON-M bit. A change of this bit generates an
interrupt.
ICON = 0 Resistive or c onstan t volt age feed ing.
ICON = 1 C ons t ant current f eeding.
VRTLIM Exceeding of a programmed voltage threshold for the TIP/RING voltage,
filtered by the DUP-IO counter and int errupt ge neration ma sked by the
VRTL IM -M bit. A c hange of this bit caus es an interrupt.
The voltage threshold for the TIP/RING voltage is set in CRAM (calculated
with DuSLICO S DC Control Pa rame ter 2/3: Tip-Ri n g Thre sh ol d ) .
VRTL IM = 0 V olt age at Rin g/ T ip is below the limit.
VRTLIM = 1 Voltage at Ring/Tip is above the limit.
OTEMP Thermal overload warning from the SLIC-E/-E2/-P line drivers masked by
the OTEMP-M bit. An interrupt is only generated if the OTEMP bit
changes from 0 to1.
OTEMP = 0 Temperature at SLIC-E/-E2/-P is below the limit.
OTEMP = 1 Temperature at SLIC-E/-E2/-P is above the limit.
In case of bit PDOT-DIS = 0 (register BCR2) the
DuSLIC is switched automa t ically into PDH m od e an d
OTEMP is hold at 1 until the SLICOFI-2 is set to PDH
by a CIOP/CIDD command.
SYNC-FAIL Failure of the Synchronization of the IOM-2/PCM interface. An interrupt is
only gen er ated if the SYNC- FAIL bit chan ges from 0 to1 .
Resy nc h roniza tion of the PCM interface can be don e with the
Resynchronization command (see Chapter 6)
SYNC-FAIL = 0 Synchronization OK.
SYNC-FAIL = 1 Synchronization failure.
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 177 2000-07-14
Preliminary
After a hardware reset the RSTAT bit is set and generates an interrupt. Therefore the
defaul t valu e of INTREG 2 i s 20h. After re a di ng all fo ur int er r upt register s, th e INTREG2
value c hanges to 4Fh.
08HINTREG2 Interrupt Register 2 (read-only) 20HY
Bit76543210
LM-
THRES READY RSTAT LM-OK IO[4:1]-DU
LM-THRES Indica tion whe th e r t he level m et ering resu lt is abov e or below the
threshold set by the CRAM coefficients
LM-THR ES = 0 Level metering re sult is below t hreshold .
LM-THR ES = 1 Level m et ering result is above threshold.
READY Indication whe th er the ram p generat or has finished. An interru pt is only
generated if the READY bit changes from 0 to 1. Upon a new start of the
ramp ge ne r ator, th e bi t i s set to 0. For further info rmatio n r eg ar d i ng soft
reversal s ee Chapter 3.7.2.1.
READY = 0 Ramp generator active.
READY = 1 Ramp generator not active.
RSTAT Rese t st atus since last int er r up t .
RSTA T = 0 No reset has oc curred s inc e t h e last inte rrupt.
RSTA T = 1 Reset ha s occurred sinc e t he last inte rrupt.
LM-OK Level m etering seque nc e has fin is hed. An int e rrupt is only generat ed if
the LM -OK bit ch anges from 0 t o 1.
LM-OK = 0 Level metering result not ready .
LM-OK = 1 Level metering result ready.
IO[4:1]-DU Data on IO pins 1 to 4 filtered by DUP-IO counter and interrupt generation
mask ed by the IO[4:1] - D U-M bits. A ch ange of any of this bits gene rates
an inte rrupt.
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 178 2000-07-14
Preliminary
09HINTREG3 Interrupt Register 3 (read-only) 00HY
Bit76543210
DTMF-
OK DTMF-KEY[4:0] UTDR-
OK UTDX-
OK
DTMF-OK Indication of a valid DTMF Key by the D TM F rece iv er. A change of
this bi t generates an in terrupt .
DTMF-OK = 0 No valid DTMF Key was encountered by the
DTMF receiver.
DTMF-OK = 1 A valid DTMF Key was encountered by the DTMF
receiver.
DTMF-KEY[4:0] Valid DT M F key s decoded by the DTM F re ceiver.
Table 48 Valid DTMF Keys (Bit DTMF-KEY4 = 1)
fLOW [Hz] fHIGH
[Hz] DIGIT DTMF-
KEY4 DTMF-
KEY3 DTMF-
KEY2 DTMF-
KEY1 DTMF-
KEY0
6971209110001
6971336210010
6971477310011
7701209410100
7701336510101
7701477610110
8521209710111
8521336811000
8521477911001
9411336011010
9411209*11011
9411477#11100
6971633A11101
7701633B11110
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 179 2000-07-14
Preliminary
8521633C11111
9411633D10000
UTDR-OK Universal Tone Detection R eceive (e.g., Fax/Modem tone s)
UTDR-OK = 0 No specific tone signal was detected.
UTDR- OK = 1 A specif ic t one signa l w as det ec t ed.
UTDX-OK Universal Tone Detection Transmit (e.g., Fax/Modem tones)
UTDX-OK = 0 No specific tone signal was detected.
UTDX-OK = 1 A spec if ic tone signal was det ec t ed.
Table 48 Valid DTMF Keys (Bit DTMF-KEY4 = 1) (cont’d)
fLOW [Hz] fHIGH
[Hz] DIGIT DTMF-
KEY4 DTMF-
KEY3 DTMF-
KEY2 DTMF-
KEY1 DTMF-
KEY0
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 180 2000-07-14
Preliminary
0AHINTREG4 Interrupt Register 4 (read-only) 00HY
Bit76543210
EDSP-
FAIL 000CIS-
BOF CIS-
BUF CIS-
REQ CIS-
ACT
EDSP-FAIL Indic at i on of a malfunction of the Enhanced Digital Signal Pro cesso r
EDSP.
EDSP-FA IL = 0 Enhanced Di gi tal Signal Pr o c essor EDSP normal
operation.
EDSP-FAIL = 1 Enh anced Di gi tal Signal Proces sor EDSP failu re. It is
nece s sary to res tart this DSP with bit EDSP-E N in the
XCR regis t er s et .
CIS-BOF Caller ID buffer overflow. An interrupt is only generated if the CIS-BOF bit
chang es from 0 to 1.
CIS-BOF = 0 Not data buffer overflow has occurred.
CIS-BOF = 1 Too many bytes have been written to the data buffer for
Caller ID generation. Caller ID generation is aborted and
the buff er is c l eared.
CIS-BUF Caller ID buffer underflow. An interrupt is only generated if the CIS-BUF
bit changes from 0 to 1.
CIS-BUF = 0 Data buffer for C alle r ID ge neration is filled.
CIS-BUF = 1 Data buffer for Caller ID generation is empty
(underflow).
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 181 2000-07-14
Preliminary
CIS-REQ Caller ID da ta reques t . An interru pt is only genera ted if the C IS -R E Q bit
chan ges f rom 0 to 1.
CIS-REQ = 0 Caller ID data buffer requests no data.
CIS-REQ = 1 Caller ID data buffer requests more data to transmit,
when the amount of data stored in the buffer is less than
the buffer request size.
CIS-ACT Caller ID generator active.
This is a st atus b it only. N o interrupt will be generated.
CIS-ACT = 0 Caller ID generator is not active.
CIS-ACT = 1 Caller ID generator is active.
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 182 2000-07-14
Preliminary
0BHCHKR1 Checksum Register 1 (High Byte)
(read-only) 00HY
Bit76543210
SUM-
OK CHKSUM-H[6:0]
SUM-OK Informat ion about the v alidity of the checksum . The che cksu m is
valid if the internal checksu m calculation is finished.
Checksum calculation:
For (cram_adr = 0 to 159) do
cram_dat = cram[cram_adr]
csum[14:0] = (csum[13:0] &1) ‘0’) xor
(‘0000000’ & cram_dat[7:0]) xor
(‘0000000000000’ & csu m[14] & csu m[14])
End
1) “&” means a concatenation, not the logic operation
SUM-OK = 0 CRAM checksum is not valid.
SUM-OK = 1 CRAM checksum is valid.
CHKSUM-H[6:0] CRAM checksum high byte
0CHCHKR2 Checksum Register 2 (Low Byte)
(read-only) 00HY
Bit76543210
CHKSUM-L[7:0]
CHKSUM-L[7:0] CRAM checksum low byte
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 183 2000-07-14
Preliminary
0DHLMRES1 Level Metering Result 1 (High Byte)
(read-only) 00HY
Bit76543210
LM-VAL-H[7:0]
LM-VAL-H[7:0] LM result high byte
(selec t ed by the LM -SEL bits in t he LM CR2 r egis t er)
0EHLMRES2 Level Metering Result 2 (Low Byte)
(read-only) 00HY
Bit76543210
LM-VAL-L[7:0]
LM-VAL-L[7:0] LM result low byte
(selec t ed by t he LM-SE L bit s in the LMCR 2 register)
0FHFUSE2 Fuse Register 2 hw Y
Bit76543210
for interna l us e only
10HFUSE3 Fuse Registe r 3 hw Y
Bit76543210
for interna l us e only
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 184 2000-07-14
Preliminary
The ma sk bi ts in th e mas k regist er only infl uenc e the gen era tion of an inter rupt . Even if
the mask bit is set to 1, the corresponding status bit in the INTREGx registers gets
upda t ed t o s how the current s tatus of the corresp onding ev ent .
11HMASK Mask Register FFHY
Bit76543210
READY
-M HOOK
-M GNDK
-M GNKP
-M ICON
-M VRTLIM
-M OTEMP
-M SYNC
-M
READY-M Mask bit for Ramp Generator READY bit
READY-M = 0 An interrupt is generated if the READY bit changes from
0 to 1.
READ Y-M = 1 Changes of the R EADY bit don’t generate interrupts.
HOOK-M Mask bit for Off-hook Detection HOOK bit
HOOK-M = 0 Each change of the HOOK bit generates an interrup t.
HOOK-M = 1 Changes of t he H O OK bit don’t ge nerate interrupts.
GNDK-M Mask bit for Ground Key Detection GNDK bit
GNDK-M = 0 Each change of the GNDK bit generat es an inte rrupt.
GNDK-M = 1 Chang es of the GN DK bit don’t ge nerate interrupts.
GNKP-M Mask bit for Ground Key Level GNKP bit
GNKP-M = 0 Each ch ange of the GNKP bit generates an interr upt .
GNKP-M = 1 C hanges of th e GN KP bit don’t generate interrupts.
ICON-M Mask bit for Constant C urrent Inform at ion ICON bit
ICON-M = 0 Each change of the IC ON bit g enerates an interrupt.
ICON_M = 1 Changes of the ICO N b it do n’t ge nerate interrupts.
VRTLIM-M Mask bit f or Programmed V olt age Limit VRTLIM bit
VRTLIM -M = 0 Each ch ange of the VR TLIM bit generates an interrupt.
VRTLIM-M = 1 Changes of the VRTLIM bit don’t generate int errup ts .
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 185 2000-07-14
Preliminary
OTEMP-M Mask bit for Th ermal Ov erload W arning OTEMP bi t
OTEMP-M = 0 A change of the OTEMP bit from 0 to 1 generates an
interrupt.
OTEMP-M = 1 A change of the OTEMP bit from 0 to 1 doesn’t generate
interrupts.
SYNC-M Mask bit for Synchronization Failure SYNC-FAIL bit
SYNC-M = 0 A change of the SYNC-FAIL bit from 0 to 1 generates an
interrupt.
SYNC-M = 1 A ch ange of th e SYNC -FAIL bit from 0 to 1 does n ’t
generate interrupt s.
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 186 2000-07-14
Preliminary
The mask bits IO[4:1]-M only influence the generation of an interrupt. Even if the mask
bit is set to 1, the corresponding status bit in the INTREGx registers gets updated to
show the current status of th e c orresponding ev ent.
12HIOCTL1 IO Contro l Register 1 0FHY
Bit76543210
IO[4:1]-INEN IO[4:1]-M
IO4-INEN Input enable for programmable IO pin IO4
IO4-INEN = 0 Input Schmitt trigger of pin IO4 is disabled.
IO4-INEN = 1 Input Schmitt trigger of pin IO4 is enabled.
IO3-INEN Input enable for programmable IO pin IO3
IO3-INEN = 0 Input Schmitt trigger of pin IO3 is disabled.
IO3-INEN = 1 Input Schmitt trigger of pin IO3 is enabled.
IO2-INEN Input enable for programmable IO pin IO2
IO2-INEN = 0 Input Schmitt trigger of pin IO2 is disabled.
IO2-INEN = 1 Input Schmitt trigger of pin IO2 is enabled.
IO1-INEN Input enable for programmable IO pin IO1
IO1-INEN = 0 Input Schmitt trigger of pin IO1 is disabled.
IO1-INEN = 1 Input Schmitt trigger of pin IO1 is enabled.
IO4-M Mask bit for IO4-DU bit
IO4-M = 0 Ea ch ch ange of th e IO4 bit generate s an interru pt .
IO4-M = 1 Changes of the IO4 bit don’t generate interrupts .
IO3-M Mask bit for IO3-DU bit
IO3-M = 0 Ea ch ch ange of th e IO3 bit generate s an interru pt .
IO3-M = 1 Changes of the IO3 bit don’t generate interrupts .
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 187 2000-07-14
Preliminary
IO2-M Mask bit for IO2-DU bit
IO2-M = 0 Ea ch ch ange of th e IO2 bit generate s an interru pt .
IO2-M = 1 Changes of the IO2 bit don’t generate interrupts .
IO1-M Mask bit for IO1-DU bit
IO1-M = 0 Ea ch ch ange of th e IO1 bit generate s an interru pt .
IO1-M = 1 Changes of the IO1 bit don’t generate interrupts .
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 188 2000-07-14
Preliminary
13HIOCTL2 IO Contro l Register 2 00HY
Bit76543210
IO[4:1]-OEN IO[4:1]-DD
IO4-OEN Enablin g output driver of the I O4 pin
IO4-O EN = 0 The out put driv er of the IO4 pin is disabled.
IO4-O EN = 1 The out put driv er of the IO4 pin is en abled.
IO3-OEN Ena bling output driv er of the IO3 pi n
IO3-O EN = 0 The out put driv er of the IO3 pin is disabled.
IO3-O EN = 1 The out put driv er of the IO3 pin is en abled.
IO2-OEN Ena bling output driv er of the IO2 pi n.
If SLIC-P is selected (bits SEL-SLIC [1:0] in register BCR1 set to 01), pin
IO2 cannot be controlled by the user but is utilized by the SLICOF I-2 to
cont rol t he C3 input of SL IC-P.
IO2-O EN = 0 The out put driv er of the IO2 pin is disabled.
IO2-O EN = 1 The out put driv er of the IO2 pin is en abled.
IO1-OEN Ena bling output driv er of the IO1 pi n.
If external ringing is selected (bit REXT-EN in register BCR2 set to 1), pin
IO1 cannot be controlled by the user but is utilized by the SLICOF I-2 to
control the ring re lay.
IO1-O EN = 0 The out put driv er of the IO1 pin is disabled.
IO1-O EN = 1 The out put driv er of the IO1 pin is en abled.
IO4-DD Valu e f or t he program mable I O pin IO 4 if programmed as an output pin.
IO4-DD = 0 The c orrespo nding pin is driv ing a logic 0.
IO4-DD = 1 The c orrespo nding pin is driv ing a logic 1.
IO3-DD Valu e f or t he program mable I O pin IO 3 if programmed as an output pin.
IO3-DD = 0 The c orrespo nding pin is driv ing a logic 0.
IO3-DD = 1 The c orrespo nding pin is driv ing a logic 1.
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 189 2000-07-14
Preliminary
IO2-DD Valu e f or t he program mable I O pin IO 2 if programmed as an output pin.
IO2-DD = 0 The c orrespo nding pin is driv ing a logic 0.
IO2-DD = 1 The c orrespo nding pin is driv ing a logic 1.
IO1-DD Valu e f or t he program mable I O pin IO 1 if programmed as an output pin.
IO1-DD = 0 The c orrespo nding pin is driv ing a logic 0.
IO1-DD = 1 The c orrespo nding pin as driv ing a logic 1.
14HIOCTL3 IO Contro l Register 3 94HY
Bit 76543210
DUP[3:0] DUP-IO[3:0]
DUP[3:0] Da t a U ps t ream Pers is t enc e Counter end value. Res t ric ts the rate
of interru pt s generat ed by th e H OOK bit in the interrupt regis t er
INTREG1. The interval is programmable from 1 to 16 ms in steps
of 1 m s (re s et va lue is 10 m s ).
The DU P[3:0] value af fects t he blocki ng period for ground key
detection (see Chapter 3.6).
DUP-IO[3:0] Da ta Upstr eam Per si s te nce Coun t er en d value for
•the IO pins wh en used a s digital input pins.
•the bit s ICON and VR T LIM in register IN T R EG1.
The int erval is pro gra mm able f rom 0 .5 t o 60. 5 ms in step s of 4 ms
(reset value is 16.5 ms).
DUP[3:0] HOOK
Active,
Ringing
HOOK
Power
Down
GNDK GNDK
fmin,ACsup1)
1) Minimum frequency for AC suppression.
0000 1 2 ms 4 ms 125 Hz
0001 2 4 ms 8 ms 62 .5 Hz
...
1111 16 32 ms 64 ms 7.8125 Hz
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 190 2000-07-14
Preliminary
15HBCR1 Basic Configuration Register 1 00HY
Bit 76543210
HIR HIT SLEEP-
EN REVPOL ACTR ACTL SEL-SLIC[1:0]
HIR This bit modifies differe nt basic modes. In ringing m ode an unbalance d
ringing on the RING wi re (ROR) is enable d. In active mode, high impe dance
on the RING wire is activated (HIR). If the HIT bit is set in addition to the HIR
bit, the HIRT mode is activate d.
HIR = 0 Normal operation (rin ging mode).
HIR = 1 C ontrols SLIC-E /-E2 /-P interfac e and set s the RING wire
to high impedanc e (ac t iv e m ode).
HIT This bit m odifie s di ff eren t basic m odes. In ringing m ode an unbalan c ed
ringing on the TIP wire (ROT) is enabled. In active mode, high impedance on
the TIP wire is performed (HIT).If the HIR bit is set in addition to the HIT bit,
the HIR T m ode is act ivated.
HIT = 0 Normal operation (ringing mode).
HIT = 1 Controls SLIC-E/-E2/-P interface and sets the TIP wire to
high impedance (active mode).
SLEEP-EN Enables Sleep mode of the DuSLIC channel. Valid only in the Power Down
mode of the SLICOFI-2 .
SLEEP -EN = 0 Sleep m ode is disa bled.
SLEEP-EN = 1 Sleep mode is enabled.
REVPOL Revers es the polarit y of DC feed ing
REVP OL = 0 Normal pol arit y .
REVPOL = 1 Reverse polarity.
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 191 2000-07-14
Preliminary
ACTR Sele ct ion of ex tended batter y feeding in Ac t ive mod e. Changes also the
voltage in Powe r Down Resist iv e mod e fo r SLIC-P . In this cas e VBATR for
SLIC-P and VHR –VBATH for SLIC-E/-E2 is used.
ACTR = 0 No extended ba t t ery feeding sel e c te d .
ACTR = 1 Exten ded battery feeding selec te d.
ACTL Select ion of the low bat tery su pply voltage VBATL on SLIC-E/-E2/-P if
available. Valid only in t he Active mode of the SLICOF I-2.
ACTL = 0 L ow battery supply voltage on SLIC-E/-E2/-P is not
selected.
ACTL = 1 Low battery s upply voltage on SLIC-E / -E2/-P is select ed.
SEL-SLIC[1:0] Selection of the current SLIC type used. For SLIC-E/-E2 and SLIC-P,
the appropriat e predefin ed mode t able has t o be selected.
SEL-SLIC[1:0] = 0 0 SLIC-E/-E2 selected.
SEL-SLIC[1:0] = 0 1 SLIC-P selected.
SEL-SLIC[1:0] = 1 0 SLIC-P selected for extremely power sensitive
applic at ions using ex t ernal ringing.
SEL-SLIC[1:0] = 1 1 Reserved fo r futu re use.
For SLIC-P two selections are possible.
•The standard SLIC-P selection automatically uses the IO2 pin of the
SLICOFI-2 to control the C3 pin of the SLIC-P. By using pin C3
additionaly to the pins C1 and C2 all possible operating modes of
the SLIC-P can be selected.
•For extremely power sensitive applications using external ringing
with SLIC-P SEL-SLIC[1:0] = 10 should be chosen. In this case
internal unbalanced ringing in not needed and therefore there is no
need to switch the C3 pin of the SLIC-P to 'High'. The C3 pin of the
SLIC-P has be connected to GND and the IO2 pin of the SLICOFI-2
is free program m able for the use r.
There is no need for a high battery voltage for ringing either. This
mode uses VBATR for the on-hook voltage (e.g. –48 V) in Power
Down Resistive (PDR) mode and the other battery supply voltages
(e.g. VBATH = –24 V and VBATL = –18 V) can be used for the
off-hook state. This will help to save power because the lowest
possib le batt er y voltag e ca n be sele cte d (se e DuS LIC Voltage and
Power Ap plication Note) .
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 192 2000-07-14
Preliminary
16HBCR2 Basic Configuration Register 2 00HY
Bit76543210
REXT-
EN SOFT-
DIS TTX-
DIS TTX-
12K HIM-AN AC-
XGAIN UTDX-
SRC PDOT-
DIS
REXT-EN Enables the use of an external ring signal generator. The synchronization
is done via the RSYNC pin and the Ring Burst Enable signal is transferred
via th e IO1 pi n.
REXT-EN = 0 External ringing is disabled.
REXT-EN = 1 External ringing enabled.
SOFT-DIS Polarity soft reversal (to minimize noise on DC feeding)
SOFT-DIS = 0 Po l arity sof t revers al activ e.
SOFT-DIS = 1 Polari t y hard reversal.
TTX-DIS Disables th e generation of TTX burs ts for met ering signals. If TTX burs ts
are disabled, reverse polarity will be used inst ead.
TTX-DIS = 0 TTX bursts ar e enabled.
TTX-DI S = 1 TTX bursts ar e dis abled, reverse polarity us ed.
TTX-12K Selection o f TT X frequencies
TTX-12K = 0 Selec ts 16 kHz TT X signals in st ead of 12 kHz signals.
TTX-12K = 1 12 kHz TTX signals.
HIM-AN Higher impedance in analog impedance matching loop.
HIM-AN corresponds to the coefficients calculated with DuSLICOS. If the
coefficients are calculated with standard impedance in analog impedance
matching loop, HIM-AN must be set to 0; if the coefficients are calculated
with high impedance in analog impedance matching loop, HIM-AN must be
set to 1.
HIM-AN = 0 Standard impeda nc e in analog impeda nc e matching
loop (300 Ω).
HIM-AN = 1 High impedance in analog impe dance mat c hing loop
(600 Ω).
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 193 2000-07-14
Preliminary
AC-XGAIN Analog gain in tran s m it direct ion (shoul d be s et to zero).
AC-XGAIN = 0 No additional analog gain in transmit direction.
AC-XGAIN = 1 Additional 6 dB analog amplification in transmit
direction.
UTDX-SRC Universal Tone D etector transmi t s ource
UTDX-SRC = 0 The Universal Tone Detection unit uses the data
from the transmit path directly (UTDX-SUM = 0) or
uses th e data from t h e sum signal of re ceive pa th
and LEC (i f LE C is enabl ed ) (UTDX- SUM = 1) .
UTDX-SRC = 1 The Universal Tone Detection unit uses the data
from the LEC output, if the LEC is enabled (LEC-EN
= 1), otherwise the UTD unit us es automatically the
transmit signal.
(see Figure 32 on Page 63)
PDOT-DIS Power Down Overtemperature Disable
PDOT -D IS = 0 When overtemperature is detecte d , the SLIC is
automatically switched into Power Down High
Imped ance m ode (PDH ). This is the saf e operat ion
mode for the SLIC-E/-E2/-P in case of
overtemperature. To leave the automatically
activate d PDH mod e , DuSLIC has to be switched
manually to P DH m ode an d t hen in th e m ode as
desired.
PDOT-DIS = 1 When over temperature is detected, the SLIC-E/-E2/
-P doesn’t automatically switch into Power Down
High Impedance mode. In this case the output
current of th e SLIC-E /-E2 /-P buffers is lim ited to a
value w h ic h k e eps th e SLIC-E/-E2 /-P te m perature
below t he upper temper at ure limit.
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 194 2000-07-14
Preliminary
17HBCR3 Basic Configuration Register 3 00HY
Bit76 5 43210
MU-
LAW LIN PCM16K PCMX-
EN CONFX
-EN CONF-
EN LPRX-
CR CRAM-
EN
MU-LAW Sele cts the PCM Law
MU-LAW = 0 A-Law enabled.
MU-LAW = 1 µ-Law enabled.
LIN Voice transm is s ion in a 16-bit linear represe nt at i on for test purposes .
Note: Voic e tra nsmis sion on th e other cha nne l is inhibi te d if one ch an nel
is set to linear mode and IOM-2-interface is used. In the PCM/
µC int erface m ode both c hannels c an be in li near mode u sing two
consecutive PCM timeslots on the highways. A proper timeslot
selection must be specified.
LIN = 0 PCM mode enabled (8 bit , A- law or µ-law).
LIN = 1 Linear mode en able d (16 bit).
PCM16K Selects 16-kHz sample rate for the PCM interface.
PCM16K = 0 16-kHz mode disabled (8 kHz sampling rate).
PCM1 6K = 1 16-kH z mode enabled.
PCMX-EN Enables w rit ing of subscriber voice data t o t he PC M highwa y.
PCM X -EN = 0 Writin g of subs c r iber voic e data to PCM hi ghway i s
disabled.
PCM X -EN = 1 Writin g of subs c r iber voic e data to PCM hi ghway i s
enabled.
CONFX-EN Enables an external three-party conference.
CONFX-EN = 0 External conference is disabled.
CONFX-EN = 1 External conference is enabled.
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 195 2000-07-14
Preliminary
CONF-EN Selection of three-party conferencing for t his channe l. The vo ic e dat a of
this c hanne l and the v oic e data from th e c o rresponding confer encing
chann els (see Chapter 5.1.1) are added and f ed to analog output (see
Chapter 3.10).
CONF-EN = 0 Three-party conferencing is not selected.
CONF-EN = 1 Three-party conferencing is selected.
LPRX-CR Select CRAM coefficients for the filter characteristic of the LPR/LPX filters.
These coef ficients m y be enabled in c ase of a m odem transmiss ion to
improv e m odem perf ormance.
LPRX-CR = 0 Coeffici ents from RO M are used.
LPRX-CR = 1 Coefficients from CRAM are used.
CRAM-EN Coeff ic i ent s from C RA M are use d for programmable filters and DC loop
behavior.
CRA M -EN = 0 Coefficie nts from R OM are us ed.
CRA M -EN = 1 Coefficie nts from C R A M are used .
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 196 2000-07-14
Preliminary
18HBCR4 Basic Configuration Register 4 00HY
Bit76543210
TH-DIS IM-DIS AX-DIS AR-DIS FRX-
DIS FRR-
DIS HPX-
DIS HPR-
DIS
TH-DIS Disables th e TH filter.
TH-DIS = 0 TH filter is enabled.
TH-DIS = 1 TH filter is disabled (HTH = 0).
IM-DIS Disables th e IM filter.
IM-DIS = 0 IM filter is enabled.
IM-DIS = 1 IM filter is disabled (HIM = 0).
AX-DIS Disables the AX filter.
AX-DIS = 0 AX filter is enabl ed.
AX-DIS = 1 AX filter is disabled (HAX = 1).
AR-DIS Disab les the AR f ilt er.
AX-DI S = 0 AR f ilter is enabled.
AX-DI S = 1 AR f ilter is disabled (HAR = 1).
FRX-DIS Disables the FR X f ilt er.
FRX-DIS = 0 FRX filter is enabled.
FRX-DI S = 1 FRX filter is di sabl ed (HFRX = 1).
FRR-DIS Disab l es the FRR filter.
FRR-DIS = 0 FRR filter is enabled.
FRR-DIS = 1 FRR filter is disabled (HFRR = 1).
HPX-DIS Disables the high -pass filt er in tr ans mit dire c tion.
HPX-D I S = 0 High-pass filt er is enabled.
HPX-DIS = 1 High-pa ss filter is disabled (HHPX = 1).
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 197 2000-07-14
Preliminary
HPR-DIS Disables the high-pass filter in receive direction.
HPR-DIS = 0 High-pass filter is enabled.
HPR-DIS = 1 High-pass filter is disabled (HHPR = 1).
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 198 2000-07-14
Preliminary
19HBCR5 Basic Configuration Register 5 00HY
Bit76543210
UTDR-
EN UTDX-
EN CIS-
AUTO CIS-EN LEC-
OUT LEC-EN DTMF-
SRC DTMF-
EN
UTDR-EN Enab les the Universal Tone detection in rec eive direction.
UTDR -EN = 0 U niversa l Tone det ec t ion is disabled.
UTDR -EN = 1 U niversa l Tone det ec t ion is enab led.
UTDX-EN Enables the Univ ersal Tone detect ion in trans mit dire c tio n.
UTDX-EN = 0 Universal Tone detection is disabled.
UTDX-EN = 1 Universal Tone detection is enabled.
CIS-AUTO Controls the turn-off behavior of the Caller ID sender.
CIS-AUTO = 0 The Caller ID sender stops when CIS-EN is switched to 0.
CIS-AUTO = 1 The Caller ID sender continues sending data until the
data buffer is empty.
CIS-EN Enab les the Caller ID sender in the SLICOFI-2.
Note: The Caller ID sender is configured directly by programming the
according POP registers. Caller ID data are written to a 48 byte
RAM buffer. Acco rding to the buffer reque st size this influences t he
CIS-REQ and CIS- BUF bi ts.
CIS-E N = 0 Caller ID sender is disabled and Caller ID data buffer is
cleared after all dat a are sent or if CI S-AUTO = 0.
CIS-E N = 1 Caller ID s ender is en abled and Caller ID data can be
written to the data buff er. Afte r the last dat a bit is sent,
stop bits ar e s ent to the s ubscri ber.
Caller ID data are sent to the subscriber when the number
of bytes writ te n to th e bu ffer exceeds CIS-B RS + 2.
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 199 2000-07-14
Preliminary
LEC-OUT Line Echo Canceller result for transmit path.
LEC-OUT = 0 Line Echo Ca nceller res ult used f or DTMF only.
LEC-OUT = 1 Line Echo Canceller result fed to transmit path.
LEC-EN Line Echo Canceller
LEC-EN = 0 Line Echo Canc eller for DT M F disabled.
LEC-EN = 1 Line Echo Canc eller for DT M F enabled.
DTMF-SRC Selects data source for DTMF receiver.
DTMF-SRC = 0 The Transmit path data (with or without LEC) is used for
the DTMF detection.
DTMF- SR C = 1 The Rece ive path d at a is used for the D T M F det ec tion.
DTMF-EN Enables the DTMF receiver of the SLICOFI-2. The DTMF receiver will be
configured in a proper way by programming regist ers in the EDSP.
DTMF -EN = 0 DTMF receiver is disabled.
DTMF -EN = 1 DTMF receiver is en abled.
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 200 2000-07-14
Preliminary
1AHDSCR DTMF Sender Co nf iguratio n R egis ter 00HY
Bit76543210
DG-KEY[3:0] COR8 PTG TG2-EN TG1-EN
DG-KEY[3:0] Selects one of si xt een DT M F key s generated by the t w o tone
genera to rs. The key will be generat ed if TG1-EN and TG 2-EN are ‘1’.
Table 49 DTMF Keys
fLOW [Hz] fHIGH [Hz] DIGIT DG-KEY3 DG-KEY2 DG-KEY1 DG-KEY0
697 1209 1 0 0 0 1
697 1336 2 0 0 1 0
697 1477 3 0 0 1 1
770 1209 4 0 1 0 0
770 1336 5 0 1 0 1
770 1477 6 0 1 1 0
852 1209 7 0 1 1 1
852 1336 8 1 0 0 0
852 1477 9 1 0 0 1
941 1336 0 1 0 1 0
941 1209 * 1 0 1 1
941 1477 # 1 1 0 0
697 1633 A 1 1 0 1
770 1633 B 1 1 1 0
852 1633 C 1 1 1 1
941 1633 D 0 0 0 0
COR8 Cuts of f receive path at 8 kH z before the ton e generato r sum m a t ion
poin t. Allows sen ding of tone generat or s ignals w it h no overlaid v oic e.
COR 8 = 0 Cut off receiv e path disabled.
COR 8 = 1 Cut off receiv e path enabled.
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 201 2000-07-14
Preliminary
PTG Programm able coefficients for tone generators will be used.
PTG = 0 Frequencies set by DG-KEY are use d f or both tone
generators.
PTG = 1 CRAM coef ficient s used for both t one gene rators.
TG2-EN Enables tone generator two
TG2-E N = 0 Tone g enerator is disabled.
TG2-E N = 1 Tone g enerator is en abled.
TG1-EN Enables tone generator one
TG1-EN = 0 Tone generator is disabled.
TG1-EN = 1 Tone generator is enabled.
1BHreserved 00HY
Bit76543210
00000000
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 202 2000-07-14
Preliminary
1CHLMCR1 Leve l Me t ering Configuratio n R egister 1 22HY
Bit765 4 3210
TEST-
EN LM-EN LM-
THM PCM2DC LM2
PCM LM-
ONCE LM-
MASK DC-
AD16
TEST-EN Activates the SLICOFI-2 test features controlled by test registers TSTR1
to TSTR5.
TEST-E N = 0 S LICOFI -2 t es t fe at ures are disabled.
TEST-E N = 1 S LICOFI -2 t es t fe at ures are en abled.
(The Test Register bits can be programmed before the TEST-EN bit is set
to 1.)
LM-EN Enables level metering. A positive transition of this bit starts level metering
(AC and DC).
LM- EN = 0 Level met ering stops.
LM- EN = 1 Level m etering enabled.
LM-THM Level met ering thre s hold mask bit
LM-THM = 0 A change of the LM-THRES bit (register INTREG2)
gener at es an interrupt.
LM-THM = 1 No interrupt is generate d.
PCM2DC PCM voic e c hannel da t a added to the DC-outp ut .
PCM2DC = 0 Normal ope rat ion.
PCM2D C = 1 PCM voic e c h annel data is added to DC output.
LM2PCM Level metering source/result (depending on LM-EN bit) feeding to PCM or
IOM-2 inte rf ac e.
LM2PCM = 0 Normal operation.
LM2PCM = 1 Le vel met ering so urce/res ult i s fed to the
PCM or IOM-2 interface.
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 203 2000-07-14
Preliminary
LM-ONCE Level m etering ex ec ution m ode.
LM-ON C E = 0 Le ve l metering is executed continu ously.
LM-ON C E = 1 Le ve l m et ering is exec ut ed only on c e. To start the
levelmet er again, the LM -EN bit m us t a gain be set
from 0 to 1.
LM-MASK Interrupt masking for level metering.
LM-M ASK = 0 An interru pt is generat ed after lev el metering.
LM-M ASK = 1 No interrupt is generated.
DC-AD16 Additional digit al amplific ation in th e DC AD pat h f or level m et ering.
DC-A D 16 = 0 Additional g ain f ac t or 16 disab led.
DC-A D 16 = 1 Additional g ain f ac t or 16 enable d.
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 204 2000-07-14
Preliminary
1DHLMCR2 Leve l Me t ering Configuratio n R egister 2 00HY
Bit76543210
LM-
NOTCH LM-
FILT LM-
RECT RAMP-
EN LM-SEL[3:0]
LM-NOTCH Selection of a notch filter instead of the band-pass filter for level
metering.
LM-NOTCH = 0 Notch filter selected.
LM-NOTCH = 1 Band-pass filter selected.
LM-FILT Enabli ng of a program m able band-pass or notch filter for level
metering.
LM-FILT = 0 N ormal op eration.
LM-FILT = 1 Band-pass/notch filter enabled.
LM-RECT Rectifier in DC level meter
LM-RE C T = 0 Rectifier disabled.
LM-RE C T = 1 Rectifier en abled.
RAMP-EN The ramp generato r works togeth er with th e RNG-OFFSE T bits in
LMCR3 an d the L M-EN bi t to cr eate di fferent volt age sl opes i n the D C-
Path.
RAMP-EN = 0 Ramp generator disabled.
RAMP-EN = 1 Ramp generator enabled.
LM-SEL[3:0] Sele ct ion of th e source for the lev el mete ring.
LM-SEL[3:0] = 0 0 0 0 AC level metering in transmit
LM-SE L[ 3: 0] = 0 0 0 1 Re al part of TTX (T T X REAL)
LM-SEL[3:0] = 0 0 1 0 Imaginary part of TTX (TTXIMG)
LM-SEL[3:0] = 0 0 1 1 Not used
LM-SE L[ 3: 0] = 0 1 0 0 DC out voltage on DCN- D CP
LM-SE L[3:0] = 0 1 0 1 DC current on IT
LM-SEL[3:0] = 0 1 1 0 AC level metering in receive
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 205 2000-07-14
Preliminary
LM-SEL[3:0] = 0 1 1 1 AC level metering in receive and transmit
LM-SEL[3:0] = 1 0 0 0 Not used
LM-SE L[3:0] = 1 0 0 1 DC current on IL
LM-SEL[3:0] = 1 0 1 0 Volt age on IO3
LM-SEL[3:0] = 1 0 1 1 Volt age on IO4
LM-SEL[3:0] = 1 1 0 0 Not used
LM-SEL[3:0] = 1 1 0 1 VDD
LM-SE L[3:0] = 1 1 1 0 Offset of DC -Prefi (short c irc uit on DC-Prefi
input)
LM-SEL[3:0] = 1 1 1 1 Volt age on IO4 –IO3
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 206 2000-07-14
Preliminary
1EHLMCR3 Level Metering Configuratio n Regis te r 3 00HY
Bit76543210
AC-
SHORT
-EN
RTR-
SEL LM-ITIME[3:0] RNG-
OFFSET[1:0]
AC-SHORT-EN The input pin ITAC will be set to a lower input impedance so that the
capacitor CITAC can be recharged faster during a soft reversal which
makes it m ore silent during conversation.
AC-SHORT-EN = 0 Input imp edance o f the I T AC pin is standard.
AC-SHORT-EN = 1 Input imp edance o f the ITAC pin is lowe red.
RTR-SEL Ring Trip method selection.
RTR-SEL = 0 Ring Trip with a DC offset is selected.
RTR-SEL = 1 AC Ring Trip is selected. Recommended for
short lines only.
LM-ITIME[3:0] Integra t ion T i m e f o r AC Lev el M etering.
LM-ITI ME[3:0] = 0 0 0 0 16 ms
LM-ITIME[3:0] = 0 0 0 1 2 ×16 ms
LM-ITIME[3:0] = 0 0 1 0 3 ×16 ms
…
LM-ITIME[3:0] = 1 1 1 1 16 ×16 ms
RNG-
OFFSET[1:0] Selection of the Ring O ffset so urc e.
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 207 2000-07-14
Preliminary
By se ttin g the R AM P_EN bit t o 1, the r am p gene rato r is star ted by sett ing LM_E N from
0 to 1 (see Figure 71).
Exception: Transition of RNG-OFFSET from 10 to 11 or 11 to 10 where the ramp
generator is started au to ma tically (see Figure 71).
For R ing Offset RO1 the usu al "Hook T hreshold R ing" is used . Using R ing Offset RO2
or RO3 in any ringing mode (Ringing and Ring Pause) also changes the hook thresholds.
In this c as e t he "H ook Mes sage Wait ing" thres hold is used automatically .
When using the Ring Offsets RO2 and RO3 for Message Waiting an additional lamp
current is expected. In this case the Hook Message Waiting threshold should be
prog ram m ed higher t han the Hook Thresho ld Ring.
RNG-
OFFSET[1:0] Ring Offset Voltage in Given Mode
Active
ACTH
ACTL
Active Ring
ACTR Ring Pa use Ringing
0 0 Voltage given by DC
regulation Voltage given by DC
regulation Ring Offset RO1
Hook Threshold Ring
0 1 Ring Offset RO1/2
(no DC regulation) Ring Offset RO1
(no DC regulation) Ring Offset RO1
Hook Threshold Ring
1 0 Ring Offset RO2/2
(no DC regulation) Ring Offset RO2
(no DC regulation) Ring Offset RO2
Hook Message Waiting
1 1 Ring Offset RO3/2
(no DC regulation) Ring Offset RO3
(no DC regulation) Ring Offset RO3
Hook Message Waiting
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 208 2000-07-14
Preliminary
Figure 71 Example for Switching Between Different Ring Offset Voltages
The three programmable Ring Offsets are typically used for the fo llowing purposes:
Beside s the typic al usage described in Table 50 the Ring Offsets RO1, RO2 and RO3
can als o be used for the generatio n of dif ferent c us t om wavef orms (see Figure 71).
Tabl e 50 Typi cal U sag e for the th r ee Ring Offsets
Ring Offset Voltage Appli cat ion
Ring Offset RO1 Ringing
Ring Of f set RO2 Low v olt age for m es sage w ait ing lamp
Ring Offset RO3 H ig h voltage for message waiting lamp
10 11
RNG-OFFSET[1:0]
RAMP-EN
(register LMCR2)
LM-EN
(register LMCR1)
Generated
Ring Offset (RO) Voltage
t
RO1 = 20 V
RO2 = 40 V
RO3 = 120 V
01 01
ezm35002.emf
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 209 2000-07-14
Preliminary
1FHOFR1 Offset Register 1 (High Byte) 00HY
Bit76543210
OFFSET-H[7:0]
OFFSET-H[7:0] Of f se t re gis t er high byte.
20HOFR2 Offset Register 2 (Low Byte) 00HY
Bit76543210
OFFSET-L[7:0]
OFFSET-L[7:0] Offset register low byte.
The value of this register together with OFFSET-H is added to the
input of the DC loop to compensate a given offset of the current
senso rs in the SLIC-E/ - E2 /-P.
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 210 2000-07-14
Preliminary
This register is not applicable and not used in IOM-2 mode. Only enabled in PCM/µC
mode.
21HPCMR1 PCM Receive Regi ster 1 00HY
Bit76543210
R1-
HW R1-TS[6:0]
R1-HW Selection of the PCM highway for receiving PCM data or the higher byte
of the f irs t data s am ple if a linear 16-kH z PC M mode is s electe d.
R1-HW = 0 PCM highway A is selected.
R1-HW = 1 PCM highway B is selected.
R1-TS[6:0] S el e ction of the PCM time sl ot used for dat a re cepti on .
Note: The programmed PCM time slot must correspond to the available
slots defined by the PCLK frequency. No reception will occur if a
slot ou tside the actu al numbers of sl ots is programm ed. In linear
mode (bit LIN = 1 in register BCR3) R1-TS defines the first of two
cons ec ut iv e s lot s used for rec ept ion.
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 211 2000-07-14
Preliminary
This register is not applicable and not used in IOM-2 mode. Only enabled in PCM/µC
mode.
22HPCMR2 PCM Receive Register 2 00HY
Bit76543210
R2-
HW R2-TS[6:0]
R2-HW Selection of the PCM highway for receiving conferencing data for
conference channel B or the lower byte of the first data sample if a linear
16-kHz PCM mode is selected.
R2-HW = 0 PCM highway A is selected.
R2-HW = 1 PCM highway B is selected.
R2-TS[6:0] Selection of the PCM time slot used for receiving data
(see des c ription of PC M R 1 register).
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 212 2000-07-14
Preliminary
This register is not applicable and not used in IOM-2 mode. Only enabled in PCM/µC
mode.
23HPCMR3 PCM Receive Register 3 00HY
Bit76543210
R3-
HW R3-TS[6:0]
R3-HW Selecti on of the PCM hi g hwa y for re ce iving con f er e ncing dat a for
conference channel C or the higher byte of the second data sample if a
linear 16-kHz PCM mode is selected.
R3-HW = 0 PCM highway A is selected .
R3-HW = 1 PCM highway B is selected .
R3-TS[6:0] S el e cti on of the PCM time slot used f or re cei ving data
(see des c ription of PC M R 1 register).
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 213 2000-07-14
Preliminary
This register is not applicable and not used in IOM-2 mode. Only enabled in PCM/µC
mode.
24HPCMR4 PCM Receive Register 4 00HY
Bit76543210
R4-
HW R4-TS[6:0]
R4-HW Selecti on of the PCM hi g hwa y for re ce iving con f er e ncing dat a for
confe r ence channel D or the low er by te of th e s econd data sample if
ali near 16-kHz PCM m ode is selected.
R4-HW = 0 PCM highway A is selected .
R4-HW = 1 PCM highway B is selected .
R4-TS[6:0] Selection of the PCM time slot used for receiving data
(see des c ription of PC M R 1 register).
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 214 2000-07-14
Preliminary
This register is not applicable and not used in IOM-2 mode. Only enabled in PCM/µC
mode.
25HPCMX1 PCM Transmit Register 1 00HY
Bit76543210
X1-
HW X1-TS[6:0]
X1-HW Sele cti o n of the PCM highwa y f or t r an smitting PCM data or the higher
byte of the first data sample if a linear 16-kHz PCM mode is selected.
X1-HW = 0 PCM highway A is selected.
X1-HW = 1 PCM highway B is selected.
X1-TS[6:0] Sel e cti on of the PCM time slot used for dat a tr an smi ssion.
Note: The programmed PCM time slot must correspond to the available
slots defined by the PCLK frequency. No transmission will occur if
a slot out side the actual nu mbers of slots is programmed . In linear
mode X1-TS defines the first of two consecutive slots used for
transmission. PCM data transmission is controlled by the bits 6
throug h 2 in register BC R 3.
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 215 2000-07-14
Preliminary
This register is not applicable and not used in IOM-2 mode. Only enabled in PCM/µC
mode.
26HPCMX2 PCM Transmit Register 2 00HY
Bit76543210
X2-
HW X2-TS[6:0]
X2-HW Sele cti o n of the PCM highwa y for t r an smi tting confere nci n g da ta f or
conference channel C + S or C + D or the lower b y te of the firs t data
samp le if a l inear 16-kH z PCM m ode is se lec t ed.
X2-HW = 0 PCM highway A is selected.
X2-HW = 1 PCM highway B is selected.
X2-TS[6:0] Sel e cti o n of the PCM time slot used for tra n smitting da ta
(see description of PCMX1 register).
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 216 2000-07-14
Preliminary
This register is not applicable and not used in IOM-2 mode. Only enabled in PCM/µC
mode.
27HPCMX3 PCM Transmit Register 3 00HY
Bit76543210
X3-
HW X3-TS[6:0]
X3-HW Selection of the PCM highway for transmitting conferencing data for
conferenc e cha nn el B + S or B + D or the lower byt e of the firs t da ta
sample if a linear 16- kHz PC M m od e is selected.
X3-HW = 0 P CM highway A is selected.
X3-HW = 1 P CM highway B is selected.
X3-TS[6:0] Sel e cti o n of the PCM time slot used for tra n smitting da ta
(see description of PCMX1 register).
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 217 2000-07-14
Preliminary
This register is not applicable and not used in IOM-2 mode. Only enabled in PCM/µC
mode.
28HPCMX4 PCM Transmit Register 4 00HY
Bit76543210
X4-
HW X4-TS[6:0]
X4-HW Selection of the PCM highway for transmitting conferencing data for
conference channel B + C or the lower by t e of the firs t data sample if a
linear 16-k H z PCM mode is selec te d.
X4-HW = 0 P CM highway A is selected.
X4-HW = 1 PCM highway B is selected.
X4-TS[6:0] Sel e cti o n of the PCM time slot used for tra n smitting da ta
(see description of PCMX1 register).
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 218 2000-07-14
Preliminary
Regis t er setting is only act iv e if bit TEST -EN in registe r L M C R1 is set t o 1.
29HTSTR1 Test Register 1 00HTY
Bit76543210
PD-AC-
PR PD-AC-
PO PD-AC-
AD PD-AC-
DA PD-AC-
GN PD-
GNKC PD-
OFHC PD-
OVTC
PD-AC-PR AC-PREFI power down
PD-AC-PR = 0 Normal op erat ion.
PD-AC-PR = 1 Power Dow n mode .
PD-AC-PO AC- PO FI power do wn
PD-AC-PO = 0 Norm al operatio n.
PD-AC-PO = 1 Pow er D own mo de.
PD-AC-AD AC-ADC power down
PD-AC-AD = 0 N ormal op eration.
PD-AC-AD = 1 Power Down mode, transmit path is inactive.
PD-AC-DA AC-DAC power down
PD-AC-D A = 0 Normal operatio n.
PD-AC -D A = 1 Power Down mo de, rec eive path is inactiv e.
PD-AC-GN AC-Gain power d ow n
PD-AC-GN = 0 N ormal op eration.
PD-AC-GN = 1 Power Down mode.
PD-GNKC Groundkey co mparator (GNKC ) is set to power dow n
PD-GNKC = 0 No r m al operat ion.
PD-GNKC = 1 Power Down mode.
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 219 2000-07-14
Preliminary
PD-OFHC Off-hook comparator (OFHC) power down
PD-OFHC = 0 Normal operation.
PD-OFHC = 1 Power Down mode.
PD-OVTC Overtemperature comparator (OVTC) power down
PD-OVTC = 0 Normal operati on.
PD-OVTC = 1 Power Down mode.
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 220 2000-07-14
Preliminary
Regis t er setting is only act iv e if bit TEST -EN in registe r L M C R1 is set t o 1.
2AHTSTR2 Test Register 2 00HTY
Bit76543210
PD-DC-
PR 0 PD-DC-
AD PD-DC-
DA PD-
DCBUF 0PD-
TTX-A PD-HVI
PD-DC-PR DC-PREFI power down
PD- DC-PR = 0 Normal operation .
PD-DC-PR = 1 Power Down mode.
PD-DC-AD DC-ADC power down
PD-DC-AD = 0 Norma l operation.
PD-DC-AD = 1 Po wer Down mode, t r ansmit path i s in active.
PD-DC-DA DC-DAC power down
PD-DC-DA = 0 Normal operation.
PD-DC-DA = 1 Power Down mode, receive path is inactive.
PD-DCBUF DC-B U F F ER power dow n
PD-DCBUF = 0 Norm al operat ion.
PD-DCBUF = 1 Power Down mode.
PD-TTX-A TTX Adaptation DAC and P OFI pow e r dow n
PD-TTX- A = 0 Normal op eration.
PD-TTX-A = 1 Power Down mode.
PD-HVI HV interface (to SLIC-E/-E2/-P) power down
PD-HVI = 0 Normal opera t i on.
PD-HVI = 1 Power Down mode.
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 221 2000-07-14
Preliminary
Regis t er setting is only act iv e if bit TEST -EN in registe r L M C R1 is set t o 1.
2BHTSTR3 Test Register 3 00HTY
Bit76543210
0 0 AC-
DLB-
4M
AC-
DLB-
128K
AC-
DLB-
32K
AC-
DLB-
8K
00
AC-DLB-4M AC digit al loop via a 4-MHz bits t ream. (Loop enclo ses all digi tal
hardware in the AC path. Together with DLB-DC, a pure digital test is
possible bec aus e there is no influence fro m the analog hardw are.)
AC-DLB-4M = 0 Normal operation.
AC-DLB-4M = 1 Digital loop closed.
AC-DLB-128K AC dig ital l oo p vi a 128 kHz
AC-DLB-128K = 0 Normal operation.
AC-D LB-128K = 1 Digita l loop clos ed.
AC-DLB-32K AC digital l oo p vi a 32 kH z
AC-DLB-32K = 0 Normal operation.
AC-D LB-32K = 1 Digital loop closed.
AC-DLB-8K AC digi ta l loop via 8 kHz
AC-DLB-8K = 0 Normal operation.
AC-D LB-8K = 1 Digital loop closed.
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 222 2000-07-14
Preliminary
Regis t er setting is only act iv e if bit TEST -EN in registe r L M C R1 is set t o 1.
2CHTSTR4 Test Register 4 00HTY
Bit76543210
OPIM-
AN OPIM-
4M COR-64COX-160000
OPIM-AN Open Imped ance Ma tching Loop i n the analog par t.
OPIM-AN = 0 Normal operation.
OPIM-AN = 1 Loop opened.
OPIM-4M Open fas t di git al Imped ance Ma t ch i ng Loop in t he hardwa re filters.
OPIM-4M = 0 Normal operation.
OPIM-4M = 1 Loop opened.
COR-64 Cut off the AC receive path at 64 kHz (just bef ore the I M filter).
COR-64 = 0 Normal operation.
COR-64 = 1 Receive path is cut off.
COX-16 Cut off the AC transm i t path at 16 kHz. (The T H filter can be tested
witho ut inf luencing the analog part.)
COX-1 6 = 0 Norm al operation.
COX-16 = 1 Transm it path is cut of f.
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 223 2000-07-14
Preliminary
Regis t er setting is only act iv e if bit TEST -EN in registe r L M C R1 is set t o 1.
2DHTSTR5 Test Register 5 00HTY
Bit76543210
000DC-
POFI-
HI
DC-
HOLD 000
DC-POFI-HI Higher value for DC post filter limit
DC-POFI-HI = 0 Limit frequency is set to 100 Hz (normal operation).
DC-POFI-HI = 1 L imit frequency is set to 300 Hz.
DC-HOLD Actual DC outpu t value hold (v alue of the last DSP filter stage will be
kept)
DC- HOLD = 0 N ormal op eration.
DC- HOLD = 1 D C output va lue hold.
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 224 2000-07-14
Preliminary
6.2.2 CO P Command
The CO P comman d gives ac cess to the CRAM da ta of the D SPs. I t is organized in the
same way as the SOP command. The offset value allows a direct as well as a block
access to the CRAM. Writing beyond the allowed offset will be ignored, reading beyond
it will give unpredictable results.
The value of a specific CRAM coefficient is calculated by the DuSLICOS software.
Bit 76543210
Byte 1 RD 1 ADR[2:0] 1 0 1
Byte 2 OFFSET[7:0 ]
RD Read Data
RD = 0 Write dat a t o chip.
RD = 1 Read data from chip.
ADR[2:0] Chann e l address for the s ubsequent data
ADR[2:0] = 0 0 0 Channel A
ADR[2:0] = 0 0 1 Channel B
(other c odes r e s e r ved for futur e use)
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 225 2000-07-14
Preliminary
Offset
[7:0] Short
Name Long Name
00HTH1 Transhybrid Filter Coefficients Part 1
08HTH2 Transhybrid Filter Coefficients Part 2
10HTH3 Transhybrid Filter Coefficients Part 3
18HFRR Frequ ency-re s ponse Filter Coef f icients R eceive Direction
20HFRX Frequency -respon s e F ilter Coef f icients T r ansmit D i rectio n
28HAR Amplification/Attenuation Stage Coefficients Receive
30HAX Amplification/Attenuation Stage Coefficients Transmit
38HPTG1 Tone Generator 1 Coefficients
40HPTG2 Tone Generator 2 Coefficients
48HLPR Low Pass Filter Coefficients Receive
50HLPX L ow Pass Filter Coefficients Transmit
58HTTX Te l et ax Coeffi c i ents
60HIM1 Impedance Matching Filter Coefficients Part 1
68HIM2 Impedance Matching Filter Coefficients Part 2
70HRINGF Ringer Frequency and Amplitude Coefficients (DC loop)
78HRAMPF Ramp Ge nerator C oefficie n t s (DC loop)
80HDCF DC Charact e ris tics Coeffi cients (D C loop)
88HHF Hook Threshold Coefficients (DC loop)
90HTPF Low-pass Filter Coefficients (DC loop)
98HReserved
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 226 2000-07-14
Preliminary
Note: CRAM coefficients are enabled by setting bit CRAM-EN in register BCR3 to 1,
except c oef ficien ts marke d 1) and 2):
Coeff ic i ent s market 1) are enabled by set ting bit PTG in register D S C R to 1.
Coeff ic i ent s market 2) are enabled by s etting bit LP R X -CR in regist er BCR 3 to 1.
Table 51 CRAM Coefficients
Byte 7 By te 6 B yte 5 Byte 4 B yte 3 B yte 2 By te 1 Byte 0 Offset
[7:0]
Transhybrid Coefficient Part 1 00HTH1
Transhybrid Coefficient Part 2 08HTH2
Transhybrid Coefficient Part 3 10HTH3
FIR Filter in Receive Direction 18HFRR
FIR Filter in Transmit Direction 20HFRX
LM Threshold 2nd Gain Stage
Receive 1st Gain Stage Receive 28HAR
Bandpass for AC LM Conference
Gain LM-
AC 2nd Gain Stage
Transmit 1st Gain Stage Transmit 30HAX
TG1 Bandpass TG1 Gain TG1 Frequency 38HPTG1 1)
TG2 Bandpass TG2 Gain TG2 Frequency 40HPTG2 1)
LPR 48HLPR 2)
LPX 50HLPX 2)
FIR Filter for TTX TTX Slope TTX Level 58HTTX
IM K Factor IM FIR Filter 60HIM1_F
IM 4 MHz Filter IM WDF Filter 68HIM2_F
LM DC Gain Ring Generator
Amplitude Ring Generator
Frequency Ring Generator
Low-pass Ring Offset RO1 70HRINGF
Extended
Battery
Feeding
Gain
Soft Reversal End Cons tant Ramp
CR Soft Ramp SS Ring Delay RD 78HRAMPF
Res. in Resistive
Zone RK12 Res. in Constant
Current Zone RIConstant Current IK1 Knee Voltage VK1 Open Circuit Volt.
VLIM 80HDCF
Hook Message
Waiting Hook Threshold
AC Ringtrip Hook Threshold
Ring Hook Threshold
Active Hook Threshold
Power Down 88HHF
Ring Offset RO3 Ring Offset RO2 Voltage Level VRT DC Low-pass Fi lter
TP2 DC Low-pass Filter
TP1 90HTPF
Reserved 98H
16151413121110987654321
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 227 2000-07-14
Preliminary
6.2.2.1 CRAM Programming Ranges
Table 52 CRAM Programming Ranges
Parameter Programming Range
Cons tant Current IK1 0...50 mA, ∆<0.5mA
Hook Mess age Waiti ng,
Hook Thresholds 0..25 mA, ∆<0.7mA
25...50 mA, ∆<1.3mA
Ring Generator F r equency fRING 3..40 Hz, ∆<1Hz
40..80 Hz, ∆<2Hz
>80Hz,
∆<4Hz
Ring Generat or Am plitud e 0..20 V, ∆<1.7V
20..85 V, ∆<0.9V
Ring Offset RO1, RO2, RO3 0..25 V, ∆<0.6V
25..50 V, ∆<1.2V
50..100 V, ∆< 2.4 V, max. 150 V
Knee Voltage VK1,
Open Circuit Voltge VLIM
0..25 V, ∆<0.6V
25..50 V, ∆<1.2V
>50V,
∆<2.4V
Resistan ce in Resi s tive Zone RK12 0..1000 Ω, ∆<30Ω
Resistance in Constant Current Zone RI1.8 kΩ..4.8 kΩ, ∆< 120 Ω
4.8 kΩ..9.6 kΩ, ∆< 240 Ω
9.6 kΩ..19 kΩ, ∆<480Ω
19 kΩ..38 kΩ, ∆<960Ω, max . 40 kΩ
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 228 2000-07-14
Preliminary
6.2.3 POP Command
The POP command provides access to the EDSP registers of the SLICOFI-2.
Before using an EDS P funct ion the ac c ording P OP registers have to be programm ed.
Any change in any of the POP registers (except registers CIS-DAT and CIS/LEC-MODE)
is only updated with enabling the corresponding device. For example a change of the
center frequency fC of the UTD is handled by changing the registers UTD-CF-H and
UTD-CF-L , switching off the UTD and switchin g it on aga in.
The POP registers do no have default values after any kind of reset.
6.2.3.1 POP Register Overview
00HCIS-DAT Caller ID Sender Data Buffer (write-only)
30HDTMF-LEV DTMF Receiver Level Byte
0be
31HDTMF-TWI DTMF Receiver Twist Byte
TWI
32HDTMF-NCF-H DTMF Receiver Notch Filter Center Frequency High Byte
NCF-H
33HDTMF-NCF-L DTMF Receiver Notch Filter Center Frequency Low Byte
NCF-L
34HDTMF-NBW-H DTMF Receiver Notch Filter Bandwidth High Byte
NBW-H
35HDTMF-NBW-L DTMF Receiver Notch Filter Bandwidth Low Byte
NBW-L
36HDTMF-GAIN Gain Stage Control for DTMF Input Signal
em
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 229 2000-07-14
Preliminary
37HDTMF-RES1 DTMF Receiver Reserved Byte 1
38HDTMF-RES2 DTMF Receiver Reserved Byte 2
39HDTMF-RES3 DTMF Receiver Reserved Byte 3
3AHLEC-LE N Line Echo Canceller Length
LEN
3BHLEC-P OWR Line Echo Canceller Power Detection Level
POWR
3CHLEC-DELP Line Echo Canceller Delta Power
DELP
3DHLEC-DELQ Line Echo Canceller Delta Quality
DELQ
3EHLE C-GAIN-XI Line Echo Canceller Input Gain Transmit
em
3FHLEC-GAIN-RI Line Echo Canceller Input Gain Receive
em
40HLEC-G AIN -XO Line Echo Canceller Output Gain Transmit
em
41HLEC-RES1 Line Echo Canceller Reserved Byte 1
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 230 2000-07-14
Preliminary
42HLEC-RES2 Line Echo Canceller Reserved Byte 2
43HCIS -LEV-H Caller ID Sender Level High Byte
LEV-H
44HCIS-LEV-L Caller ID Sender Level Low Byte
LEV-L
45HCIS-BRS Caller ID Sender Buffer Request Size
BRS
46HCIS-SEIZ-H Caller ID Sender Number of Seizure Bits High Byte
SEIZ-H
47HCIS-SEIZ-L Caller ID Sender Number of Seizure Bits Low Byte
SEIZ-L
48HCIS-MARK-H Caller ID Sender Number of Mark Bits High Byte
MARK-H
49HCIS-MARK-L Caller ID Sender Number of Mark Bits Low Byte
MARK-L
4AHCIS/LEC-MO DE CIS/LEC Mode Setting
LEC-ADAPT LEC-FREZE UTDX-SUM UTDR-SUM 0 0 CIS-FRM CIS-V23
4BHUT D-CF-H Universal Tone Detection Center Frequency High Byte
CF-H
4CHUT D-CF-L Universal Tone Detection Center Frequency Low Byte
CF-L
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 231 2000-07-14
Preliminary
4DHUTD-BW-H Universal Tone Detection Bandwidth High Byte
BW-H
4EHUTD-BW-L Universal Tone Detection B andwidth Low Byte
BW-L
4FHUTD-NLEV Univer sal Tone Detection Noise Level
NLEV
50HUT D-SLEV -H Universal Tone Detection Signal Level High Byte
SLEV-H
51HUTD-SLEV-L Universal Tone Detection Signal Level Low Byte
SLEV-L
52HUTD-DELT Universal Tone Detection Delta
DELT-H
53HUTD-RBRK Universal Tone Detection Recognition Break Time
RBRK
54HUTD-RTIME Universal Tone Detection Recognition Time
RTIME
55HUTD-EBRK UTD Allowed Tone End Detection Break Time
EBRK
56HUTD-ETIME UTD Tone End Detection Time
ETIME
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 232 2000-07-14
Preliminary
6.2.4 POP Register Description
00HCIS-DAT Caller ID Sende r Data Buffer (write-only) Y
Bit76543210
Byte 0
Byte 1
Byte 2
Byte 47
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 233 2000-07-14
Preliminary
Minimum DTMF Signal Detection Level LevelDTMFdet
•for DTMF detecti on in tr an smi t :
LevelDTMFdet[dB] = LevelDTMFdet[dBm0] –3.14 + GDTMF[dB]
LevelDTMFdet[dB] = LevelDTMFdet[dBm] –Lx[dBr] –3.14 + GDTMF[dB]
•for DTMF detection in re ceive:
LevelDTMFdet[dB] = LevelDTMFdet[dBm0] –3.14 + AR1[dB] + GDTMF[dB]
LevelDTMFdet[dB] = LevelDTMFdet[dBm] –LR[dBr] –3.14 + AR1[dB] + GDTMF[dB]
AR1[ dB]: The ex act value for AR 1 is show n in the D uSLICO S result file;
approx imate valu e AR 1 ≈LR for LR≤–2 dBr, AR 1 ≈–2dB for L
R>–2dBr.
LevelDTMFdet[dB] = –30 –b–3×e[dB]
–54 dB ≤LevelDTMFdet ≤–30 dB
with
0≤e≤7
0≤b≤3
Alternative representation
b=MOD[(–LevelDTMFdet[dB] –30),3]
e=INT[(–LevelDTMFdet[dB] –30)/3]
Note: MOD = Modulo function, INT = Integer function
30HDTMF-LEV DTMF Receiver Level Byt e Y
Bit76543210
0be
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 234 2000-07-14
Preliminary
DTMF Receiver Twist is the maximum allowed difference between the signal levels of
the two tones for DTMF detection:
TWI[dB] = 2 ×Twistacc[dB]
0dB≤Twistacc ≤12 dB
31HDTMF-TWI DTMF Receiver Twist Byte Y
Bit76543210
TWI
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 235 2000-07-14
Preliminary
DTMF Receiver Notch Filter Center Frequency:
NCF = 32768 × = NCF-L + 256 ×NCF-H
0Hz≤fNCF ≤2000 Hz
The by t es are c alc ulated as f ollows:
NCF-L = MOD (NCF,256) = NCF & 0x00FF
NCF-H = INT (NCF/256) = NCF >> 8
The echo of the dial tone can activate the double talk detection which means that the
DTMF tone w ill not be detected . Therefore a notchfilter can be prog ramme d to filter out
the echo of the dialtone, because the frequency of the dialtone is known. The center
frequ en cy an d the band wi th of the not ch fi lter can be pr og rammed.
32HDTMF-NCF-H DTMF Receiver Notch Fi l te r Cen te r
Frequency H igh Byte Y
Bit76543210
NCF-H
33HDTMF-NCF-L DTMF Receiver Notch Fi l te r Cen te r
Frequency Low By t e Y
Bit76543210
NCF-L
2πfNCF Hz[]
8000
----------------------
è
æö
cos
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 236 2000-07-14
Preliminary
DTMF Receiver Notch Fil te r Ba nd width :
NBW = 65536 × = NBW-L + 2 56 ×NBW-H
with
a =
0Hz≤FNBW ≤2000 Hz
NBWL=MOD(NBW,256)
NBWH= INT (NBW/256)
34HDTMF-NBW-H DTMF Receiver Notch Filter Bandwidth
High Byte Y
Bit76543210
NBW-H
35HDTMF-NBW-L DTMF Receiver Notch Filter
Bandwidth Low Byte Y
Bit76543210
NBW-L
a
1a+
-------------
πFNBW Hz[]
8000
----------------------------
⋅
tan
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 237 2000-07-14
Preliminary
DTMF Input Signal Gain:
GDTMF[dB] = 20 ×log1016 + 20 ×log10[g/32768] ≈24.08 + 20 ×log10[g/32768]
–24.08 dB ≤GDTMF ≤23.95 dB
with
g=2
(9 - e) (32 + m) and
0≤m≤31, 0 ≤e≤7
Alternative representat ion:
Choos e "e" as the next in teger num ber whic h is bigge r tha n or equal to:
36HDTMF-GAIN Gain Stage Control for DTMF Input Signal Y
Bit76543210
em
Table 53 Ranges of GDTMF[dB] dependent on “e”
e DTMF Input Signal Gain GDTMF [dB] Range
0 23.95 dB ≥GDTMF ≥18.06 dB
1 17.93 dB ≥GDTMF ≥12.04 dB
7–18.20 dB ≥GDTMF ≥–24.08 dB
Table 54 Example for DTMF- GAIN Calculation
GDTMF[dB] GDTMF e m DTMF-GAIN
0 1300x60
–6.02 0.5 4 0 0x80
6.02 2 2 0 0x40
e3 G
2DTMF 3G
10 DTMF
log 2
10
log
--------------------------------–3GDTMF dB[]
6.02
-------------------------------–
≈=log–≥
mG
DTMF 22e+
×32 10
GDTMF dB[]
20
------------------------------ 22e+
×32–=–=
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 238 2000-07-14
Preliminary
37HDTMF-RES1 DTMF Receiver Reserved Byte 1 Y
Bit76543210
38HDTMF-RES2 DTMF Receiver Reserved Byte 2 Y
Bit76543210
39HDTMF-RES3 DTMF Receiver Reserved Byte 3 Y
Bit76543210
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 239 2000-07-14
Preliminary
Line Ech o Cance ller Length :
LEN = LEC Length[ms] / 0.125
LEC Length ha s to be ente red in multiples of 0.125 m s .
The sele cted LEC Len gth has to be h igher than th e maximum line echo le ngth but not
high er t han 8 ms.
3AHLEC-LEN Line Echo Ca nc eller Lengt h Y
Bit76543210
LEN
Table 6-1 LEC Length
LEN LEC Length
10.125ms
…
64 8 ms
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 240 2000-07-14
Preliminary
Minimum Powe r Dete cti on Level for Lin e Echo Cancell er :
PowLECR[dB] = SR,LEC-POWR[dBm0] –3.14 + AR1[dB] + GLEC-RI[dB] –20*log10(π/2)
SR,LEC-POWR[d Bm 0]: Minim um Pow er Dete ction Le v el for Line Echo Ca nc eller
at digital input
AR1[ dB]: The ex act value for AR 1 is show n in the D uSLICO S result file;
approx imate valu e AR 1 ≈LR for LR≤–2 dBr, AR 1 ≈–2dB for L
R>–2dBr.
POWR = (6.02 ×16 + PowLECR[dB]) ×2/(5×log102)
=(96.32+Pow
LECR[dB]) ×1.329
–96 dB ≤PowLECR ≤0dB
Example:
AR1 = –3dB
SR,LEC-POWR =–40 dBm0
PowLECR =–46.14 dB
POWR = 66.69 ≈67 = 0x43
3BHLEC-POWR Line Echo Cance ller
Po w er Det ectio n Lev el Y
Bit76543210
POWR
Tabl e 55 Characteris ti c Values
POWR PowLECR[dB]
0x00 –96
…
0x7F 0
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 241 2000-07-14
Preliminary
Line Ec ho C ancelle r De lt a Pow er for D ouble Talk D etection ( DTD ):
DeltaPLEC[dB] = (SR–SX)DTDThr[dB] + AR1[dB] + GLEC-RI[dB] –GLEC-XI[dB]
(SR–SX)DTDThr[dB]: Double Talk Detection threshold
AR1[ dB]: The ex act value for AR 1 is show n in the D uSLICO S result file;
approx imate valu e AR 1 ≈LR for LR≤–2 dBr, AR 1 ≈–2dB for L
R>–2dBr.
DELP = DeltaPLEC[dB] ×2/5 ×log102=DeltaP
LEC[dB] ×1.329
–96 dB ≤DeltaPLEC ≤96 dB
Example:
AR1 = –3dB
expected echo signal < –15 dB → (S R–SX)DTDThr =–15 dB
DeltaPLEC =12dB
DELP = 16 = 0x10
3CHLEC-DELP Line Echo Canceller Del ta Power Y
Bit76543210
DELP
Tabl e 56 Characteris ti c Values
DELP DeltaPLEC[dB]
0x81 –96
…
0x7F 96
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 242 2000-07-14
Preliminary
Line Echo Canceller Delta Quality Between Shadow Filter and Main Filter:
The higher DeltaQ is, the less copying between shadow filter and main filter takes place
and the higher is the qualit y .
DELQ[dB] = DeltaQ[dB] ×2/5 ×log102=DeltaQ[dB]×1.329
0dB≤DeltaQ ≤10 dB
3DHLEC-DELQ Line Echo Cancelle r Delta Quality Y
Bit76543210
DELQ
Tabl e 57 Characteris ti c Values
DELQ DeltaQ[dB]
86.02dB
43.01dB (typical)
32.26dB
21.505dB
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 243 2000-07-14
Preliminary
Line Ec ho C ancelle r Input Gain Transm it:
It is importan t, that GLEC-XI[d B] will not be cha nged, so GLEC-XI[dB] = –GLEC-X0[dB]
GLEC-XI[dB] = 20 ×log1016 + 20 ×log10[g/32768] ≈24.08 + 20 ×log10[g/32768]
–24.08 dB ≤GLEC-XI ≤23.95 dB
with
g=2
9-e (32 + m) and
0≤m≤31, 0 ≤e≤7
Alternative representat ion:
Choos e "e" as the next in teger num ber whic h is bigge r tha n or equal to:
3EHLEC-GAIN-XI Line Ec ho Canc eller Input Gain Trans mit Y
Bit76543210
em
Table 58 Ranges of GLEC-XI[dB] Dependent on “e”
e Input Gain GLEC-XI[dB] Range
0 23.95 dB ≥GLEC-XI ≥18.06 dB
1 17.93 dB ≥GLEC-XI ≥12.04 dB
7–18.20 dB ≥GLEC-XI ≥–24.08 dB
Ta ble 59 Example f or LEC- GA IN-XI Calc ula t ion
GLEC-XI[dB] GLEC-XI emLEC-GAIN-XI
0 1300x60
–6.02 0.5 4 0 0x80
6.02 2 2 0 0x40
e3 G
2 LEC XI–3G
10 LEC XI–
log 2
10
log
-------------------------------------–3GLEC XI–dB[]
6.02
-------------------------------------–
≈=log–≥
mG
LEC XI–22e+
×32 10
GLEC XI–dB[]
20
----------------------------------- 22e+
×32–=–=
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 244 2000-07-14
Preliminary
Line Echo Canc eller Input Gain Receiv e:
GLEC-RI[dB] = 20 ×log1016 + 20 ×log10[g/32768] ≈24.08 + 20 ×log10[g/32768]
–24.08 dB ≤GLEC-RI ≤23.95 dB
with
g=2
9-e (32 + m) and
0≤m≤31, 0 ≤e≤7
Alternative representat ion:
Choos e "e" as the next in teger num ber whic h is bigge r tha n or equal to:
3FHLEC-GAIN-RI Line Ec ho Canc ell er In put Ga in Rece ive Y
Bit76543210
em
Table 60 Ranges of GLEC-RI[dB] Dependent on “e”
e Input Gain GLEC-RI[dB] Range
0 23.95 dB ≥GLEC-RI ≥18.06 dB
1 17.93 dB ≥GLEC-RI ≥12.04 dB
7–18.20 dB ≥GLEC-RI ≥–24.08 dB
Table 61 Example for LEC-GAIN-RI Calculation
GLEC-RI[dB] GLEC-RI emLEC-GAIN-RI
0 1300x60
–6.02 0.5 4 0 0x80
6.02 2 2 0 0x40
e3 G
2LECRI–3G
10 LEC RI–
log 2
10
log
-------------------------------------–3GLEC RI–dB[]
6.02
-------------------------------------–
≈=log–≥
mG
LEC RI–22e+
×32 10
GLEC RI–dB[]
20
----------------------------------- 22e+
×32–=–=
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 245 2000-07-14
Preliminary
Line Echo Canceller Output Gai n Tr an smit:
It is importan t, that GLEC-X0[dB] will not be c hanged, so GLEC-X0[dB] = –GLEC-XI[dB]
GLEC-X0[dB] = 20 ×log1016 + 20 ×log10[g/32768] ≈24.08 + 20 ×log10[g/32768]
–24.08 dB ≤GLEC-X0 ≤23.95 dB
with
g=2
9-e (32 + m) and
0≤m≤31, 0 ≤e≤7
Alternative representat ion:
Choos e "e" as the next in teger num ber whic h is bigge r tha n or equal to:
40HLEC-GAIN-XO Line Echo Cance l l er Ou tput Gain Tr ansmit Y
Bit76543210
em
Table 62 Ranges of GLEC-X0[dB] Dependent on “e”
e Output Gain GLEC-X0[dB] Range
0 23.95 dB ≥GLEC-X0 ≥18.06 dB
1 17.93 dB ≥GLEC-X0 ≥12.04 dB
7–18.20 dB ≥GLEC-X0 ≥–24.08 dB
Table 63 Example for LEC-GAIN-X0 Calculation
GLEC-X0[dB] GLEC-X0 emLEC-GAIN-X0
0 1300x60
–6.02 0.5 4 0 0x80
6.02 2 2 0 0x40
e3 G
2 LEC X0–3G
10 LEC X0–
log 2
10
log
---------------------------------------–3GLEC X0–dB[]
6.02
--------------------------------------–
≈=log–≥
mG
LEC X0–22e+
×32 10
GLEC X0–dB[]
20
------------------------------------ 22e+
×32–=–=
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 246 2000-07-14
Preliminary
41HLEC-RES1 Line Ec ho Canceller Reserved Byt e 1 Y
Bit76543210
42HLEC-RES2 Line Ec ho Canceller Reserved Byt e 2 Y
Bit76543210
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 247 2000-07-14
Preliminary
Caller ID Sender Level:
LevCIS[dB] = LevCIS[dBm0] –3.14 –3.37
LevCIS[dB] = LevCIS[dBm] –LR[dBr] –3.14 –3.37
LEV = 32767 ×10 (LevCIS[dB]/20)
–90.31 dB ≤LevCIS ≤0dB
LEV-L = MOD (LEV,256)
LEV-H = INT (LEV/256)
43HCIS-LEV-H Caller ID Sender Lev el High Byte Y
Bit76543210
LEV-H
44HCIS-LEV-L Caller ID Sender Lev el Low Byt e Y
Bit76543210
LEV-L
Table 64 Examples
LEV Level [d B]
0 (signal off)
1–90.31
32767 0
∞–
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 248 2000-07-14
Preliminary
Caller ID Sender Buffer Request Size:
0≤BRS ≤46
CIS-BRS is a threshold to be set within the Caller ID sender buffer (CIS-DAT, 48 bytes).
If the number of bytes in the CID sender buffer falls below the buffer request size an
interrupt is gene rated. This is the indication to fill up the buffer again.
The first bit will be sent if the number of bytes in the CID sender buffer exceeds the buffer
request size (st art sending with BRS + 1 num ber of byt es ).
The buffer request size BRS must always be smaller than the number of bytes to be sent:
BRS < N u m ber of by tes to be sent
Typical values : 10 –30.
45HCIS-BRS Caller ID Sender Buff er Reque s t Size Y
Bit76543210
BRS
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 249 2000-07-14
Preliminary
Caller ID Sender Number of Seizure Bits:
(only if Hig h Level F r am ing is selec t ed in the CIS/LEC-MOD E register (s ee Page 251))
0≤SEIZ ≤32767
SEIZ-L = MOD (SEIZ,256)
SEIZ-H = INT (SEIZ/256)
46HCIS-SEIZ-H Caller ID Sender N um ber of Seizure Bits
High Byte Y
Bit76543210
SEIZ-H
47HCIS-SEIZ-L Caller ID Sender N um ber of Seizure Bits
Low Byte Y
Bit 76543210
SEIZ-L
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 250 2000-07-14
Preliminary
Caller ID Sender Number of Mark Bits:
(only if High Level Framing is selected in the CIS/LEC-MODE register)
0≤MARK ≤32767
MARK-L = MOD (MARK,256)
MARK-H = INT (MARK/256)
48HCIS-MARK-H Caller ID Sender N um ber of Mark Bit s
High Byte Y
Bit76543210
MARK-H
49HCIS-MARK-L Caller ID Sender N um ber of Mark Bit s
Low Byte Y
Bit76543210
MARK-L
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 251 2000-07-14
Preliminary
4AHCIS/LEC-
MODE CIS/LEC Mode Setting Y
Bit7 6543210
LEC-
ADAPT LEC-
FREEZE UTDX-
SUM UTDR-
SUM 00CIS-
FRM CIS-
V23
LEC-ADAPT Line Echo C anc eller A daptat i on Start. T he LEC-ADAPT bit is only
evaluat ed if the LEC-EN is c hanged f rom 0 to 1.
To initialize the LEC co ef ficient s to 0 requires t he LEC-ADAPT bit set
to 0 follo w ed by t he LEC-EN bit cha nged from 0 t o 1.
It is not possible to reset the LEC coefficients to 0 while the LEC is
running. The LEC has to be disabled first by setting bit LEC-EN to 0 and
then it is necessary to enable the LEC again (LEC-EN = 1, LEC-ADAPT
= 0). If valid coefficient s from a former LE C adaptat ion are pr es ent in
the RAM, it is possible to activate the LEC with this coefficents by
setting bit LE C - AD APT t o 1.
It is also p os s ible to read ou t adapted coefficien t s f rom t he LEC fo r
external storage and to reuse these coefficients as a start up value for
the next connection (see the av aila ble Apllication Notes).
LEC-AD APT = 0 Line Echo Canceller coefficien ts initia lized w ith
zero
LEC-ADAPT = 1 Line Echo Canceller coefficients initialized with old
coefficients
LEC-FREEZE Li ne Echo Cance ller Ad aptati o n Fr eeze
LEC-F R EEZE = 0 No freezing of coe ffic ients
LEC-FREEZE = 1 Freezing of coefficients
UTDX-SUM Sum signal for Universa l Tone De tectio n unit in transmit direction
UTDX-SUM = 0 The transmit signal is fed through
UTDX-SUM = 1 The sum signal SSUM (receive signal + LEC signal,
if LEC is enabled) is fed thro ugh
(see bit UTDX-SRC in BCR2 and Figure 32)
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 252 2000-07-14
Preliminary
UTDR-SUM Sum signal for Universa l Tone De tection unit in receive di rection
UTDR-SUM = 0 The rec eiv e signal is fed to the UDT unit
UTDR-SUM = 1 The sum signal SSUM (receive signal + LEC signal,
if LEC is enabled) is fed to th e U TD unit
CIS-FRM Caller ID Sender Fr am ing
CIS -F R M = 0 Low-lev el f raming: all data for CID transm is s ions have
to be written to the CID Buffer including channel seizure
and mark s equence , start and st op bits.
CIS-FRM = 1 High-level framing: channel seizure and mark sequence
as well as start and stop bits are automatically inserted
by the SLICOFI-2x. Only transm i ssion bytes from the
Data Packet (see Figure 33) have to be written to th e
CIS buffer.
CIS-V23 Caller ID Sender M ode
CIS-V23 = 0 Bell 202 selected
CIS-V23 = 1 V.23 selected
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 253 2000-07-14
Preliminary
Univers al T one Detec t ion Center F requency :
CF = 32768 ×
0<fC<4000Hz
CF-L = MOD (CF,256)
CF-H = INT (CF/256)
4BHUTD-CF-H Universal Tone Detection Center
Frequency H i gh Byte Y
Bit76543210
CF-H
4CHUTD-CF-L Universal Tone Detection Center
Frequ ency Lo w Byte Y
Bit76543210
CF-L
2
···
πfcHz[]
8000
------------------------
cos
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 254 2000-07-14
Preliminary
Universal Tone Detection Bandwidth:
BW = 65536 ×
with
a=
0<fBW < 2000 Hz
BW-L = MOD (BW,256)
BW-H = INT (BW/256)
4DHUTD-BW-H Universal Tone Detection Bandwidth
High Byte Y
Bit76543210
BW-H
4EHUTD-BW-L Universal Tone Detection Bandwidth Low
Byte Y
Bit76543210
BW-L
a
1a+
-------------
fBW Hz[]π×
8000
--------------------------------
tan
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 255 2000-07-14
Preliminary
Universal Tone Detection Noise Level:
NLEV = 32768 ×10(LevN[dB])/20
–96 dB ≤LevN≤–42.18 dB
4FHUTD-NLEV Universal Tone De tectio n Noise Level Y
Bit76543210
NLEV
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 256 2000-07-14
Preliminary
Univers al T one Detec t ion Signal Level:
Calc ulat ion for T rans mit:
LevS[dB] = LevS[dBm0] –3.14 –20*log10(π/2)
LevS[dB] = LevS[dBm] –Lx[dBr] –3.14 –20*log10(π/2)
Calc ulat ion for R ec eiv e:
LevS[dB] = LevS[dBm0] –3.14 + AR1[dB] –20*log10(π/2)
LevS[dB] = LevS[dBm] –LR[dBr] –3.14 + AR1[dB] –20*log10(π/2)
AR1[ dB]: The ex act value for AR 1 is show n in the D uSLICO S result file;
approx imate valu e AR 1 ≈LR for LR≤–2 dBr, AR 1 ≈–2dB for L
R>–2dBr.
SLEV = 32768 ×10(LevS[dB])/20 –NLEV
–96 dB ≤LevS≤0dB
Sign al Level:
SLEV-L = MOD (SLEV,256)
SLEV-H = INT (SLEV/256)
UTD for Receive and Transmit:
By enabling the UTD t he coef fic ients in the UT D registers are co pied to th e main
mem ory. Therefore different coefficients can be se t for receive an d transmi t direction.
50HUTD-SLEV-H Universal Tone Dete ctio n Signal Level
High Byte Y
Bit76543210
SLEV-H
51HUTD-SLEV-L Universal Tone Det ectio n Signal Level
Low Byte Y
Bit76543210
SLEV-L
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 257 2000-07-14
Preliminary
Univ ers al T one Detec tion Delta Inban d/ Outban d:
DELT = Sign(DeltaUTD)×128 ×10–|DeltaUTD[dB]|/20
–42 dB ≤DeltaUTD ≤42 dB
Example:
Detectio n of a tone that is betwe en 1975 Hz an d 2025 H z →=fC=2000Hz
•fBW =50Hz
Tone at 2025 H z: Outban d = –3 dB, Inband = –3dB (see Table 65)
DeltaUTD =0dB →DELT = 128 = 0x80
•fBW =500Hz
Tone at 2025 H z: Outban d = –20 dB, In band = –0.04 dB (see Table 65)
DeltaUTD ≈20 dB →DELT = 13 = 0x0D
52HUTD-DELT Universal Tone Dete ctio n D elta Y
Bit76543210
DELT
Table 65 UTD Inband/Outband Attenuation
f Outband Inband
fC ± fBW/0.2 –0.04 dB –20 dB
fC ± fBW/2 –3dB –3dB
fC ± fBW/20 –20 dB –0.04 dB
fC ± fBW/200 –40 dB –0dB
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 258 2000-07-14
Preliminary
Allowed Recognition Break Time for Universal Tone Detection:
RBRK = RBRKTime[ms]/4
RBR KT i m e has to be entered in multiples of 4 ms.
0ms≤RBRKTime ≤1000 ms
For an exam ple see Figure 72.
53HUTD-RBRK Universa l Tone Detection Recognition
Break Time Y
Bit76543210
RBRK
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 259 2000-07-14
Preliminary
Universal Tone D etection Recognition Time:
RTIME = RTime[ms]/16
RTime has to be entered in multiples of 16 ms.
0ms≤RTime ≤4000 ms
Figure 72 Example for UTD Recognition Timing
54HUTD-RTIME Universa l Tone Detection Recognition
Time Y
Bit76543210
RTIME
duslic_0013_RBRK_timing.emf
Tone
UTDi-OK bit
(INTREG3)
UTDi-OK bit
(INTREG3)
t
t
t
1
0
1
0
1
0
RBRKTime
RBRKTime
RTime
RTime
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 260 2000-07-14
Preliminary
Allowed tone end de t ec tion break tim e for Univ ers al Tone D etect ion:
EBRK = EBRKTime [ms]
0ms≤EBRKTime ≤255 ms
For an exam ple see Figure 73.
55HUTD-EBRK UTD Allowed Tone End Detection Break
Time Y
Bit76543210
EBRK
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 261 2000-07-14
Preliminary
Tone End Detec t ion Time for Univers al Tone Det ec t ion:
ETIME = ETime[ms]/4
ETim e has to be e nt ered in multiples of 4 ms.
0ms≤ETime ≤1000 ms
Figure 73 Example for UTD Tone End Detection Timing
56HUTD-ETIME UTD Tone End Detection Time Y
Bit76543210
ETIME
Tone
UTDi-OK bit
(INTREG3)
UTDi-O K bit
(INTREG3)
t
t
t
1
0
1
0
1
0
EBRKTime
EBRKTime
ETime
ETime
duslic_0014_EBRK_timing.emf
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 262 2000-07-14
Preliminary
6.2.5 IOM-2 Interface Command / Indication B yte
The Command/Indication (C/I) channel is used to communicate real-time status
information and for fast controlling of the DuSLIC. Data on the C/I channel are
cont inuously transmit t ed in each f ram e until ne w data are se nt .
Data Downstream C/I – Channel Byte (Recei ve) – IOM - CIDD
The first six CIDD data bits control the general operating modes for both DuSLIC
channels. According to the IOM-2 specifications, new data have to be present for at least
two fr am es to be ac cepted.
)
Table 66 M2, M1, M0: General Opera t ing Mode
CIDD SLICOF I-2 Ope rating Mode
(for details see “Operating Mode s fo r the DuSLIC
Chip Set” on Page 78)
M2 M1 M0
1 1 1 Sleep, Power Down (PDRx)
0 0 0 Power Dow n High Impedance (PD H )
0 1 0 Any Active mode
1 0 1 Ringing (ACT R Burst On)
1 1 0 Active with Metering
1 0 0 Ground Sta rt
001Ring Pause
CIDD Data Downstream C/I – Channel By te N
Bit 76543210
M2A M1A M0A M2B M1B M0B MR MX
M2A, M1A, M0A Select operating mo de for DuSLI C channel A
M2B, M1B, M0B Select operating mo de for DuSLI C channel B
MR, MX Hand shake b i ts Monitor Receive a nd T ransmit
(see “IOM-2 Interface Monitor Transfer Protoc ol ” on
Page 148)
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 263 2000-07-14
Preliminary
Data Upstream C/I – Channel Byte (Transmit) – IOM-CI DU
This byte is used to quickly transfer the most important and time-critical information from
the DuSLIC . Each tra n s f er from the DuSLIC l as ts f or at least 2 conse cutive frames .
CIDU Data Upstream C/I – Channel Byte 00HN
Bit 7 6 5 4 3 2 1 0
INT-CHA HOOKA GNDKA INT-CHB HOOKB GNDKB MR MX
INT-CHA Interrupt information channel A
INT-CHA = 0 No interrupt in channel A
INT-CHA = 1 Interrupt in channel A
HOOKA Hook information channel A
HOOKA = 0 On-hook channel A
HOOKA = 1 Off-hoo k channel A
GNDKA Ground key info rm ation c hannel A
GNDKA = 0 No longitudin al current det ected
GNDKA = 1 Long it udinal current detected in cha nnel A
INT-CHB Interrupt information channel B
INT-CHB = 0 No interrupt in channel B
INT-CHB = 1 Interrupt in channel B
HOOKB Hook information channel B
HOOKB = 0 On-hook Channel B
HOOKB = 1 Off-hook Channel B
GNDKB Ground key info rm ation c hannel B
GNDKB = 0 No longitudin al current det ected
GNDKB = 1 Long it udinal current detected in cha nnel B
MR, MX Handshake bits Mo nitor Receive and Transm it
(see “IOM-2 Interface Monitor Transfer Protocol” on Page 148)
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 264 2000-07-14
Preliminary
6.2.6 Programming Examples of the SLICOFI-2
6.2.6.1 Mic roc ontroller Interfa ce
SOP Wri te to Chan n el 0 Starting A fter the Ch an n el Specific Read-on l y R egisters
01000100 First command byt e ( SO P write for chann el 0)
00010101 Second command byte (Offset to BCR1 register)
00000000 Contents of BCR1 register
00000000 Contents of BCR2 register
00010001 Contents of BCR3 register
00000000 Contents of BCR4 register
00000000 Contents of BCR5 register
Figure 74 Waveform of Programming Example SOP-Write to Channel 0
SOP Read from Channel 1 Reading Out the Interrupt Registers
11001100 First command byte (SOP read for channel 1).
00000111 Second command byte (Offset to Interrupt register 1).
The SLICOFI-2 will send data when it has completely received the second command
byte.
11111111 Dump byte (This by te is always FFH).
11000000 Interrup t re gist er I N TREG 1 (An inter ru pt ha s occ urred, Off-hook was detected) .
00000010 Interrup t re gist er IN TREG 2 (I O pin 2 is ‘1’).
00000000 Interrup t re gist er I NTREG 3
00000000 Interrup t re gist er I NTREG 4
Figure 75 Waveform of Programming Example SOP Read from Channel 0
Command Offset BCR1
DIN
DCLK
CS
BCR2 BCR3 BCR4 BCR5
ezm220121.wmf
ezm220122.emf
DCLK
CS
Command Offset Dump Intreg 1
DOUT
DIN
Intreg 2 Intreg 3 Intreg 4
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 265 2000-07-14
Preliminary
6.2.6.2 IOM-2 Interface
An example with the same programming sequence as before, using the IOM-2 interface
is presented here to show the differences between the microcontroller interface and the
IOM-2 interface.
SOP Wri te to Chann el 0 Starting A fter th e Channel -Specifi c R ead-on ly Re g is ter s
Monitor MR/MX Monitor MR/MXComment
data down data up
10000001 10 11111111 11 IOM-2 address f irst byt e
10000001 10 11111111 01 IOM-2 address second byt e
01000100 11 11111111 01 First command byte (SOP write for channel 0)
01000100 10 11111111 11 First com ma nd byte secon d time
00010101 11 11111111 01 Second command byte (Offset to BCR1 register)
00010101 10 11111111 11 Second command byte second time
00000000 11 1111 1111 01 Contents of BCR1 register
00000000 10 1111 1111 11 Contents of BCR1 register second time
00000000 11 1111 1111 01 Contents of BCR2 register
00000000 10 1111 1111 11 Contents of BCR2 register second time
00010001 11 1111 1111 01 Contents of BCR3 register
00010001 10 1111 1111 11 Contents of BCR3 register second time
00000000 11 1111 1111 01 Contents of BCR4 register
00000000 10 1111 1111 11 Contents of BCR4 register second time
11111 111 11 1111 1111 01 No more in fo rm at ion (dummy byt e)
11111111 11 11111111 11 Signaling EOM (end of message) by holding MX bit at ‘1’.
Since the SLICOFI-2 has an open command structure there is no fixed command length.
The IOM-2 ha ndshake protocol allows for an infinite length of a da ta stream, therefore
the host has to terminate the data transfer by sending an end-of-message signal (EOM)
to the SL ICOFI-2. The SLI COFI-2 wil l abort the tran sfer only if the host tries to write or
read beyond the allowed maximum offset given by the different types of commands.
Each transfer has to start with the SLICOFI-2-specific IOM-2 address (81H) and must
end with an EOM of the handshake bits. Appending a command immediately to its
pred ec es s or w i t hout an EO M in betwe en is not allowed .
When reading interrupt registers, SLICOFI-2 stops the transfer after the fourth register
in IOM-2 mode. Thi s i s to preve n t so me h ost chi ps r e ading 16 bytes because they can ’t
terminate the tra ns f er af t er n by t es .
DuSLIC-E/-E2/-P
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 266 2000-07-14
Preliminary
SOP-Read from Channel 1 Reading Out the Interrupt Registers
Monitor MR/MX Monitor MR/MXComment
data down data up
10000001 10 11111111 11 IOM-2 address f irst byt e
10000001 10 11111111 01 IOM-2 address second byt e
11001100 11 11111111 01 First command byte (SOP read for channel 1)
11001100 10 11111111 11 First com ma nd byte secon d time
00001000 11 11111111 01 Second command byte (offset to interrupt register 1)
00001000 10 11111111 11 Second command byte second time
11111111 11 11111111 01 Acknowledgemen t for t he second com m and byte
11111111 11 10000001 10 IOM -2 Address first byt e (ans wer )
11111111 01 10000001 10 IOM-2 Address sec ond b yte
11111111 01 11000000 11 Interrup t re gist er I N TREG 1
11111111 11 11000000 10 Interrupt register I NTREG 1 second time
11111111 01 00000010 11 Interrup t re gist er I N TREG 2
11111111 11 00000010 10 Interrupt register I NTREG 2 second time
11111111 01 00000000 11 Interrup t re gist er I N TREG 3
11111111 11 00000000 10 Interrupt register I NTREG 3 second time
11111111 01 00000000 11 Interrup t re gist er I N TREG 4
11111111 11 00000000 10 Interrupt register I NTREG 4 second time
11111111 11 01001101 11 SLICOFI-2 sends the next register
11111111 11 11111111 11 SLICOFI-2 aborts transmission
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 267 2000-07-14
Preliminary
6.3 SLICOFI-2S/-2S2 Command Structure and Programming
This chapter comprises only the SLICOFI-2S/-2S2 PEB 3264/-2 and therefore the
DuSLIC-S and DuS L IC-S2 chip sets.
6.3.1 SOP Command
The SO P “Status Operation” command prov id es acc ess to the conf igura tion an d st atus
registers of the SLICOFI-2S/-2S2. Common registers change the mode of the entire
SLICOFI-2S/-2S2 chip, all other registers are channel-specific. It is possible to access
single or multiple registers. Multiple register access is realized by an automatic offset
increment. Write access to read-only registers is ignored and does not abort the
command sequenc e. Offset s m a y c hange in new er versions o f the SLIC OF I - 2S/-2S2.
(All empty register bits have to be filled with zeros.)
6.3.1.1 SOP Register Overview
00HREVISION Revision Number (read-only)
REV[7:0]
01HCHIPID 1 Chip Identification 1 (read-only)
for internal use only
02HCHIPID 2 Chip Identification 2 (read-only)
for internal use only
03HCHIPID 3 Chip Identification 3 (read-only)
for internal use only
04HF USE1 Fuse Register 1
for internal use only
05HPCMC1 PCM Configuration Register 1
DBL-CLK X-SLOPE R-SLOPE NO-DRIVE-0 SHIFT PCMO[2:0]
06HXCR Extended Configuration Register
0 ASYNCH-R 0 0 0 0 0 0
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 268 2000-07-14
Preliminary
07HINT REG1 Interrupt Register 1 (read-only)
INT-CH HOOK GNDK GNKP ICON VRTLIM OTEMP SYNC-FAIL
08HINTR EG2 Interrupt Register 2 (read-only)
0 READY RSTAT 0 IO[4:1]-DU
09HINTR EG3 Interrupt Register 3 (read-only)
00000000
0AHINTREG 4 Interrupt Register 4 (read-only)
00000000
0BHCHKR1 Checksum Register 1 (High Byte) (read-only)
SUM-OK CHKSUM-H[6:0]
0CHCHKR2 Checksum Register 2 (Low Byte) (read-only)
CHKSUM-L[7:0]
0DHreserved
00000000
0EHreserved
00000000
0FHFUSE2 Fuse Register 2
for internal use only
10HF USE3 Fuse Register 3
for internal use only
11HMASK Mask Register
READY-M HOOK-M GNDK-M GNKP-M ICON-M VRTLIM-M OTEMP-M SYNC-M
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 269 2000-07-14
Preliminary
12HIOCT L1 I O Control Register 1
IO[4:1]-INEN IO[4:1]-M
13HIOCT L2 I O Control Register 2
IO[4:1]-OEN IO[4:1]-DD
14HIOCT L3 I O Control Register 3
DUP[3:0] DUP-IO[3:0]
15HBCR1 Basic Configuration Register 1
HIR HIT 0 REVPOL ACTR ACTL 0 0
16HBCR2 Basic Configuration Register 2
REXT-EN SOFT-DIS TTX-DIS1) TTX-12K2) HIM-AN AC-XGAIN 0 PDOT-DIS
17HBCR3 Basic Configuration Register 3
MU-LAW LIN 0 PCMX-EN 0 0 0 CRAM-EN
18HBCR4 Basic Configuration Register 4
TH-DIS IM-DIS AX-DIS AR-DIS FRX-DIS FRR-DIS HPX-DIS HPR-DIS
19Hreserved
00000000
1AHDSCR DTMF Sender Configuration Register
DG-KEY[3:0] COR8 PTG TG2-EN TG1-EN
1BHreserved
00000000
1CHLMCR1 Level Metering Configuration Register 1
TEST-EN 0 1 PCM2DC 0 0 1 0
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 270 2000-07-14
Preliminary
1DHLMCR2 Level Metering Configuration Register 2
00000000
1EHLM CR3 Level Metering Configuration Register 3
AC-SHORT-
EN RTR-SEL000000
1FHOFR1 Offset Register 1 (High Byte)
OFFSET-H[7:0]
20HOFR2 Offset Register 2 (Low Byte)
OFFSET-L[7:0]
21HPCMR1 PCM Receive Register 1
R1-HW R1-TS[6:0]
22Hreserved
23Hreserved
24Hreserved
25HPCMX1 PCM Transmit Register 1
X1-HW X1-TS[6:0]
26Hreserved
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 271 2000-07-14
Preliminary
1) Only for DuSLIC-S, is set to 1 for DuSLIC-S2
2) Only for DuSLIC-S, is set to 0 for DuSLIC-S2
27Hreserved
28Hreserved
29HTSTR1 Test Register 1
PD-AC-PR PD-AC-PO PD-AC-AD PD-AC-DA PD-AC-GN PD-GNKC PD-OFHC PD-OVTC
2AHTSTR2 Test Register 2
PD-DC-PR 0 PD-DC-AD PD-DC-DA PD-DCBUF 0 PD-TTX-A2) PD-HVI
2BHTSTR3 Test Register 3
0 0 AC-DLB-4M AC-DLB-
128K AC-DLB-
32K AC-DLB-
8K 00
2CHTSTR4 Test Register 4
OPIM-AN OPIM-4M COR-64 COX-16 0 0 0 0
2DHTSTR5 Test Register 5
000DC-POFI-
HI DC-HOLD 0 0 0
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 272 2000-07-14
Preliminary
6.3.1.2 SOP Register Description
00HREVISION Revision Number (read-only) curr.
rev. N
Bit76543210
REV[7:0]
REV[7:0] Current rev is i on number of the SLIC OFI-2S/-2S2.
01HCHIPID 1 Chip Identification 1 (read-only) hw N
Bit76543210
for interna l us e only
02HCHIPID 2 Chip Identification 2 (read-only) hw N
Bit76543210
for interna l us e only
03HCHIPID 3 Chip Identification 3 (read-only) hw N
Bit76543210
for interna l us e only
04HFUSE1 Fuse Register 1 hw N
Bit76543210
for interna l us e only
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 273 2000-07-14
Preliminary
05HPCMC1 PCM Configuration Register 1 00HN
Bit 7 6 5 4 3 2 1 0
DBL-CLK X-SLOPE R-SLOPE NO-DRIVE-0 SHIFT PCMO[2:0]
DBL-CLK Clock mode for the PCM interface (see Figure 59 on Page 141).
DBL-C LK = 0 Single clocking is used.
DBL-C LK = 1 Double cloc k ing is used.
X-SLOPE Transm it Slope (see Figure 59 on Page 141).
X-SLOPE = 0 Transmission starts with rising edge of the clock.
X-SLOPE = 1 Transmission starts with falling edge of the clock.
R-SLOPE Receive Slope (see Figure 59 on Page 141).
R-SLOPE = 0 Data is samp l ed with fallin g ed ge of the cl ock.
R-SLOPE =1 Data is sampled with rising edge of the clock.
NO-
DRIVE-0 Driving Mode for Bit 0 (only av ailable in s ingle-clo ck ing mod e).
NO-DRIV E = 0 B i t 0 is dr i ven the en t i re clock peri od.
NO-DRIVE = 1 Bit 0 is driven during the first half of the clock period
only.
SHIFT Shifts the access edges by one cloc k c y cle in double clocking mode.
SHIFT = 0 No shift takes place.
SHIFT = 1 Shift takes place.
PCMO[2:0] The whole PCM timing is moved by PCMO data periods against the FSC
signal.
PCMO[2:0 ] = 0 0 0 No offset is adde d.
PCMO[2:0] =0 0 1 One data period is added.
…
PCMO[2:0] =1 1 1 Sev en data pe riods are a dded.
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 274 2000-07-14
Preliminary
06HXCR Extended Configuration Register 00HN
Bit 7 6 5 4 3 2 1 0
0 ASYNCH
-R 000000
ASYNCH-R Enables as y n c hronous ringing in case of ex ternal r inging.
ASYNCH-R = 0 External ringing with zero crossing selected
ASYNCH-R = 1 Asy nchronous rin ging selec ted.
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 275 2000-07-14
Preliminary
07HINTREG1 Interrupt Register 1 (read-only) 80HY
Bit76543210
INT-CH HOOK GNDK GNKP ICON VRTLIM OTEMP SYNC-
FAIL
INT-CH Interrupt channel bit . This b it indicates t hat the corr es ponding c hannel
caused the last interrupt. Will be set automatical ly to zero after all interrup t
regist ers were read.
INT-CH = 0 No interrupt in corresponding channel.
INT-CH = 1 Interrupt caused by corresp onding ch annel.
HOOK On/Off-hook information for the loop in all operating modes, filtered by DUP
(Data Ups t ream Per si stence) counter an d int errupt ge neration masked by
the HOOK- M bi t. A c h ange of this bit gener at es an interrupt.
HOOK = 0 On-hook .
HOOK = 1 Off-hook.
GNDK Ground Ke y or Gr ou nd Start in formati o n via the IL pin in all act ive modes ,
filtere d f or AC s uppression by th e DUP counter an d int e rrupt ge neration
mask ed by the GNDK-M bit. A cha nge of th is bit generates an interrupt.
GNDK = 0 No longitudinal current detected.
GND K = 1 Longitudinal current det ected (Ground Key or Ground
Start).
GNKP Grou nd k e y polarity. Indicating th e active ground key level (posi tiv e/
negative) interrupt generation masked by the GNKP-M bit. A change of this
bit ge nerates an interrupt. This bit c an be used to get inform ation about
interference voltage inf l uence .
GNKP = 0 Negative ground key threshol d lev el active.
GNKP = 1 Positive ground key threshold level acti ve.
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 276 2000-07-14
Preliminary
ICON Constant current information. Filtered by DUP-IO counter and interrupt
generation masked by the ICON-M bit. A change of this bit generates an
interrupt.
ICON = 0 Resistive or constant voltage feeding.
ICON = 1 Constant current feeding.
VRTLIM Exceeding of a programmed voltage threshold for the TIP/RING voltage,
filtered by the DUP-IO counter and int errupt ge neration ma sked by the
VRTL IM -M bit. A c hange of this bit caus es an interrupt.
The voltage threshold for the TIP/RING voltage is set in CRAM (calculated
with DuSLICO S DC Control Pa rame ter 2/3: Tip-Ri n g Thre sh ol d ) .
VRTL IM = 0 V olt age at Rin g/ T ip is below the limit.
VRTLIM = 1 Voltage at Ring/Tip is above the limit.
OTEMP Thermal overload warning from the SLIC-S/-S2 line drivers masked by the
OTEMP-M bit. An interrupt is only generated if the OTEMP bit changes
from 0 to1.
OTEMP = 0 Temperature at SLIC-S/-S2 is below the limit.
OTEM P = 1 Tem perature at SL I C- S / -S2 is above the li m it.
In case of bit PDOT-DIS = 0 (register BCR2) the
DuSLIC is switched automa t ically into PDH m od e an d
OTEMP is hold at 1 until the SLICOFI-2S/-2S2 is set to
PDH by a CIOP/CIDD command.
SYNC-FAIL Failure of the synchronization of the IOM-2/PCM Interface. An interrupt is
only gen er ated if the SYNC-FA IL bit chan ges from 0 to 1.
Resy nc h roniza tion of the PCM interface can be don e with the
Resynchronization command (see Chapter 6)
SYNC-FAIL = 0 Synchronization OK.
SYNC-FAIL = 1 Synchronization failure.
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 277 2000-07-14
Preliminary
After a hardware reset the RSTAT bit is set and generates an interrupt. Therefore the
defaul t valu e of INTREG 2 i s 20h. After re a di ng all fo ur int er r upt register s, th e INTREG2
value c hanges to 4Fh.
08HINTREG2 Interrupt Register 2 (read-only) 20HY
Bit76543210
0 READY RSTAT 0 IO[4:1]-DU
READY Indication whe th er ramp gen erator has f inis hed. An interru p t is on ly
genera t ed if the READY bit changes f r om 0 t o 1. At a new start of t he
ramp ge ne r ator, th e bi t i s set to 0. For further info rmatio n r eg ar d i ng soft
reversal s ee Chapter 3.7.2.1.
READY = 0 Ramp generator active.
READY = 1 Ramp generator not active.
RSTAT Rese t st atus since last int er r up t .
RSTA T = 0 No reset has oc curred s inc e t h e last inte rrupt.
RSTA T = 1 Reset ha s occurred sinc e t he last inte rrupt.
IO[4:1]-DU Data on IO pi ns 1 to 4 filter ed by the DUP-IO counter and interrupt
genera tion masked by the IO[4: 1] - D U-M bit s . A c h ange of any of these
bits gene rat es an int errupt.
09HINTREG3 Interrupt Register 3 (read-only) 00HY
Bit76543210
00000000
0AHINTREG4 Interrupt Register 4 (read-only) 00HY
Bit76543210
00000000
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 278 2000-07-14
Preliminary
0BHCHKR1 Checksum Register 1 (High Byte)
(read-only) 00HY
Bit76543210
SUM-
OK CHKSUM-H[6:0]
SUM-OK Informat ion about the v alidity of the checksum . The che cksu m is
valid if the internal checksu m calculation is finished.
Checksum calculation:
For (cram_adr = 0 to 159) do
cram_dat = cram[cram_adr]
csum[14:0] = (csum[13:0] &1) ‘0’) xor
(‘0000000’ & cram_dat[7:0]) xor
(‘0000000000000’ & csu m[14] & csu m[14])
End
1) “&” means a concatenation, not the logic operation
SUM-OK = 0 CRAM checksum is not valid.
SUM-OK = 1 CRAM checksum is valid.
CHKSUM-H[6:0] CRAM checksum high byte
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 279 2000-07-14
Preliminary
0CHCHKR2 Checksum Register 2 (Low Byte)
(read-only) 00HY
Bit76543210
CHKSUM-L[7:0]
CHKSUM-L[7:0] CRAM-che cksum low byte
0DHreserved 00HY
Bit76543210
00000000
0EHreserved 00HY
Bit76543210
00000000
0FHFUSE2 Fuse Register 2 hw Y
Bit76543210
for interna l us e only
10HFUSE3 Fuse Register 3 hw Y
Bit76543210
for interna l us e only
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 280 2000-07-14
Preliminary
The ma sk bi ts in th e mas k regist er only infl uenc e the gen era tion of an inter rupt . Even if
the mask bit is set to 1, the corresponding status bit in the INTREGx registers gets
upda t ed t o s how the current s tatus of the corresp onding ev ent .
11HMASK Mask Register FFHY
Bit76543210
READY
-M HOOK
-M GNDK
-M GNKP
-M ICON
-M VRTLIM
-M OTEMP
-M SYNC
-M
READY-M Mask bit for Ramp Generator READY bit
READY-M = 0 An interrupt is generated if the READY bit changes from
0 to 1.
READ Y-M = 1 Changes of the R EADY bit don’t generate interrupts.
HOOK-M Mask b it for O ff-Hook De tection HO OK bi t
HOOK-M = 0 Each change of the HOOK bit generates an interrup t.
HOOK-M = 1 Changes of t he H O OK bit don’t ge nerate interrupts.
GNDK-M Mask bit for Ground Key Detection GNDK bit
GNDK-M = 0 Each change of the GNDK bit generat es an inte rrupt.
GNDK-M = 1 Chang es of the GN DK bit don’t ge nerate interrupts.
GNKP-M Mask bit for Ground Key Level GNKP bit
GNKP-M = 0 Each ch ange of the GNKP bit generates an interr upt .
GNKP-M = 1 C hanges of th e GN KP bit don’t generate interrupts.
ICON-M Mask bit for Constant C urrent Inform at ion ICON bit
ICON-M = 0 Each cha nge of the ICON bit generate s an interru pt .
ICON_M = 1 Changes of the ICO N b it do n’t ge nerate interrupts.
VRTLIM-M Mask bit f or Programmed V olt age Limit VRTLIM bit
VRTLIM -M = 0 Each ch ange of the VR TLIM bit generates an interrupt.
VRTLIM-M = 1 Changes of the VRTLIM bit don’t generate int errup ts .
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 281 2000-07-14
Preliminary
OTEMP-M Mask bit for Th ermal Ov erload W arning OTEMP bi t
OTEMP-M = 0 A change of the OTEMP bit from 0 to 1 generates an
interrupt.
OTEMP-M = 1 A change of the OTEMP bit from 0 to 1 doesn’t generate
interrupts.
SYNC-M Mask bit for Synchronization Failure SYNC-FAIL bit
SYNC-M = 0 A change of the SYNC-FAIL bit from 0 to 1 generates an
interrupt.
SYNC-M = 1 A ch ange of th e SYNC -FAIL bit from 0 to 1 does n ’t
generate interrupt s.
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 282 2000-07-14
Preliminary
The mask bits IO[4:1]-M only influence the generation of an interrupt. Even if the mask
bit is set to 1, the corresponding status bit in the INTREGx registers gets updated to
show the current status of th e c orresponding ev ent.
12HIOCTL1 IO Contro l Register 1 0FHY
Bit76543210
IO[4:1]-INEN IO[4:1]-M
IO4-INEN Input enable for programmable IO pin IO4
IO4-INEN = 0 Input Schmitt trigger of pin IO4 is disabled.
IO4-INEN = 1 Input Schmitt trigger of pin IO4 is enabled.
IO3-INEN Input enable for programmable IO pin IO3
IO3-INEN = 0 Input Schmitt trigger of pin IO3 is disabled.
IO3-INEN = 1 Input Schmitt trigger of pin IO3 is enabled.
IO2-INEN Input enable for programmable IO pin IO2
IO2-INEN = 0 Input Schmitt trigger of pin IO2 is disabled.
IO2-INEN = 1 Input Schmitt trigger of pin IO2 is enabled.
IO1-INEN Input enable for programmable IO pin IO1
IO1-INEN = 0 Input Schmitt trigger of pin IO1 is disabled.
IO1-INEN = 1 Input Schmitt trigger of pin IO1 is enabled.
IO4-M Mask bit for IO4-DU bit
IO4-M = 0 Each change of th e I O4 bit generates an interrupt.
IO4-M = 1 Change s of the IO4 bit don’t generate interrupts .
IO3-M Mask bit for IO3-DU bit
IO3-M = 0 Each change of th e I O3 bit generates an interrupt.
IO3-M = 1 Change s of the IO3 bit don’t generate interrupts .
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 283 2000-07-14
Preliminary
IO2-M Mask bit for IO2-DU bit
IO2-M = 0 Each change of th e I O2 bit generates an interrupt.
IO2-M = 1 Change s of the IO2 bit don’t generate interrupts .
IO1-M Mask bit for IO1-DU bit
IO1-M = 0 Each change of th e I O1 bit generates an interrupt.
IO1-M = 1 Change s of the IO1 bit don’t generate interrupts .
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 284 2000-07-14
Preliminary
13HIOCTL2 IO Contro l Register 2 00HY
Bit76543210
IO[4:1]-OEN IO[4:1]-DD
IO4-OEN Enablin g the output driv er of pin IO4
IO4-O EN = 0 The out put driv er of pin I O4 is dis abled.
IO4-O EN = 1 The out put driv er of pin I O4 is enabled.
IO3-OEN Enabling the output driver of pin IO3
IO3-O EN = 0 The out put driv er of pin I O3 is dis abled.
IO3-O EN = 1 The out put driv er of pin I O3 is enabled.
IO2-OEN Enabling the output driver of pin IO2
IO2-O EN = 0 The out put driv er of pin I O2 is dis abled.
IO2-O EN = 1 The out put driv er of pin I O2 is enabled.
IO1-OEN Enabling the output driver of pin IO1
If external ringing is selected (bit REXT-EN in register BCR2 set to 1), pin
IO1 cannot be controlled by the user but is utilized by the SLICOFI-2S/-2S2
to control the ring relay.
IO1-O EN = 0 The out put driv er of pin I O1 is dis abled.
IO1-O EN = 1 The out put driv er of pin I O1 is enabled.
IO4-DD Valu e f or t he program mable I O pin IO 4 if programmed as an output pin.
IO4-DD = 0 The c orrespo nding pin is driv ing a logica l 0.
IO4-DD = 1 The c orrespo nding pin is driv ing a logica l 1.
IO3-DD Valu e f or t he program mable I O pin IO 3 if programmed as an output pin.
IO3-DD = 0 The c orrespo nding pin is driv ing a logica l 0.
IO3-DD = 1 The c orrespo nding pin is driv ing a logica l 1.
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 285 2000-07-14
Preliminary
IO2-DD Valu e f or t he program mable I O pin IO 2 if programmed as an output pin.
IO2-DD = 0 The c orrespo nding pin is driv ing a logica l 0.
IO2-DD = 1 The c orrespo nding pin is driv ing a logica l 1.
IO1-DD Valu e f or t he program mable I O pin IO 1 if programmed as an output pin.
IO1-DD = 0 The c orrespo nding pin is driv ing a logica l 0.
IO1-DD = 1 The c orrespo nding pin as driv ing a logical 1.
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 286 2000-07-14
Preliminary
14HIOCTL3 IO Contro l Register 3 94HY
Bit76543210
DUP[3:0] DUP-IO[3:0]
DUP[3:0] Da t a U ps t ream Pers is t enc e Counter end value. Res t ric ts the rate
of interru pt s generat ed by th e H OOK bit in the interrupt regis t er
INTREG1. The interval is programmable from 1 to 16 ms in steps
of 1 ms (reset va lue is 10 ms).
The DU P[3:0] value af fects t he blocki ng period for ground key
detection (see Chapter 3.6).
DUP-IO[3:0] Da ta Upstr eam Per si s te nce Coun t er en d value for
•the IO pins wh en used a s digital input pins.
•the bit s ICON and VR T LIM in register IN T R EG1.
The int erval is pro gra mm able f rom 0 .5 t o 60. 5 ms in step s of 4 ms
(reset value is 16.5 ms).
DUP[3:0] HOOK
Active,
Ringing
HOOK
Power
Down
GNDK GNDK
fmin,ACsup1)
1) Minimum frequency for AC suppression.
0000 1 2 ms 4 ms 125 Hz
0001 2 4 ms 8 ms 62 .5 Hz
...
1111 16 32 ms 64 ms 7.8125 Hz
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 287 2000-07-14
Preliminary
15HBCR1 Basic Configuration Register 1 00HY
Bit 76543210
HIR HIT 0 REVPOL ACTR ACTL 0 0
HIR This bit modifies differe nt basic modes. In ringing m ode an unbalance d
ringing on the RING-wire (ROR) is enabled. In active mode, high impedance
on the RIN G-wire is perf ormed (H I R ). It enables the HIRT -m ode together
with the HIT bit.
HIR = 0 Normal operation (rin ging mode).
HIR = 1 Cont r ols SLIC-S/-S2-interf ace and sets the R I NG wire to
high impedanc e (active m ode).
HIT This bit m odifie s di ff eren t basic m odes. In ringing m ode an unbalan c ed
ringing on t he T I P-w ire (ROT ) is enabled. In active mode, high impe dance
on the TIP-wire is performed (HIT). It enables the HIRT-mode together with
the HIR bit.
HIT = 0 Normal operation (ringing mode).
HIT = 1 Co nt r ols SLIC-S/-S2 -interface and sets t he T IP-wire to
high impedance (active mode).
REVPOL Reverse polarity of DC feed ing
REVP OL = 0 Normal pol arit y .
REVPOL = 1 Reverse polarity.
ACTR Sele ct ion of extended batte ry feeding in Ac t ive mod e.
In this caseVHR –VBATH for SLIC-S/-S2 is used.
ACTR = 0 No extended ba t t ery feeding sel e c te d .
ACTR = 1 Exten ded battery feeding selec te d.
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 288 2000-07-14
Preliminary
ACTL Selection of the low battery supply voltage VBATL on SLIC-S/-S2 if available.
Valid only in Active mode of the SLICOFI-2S/-2S2.
ACTL = 0 L ow battery supply voltage on SLIC-S/-S2 is not
selected.
ACTL = 1 L ow battery supply voltage on SLIC-S/-S2 is selected.
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 289 2000-07-14
Preliminary
1) Only for DuSLIC-S, is set to 1 for DuSLIC-S2
2) Only for DuSLIC-S, is set to 0 for DuSLIC-S2
16HBCR2 Basic Configuration Register 2 00HY
Bit76543210
REXT-
EN SOFT-
DIS TTX-
DIS1) TTX-
12K2) HIM-AN AC-
XGAIN 0PDOT-
DIS
REXT-EN En ables the use of an exte rnal rin g-sign al generat or. The synch roniza tion
is done via the RSYNC pin and the ring-burst-enable signal is transferred
via th e IO1 pi n.
REXT-EN = 0 External ringing is disabled.
REXT-EN = 1 External ringing enabled.
SOFT-DIS Polarity soft reversal (to minimize noise on DC feeding)
SOFT-DIS = 0 Po l arity sof t revers al activ e.
SOFT-DIS = 1 Polari t y hard reversal.
TTX-DIS Disables th e generation of TTX burs ts for mete ring sign als. If th ey are
disabled, reves e polarity is us ed instea d.
TTX-DIS = 0 TTX bursts ar e enabled.
TTX-DI S = 1 TTX bursts ar e dis abled, reverse polarity us ed.
TTX-12K Selection o f TT X frequencies
TTX-12K = 0 Selects 16 kHz TTX signals instead of 12 kHz signals.
TTX-12K = 1 12 kHz TTX signals.
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 290 2000-07-14
Preliminary
HIM-AN Higher impedance in analog impedance matching loop.
HIM-AN corresponds to the coefficients calculated with DuSLICOS. If the
coefficients are calculated with standard impedance in analog impedance
matching loop, HIM-AN must be set to 0; if the coefficients are calculated
with high impedance in analog impedance matching loop, HIM-AN must be
set to 1.
HIM-AN = 0 Standard impeda nc e in analog impeda nc e matching
loop (300 Ω).
HIM-AN = 1 High impedance in analog impe dance mat c hing loop
(600 Ω).
AC-XGAIN Analog gain in tran s m it direct ion (shoul d be s et to zero).
AC-XGAIN = 0 No additional analog gain in transmit direction.
AC-XGAIN = 1 Additional 6 dB analog amplification in transmit
direction.
PDOT-DIS Power Down Overtemperature Disable
PDOT-DIS = 0 W h en over temperat ur e is de te cted, th e SLI C - S/-S2
is automatically swi tched into P ow er Do wn High
Imped ance m ode (PDH ). This is the saf e operat ion
mode for the SLIC-S/-S2 in case of overtemperature.
To leave the autom atically ac t i v a t ed PDH mode,
DuSL I C has to be switched manually to P D H mode
and then in the m ode as des ired.
PDOT-DIS = 1 W h en over temperat ur e is de te cted, th e SLI C - S/-S2
doesn’t automatically switch into Power Down High
Impedance mode . In this case the output current o f
the SLIC-S/-S2 buffers is limited to a value which
keeps th e SLIC-S /-S2 tem peratu re below the upper
temperature lim it.
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 291 2000-07-14
Preliminary
17HBCR3 Basic Configuration Register 3 00HY
Bit76 5 43210
MU-
LAW LIN 0 PCMX-
EN 0 0 0 CRAM-
EN
MU-LAW Sele cts the PCM Law
MU-LAW = 0 A-Law enabled.
MU-LAW = 1 µ-Law enabled.
LIN Voice transmis sion in a 16 bit linear repres ent ation f or test purposes.
Note: Voic e tra nsmis sion on th e other cha nne l is inhibi te d if one ch an nel
is set to linear mode and the IOM-2 interface is used. In PCM/
µC int erface m ode both c hannels c an be in li near mode u sing two
consecutive PCM timeslots on the highways. A proper timeslot
selection must be specified.
LIN = 0 PCM mode enabled (8 bit , A- law or µ-law).
LIN = 1 Linear mode en able d (16 bit).
PCMX-EN Enables w rit ing of subscriber voice data t o t he PC M highwa y.
PCM X -EN = 0 Writin g of subs c r iber voic e data to PCM hi ghway is
disabled.
PCM X -EN = 1 Writin g of subs c r iber voic e data to PCM hi ghway is
enabled.
CRAM-EN Coeff ic i ent s from C RA M are use d for programmable filters and DC loop
behavior.
CRA M -EN = 0 Coefficie nts from R OM are us ed.
CRA M -EN = 1 Coefficie nts from C R A M are used .
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 292 2000-07-14
Preliminary
18HBCR4 Basic Configuration Register 4 00HY
Bit76543210
TH-DIS IM-DIS AX-DIS AR-DIS FRX-
DIS FRR-
DIS HPX-
DIS HPR-
DIS
TH-DIS Disables th e TH filter.
TH-DIS = 0 TH filter is enabled.
TH-DIS = 1 TH filter is disabled (HTH = 0).
IM-DIS Disables th e IM filter.
IM-DIS = 0 IM filter is enabled.
IM-DIS = 1 IM filter is disabled (HIM = 0).
AX-DIS Disables the AX filter.
AX-DIS = 0 AX filter is enabl ed.
AX-DIS = 1 AX filter is disabled (HAX = 1).
AR-DIS Disab les the AR f ilt er.
AX-DI S = 0 AR f ilter is enabled.
AX-DI S = 1 AR f ilter is disabled (HAR = 1).
FRX-DIS Disables the FR X f ilt er.
FRX-DIS = 0 FRX filter is enabled.
FRX-DI S = 1 FRX filter is di sabl ed (HFRX = 1).
FRR-DIS Disab l es the FRR filter.
FRR-DIS = 0 FRR filter is enabled.
FRR-DIS = 1 FRR filter is disabled (HFRR = 1).
HPX-DIS Disables the high -pass filt er in tr ans mit dire c tion.
HPX-D I S = 0 High-pass filt er is enabled.
HPX-DIS = 1 High-pa ss filter is disabled (HHPX = 1).
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 293 2000-07-14
Preliminary
HPR-DIS Disables the high-pass filter in receive direction.
HPR-DIS = 0 High-pass filter is enabled.
HPR-DIS = 1 High-pass filter is disabled (HHPR = 1).
19Hreserved 00HY
Bit76543210
00000000
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 294 2000-07-14
Preliminary
1AHDSCR DTMF Sender Co nf iguratio n R egis ter 00HY
Bit76543210
DG-KEY[3:0] COR8 PTG TG2-EN TG1-EN
DG-KEY[3:0] Selec ts one of si xteen D T M F keys ge nerated by the two tone gene-
rators. The key will be gene rated if both TG1-EN and TG2-E N are ‘1’.
Table 67 DTMF Keys
fLOW [Hz] fHIGH [Hz] DIGIT DG-KEY3 DG-KEY2 DG-KEY1 DG-KEY0
697 1209 1 0 0 0 1
697 1336 2 0 0 1 0
697 1477 3 0 0 1 1
770 1209 4 0 1 0 0
770 1336 5 0 1 0 1
770 1477 6 0 1 1 0
852 1209 7 0 1 1 1
852 1336 8 1 0 0 0
852 1477 9 1 0 0 1
941 1336 0 1 0 1 0
941 1209 * 1 0 1 1
941 1477 # 1 1 0 0
697 1633 A 1 1 0 1
770 1633 B 1 1 1 0
852 1633 C 1 1 1 1
941 1633 D 0 0 0 0
COR8 Cuts off the receive path at 8 kHz before the tone generator summation point.
Allows sending of tone gene rat or signals w it hout overlaid voice.
COR8 = 0 C ut of f receive path disabled.
COR8 = 1 C ut of f rece iv e path en abled.
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 295 2000-07-14
Preliminary
PTG Programmable coefficients for tone generators will be used.
PTG = 0 Frequencies set by DG-KEY are use d f or both tone
generators.
PTG = 1 CRAM coef ficient s used for both t one gene rators.
TG2-EN Enables tone generator two
TG2-E N = 0 Tone g enerator is disabled.
TG2-E N = 1 Tone g enerator is en abled.
TG1-EN Enables tone generator one
TG1-EN = 0 Tone generator is disabled.
TG1-EN = 1 Tone generator is enabled.
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 296 2000-07-14
Preliminary
1BHreserved 00HY
Bit76543210
00000000
1CHLMCR1 Leve l Me t ering Configuratio n R egister 1 22HY
Bit765 4 3210
TEST-
EN 01PCM2DC0010
TEST-EN Activates the SLICOFI-2S/-2S2 test features controlled by test registers
TSTR1 to TSTR5.
TEST-E N = 0 SLICOF I -2S/-2S 2 test features are dis abled.
TEST-EN = 1 SLICOFI-2S/-2S2 test features are enabled.
(The Test Register bits can be programmed before the TEST-EN bit is set
to 1.)
PCM2DC PCM voic e c hannel da t a added to the DC-outp ut .
PCM2DC = 0 N orm al operation.
PCM2DC = 1 PCM v oic e channel data is adde d to DC-o utput.
1DHLMCR2 Leve l Me t ering Configuratio n R egister 2 00HY
Bit76543210
00000000
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 297 2000-07-14
Preliminary
1EHLMCR3 Level Metering Configuratio n Regis te r 3 00HY
Bit76543210
AC-
SHORT
-EN
RTR-
SEL 000000
AC-
SHORT-EN The input pin ITAC will be set to a lower input impedance so that the
capacitor CITAC c an be recha rged faster dur ing s of t reversal which
makes it m ore silen t during conver sation.
AC-SH OR T -EN = 0 Input imp edance of the ITAC pin is stand ard.
AC-SH OR T -EN = 1 Input imp edance of the ITAC pin is lowered.
RTR-SEL Ring Trip method selection.
RTR-SEL = 0 Ring Trip with a DC offset is selected.
RTR-SEL = 1 AC Ring Trip is selected. Recommended for short
lines only.
1FHOFR1 Offset Register 1 (High Byte) 00HY
Bit76543210
OFFSET-H[7:0]
OFFSET-H[7:0] Of f se t re gis t er high byte.
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 298 2000-07-14
Preliminary
20HOFR2 Offset Register 2 (Low Byte) 00HY
Bit76543210
OFFSET-L[7:0]
OFFSET-L[7:0] Offset register low byte.
The value of this register together with OFFSET-H is added to the
input of the DC loop to compensate a given offset of the current
sensors in the SLIC-S/-S2.
21HPCMR1 PCM Receive Regi ster 1 00HY
Bit76543210
R1-
HW R1-TS[6:0]
R1-HW Selection of the PCM highway for receiving PCM data or the higher byte
of the f i rs t data s ample if linear 16 k H z PCM mode is selected.
R1-HW = 0 PCM highway A is selected.
R1-HW = 1 PCM highway B is selected.
R1-TS[6:0] S el e ction of the PCM time sl ot used for dat a re cepti on .
Note: The programmed PCM time slot must correspond to the available
slots defined by the PCLK frequency. No reception will occur if a
slot ou tside the actu al numbers of sl ots is programm ed. In linear
mode (bit LIN = 1 in register BCR3) R1-TS defines the first of two
cons ec ut iv e s lot s used for rec ept ion.
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 299 2000-07-14
Preliminary
22Hreserved 00HY
Bit76543210
23Hreserved 00HY
Bit76543210
24Hreserved 00HY
Bit76543210
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 300 2000-07-14
Preliminary
25HPCMX1 PCM Transmit Register 1 00HY
Bit76543210
X1-HW X1-TS[6:0]
X1-HW Sele cti o n of the PCM highwa y f or t r an smitting PCM data or the higher
byte of the firs t data s a m ple if linear 16 kHz PCM mode is selected.
X1-HW = 0 PCM highway A is selected.
X1-HW = 1 PCM highway B is selected.
X1-TS[6:0] Sel e cti on of the PCM time slot used for dat a tr an smi ssion.
Note: The programmed PCM time slot must correspond to the available
slots defined by the PCLK frequency. No transmission will occur if
a slot out side the actual nu mbers of slots is programmed . In linear
mode X1-TS defines the first of two consecutive slots used for
transmission. PCM data transmission is controlled by bits 6 to 2 in
register BCR3.
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 301 2000-07-14
Preliminary
26Hreserved 00HY
Bit76543210
27Hreserved 00HY
Bit76543210
28Hreserved 00HY
Bit76543210
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 302 2000-07-14
Preliminary
Regis t er setting is only act iv e if bit TEST -EN in registe r L M C R1 is set t o 1.
29HTSTR1 Test Register 1 00HTY
Bit76543210
PD-AC-
PR PD-AC-
PO PD-AC-
AD PD-AC-
DA PD-AC-
GN PD-
GNKC PD-
OFHC PD-
OVTC
PD-AC-PR AC-PREFI power down
PD-AC-PR = 0 Normal op erat ion.
PD-AC-PR = 1 Po wer down mode.
PD-AC-PO AC- PO FI power do wn
PD-AC-PO = 0 Norm al operatio n.
PD-AC-PO = 1 Power down m ode.
PD-AC-AD AC-ADC power down
PD-AC-AD = 0 N ormal op eration.
PD-AC- AD = 1 Power down mode, t ransmit path is inacti ve.
PD-AC-DA AC-DAC power down
PD-AC-D A = 0 Normal operatio n.
PD-AC-DA = 1 Power down mode, receive path is inactive.
PD-AC-GN AC-Gain power d ow n
PD-AC-GN = 0 N ormal op eration.
PD-AC- GN = 1 Pow er down mode.
PD-GNKC Ground Key c om parator (GNKC) is s et to p ow er down
PD-GNKC = 0 No r m al operation.
PD-GNKC = 1 Power down mode.
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 303 2000-07-14
Preliminary
PD-OFHC Off-hook comparator (OFHC) power down
PD-OFHC = 0 Normal operation.
PD-OF H C = 1 Power down mode.
PD-OVTC Overtemperature comparator (OVTC) power down
PD-OVTC = 0 Normal operati on.
PD-OVTC = 1 Power down mode .
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 304 2000-07-14
Preliminary
1) Only for DuSLIC-S, is set to 0 for DuSLIC-S2
Regis t er setting is only act iv e if bit TEST -EN in registe r L M C R1 is set t o 1.
2AHTSTR2 Test Register 2 00HTY
Bit76543210
PD-DC-
PR 0 PD-DC-
AD PD-DC-
DA PD-
DCBUF 0PD-
TTX-A1) PD-HVI
PD-DC-PR DC-PREFI power down
PD- DC-PR = 0 Normal operation .
PD- DC -PR = 1 Power dow n mode.
PD-DC-AD DC-ADC power down
PD-DC-AD = 0 Norma l operation.
PD-DC-AD = 1 Power down mode, transmit path is inactive.
PD-DC-DA DC-DAC power down
PD-DC-DA = 0 Normal operation.
PD-DC-D A = 1 P ow er down mo de, receiv e path is inactive.
PD-DCBUF DC-B U F F ER power dow n
PD-DCBUF = 0 Norm al operat ion.
PD-DCBUF = 1 Power down mode.
PD-TTX-A TTX adaptation DAC and PO F I po w er down
PD-TTX-A = 0 Normal operation.
PD-TTX-A = 1 Power down mode.
PD-HVI HV interface (to SLIC-S/-S2) power down
PD-HVI = 0 Normal opera t i on.
PD-HVI = 1 Power down mode .
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 305 2000-07-14
Preliminary
Regis t er setting is only act iv e if bit TEST -EN in registe r L M C R1 is set t o 1.
2BHTSTR3 Test Register 3 00HTY
Bit76543210
0 0 AC-
DLB-
4M
AC-
DLB-
128K
AC-
DLB-
32K
AC-
DLB-
8K
00
AC-DLB-4M AC digit al loop via 4 MH z bit stream. (Th e loop enc los es all digital
hardware in the AC path. Together with DLB-DC a pure digital test is
possible bec aus e there is no influence th e analog hardware.)
AC-DLB-4M = 0 Normal operation.
AC-DLB-4M = 1 Digital loop closed.
AC-DLB-128K AC dig ital l oo p vi a 128 kHz
AC-DLB-128K = 0 Normal operation.
AC-D LB-128K = 1 Digita l loop clos ed.
AC-DLB-32K AC digital l oo p vi a 32 kH z
AC-DLB-32K = 0 Normal operation.
AC-D LB-32K = 1 Digital loop closed.
AC-DLB-8K AC digi ta l loop via 8 kHz
AC-DLB-8K = 0 Normal operation.
AC-D LB-8K = 1 Digital loop closed.
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 306 2000-07-14
Preliminary
Regis t er setting is only act iv e if bit TEST -EN in registe r L M C R1 is set t o 1.
2CHTSTR4 Test Register 4 00HTY
Bit76543210
OPIM-
AN OPIM-
4M COR-64COX-160000
OPIM-AN Open Imped ance Ma tching Loop i n the analog par t.
OPIM-AN = 0 Normal operation.
OPIM-AN = 1 Loop opened.
OPIM-4M Open fas t di git al Imped ance Ma t ch i ng Loop in t he hardwa re filters.
OPIM-4M = 0 Normal operation.
OPIM-4M = 1 Loop opened.
COR-64 Cut off the AC receive path at 64 kHz (just bef ore the I M filter).
COR-64 = 0 Normal operation.
COR-64 = 1 Receive path is cut off.
COX-16 Cut off the AC transm i t path at 16 kHz . (The TH filter can be tes t ed
witho ut inf luencing the analog part.)
COX-1 6 = 0 Norm al operation.
COX-16 = 1 Transm it path is cut of f.
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 307 2000-07-14
Preliminary
Regis t er setting is only act iv e if bit TEST -EN in registe r L M C R1 is set t o 1.
2DHTSTR5 Test Register 5 00HTY
Bit76543210
000DC-
POFI-
HI
DC-
HOLD 000
DC-POFI-HI DC pos t filter limit frequenc y higher value
DC-POFI-HI = 0 Limit frequency is set to 100 Hz (normal operation).
DC-POFI-HI = 1 L imit frequency is set to 300 Hz.
DC-HOLD Actual DC outpu t value hold (v alue of the last DSP filter stage will be
kept)
DC- HOLD = 0 N ormal op eration.
DC- HOLD = 1 D C output va lue hold.
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 308 2000-07-14
Preliminary
6.3.2 CO P Command
The CO P comm and give s acces s to the CR AM data of the DSP s. It is orga nized in the
same way as the SOP command. The offset value allows a direct as well as a block
access to the CRAM. Writing beyond the allowed offset will be ignored, reading beyond
it will give u npredictable resu lts.
The value of a specific CRAM coefficient is calculated by the DuSLICOS software.
Bit 76543210
Byte 1 RD 1 ADR[2:0] 1 0 1
Byte 2 OFFSET[7:0 ]
RD Read Data
RD = 0 Write dat a t o chip.
RD = 1 Read data from chip.
ADR[2:0] Chann e l address for the s ubsequent data
ADR[2:0] = 0 0 0 Channel A
ADR[2:0] = 0 0 1 Channel B
(other c odes r e s e r ved for futur e use)
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 309 2000-07-14
Preliminary
Offset
[7:0] Short
Name Long Name
00HTH1 Transhybrid Filter Coefficients Part 1
08HTH2 Transhybrid Filter Coefficients Part 2
10HTH3 Transhybrid Filter Coefficients Part 3
18HFRR Frequency-respon s e Filter Coefficien ts Receive Direction
20HFRX Frequency -respon se Filter C oefficients T ransm it D irection
28HAR Amplification/Attenuation Stage Coefficients Receive
30HAX Amplification/Attenuation Stage Coefficients Transmit
38HPTG1 Tone Generator 1 Coefficients
40HPTG2 Tone Generator 2 Coefficients
48HLPR Low Pass Filter Coefficients Receive
50HLPX L ow Pass Filter Coefficients Transmit
58HTTX Te l et ax Coeffi c i ents
60HIM1 Impedance Matching Filter Coefficients Part 1
68HIM2 Impedance Matching Filter Coefficients Part 2
70HRINGF Ringer Frequency and Amplitude Coefficients (DC loop)
78HRAMPF Ramp Ge nerator C oefficie n t s (DC loop)
80HDCF DC-Characteristics Coefficients (DC loop)
88HHF Hook Threshold Coefficients (DC loop)
90HTPF L ow Pass Filter Coefficients (DC loop)
98HReserved
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 310 2000-07-14
Preliminary
Note: CRAM coefficients are enabled by setting bit CRAM-EN in register BCR3 to 1,
except coefficients PTG1 and PTG21) which are enabled by setting bit PTG in
register DSCR to 1.
Table 68 CRAM Coefficients
Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 B yte 1 Byte 0 Offse t
[7:0]
Transhybrid Coefficient Part 1 00HTH1
Transhybrid Coefficient Part 2 08HTH2
Transhybrid Coefficient Part 3 10HTH3
FIR Filter in Receive Direction 18HFRR
FIR Filter in Transmit Direction 20HFRX
2nd Gain Stage
Receive 1st Gain Stage Receive 28HAR
2nd Gain Stage
Transmit 1st Gain Stage Transmit 30HAX
TG1 Bandpass TG1 Gain T G1 Frequency 38HPTG11)
TG2 Bandpass TG2 Gain T G2 Frequency 40HPTG21)
Reserved 48H
Reserved 50H
FIR Filter for TTX TTX Slope TTX Level 58HTTX
IM K Factor IM FIR Filt er 60HIM1_F
IM 4 MHz Filter IM WDF Filter 68HIM2_F
Ring Generator
Amplitude Ring Generator
Frequency Ring Generator
Lowpass Ring Offset RO1 70HRINGF
Extended
Battery
Feeding
Gain
Soft Reversal End Constant Ramp
CR Soft Ramp SS Ring Delay RD 78HRAMPF
Res. in Resistive
Zone RK12 Res. in Constant
Current Zone RIConstant Current IK1 Knee Vol tage VK1 Open Circuit Volt.
VLIM 80HDCF
Hook Message
Waiting Hook Threshold
AC Ring Trip Hook Threshold
Ring Hook Threshold
Active Hook Threshold
Power Down 88HHF
Voltage Level VRT DC Lowpass Filter
TP2 DC Lowpass Filter
TP1 90HTPF
Reserved 98H
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 311 2000-07-14
Preliminary
6.3.2.1 CRAM Programming Ranges
Table 69 CRAM Programming Ranges
Parameter Programming Range
Cons tant Current IK1 0...50 mA, ∆<0.5mA
Hook Mess age Waiti ng,
Hook Thresholds 0..25 mA, ∆<0.7mA
25...50 mA, ∆<1.3mA
Ring Generator F r equency fRING 3..40 Hz, ∆<1Hz
40..80 Hz, ∆<2Hz
>80Hz,
∆<4Hz
Ring Generat or Am plitud e 0..20 V, ∆<1.7V
20..85 V, ∆<0.9V
Ring Offset RO1 0..25 V, ∆<0.6V
25..50 V, ∆<1.2V
50..100 V, ∆< 2.4 V, max. 150 V
Knee Voltage VK1,
Open Circuit Voltge VLIM
0..25 V, ∆<0.6V
25..50 V, ∆<1.2V
>50V,
∆<2.4V
Resistan ce in Resi s tive Zone RK12 0..1000 Ω, ∆<30Ω
Resistance in Constant Current Zone RI1.8 kΩ..4.8 kΩ, ∆< 120 Ω
4.8 kΩ..9.6 kΩ, ∆< 240 Ω
9.6 kΩ..19 kΩ, ∆<480Ω
19 kΩ..38 kΩ, ∆<960Ω, max . 40 kΩ
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 312 2000-07-14
Preliminary
6.3.3 IOM-2 Interface Command / Indication B yte
The Command/Indication (C/I) channel is used to communicate real time status
information and for fast controlling of the DuSLIC. Data on the C/I channel are
cont inuously transmit t ed in each f ram e until ne w data are se nt .
Data Downstream C/I – Chan nel Byte (R eceive ) – IOM - CIDD
The first six CIDD data bits control the general operating modes for both DuSLIC
channels. According to the IOM-2 specification, new data have to be present for at least
two fr am es to be ac cepted.
)
Table 70 M2, M1, M0: General Opera t ing Mode
CIDD SLICOFI-2S/-2S2 Operating Mode
(for details see “Operating Mode s fo r the DuSLIC
Chip Set” on Page 78)
M2 M1 M0
1 1 1 Sleep, Power Down (PDRx)
0 0 0 Power Dow n High Impedance (PD H )
0 1 0 Any Active mode
1 0 1 Ringing (ACT R Burst On)
1 1 0 Active with Metering
1 0 0 Ground Sta rt
001Ring Pause
CIDD Data Downstream C/I – Channel By te N
Bit 76543210
M2A M1A M0A M2B M1B M0B MR MX
M2A, M1A, M0A Select operating mo de for DuSLI C channel A
M2B, M1B, M0B Select operating mo de for DuSLI C channel B
MR, MX Hand shake b i ts Monitor Receive a nd T ransmit
(see “IOM-2 Interface Monitor Transfer Protoc ol ” on
Page 148)
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 313 2000-07-14
Preliminary
Data Upstream C/I – Channel Byte (Transmit) – IOM-CI DU
This byte is used to quickly transfer the most important and time-critical information from
the DuSLIC. Each transfer from th e DuSLIC lasts for at least two consecutive frames.
CIDU Data Upstream C/I – Channel Byte 00HN
Bit 7 6 5 4 3 2 1 0
INT-CHA HOOKA GNDKA INT-CHB HOOKB GNDKB MR MX
INT-CHA Interrupt information channel A
INT-CHA = 0 No interrupt in channel A
INT-CHA = 1 Interrupt in channel A
HOOKA Hook information channel A
HOOKA = 0 On-hook channel A
HOOKA = 1 Off-hoo k channel A
GNDKA Ground key info rm ation c hannel A
GNDKA = 0 No longitudin al current det ected
GNDKA = 1 Long it udinal current detected in cha nnel A
INT-CHB Interrupt information channel B
INT-CHB = 0 No interrupt in channel B
INT-CHB = 1 Interrupt in channel B
HOOKB Hook information channel B
HOOKB = 0 On-hook Channel B
HOOKB = 1 Off-hook Channel B
GNDKB Ground key info rm ation c hannel B
GNDKB = 0 No longitudin al current det ected
GNDKB = 1 Long it udinal current detected in cha nnel B
MR, MX Handshake bits Mo nitor Receive and Transm it
(see “IOM-2 Interface Monitor Transfer Protocol” on Page 148)
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 314 2000-07-14
Preliminary
6.3.4 Programming Examples of th e SLICOFI-2S/-2S2
6.3.4.1 Mic roc ontroller Interfa ce
SOP W r i t e to C h an n el 0 Starting After th e C h an n el -Specifi c R ead-Onl y R eg i sters
01000100 First command byt e ( SO P write for chann el 0)
00010101 Second command byte (offset to BCR1 register)
00000000 Conte nts of BCR1 regist er
00000000 Conte nts of BCR2 regist er
00010001 Conte nts of BCR3 regist er
00000000 Conte nts of BCR4 regist er
00000000 Conte nts of BCR5 regist er
Figure 76 Waveform of Programming Example SOP Write to Channel 0
SOP Read from Channel 1 Reading Out the Interrupt Registers
11001100 First command byte (SOP read for channel 1).
00000111 Second command byte (offset to Inte rr upt register 1).
The SLICOFI-2S/-2S2 will send data when it has completely received the second
command byt e.
11111111 Dump byte (this byte is always FFH).
11000000 Interrup t re gist er I N TREG 1 (a n inter rupt has occur red , Off- hook was detected).
00000010 Interrup t re gist er IN TREG 2 (I O pin 2 is ‘1’).
00000000 Interrup t re gist er I NTREG 3
00000000 Interrup t re gist er I NTREG 4
Figure 77 Waveform of Programming Example SOP Read from Channel 0
Command Offset BCR1
DIN
DCLK
CS
BCR2 BCR3 BCR4 BCR5
ezm220121.wmf
ezm220122.emf
DCLK
CS
Command Offset Dump Intreg 1
DOUT
DIN
Intreg 2 Intreg 3 Intreg 4
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 315 2000-07-14
Preliminary
6.3.4.2 IOM-2 Interface
An example with the same programming sequence as before, using the IOM-2 interface
is presented here to show the differences between the microcontroller interface and the
IOM-2 interface.
SOP W r i t e to C h an n el 0 Starting After th e C h an n el -Specifi c R ead-Onl y R eg i sters
Monitor MR/MX Monitor MR/MXComment
data down data up
10000001 10 11111111 11 IOM-2 address f irst byt e
10000001 10 11111111 01 IOM-2 address second byt e
01000100 11 11111111 01 First command byte (SOP write for channel 0)
01000100 10 11111111 11 First com ma nd byte secon d time
00010101 11 11111111 01 Second command byte (offset to BCR1 register)
00010101 10 11111111 11 Second command byte second time
00000000 11 1111 1111 01 C ontent s of BCR1 register
00000000 10 1111 1111 11 C ontent s of BCR1 register seco nd tim e
00000000 11 1111 1111 01 C ontent s of BCR2 register
00000000 10 1111 1111 11 C ontent s of BCR2 register seco nd tim e
00010001 11 1111 1111 01 C ontent s of BCR3 register
00010001 10 1111 1111 11 C ontent s of BCR3 register seco nd tim e
00000000 11 1111 1111 01 C ontent s of BCR4 register
00000000 10 1111 1111 11 C ontent s of BCR4 register seco nd tim e
11111 111 11 1111 1111 01 No more in fo rm at ion (dummy byt e)
11111111 11 11111111 11 Signaling EOM (end of message) by holding MX bit at ‘1’.
Since the SLICOFI-2S/-2S2 has an open command structure, no fixed command length
is given. The IOM-2 handshake protocol allows for an infinite length of a data stream,
therefore the host has to terminate the data transfer by sending an end-of-message
signal (EOM) to the SLICOFI-2S/-2S2. The SLICOFI-2S/-2S2 will abort the transfer only
if the host tries to write or read beyond the allowed maximum offsets given by the
different types of commands. Each transfer has to start with the SLICOFI-2S/-2S2-
specific IOM-2 Address (81H) and must end with an EOM of the handshake bits.
Appending a command immediately to its predecessor without an EOM in between is not
allowed.
When reading interrupt registers, SLICOFI-2S/-2S2 stops the transfer after the fourth
register in IOM-2 mode. This is to prevent some host chips reading 16 bytes because
they can’t terminat e th e tran sfe r afte r n bytes.
DuSLIC-S/-S2
SLICOF I-2x Co mmand Str uctur e and Programmi ng
Data Sheet 316 2000-07-14
Preliminary
SOP-Read from Channel 1 Reading Out the Interrupt Registers
Monitor MR/MX Monitor MR/MXComment
data down data up
10000001 10 11111111 11 IOM-2 address f irst byt e
10000001 10 11111111 01 IOM-2 address second byt e
11001100 11 11111111 01 First command byte (SOP read for channel 1)
11001100 10 11111111 11 First com ma nd byte secon d time
00001000 11 11111111 01 Second command byte (offset to interrupt register 1)
00001000 10 11111111 11 Second command byte second time
11111111 11 11111111 01 Acknowledgemen t for t he second com m and byte
11111111 11 10000001 10 IOM -2 Address first byt e (ans wer )
11111111 01 10000001 10 IOM-2 Address sec ond b yte
11111111 01 11000000 11 Interrup t re gist er I N TREG 1
11111111 11 11000000 10 Interrupt register I NTREG 1 second time
11111111 01 00000010 11 Interrup t re gist er I N TREG 2
11111111 11 00000010 10 Interrupt register I NTREG 2 second time
11111111 01 00000000 11 Interrup t re gist er I N TREG 3
11111111 11 00000000 10 Interrupt register I NTREG 3 second time
11111111 01 00000000 11 Interrup t re gist er I N TREG 4
11111111 11 00000000 10 Interrupt register I NTREG 4 second time
11111111 11 01001101 11 SLICOFI-2S/-2S2 sends the next register
11111111 11 1111 1111 11 SLICOFI-2S/-2S2 aborts transmission
DuSLIC
Electri cal Characteristics
Data Sheet 317 2000-07-14
Preliminary
7 Electrical Characteristics
7.1 Electrical Characteristics PEB 4264/-2 (SLIC-S/-S2)
7.1.1 Absolute Maximum Ratings PEB 4264/-2 (SLIC-S/-S2)
Parameter S ymbol Limit Value s Unit Test Condition
min. max.
Battery voltage L VBATL
VBATL – VBATH
– 65
– 0.4 0.4 V ref erred to
VBGND
Battery vo lt age VBATH – 70 0.4 V referred to
VBGND
Auxiliary supply
voltage VHR – 0.4 50 V referred to
VBGND
Total battery supply
voltage, contin uous VHR – VBATH – 0.4 95 V –
VDD supply voltage VDD – 0.4 7 V referred to
VAGND
Ground voltage
difference VBGND –
VAGND
– 0.4 0.4 V –
Input voltages VDCP, VDCN,
VACP, VACN,
VC1, VC2, VCMS
– 0.4 VDD + 0.4 V referred to
VAGND
Voltages on current
outputs VIT, VIL – 0.4 VDD + 0.4 V referred to
VAGND
RING, TIP voltages,
continuous VR, VTVBATL –0.4
VBATH –0.4
VBATH –0.4
0.4
0.4
VHR +0.4
V
V
V
ACTL
ACTH, PDRH,
PDRHL
ACTR, PDH,
HIT, HIR
RING,TIP voltages,
pulse < 10 ms VR, VTt.b.d t.b.d V all modes
RING,TIP voltages,
pulse < 1 ms VR, VTVBATH – 10 VHR + 10 V all modes
RING, TIP voltages,
pulse < 1 µsVR, VTVBATH – 10 VHR + 30 V all modes
DuSLIC
Electri cal Characteristics
Data Sheet 318 2000-07-14
Preliminary
Note: Stresses above those listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Maximum ratings are absolute ratings; even if only one of these values is
exceed ed, t he integrated circ uit m ay be irreversibly damaged.
ESD voltage, all
pins ––1 kV SDM (Socketed
Device Model)1)
Junction
temperature Tj–150 2) °C
1) EOS/ESD Assn. Standard DS5.3-1993.
2) Even higher value is possible when internal junction temperature protection is operative.
7.1.1 Absolute Maximum Ratings PEB 4264/-2 (SLIC-S/-S2) (cont’d)
Parameter S ymbol Limit Value s Unit Test Condition
min. max.
DuSLIC
Electri cal Characteristics
Data Sheet 319 2000-07-14
Preliminary
7.1.2 Operating Range PEB 4264/-2 (SLIC-S/-S2)
7.1.3 Thermal R esistances PEB 4264/- 2 (S LIC-S/-S2)
Parameter Symbol Limit Values Unit Test Condition
min. max.
Battery voltage L 1)
1) If the battery switch is not used both pins VBATL and VBATH should be connected together externally. In this
case the full voltage range of –15 V to –65 V can be used.
VBATL – 60 – 15 V referred to VBGND
Battery voltage H1) VBATH – 65 – 20 V r ef erred to VBGND
Auxiliary supply
voltage VHR 5 45 V referred to VBGND
Total battery supply
voltage VHR – VBATH –90 V –
VDD supply voltage VDD 4.75 5.25 V referred to VAGND
Ground voltage
difference VBGND –VAGND – 0.4 0.4 V –
Junction temperature Tj–125 °C simulate d for a
lifetime of 15
years
Voltage at pins I T , IL VIT, VIL – 0.4 3.5 V referred to VAGND
Input range VDCP,
VDCN, VACP, VACN
VACDC 0 3.3 V referred t o VAGND
Parameter Symbol Limit Values Unit Test Condition
Junction to case Rth, jC < 2 K/W –
Junction to ambient Rth, jA < 50 K/W withou t heatsink
DuSLIC
Electri cal Characteristics
Data Sheet 320 2000-07-14
Preliminary
7.1.4 Electrical Parameters PEB 4264/-2 (SLIC-S/-S2)
Minim u m and maximum v alues are va lid within the full operat ing range.
Func tionality and perform ance is gua ranteed for TA=0 to 70°C by producti on tes ting.
Extented temperature range operation at –40 °C<TA<85°C is guaranteed by design,
characterization and periodically sampling and testing production devices at the
temperature extremes.
Testing is performed according to the specific test figures. Unless otherwise stated, load
impedance RL = 600 Ω, VBATH = –48 V, VBATL = –24 V, VHR = + 32 V and VDD = + 5 V,
RIT = 1 kΩ, RIL = 2 kΩ,=CEXT = 470 nF. Ty pical val ues are te st ed at TA=25°C.
Supply Currents and Power Dissipation
(IR = IT = 0 A; VCMS =VACP =VACN =VDCP = VDCN =1.5V)
No. P arameter Symbo l Mode Limi t Value s U n it
min. typ. max.
Power Down High Impedance, Power Down Resistive High
1.
2. VDD current IDD PDH
PDRH –
–120
120 –
–µA
3.
4. VBATH current IBATH PDH
PDRH –
–65
80 –
–µA
5.
6. VBATL current IBATL PDH
PDRH –
–0
0–
–µA
7.
8. VHR current IHR PDH
PDRH –
–0
0–
–µA
9.
10. Quiescent power dissipation PQPDH
PDRH –
–3.7
4.4 –
–mW
Active Low
11. VDD current IDD ACTL –1000 1200 µA
12. VBATH current IBATH ACTL –25 45 µA
13. VBATL current IBATL ACTL –2800 3400 µA
14. VHR current IHR ACTL –010µA
15. Quiescent power dissipation PQACTL –73.4 89.8 mW
DuSLIC
Electri cal Characteristics
Data Sheet 321 2000-07-14
Preliminary
Active High
16. VDD current IDD ACTH –1000 1300 µA
17. VBATH current IBATH ACTH –3500 4300 µA
18. VBATL current IBATL ACTH –010µA
19. VHR current IHR ACTH –010µA
20. Quiescent power dissipation PQACTH –173 213.5 mW
Active Ring
21. VDD current IDD ACTR –500 700 µA
22. VBATH current IBATH ACTR –3100 3700 µA
23. VBATL current IBATL ACTR –010µA
24. VHR current IHR ACTR –2300 2800 µA
25. Quiescent power dissipation PQACTR –225 271 mW
High Impedance on RING, High Impe da nce on TIP
26. VDD current IDD HIR, HIT –500 700 µA
27. VBATH current IBATH HIR, HIT –2100 2600 µA
28. VBATL current IBATL HIR, HIT –010µA
29. VHR current IHR HIR, HIT –1500 2200 µA
30. Quiescent power dissipation PQHIR, HIT –151 199 mW
Supply Currents and Power Dissipation
(IR = IT = 0 A; VCMS =VACP =VACN =VDCP = VDCN =1.5V) (cont’d)
No. P arameter Symbo l Mode Limi t Value s U n it
min. typ. max.
DuSLIC
Electri cal Characteristics
Data Sheet 322 2000-07-14
Preliminary
7.1.5 Power Calculation PEB 4264/-2 (SLIC-S/-S2)
The total power dissipation consists of the quiescent power dissipation PQ given above,
the cur rent sens or power dissi pation PI (see Table 71), the gain stage power dissipation
correction PG1) (see Table 72) and the output stage power dissipation PO (see
Table 73):
Ptot = PQ + PI + PG + PO
with PQ=VDD ×IDD +IVBATHI×IBATH +IVBATLI×IBATL +VHR ×IHR
For the calcula tio n of PI, PG and PO see the f ollowi ng t ables:
.
1) The gain stage power dissipation correction PG is a correcting term necessary to ensure a correct power
calculation if other as the defined supply voltages are used.
Table 71 PI Calculation PEB 426 4 /-2 (SLIC-S/-S2)
Operating
Mode Equation for PI Calculation
PDH PI = 0 (no DC loop curren t)
PDRH,
PDRHL PI = ITrans=×=ITrans=×=(10000 + 500 + 16) + ITrans ×(0.6 + 0.425 ×|VBATH|)
ACTL PI = 0.055 ×ITrans ×|VBATL| + 0.04 ×ITrans ×VDD
ACTH PI = 0.055 ×ITrans ×|VBATH| + 0.04 ×ITrans ×VDD
ACTR PI = 0.015 ×ITrans ×VHR + 0.055 ×ITrans ×|VBATH| + 0.04 ×ITrans ×VDD
HIR, HIT PI = 0.015 ×ITorR1) ×VHR + 0.04 ×ITorR ×|VBATH| + 0.02 ×ITorR ×VDD
1) ITorR = ITIP or IRING
HIRT PI = 0 (no DC loop curren t)
DuSLIC
Electri cal Characteristics
Data Sheet 323 2000-07-14
Preliminary
7.1.6 Power Up Sequence PEB 4264/-2 (SLIC-S / -S2)
The supply voltages of the SLIC-S/-S2 have to be applied in the fol lowing order to the
respect iv e pin:
1) Gro und to pins AGND a nd BGND
2) VDD to pin VDD
3) VBATH to pin VB ATH
4) VHR to pin VHR and VBATL to pin VBATL
If the VDD voltage is applied more than one second later as VBATH, VHR or VBATL thermal
dama ge of th e SLIC-S/-S2 can ac c ur.
If the abov e sequenc e of the batt ery voltages can not be guarante ed, a diode (1N4007)
has to be inserted in the VBATH line
Table 72 PG Calculation PEB 4264/-2 (SLIC-S/-S2)
Operating
Mode Equation for PG Calculation
PDH, PDRH PG = 0 (gain stage not working)
ACTL PG = (VBATL2 –242)× (1/60k + 1/216 k)
ACTH, PDRHL PG = (VBATH2 –482)×(1/ 60k + 1/216k)
ACTR PG = (VHR + | VBATH|) ×(|VHR +VBATH +VTIP/RING|+
|VHR +VBATH –VTIP/RING|–2×|VHR +VBATH|)/120k +
(VHR2–322+VBATH2 –482)×(1/6 0k + 1/216k)
HIR, HIT, HIRT PG=(VHR +|VBATH|) ×(|VHR +VBATH +expVTIP/RING1)|+
|VHR +VBATH –VTIP/RING|–2×|VHR +VBATH|)/120k +
(VHR2–322+VBATH2–482)×(1/60k + 1/216k)
1) Expected VTIP/RING when SLIC-S/-S2 output buffer in high impedance.
Table 73 PO Calculation PEB 4264/-2 (SLIC-S/-S2)
Operating Mode Equation for PO Calculation
PDH, PDRH, PDRHL PO = 0 (outp ut stage not w orking)
ACTL PO = (|VBATL| – VTIP/RING)×ITrans
ACTH PO = (|VBATH| – VTIP/RING)×ITrans
ACTR PO = (VHR + |VBATH| – VTIP/RING)×ITrans
HIR, HIT PO = VSupply-TorR1) ×ITorR
1) VSupply-TorR = VSupply – VTIP or VRING
HIRT PO = 0 (output stage not w orking)
DuSLIC
Electri cal Characteristics
Data Sheet 324 2000-07-14
Preliminary
7.2 Electrical Characteristics PEB 4265/-2 (SLIC-E/-E2)
7.2.1 Absolute Maximum Ratings PEB 4265/-2 (SLIC-E/-E2)
Parameter Symbol Limit Values Unit Test Condition
min. max.
Battery voltage L VBATL
VBATL –VBATH
–85
–0.4 0.4
–V
Vreferred to VBGND
Battery voltage H VBATH –90 0.4 V referred to VBGND
Auxiliary supply
voltage VHR –0.4 90 V referred to VBGND
Total battery supply
voltage, contin uous VHR –VBATH –160 V –
VDD supply voltage VDD –0.4 7 V referred to VAGND
Ground voltage
difference VBGND –VAGND –0.4 0.4 V –
Input voltages VDCP, VDCN,
VACP, VACN,
VC1, VC2, VCMS
–0.4 VDD + 0.4 V referr ed to VAGND
Voltages on current
outputs VIT, VIL –0.4 VDD + 0.4 V refer red to VAGND
RING, TIP voltages,
continuous VR, VTVBATL –0.4
VBATH –0.4
VBATH –0.4
0.4
0.4
VHR +0.4
V
V
V
ACTL
ACTH, PDRH,
PDRHL
ACTR, PDH,
HIRT, HIT, HIR
RING, TIP voltages,
pulse < 10 ms VR, VTt.b.d t.b.d V all modes
RING, TIP voltages,
pulse < 1 ms VR, VTVBATH –10 VHR + 10 V all modes
RING, TIP voltages,
pulse < 1 µsVR, VTVBATH –10 VHR + 30 V all modes
ESD volt age,
all pins ––1 kV SDM (Socketed
Device Model)1)
1) EOS/ESD Assn. Standard DS5.3-1993.
Junction
temperature Tj–150 2)
2) Even higher value is possible when internal junction temperature protection is operative.
°C
DuSLIC
Electri cal Characteristics
Data Sheet 325 2000-07-14
Preliminary
Note: Stresses above those listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Maximum ratings are absolute ratings; even if only one of these values is
exceed ed, t he integrated circ uit m ay be irreversibly damaged.
7.2.2 Operating Range PEB 4265/-2 (SLIC-E/-E2)
7.2.3 Thermal R esistances PEB 4265/- 2 (S LIC-E/-E2)
Parameter Symbol Limit Values Unit Test Condition
min. max.
Battery voltage L 1)
1) If the battery switch is not used both pins VBATL and VBATH should be connected together externally. In this
case the full voltage range of –15 V to –85 V can be used.
VBATL –80 –15 V ref erred to VBGND
Battery voltage H1) VBATH –85 –20 V referred to VBGND
Auxiliary supply voltage VHR 5 85 V referred to VBGND
Total battery supply
voltage VHR –VBATH –150 V –
VDD supply voltage VDD 4 .7 5 5.25 V referred to VAGND
Ground voltage
difference VBGND –VAGND –0.4 0.4 V –
Junction temperature Tj–125 °C simulated for a
lifetim e of 15 y ears
Voltage at pins I T , IL VIT, VIL –0.4 3. 5 V referred to VAGND
Input range VDCP,
VDCN, VACP, VACN
VACDC 0 3.3 V referred t o VAGND
Parameter Symbol Limit Values Unit Test Condition
Junction to case Rth, jC < 2 K/W –
Junction to ambient Rth, jA < 50 K/W withou t heatsink
DuSLIC
Electri cal Characteristics
Data Sheet 326 2000-07-14
Preliminary
7.2.4 Electrical Parameters PEB 4265/-2 (SLIC-E/-E2)
Minim u m and maximum v alues are va lid within the full operat ing range.
Func tionality and perform ance is gua ranteed for TA=0 to 70°C by producti on tes ting.
Extented temperature range operation at –40 °C<TA<85°C is guaranteed by design,
characterization and periodically sampling and testing production devices at the
temperature extremes.
Testing is performed according to the specific test figures. Unless otherwise stated, load
impedance RL = 600 Ω, VBATH = –48 V, VBATL = –24 V, VHR = + 32 V and VDD = + 5 V,
RIT = 1 kΩ, RIL = 2 kΩ,=CEXT = 470 nF. Ty pical val ues are te st ed at TA=25°C.
Supply Currents and Power Dissipation
(IR = IT = 0 A; VCMS =VACP =VACN =VDCP = VDCN =1.5V)
No. P arameter Symbo l Mode Limi t Value s U n it
min. typ. max.
Power Down High Impedance, Power Down Resistive High
1.
2. VDD current IDD PDH
PDRH –
–120
120 –
–µA
3.
4. VBATH current IBATH PDH
PDRH –
–65
80 –
–µA
5.
6. VBATL current IBATL PDH
PDRH –
–0
0–
–µA
7.
8. VHR current IHR PDH
PDRH –
–0
0–
–µA
9.
10. Quiesc ent pow er
dissipation PQPDH
PDRH –
–3.7
4.4 –
–mW
Active Low
11. VDD current IDD ACTL –1000 1200 µA
12. VBATH current IBATH ACTL –25 45 µA
13. VBATL current IBATL ACTL –2800 3400 µA
14. VHR current IHR ACTL –010µA
15. Quiescent power dissipation PQACTL –73.4 89.8 mW
DuSLIC
Electri cal Characteristics
Data Sheet 327 2000-07-14
Preliminary
Active High
16. VDD current IDD ACTH –1000 1300 µA
17. VBATH current IBATH ACTH –3500 4300 µA
18. VBATL current IBATL ACTH –010µA
19. VHR current IHR ACTH –010µA
20. Quiescent power dissipation PQACTH –173 213.5 mW
Active Ring
21. VDD current IDD ACTR –500 700 µA
22. VBATH current IBATH ACTR –3100 3700 µA
23. VBATL current IBATL ACTR –010µA
24. VHR current IHR ACTR –2300 2800 µA
25. Quiescent power dissipation PQACTR –225 271 mW
High Impedance on RING, High Impe da nce on TIP
26. VDD current IDD HIR, HIT –500 700 µA
27. VBATH current IBATH HIR, HIT –2100 2600 µA
28. VBATL current IBATL HIR, HIT –010µA
29. VHR current IHR HIR, HIT –1500 2200 µA
30. Quiescent power dissipation PQHIR, HIT –151 199 mW
High Impedance on RING and TIP
31. VDD current IDD HIRT –500 700 µA
32. VBATH current IBATH HIRT –1000 1500 µA
33. VBATL current IBATL HIRT –010µA
34. VHR current IHR HIRT –600 800 µA
35. Quiescent power dissipation PQHIRT –69.7 101.3 mW
Supply Currents and Power Dissipation
(IR = IT = 0 A; VCMS =VACP =VACN =VDCP = VDCN =1.5V) (cont’d)
No. P arameter Symbo l Mode Limi t Value s U n it
min. typ. max.
DuSLIC
Electri cal Characteristics
Data Sheet 328 2000-07-14
Preliminary
7.2.5 Power Calculation PEB 4265/-2 (SLIC-E/-E2)
The total power dissipation consists of the quiescent power dissipation PQ given above,
the cur rent sens or power dissi pation PI (see Table 74), the gain stage power dissipation
correction PG1) (see Table 75) and the output stage power dissipation PO (see
Table 76):
Ptot = PQ + PI + PG + PO
with PQ=VDD ×IDD +IVBATHI×IBATH +IVBATLI×IBATL +VHR ×IHR
For the calcula tio n of PI, PG and PO see the f ollowi ng t ables:
1) The gain stage power dissipation correction PG is a correcting term necessary to ensure a correct power
calculation if other as the defined supply voltages are used.
Table 74 PI Calculation PEB 426 5 /-2 (SLIC-E/-E2)
Operating
Mode Equation for PI Calculation
PDH PI = 0 (no DC loop curren t)
PDRH,
PDRHL PI = ITrans ×ITrans ×(10000 + 500 + 16 ) + ITrans ×(0.6 + 0.425 ×|VBATH|)
ACTL PI = 0.055 ×ITrans ×|VBATL| + 0.04 ×ITrans ×VDD
ACTH PI = 0.055 ×ITrans ×|VBATH| + 0.04 ×ITrans ×VDD
ACTR PI = 0.015 ×ITrans ×VHR + 0.055 ×ITrans ×|VBATH| + 0.04 ×ITrans ×VDD
HIR, HIT PI = 0.015 ×ITorR ×VHR + 0.04 ×ITorR ×|VBATH| + 0.02 ×ITorR ×VDD
HIRT PI = 0 (no DC loop curren t)
DuSLIC
Electri cal Characteristics
Data Sheet 329 2000-07-14
Preliminary
7.2.6 Power Up Sequence PEB 4265/-2 (SLIC-E / -E2)
The supply voltages of the SLIC-E/-E2 have to be applied in the fol lowing order to the
respect iv e pin:
1) Gro und to pins AGND a nd BGND
2) VDD to pin VDD
3) VBATH to pin VB ATH
4) VHR to pin VHR and VBATL to pin VBATL
If the VDD voltage is applied more than one second later as VBATH, VHR or VBATL thermal
dama ge of th e SLIC-E/-E2 can ac c ur.
If the abov e sequenc e of the batt ery voltages can not be guarante ed, a diode (1N4007)
has to be inserted in the VBATH line.
Table 75 PG Calculation PEB 4265/-2 (SLIC-E/-E2)
Operating Mode Equation for PG Calculation
PDH, PDRH PG = 0 (gain stage not w ork ing)
ACTL PG = (VBATL2 – 242)×(1/60k + 1/216k)
ACTH, PDRHL PG = (VBATH2 – 482)×(1/60k + 1/216k )
ACTR PG=(VHR +|VBATH|) ×(|VHR +VBATH +VTIP/RING|+
|VHR +VBATH –VTIP/RING|–2×|VHR +VBATH|)/120k +
(VHR2–322+VBATH2–482)×(1/60k + 1/216k)
HIR, HIT, HIRT PG=(VHR +|VBATH|) ×(|VHR +VBATH +expVTIP/RING1)|+
|VHR + VBATH –expVTIP/RING|– 2 ×|VHR +VBATH|)/120k +
(VHR2–322+VBATH2–482)×(1/6 0k + 1/216k)
1) Expected VTIP/RING when SLIC-E/-E2 output buffer in high impedance.
Table 76 PO Calculation PEB 4265/-2 (SLIC-E/-E2)
Operating Mode Equation for PO Calculation
PDH, PDRH, PDRHL PO = 0 (output stage not working)
ACTL PO = (|VBATL| – VTIP/RING)×ITrans
ACTH PO = (|VBATH| – VTIP/RING)×ITrans
ACTR PO = (VHR + |VBATH| – VTIP/RING)×ITrans
HIR, HIT PO = VSupply-TorR ×ITorR
HIRT PO = 0 (output stage not working)
DuSLIC
Electri cal Characteristics
Data Sheet 330 2000-07-14
Preliminary
7.3 Electrical Characteristics PEB 4266 (SLIC-P)
7.3.1 Absolute Maximum Ratings PEB 4266 (SLIC-P)
Parameter Symbol Limit Values Unit Test Condition
min. max.
Battery voltage L VBATL
VBATL – VBATH
– 145
– 0.4 0.4 V referred to VBGND
Battery voltage H VBATH – 150 0.4 V referred t o VBGND
Battery voltage R VBATR
VBATH – VBATR
– 155
– 0.4 0.4 V referred to VBGND
Total battery supply
voltage, contin uous VDD – VBATR –160 V –
VDD supply voltage VDD – 0.4 7 V referred t o VAGND
Ground voltage
difference VBGND – VAGND – 0.4 0.4 V –
Input voltages VDCP, VDCN,
VACP, VACN,
VCMS VC1, VC2,
VC3
– 0.4 VDD + 0.4 V referred to VAGND
Voltages on current
outputs VIT, VIL – 0. 4 VDD + 0.4 V referred to VAGND
RING, TIP voltages,
continuous VR, VTVBATL – 0.4
VBATH – 0. 4
VBATR – 0. 4
+ 0.4
+ 0.4
+ 0.4
V
V
V
ACTL
ACTH, PDRH,
PDRHL
ACTR , PDH,
PDRR, PDRRL,
HIRT, HIT, HIT,
ROT, ROR
RING,TIP voltages,
pulse < 10 ms VR, VTt.b.d t.b.d V all mod e s
RING,TIP voltages,
pulse < 1 ms VR, VTVBATR – 10 + 10 V all mod es
RING, TIP voltages,
pulse < 1 µsVR, VTVBATR – 10 + 30 V all modes
DuSLIC
Electri cal Characteristics
Data Sheet 331 2000-07-14
Preliminary
Note: Stresses above those listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Maximum ratings are absolute ratings; even if only one of these values is
exceed ed, t he intergated circ uit m ay be irreversibly damaged.
ESD voltage, all
pins ––1kVSDM (Socketed
Device Model)1)
Junction
temperature Tj–150 2) °C
1) EOS/ESD Assn. Standard DS5.3-1993.
2) Even higher value is possible when internal junction temperature protection is operative.
7.3.1 Absolute Maximum Ratings PEB 4266 (SLIC-P) (cont’d)
Parameter Symbol Limit Values Unit Test Condition
min. max.
DuSLIC
Electri cal Characteristics
Data Sheet 332 2000-07-14
Preliminary
7.3.2 Operating Range PEB 4266 (SLIC-P)
7.3.3 T hermal R esistances P E B 4266 (SLIC - P)
Parameter Symbol Limit Values Unit Test Condition
min. max.
Battery voltage L 1)
1) Internal ringing: If the battery switch is not used both pins VBATL and VBATH should be connected together
externally. In this case the full voltage range of –15 V to –145 V can be used.
External ringing: If only one negative battery voltage is used the pins VBATL, VBATH and VBATR should be
connected together externally. In this case the full voltage range of –15 V to –145 V can be used.
VBATL – 140 – 15 V referred to VBGND
Battery voltage H1) VBATH – 145 – 20 V referred to VBGND
Battery voltage R1) VBATR – 150 – 25 V referred to VBGND
Total battery supply
voltage VDD – VBATR –155 V –
VDD supply voltage VDD 3.1 5.5 V referred to VAGND
Ground voltage
difference VBGND – VAGND – 0.4 0.4 V –
Junction temperature Tj–125 °C simulated fo r a
lifetim e of 15
years
Voltage at pins I T , IL VIT, VIL – 0.4 3.5 V referred to VAGND
Input range VDCP,
VDCN, VACP, VACN
VACDC 0 3. 3 V referred t o VAGND
Parameter Symbol Limit Values Unit Test Condition
Junction to case Rth, jC 2K/W–
Junction to ambient Rth, jA 50 K/W w it hout heat s i nk
DuSLIC
Electri cal Characteristics
Data Sheet 333 2000-07-14
Preliminary
7.3.4 Electrical Parameters PEB 4266 (SLIC-P)
Minim u m and maximum v alues are va lid within the full operat ing range.
Func tionality and perform ance is gua ranteed for TA=0 to 70°C by producti on tes ting.
Extented temperature range operation at –40 °C<TA<85°C is guaranteed by design,
characterization and periodically sampling and testing production devices at the
temperature extremes.
Testing is performed according to the test figures with external circuitry as indicated in
the tables. Unles s ot herwise s ta te d, load imped ance RL=600Ω, VBATH =–48 V,
VBATL =–24 V, VBATR =–80 V and VDD =+5V, RIT =1kΩ, RIL =2kΩ,
CEXT = 4 70 nF. Typi c al v alues are test ed at TA=25°C.
Supply Currents and Power Dissipation
(IR = IT = 0 A; VCMS =VACP =VACN =VDCP = VDCN =1.5V)
No. P ar ameter Symb o l M o d e Limi t Val u es Unit
min. typ. max.
Power Down High Impedance, Power Down Resistive Ring,
Power Down Resistive High
1.
2.
3.
VDD current IDD PDH
PDRR
PDRH
–130
140
140
180
190
190
µA
µA
µA
4.
5.
6.
VBATH current IBATH PDH
PDRR
PDRH
–0
0
60
10
10
120
µA
µA
µA
7.
8.
9.
VBATL current IBATL PDH
PDRR
PDRH
–0
0
0
10
10
10
µA
µA
µA
10.
11.
12.
VBATR current IBATR PDH
PDRR
PDRH
–75
90
35
110
150
90
µA
µA
µA
13.
14.
15.
Quiescent power dissipation PQPDH
PDRR
PDRH
–6.7
7.9
6.4
10.4
13.7
14.1
mW
mW
mW
DuSLIC
Electri cal Characteristics
Data Sheet 334 2000-07-14
Preliminary
Active Low
16. VDD current IDD ACTL –900 1100 µA
17. VBATH current IBATH ACTL –10 15 µA
18. VBATL current IBATL ACTL –2100 2700 µA
19. VBATR current IBATR ACTL –10 25 µA
20. Quiescent power dissipation PQACTL –56.1 73.0 mW
Active High
21. VDD current IDD ACTH –900 1100 µA
22. VBATH current IBATH ACTH –2700 3400 µA
23. VBATL current IBATL ACTH –010µA
24. VBATR current IBATR ACTH –10 25 µA
25. Quiescent power dissipation PQACTH –134.9 170.9 mW
Active Ring1)
26. VDD current IDD ACTR –900 1200 µA
27. VBATH current IBATH ACTR –010µA
28. VBATL current IBATL ACTR –010µA
29. VBATR current IBATR ACTR –3500 4400 µA
30. Quiescent power dissipation PQACTR –284.5 358.7 mW
Ring on Ring, Ring on Tip
31. VDD current IDD ROR, ROT –800 1100 µA
32. VBATH current IBATH ROR, ROT –010µA
33. VBATL current IBATL ROR, ROT –010µA
34. VBATR current IBATR ROR, ROT –2400 2800 µA
35. Quiescent power dissipation PQROR, ROT –196 230.2 mW
Supply Currents and Power Dissipation
(IR = IT = 0 A; VCMS =VACP =VACN =VDCP = VDCN =1.5V) (cont’d)
No. P ar ameter Symb ol Mode Limit Val ues Unit
min. typ. max.
DuSLIC
Electri cal Characteristics
Data Sheet 335 2000-07-14
Preliminary
High Impedance on RING, High Impe da nce on TIP
36. VDD current IDD HIR, HIT –700 900 µA
37. VBATH current IBATH HIR, HIT –010µA
38. VBATL current IBATL HIR, HIT –010µA
39. VBATR current IBATR HIR, HIT –3000 3900 µA
40. Quiescent power dissipation PQHIR, HIT –243.5 317.2 mW
High Impedance on RING and TIP
41. VDD current IDD HIRT –500 800 µA
42. VBATH current IBATH HIRT –010µA
43. VBATL current IBATL HIRT –010µA
44. VBATR current IBATR HIRT –2400 2900 µA
45. Quiescent power dissipation PQHIRT –194.5 236.7 mW
1) ROR and ROT for IR = IT = 0 and VTR = VBATR/2
Supply Currents and Power Dissipation
(IR = IT = 0 A; VCMS =VACP =VACN =VDCP = VDCN =1.5V) (cont’d)
No. P ar ameter Symb ol Mode Limit Val ues Unit
min. typ. max.
DuSLIC
Electri cal Characteristics
Data Sheet 336 2000-07-14
Preliminary
7.3.5 Power Ca l cu l ati on PEB 426 6 (S LIC-P)
The total power dissipation includes the quiescent power dissipation PQ given above, the
current sensor power dissipation PI (see Table 77), the gain stage power dissipation
correction PG1) (see Table 78), and the output stage power dissipation PO (see
Table 79):
Ptot = PQ + PI + PG + PO
with PQ = VDD ×IDD + IVBATRI×IBATR+ IVBATHI×IBATH +VBATL ×IBATL
For the calcula tio n of PI, PG and PO see the f ollowi ng t ables:
1) The gain stage power dissipation correction PG is a correcting term necessary to ensure a correct power
calculation if other as the defined supply voltages are used.
Table 77 PI Calculation PEB 4266 (SLIC-P)
Operating Mode Equation for PI Calculation
PDH PI = 0 (no DC lo op c urrent)
PDRH, PDRHL PI = ITrans ×ITrans ×(10000 + 50 0 + 24)
+ ITrans ×(0.6 + 0.425 ×|VBATH|)
PDRR, PDRRL PI = ITrans ×ITrans ×(10000 + 50 0 + 16)
+ ITrans ×(0.6 + 0.425 ×|VBATR|)
ACTL PI = 0.055 ×ITrans ×|VBATL| + 0.04 ×ITrans ×VDD
ACTH PI = 0.055 ×ITrans ×|VBATH| + 0.04 ×ITrans ×VDD
ACTR PI = 0.055 ×ITrans ×|VBATR| + 0.04 ×ITrans ×VDD
ROR, ROT PI = 0.055 ×ITrans ×|VBATR| + 0.04 ×ITrans ×VDD
HIR, HIT PI = 0.05 5 ×ITorR ×|VBATR| + 0.04 ×ITorR ×VDD
HIRT PI = 0 (no DC lo op c urrent)
DuSLIC
Electri cal Characteristics
Data Sheet 337 2000-07-14
Preliminary
7.3.6 P ower Up Sequ en ce PE B 4266 (SLIC - P)
The supply voltages of the SLIC-P have to be applied in the following order to the
respect iv e pin:
1) Gro und to pins AGND a nd BGND
2) VDD to pin VDD
3) VBATR to pin VB ATR
4) VBATH to pin VB AT H and VBATL to pin VBATL
If the VDD voltage is applied more than one second later as VBATR, VBATH or VBATL
thermal dam age of the SLIC -P can accur.
If the abov e sequenc e of the batt ery voltages can not be guarante ed, a diode (1N4007)
has to be inserted in the VBATR line.
Table 78 PG Calculation PEB 4266 (SLIC-P)
Operating Mode Eq uation for PG Calculation
PDH, PDRH, PDRR PG = 0 (gain stage not working)
ACTL PG = (VBATL2–242)×(1/60k + 1/216k)
ACTH, PDRHL PG = (VBATH2–482)×(1/60k + 1/216k)
ACTR, PDRRL, HIR,
HIT, HIRT PG = (VBATR2 –802)×(1/60k + 1/216k)
ROR, ROT PG = (VTIP/RING2–(VBATR/2)2)/60k
+ (VBATR2–802×(1/60k + 1/216k)
Table 79 PO Calculation PEB 4266 (SLIC-P)
Operating Mode Equation for PO Calculation
PDH, PDRH, PDRHL,
PDRR, PDRRL PO = 0 (output stage not working)
ACTL PO = (|VBATL| – VTIP/RING)×ITrans
ACTH PO = (|VBATH| – VTIP/RING)×ITrans
ACTR PO = (|VBATR| – VTIP/RING)×ITrans
ROR, ROT PO = (|VBATR| – VTIP/RING)×ITrans
HIR, HIT PO = VSupply-TorR ×ITorR
HIRT PO = 0 (output stage not working)
DuSLIC
Electri cal Characteristics
Data Sheet 338 2000-07-14
Preliminary
7.4 Electric al Char a cteristics PEB 3265/PEB 3264/PEB 3264-2
(SLICOFI-2/-2S/-2S2)
7.4.1 Absolute Maximum Ratings
Note: Stresses above those listed under Absolute Maximum Ratings may cause
permane nt da mage to the devic e . Func tion al opera tion und er th ese con ditio ns is
not guaranteed. Exposure to conditions beyond those indicated in the
recommended operational conditions of this specification may affect device
reliability.
Parameter1)
1) i, j = A, B, D, R, PLL
Symbol Limit Value s Unit Test Condition
min. max.
Supply pins ( VDDi) referred to
the corresponding ground pin
(GNDi)
––
=0.3 4.6 V –
Ground pins (GNDi) referred to
any ot her ground pin (GNDj) ––
=0.3 0.3 V –
Supply pins ( VDDi) referred to
any ot her supply pin (VDDj) ––
=0.3 0.3 V –
Analog input an d out put pins ––
=0.3 3.6 V VDDA =3.3V,
VGNDA/B =0V
Digita l in put and ou tput pi ns ––
=0.3 5.5 V VDDD = 3.3 V,
VGNDD = 0 V
DC input and output current at
any input or output pin (free from
latch-up)
––100 mA –
Storage tempe r at ure TSTG –65 125 °C–
Ambient temperature under bias TA–40 85 °C–
Power dissipation PD–1W–
ESD voltage ––2 kV Human body
model2)
2) MIL STD 883D, method 3015.7 and ESD Assn. standard S5.1-1993.
ESD v olt age, all pin s ––1 kV SDM (Socketed
Device Model)3)
3) EOS/ESD Assn. Standard DS5.3-1993.
DuSLIC
Electri cal Characteristics
Data Sheet 339 2000-07-14
Preliminary
7.4.2 Operating Range
VGNDD = VGNDPLL = VGNDR = VGNDA/B = 0 V
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Supply pins (VDDi) referred
to the corresponding
ground pin (GN Di)
(i = A, B, D, R, PLL)
3.135 3.3 3.465 V
Anal og input pins referre d
to the ground pin (GN D j)
(j = A, B)
ITj, ILj,
ITACj,
VCMITj
0–3.3 V VDDj =3.3V
VGNDj =0V
Analog output pins referred
to the ground pin (GN D j)
(j = A, B)
ACPj, DCPj, ACNj , DCNj ,
VCMS, VCM
C1, C2
0.3
1.3
0
–
–
–
2.7
1.7
3.3
V
V
V
VDDj =3.3V
VGNDj =0V
Analog pins for passive
devices to ground pin
(GNDj) (j = A, B)
CDCPj, CDCNj
CREF 0
1.3 –
–3.3
1.7 V
V
VDDj =3.3V
VGNDj =0V
Digita l input and outpu t pins 0 –5V
Ambient temperature TA–40 –+85 °C
DuSLIC
Electri cal Characteristics
Data Sheet 340 2000-07-14
Preliminary
7.4.3 Po w er D i ssipation PEB 326 5 (S LICOFI -2)
TA=–40 °C to 85 °C, unless otherwise stated.
VDDD = VDDA = VDDB = VDDR = VDDPLL =3.3V±5%;
VGNDA = VGNDB = VGNDR = VGNDD = VGNDPLL =0V
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
VDD supply current 1)
1) Power dissipation and supply currents are target values
Sleep bot h chann els IDDSleep –5 7 mA (MCLK, PCLK = 2 MHz)
Power Down bo t h
channels IDDPDown –24 30 mA –
Active one channel IDDAct1 –
–
–
39
43
47
46
50
55
mA
mA
mA
without EDSP2)
with 8 MIPS
(DTMF detection)
with 16 MIPS
2) EDSP features are DTMF detection, Caller ID generation, Line Echo Cancellat ion (LEC) and Universal Tone
Detection (UTD).
Active both channels IDDAct2 –
–55
70 70
90 mA
mA without EDSP
with 32 MIPS
Power dissipation1)
Sleep bot h chann els PDDSleep –17 25 mW (MCLK, PCLK = 2 MHz )
Power Down bo t h
channels PDDPDown –79 104 mW –
Active one channel PDDAct1 –
–
–
129
142
155
160
174
191
mW
mW
mW
without EDSP
with 8 MIPS
(DTMF detection)
with 16 MIPS
Active both channels PDDAct2 –
–182
231 243
315 mW
mW without EDSP
with 32 MIPS
DuSLIC
Electri cal Characteristics
Data Sheet 341 2000-07-14
Preliminary
7.4.4 Power Dissipation PEB 3264, PEB 3264-2 (SLICOFI-2S/-2S2)
TA=–40 °C to 85 °C, unless otherwise stated.
VDDD = VDDA = VDDB = VDDR = VDDPLL =3.3V±5%;
VGNDA = VGNDB = VGNDR = VGNDD = VGNDPLL =0V
7.4.5 Power Up Sequence for Supply Voltages
The power up of VDDA, VDDB, VDDR, VDDD and VDDPLL should be performed
simultaneously. No voltage should be supplied to any input or output pin before the VDD
voltages are app lied.
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
VDD supply current 1)
1) Power dissipation and supply currents are target values
Power Down bo t h
channels IDDPDown –24 30 mA –
Active one channel IDDAct1 –39 46 mA
Active both channels IDDAct2 –55 70 mA
Power dissipation1)
Power Down bo t h
channels PDDPDown –79 104 mW –
Active one channel PDDAct1 –129 160 mW
Active both channels PDDAct2 –182 243 mW
DuSLIC
Electri cal Characteristics
Data Sheet 342 2000-07-14
Preliminary
7.4.6 Digital Interface
TA = –40 to + 85 °C, unless otherwise stated.
VDD = VDDD = VDDA/B = 3.3 V ± 5%; VGNDD = VGNDA/B = 0 V
Figure 78 Hysteresis for Input Pins
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
For all input pins
(including IO pins):
Low-input po s. -going VT+ –1.70 1.82 V see Figure 78
High-input neg.-going VT- 1.13 1.20 –Vsee Figure 78
Input hysteresis VH0.48 0.5 0.56 V VH = VT+ –VT-
Spike rejection for reset trej 1–4µs–
For all ou t put pin s
except DU, DXA, DXB,
IO1, IO2 (including
IO pins):
Low-o ut put voltage VOL –0.35 0.4 V IO = –=3.6 mA
High-outpu t v o lt age VOH 2.7 3.0 –VIO = 3.3 mA
for pins DU, DXA, DXB
Low-o ut put voltage VOLDU –0.35 0.4 V IO = –=6 mA
High-outpu t v o lt age VOHDU 2.7 3.0 –VIO = 5.3 mA
for p ins IO1, IO2
Low-o ut put voltage VOLDU –0.35 0.4 V IO = –=50 mA
(PEB 3265)
VOLDU –0.35 0.4 V IO = –=30 mA
(PEB 3264/-2)
High-outpu t v o lt age VOHDU 2.7 3.0 –VIO = 3.3 mA
VT- VT+ VIN
VOUT
ezm04122.emf
DuSLIC
Electri cal Characteristics
Data Sheet 343 2000-07-14
Preliminary
7.5 AC Transmission DuSLIC
The target figures in this specification are based on the subscriber linecard
requirements. The proper adjustment of the programmable filters (transhybrid balancing,
imped ance matc hing, freque ncy-respons e correc tion) requir es the c onsideration of the
comp let e analog environ ment of the SLICOFI-2x device.
Func tionality and perform ance is gua ranteed for TA=0 to 70°C by producti on tes ting.
Extented temperature range operation at –40 °C<TA<85°C is guaranteed by design,
characterization and periodically sampling and testing production devices at the
temperature extremes.
Test Conditions
TA=–40 °C to 85 °C, unless otherwise stated.
VDDD = VDDA = VDDB = VDDR = VDDPLL = 3.3 V ± 5%;
VGNDA = VGNDB = VGNDR = VGNDD = VGNDPLL = 0 V
RL > 600 Ω; CL < 10 pF
LR = 0 … -10dBr
LX = 0 … +3dBr
f = 1014 Hz; 0 dBm0; A-Law or µ-Law;
Figure 79 Signal Definitions Transmit, Receive
Note: To ensure the stability of the SLIC output buffer, RSTAB and CSTAB have to be set
to the values RSTAB =30Ω and CSTAB ≥300 pF (1 nF in the test circuit
Figure 79).
For electromagn etic compatibility CSTAB must be s et to t he m uch h igh er v alu e of
CSTAB =15nF (see Figure 98).
IOM
®
-2
PCM
0.775V
rms
TIP
RING
2·0.775V
rms
600
tra ns mit (x )
0dBm0
re c e ive (r)
0dBm0
600
R
STAB
30
C
STAB
1n
xr
r
x
SLIC
PEB 426x
SLICOFI-2x
PEB 326x
R
STAB
30
C
STAB
1n
ezm22018.emf
DuSLIC
Electri cal Characteristics
Data Sheet 344 2000-07-14
Preliminary
The 0 dBm0 definitions f or R eceive and Trans m it are:
A 0 dBm0 AC signal in Transmit direction is equivalent to 0.775 Vrms (referred to an
impe da nce of 600 Ω).
A 0 dBm0 AC signal in Receive direction is equivalent to 0.775 Vrms (referred to an
impe da nce of 600 Ω).
LR=–10 dBr means:
A signal of 0 d Bm0 at the digital in put c orrespond to -10 dBm at the analog i nt erf ac e.
LX= + 3 dBr means:
A signal of 3 dBm at the analog interfac e corres pond to 0 dBm0 at t he digital ou tput.
Table 80 AC Transmission
Parameter Sym bol Conditions Limit Values Unit
min. typ. max.
Longit udinal cur rent
capability AC Ill per active line 30 –– mArms
Overload level VRT 300 - 4000 Hz 2.3 –– Vrms
Transmission Performance (2-wire)
Return loss RL 200 - 3600 Hz 26 –– dB
Insertion Loss (2-wire to 4-wire and 4-wire to 2-wire)
Gain accuracy –
Transmit GX0 dBm0, 10 14 Hz –0.25 –+0.25 dB
Gain accuracy –
Receive GR0 dBm0, 10 14 Hz –0.25 –+0.25 dB
Gain variation with
temperature
–40 …+85°C
–– ––± 0.1 d B
DuSLIC
Electri cal Characteristics
Data Sheet 345 2000-07-14
Preliminary
Frequency Response (see Figure 81 and Figure 82)
Receive loss
Frequency variatio n GRAF Reference frequenc y 10 14 Hz, signal lev el 0 dBm0,
HFRR =1
f = 0 - 300 Hz –0.25 –– dB
f = 300 - 400 Hz –0.25 –0.9 dB
f = 400 - 600 Hz –0.25 –0.65 dB
f = 600 - 2400 Hz –0.25 –0.25 dB
f = 2400 - 3000 H z –0.25 –0.45 dB
f = 3000 - 3400 H z –0.25 –1.4 dB
f = 3400 - 3600 H z –0.25 –– dB
Transmit loss
Frequency variatio n GXAF Reference frequenc y 10 14 Hz, signal lev el 0 dBm0,
HFRX=1
f = 0 - 200 Hz 0–– dB
f = 200 - 300 Hz –0.25 –– dB
f = 300 - 400 Hz –0.25 –0.9 dB
f = 400 - 600 Hz –0.25 –0.65 dB
f = 600 - 2400 Hz –0.25 –0.25 dB
f = 2400 - 3000 Hz –0.25 –0.45 dB
f = 3000 - 3400 Hz –0.25 –1.4 dB
f = 3400 - 3600 Hz –0.25 –– dB
Table 80 AC Transmission (cont’d)
Parameter Sym bol Conditions Limit Values Unit
min. typ. max.
DuSLIC
Electri cal Characteristics
Data Sheet 346 2000-07-14
Preliminary
Gain Tracking (see Figure 83 and Figure 84)
Transmi t gain
Signal lev el variation GXAL Sinusoidal test method
f = 1014 Hz, reference level –10 dBm0
VFXI = – 55 to
–50 dBm0 –1.4 –1.4 dB
VFXI = – 50 to
–40 dBm0 –0.5 –0.5 dB
VFXI = – 40 to
+3dBm0 –0.25 –0.25 dB
Receive ga in
Signal lev el variation GRAL Sinusoidal test meth od
f = 1014 Hz, reference level –10 dBm0
DR0 = – 55 to
– 50 dBm 0 – 1.4 –1.4 dB
DR0 = – 50 to
– 40 dBm 0 – 0.5 –0.5 dB
DR0 = – 40 to
+ 3 dBm0 – 0.25 –0.25 dB
Balanc e ret urn loss 300 - 3400 H z 26 –– dB
Group Delay (see Figure 85)
Transmit de lay,
absolute DXA f = 500 - 2800 Hz 400 490 585 µs
Receive de lay ,
absolute DRA f = 500 - 2800 Hz 290 380 475 µs
Grou p delay, Receiv e
and Transmit, relative
to 1500 Hz
DXR f = 500 - 600 Hz ––300 µs
f = 600 - 1000 Hz ––150 µs
f = 1000 - 2600 H z ––100 µs
f = 2600 - 2800 H z ––150 µs
f = 2800 - 3000 H z ––300 µs
Overload compression
A/D OC –––––
Table 80 AC Transmission (cont’d)
Parameter Sym bol Conditions Limit Values Unit
min. typ. max.
DuSLIC
Electri cal Characteristics
Data Sheet 347 2000-07-14
Preliminary
Longitudina l Balanc e (ac cor ding to ITU-T O.9 )
Longitudinal
conversion loss L-T 300 - 1000 Hz
DuSLIC-S/-E/-P
DuSLIC-S2/-E2
3400 Hz
DuSLIC-S/-E/-P
DuSLIC-S2/-E2
53
60
52
56
58
65
55
59
–
–
–
–
dB
dB
dB
dB
Input longitudi nal
interference loss L-4 300 - 1000 H z
DuSLIC-S/-E/-P
DuSLIC-S2/-E2
3400 Hz
DuSLIC-S/-E/-P
DuSLIC-S2/-E2
53
60
52
56
58
65
55
59
–
–
–
–
dB
dB
dB
dB
Transversal to
longitudinal T-L 300 - 4000 H z 46 –– dB
Longit udinal sign al
generation 4-L 300 - 4000 Hz 46 –– dB
TTX Signal Generation
TTX signal VTTX at 200 Ω––2.5 Vrms
Out-of-Band Noise (Single Frequency Inband –25 dBm0)
Transversal VRT 12 kHz - 200 kHz ––55 –50 dBm
Longitudinal VRT 12 kHz - 200 kHz ––55 –50 dBm
Out-of-Band Idle Channel Noise at Analog Output
Measured with 3 kHz Bandwidth
VRT 10 kHz ––– 50 dBm
VRT 300 kHz ––– 50 d Bm
VRT 500 kHz ––– 70 d Bm
VRT 1000 kH z ––– 70 dBm
Table 80 AC Transmission (cont’d)
Parameter Sym bol Conditions Limit Values Unit
min. typ. max.
DuSLIC
Electri cal Characteristics
Data Sheet 348 2000-07-14
Preliminary
Out-of-Band Signals at Analog Output (Receive) (see Figure 86)
Out-of-Band Signals at Analog Input (Transmit) (see Figure 87)
Total Harmonic Distortion
2-wire to 4-wire THD4 –7dBm0,
300 - 3400 Hz ––50 – 44 d B
4-wire to 2-wire THD2 – 7 dBm 0,
300 - 3400 Hz –– 50 – 44 dB
Idle Channel Noise
2-wire port (receive)
A-law NRP Psophometric
TTX disabled
TTX enabled –
––
––74
–70 dBmp
dBmp
µ-law NRC C message
TTX disabled
TTX enabled –
––
–16
20 dBrnC
dBrnC
PCM side (transmit)
A-Law NTP Psophometric
TTX disabled
TTX enabled –
––
––69
–67 dBm0p
dBm0p
µ-Law NTC C message
TTX disabled
TTX enabled –
––
–18
20 dBrnC
dBrnC
Table 80 AC Transmission (cont’d)
Parameter Sym bol Conditions Limit Values Unit
min. typ. max.
DuSLIC
Electri cal Characteristics
Data Sheet 349 2000-07-14
Preliminary
Distortion (Sinusoidal Test Method, see Figure 89, Figure 88 and Figure 90)
Signal to to tal
distortion Transmit STDXOutput connection: LX=0dBr
f = 1014 Hz ( C me ssage-weigh t ed f or µ-law,
psophometrically w eighted for A-law)
–45 dBm0 22 –– dB
–40 dBm0 27 –– dB
–30 dBm0 34 –– dB
–20 dBm0 36 –– dB
–10 dBm0 36 –– dB
3 dBm0 36 –– dB
Signal to to tal
distortion Receive STDRIn put connect i on: LR=–7dBr
f = 1014 Hz ( C me ssage-weigh t ed f or µ-law,
psophometrically w eighted for A-law)
–45 dBm0 17 –– dB
–40 dBm0 22 –– dB
–30 dBm0 31 –– dB
–20 dBm0 35.5 –– dB
–10 dBm0 36 –– dB
3 dBm0 36 –– dB
Signal to to tal
distortion Receive STDRIn put connect i on: LR=0dBr
f = 1014 Hz ( C me ssage-weigh t ed f or µ-law,
psophometrically w eighted for A-law)
–45 dBm0 22 –– dB
–40 dBm0 27 –– dB
–30 dBm0 34 –– dB
–20 dBm0 36 –– dB
–10 dBm0 36 –– dB
3 dBm0 36 –– dB
Table 80 AC Transmission (cont’d)
Parameter Sym bol Conditions Limit Values Unit
min. typ. max.
DuSLIC
Electri cal Characteristics
Data Sheet 350 2000-07-14
Preliminary
Figure 80 Overload Compression
Power Supply Rejection Ratio
VDD/VRT
(SLIC) PSRR 300 - 3400 Hz
ACTL, AC T H 33 –– dB
VDDi/VRT
(SLICOFI-2x)
i = A, B, D, R, PLL
PSRR 300 - 3400 Hz
ACTL, AC T H 27 –– dB
VBATH/VRT,
VBATL/VRT
(SLIC)
PSRR 300 - 3400 Hz 33 –– dB
Table 80 AC Transmission (cont’d)
Parameter Sym bol Conditions Limit Values Unit
min. typ. max.
01 2 4 56789
-1
0
2
3
4
5
6
7
8
9
1
0.25
-0.25
3
Funda mental Input Pow er (dB m0)
Fundamental
Output
Power
(dBm0)
3.4
4.2
4.5
ezm14009.emf
DuSLIC
Electri cal Characteristics
Data Sheet 351 2000-07-14
Preliminary
7.5.1 Frequency Response
Figure 81 Frequ enc y Respons e Transmit
Reference frequency 1 kHz, signal level 0 dBm0, HFRX =1
Figure 82 Frequency Respons e Receive
Reference frequency 1 kHz, signal level 0 dBm0, HFRR = 1
1.0
-1
0
1
2
kHz
Frequency
dB
Attenuation
3.02.0
3.4
0
.3 3.6.2 .4 .6 2.4
-0.25
0.25
0.45
0.65
0.9
1.4
x
ezm00110.emf
1.0
-1
0
1
2
kHz
Frequency
dB
Attenuation
3.02.0
3.4
0
.3 3.6.4 .6 2.4
-0.25
0.25
0.45
0.65
0.9
1.4
x
ezm00111.emf
DuSLIC
Electri cal Characteristics
Data Sheet 352 2000-07-14
Preliminary
7.5.2 G ain Tr acking (Rec ei ve or Tran smit)
The gain devia tions s ta y within the limit s in the figures below.
Figure 83 Gain Tracking Receive
Measured w i t h a sine wave of f = 1014 Hz, the refere nce level is –10 dBm0.
Figure 84 Gain Tracking Transmit
Measured w i t h a sine wave of f= 1014 Hz, th e ref erence level is –10 dBm0.
-70 -60 -55 -50 -40 -30 -20 -10 0 3 10
Input level dBm0
+ 0.25
+ 0.5
+ 1
+ 1.4
+ 2
- 0.25
- 0.5
- 1
- 1.4
- 2
dB
G
ezm00117.emf
-70 -60 -55 -50 -40 -30 -20 -10 0 3 10
Input level dBm0
+ 0.25
+ 0.5
+ 1
+ 1.4
+ 2
- 0.25
- 0.5
- 1
- 1.4
- 2
dB
G
ezm00118.emf
DuSLIC
Electri cal Characteristics
Data Sheet 353 2000-07-14
Preliminary
7.5.3 Group Delay
Minimum delays occure when the SLICOFI-2x is operating with disabled Frequency
Response Receive and Transmit filters (bit FRR-DIS and bit FRX-DIS in
register BCR4 set to 1) including the delay through A/D and D/A converters. Specific
filter programming may cause additional group delays. Absolute Group delay also
depe nds on the programmed time sl ot .
Grou p delay dist ort ion stays within t he limits in the f igures be low.
Figure 85 Group Delay Distortion Receive and Transmit
Signal lev el 0 dBm 0
Table 81 Group Delay Absolute Values: Signal level 0 dBm0
Parameter Symbol Limit Values Unit Test Condition Fig.
min. typ. max.
Transmi t delay DXA 400 490 585 µsf = 1.5 kHz –
Receive de lay DRA 290 380 475 µsf = 1.5 kHz –
00.50.6 11.5 2 2.6 2.8 3 3.5 4
Frequency kHz
0
100
150
200
300
400
500
T
G
µs
ezm00112.emf
DuSLIC
Electri cal Characteristics
Data Sheet 354 2000-07-14
Preliminary
7.5.4 Out-of-Band Signals at Analog Output (Receive)
With a 0 dBm0 sine wave with a frequency of f (300 Hz to 3.4 kHz) applied to the digital
inpu t, the level of any re sulting out-of-b and signal at the analo g outp ut will stay at least
X dB be low a 0 dBm0, 1 kHz sine wave ref erence s ignal at the analog output .
Figure 86 Out-of-Band Signal s at Analog Outpu t ( Rec eive)
itd09762.emf
00.06 0.1 3.4 4.0 4.6 6.0 10.0 18.0 200
dB
35
30
25
20
15
10
0
Receive Out-of-Band
Discrimination X
45
28
5
kHz
f
40
3.4 ... 4.6 kHz: X 14 π4000 f–
1200
---------------------
sin 1
–
–=
DuSLIC
Electri cal Characteristics
Data Sheet 355 2000-07-14
Preliminary
7.5.5 Out-of-Band Signals at Analog Input (Transmit)
With a 0 d Bm 0 out -of-b and sine w av e sign al wi th a frequ en cy o f f (< 100 H z or 3.4 kHz
to 100 kHz) appl ied to the an alo g input , the level of any resul ting f requen cy c omp onent
at the digita l output will stay at least X dB be low a 0 dBm0 , 1 kHz sine wa ve reference
signal a t the analog input.1)
Figure 87 Out-of-Band Signals at Analog Input (Transmit)
1) Poles at 12 kHz ± 150 Hz and 16 kHz ± 150 Hz respectively and harmonics will be provided
itd09763.emf
3.4 ... 4. 0 kHz: X 14 π4000 f–
1200
---------------------
sin 1
–
–=
4.0 ... 4. 6 kHz: X 18 π4000 f–
1200
---------------------
sin 7
9
---–
–=
0 0.06 0.1 3.4 4.0 4.6 6.0 10.0 18.0 100
40
35
32
30
25
20
15
10
0
Transmit Out-of-Band
Discrimination X
kHz
f
dB
DuSLIC
Electri cal Characteristics
Data Sheet 356 2000-07-14
Preliminary
7.5.6 Total Distorti on Me asured with Sine Wave
The signal to total d is tortion ratio ex c eeds the limits in the following figure:
Figure 88 Total Distortion Transmit (LX=0dBr)
Measured with a sine wave of f= 1014 Hz (C message-weighted forΙµ-law, psoph ome -
trically weighte d for A-law).
Figure 89 Total Distortion Receive (LR=–7dBr)
Meas ured w ith a sine wave o f f= 1014 H z (C m e ssa ge- weigh te d for µ-law, psophome-
trically weighte d for A-law).
-60 -50 -40 -30 -20 -10 0
dBm0
d
B
40
30
20
10
0-45
27
Input level
S/D
22
34
3
36
ezm00120.emf
-60 -50 -40 -30 -20 -10 0
dBm0
dB
40
30
20
10
0-45
31
22
Input level
S/D
36
17
35,5
3
ezm00119.emf
DuSLIC
Electri cal Characteristics
Data Sheet 357 2000-07-14
Preliminary
Figure 90 Total Distortion Receive (LR=0dBr)
Meas ured w ith a sine wave o f f= 1014 H z (C m e ssa ge- weigh te d for µ-law, psophome-
trically weighte d for A-law).
-60 -50 -40 -30 -20 -10 0
dBm0
dB
40
30
20
10
0-45
27
Inpu t le v el
S/D
22
34
3
36
ezm00120.emf
DuSLIC
Electri cal Characteristics
Data Sheet 358 2000-07-14
Preliminary
7.6 DC Characteristics
TA=–40 °C to 85 °C, unless otherwise stated.
Table 82 DC Characteri s ti cs
Parameter Symbol Conditi ons Limit Values Unit
min. typ. max.
Line Termination Tip, Ring
Sinu soida l Ringin g
Max. ringing voltage VRNG0 VHR –VBATH = 150 V,
VDC = 20 V for ring trip
(DuSLIC-E/-E2)
–VBATR = 150 V,
VDC = 20 V for ring trip
(DuSLIC-P)
VHR –VBATH = 90 V,
VDC = 20 V for ring trip
(DuSLIC-S/-S2)
85
85
45
–
–
–
–
Vrms
Vrms
Vrms
Outpu t impedanc e ROUT SLIC output buffer and
RSTAB
–61 –Ω
Harmonic distortion THD –––5%
Output current limit |IR, max.|,
|IT, max.|Modes: Active
SLIC-E/-E2/-S/-S2:
SLIC-P: 80
70
–
105
90 130
110 mA
mA
Loop current gain
accuracy –– ––3%
Loop current offset
error1) –– –0.75 0.75 mA
Loop open resist ance
TIP to VBGND
RTG Modes: Power Down
IT=2mA, TA=25°C–5–kΩ
Loop open resist ance
RING to VBAT
RBG Modes: Power Down
IR=2mA, TA=25°C–5–kΩ
Ring trip function –– ––––
Ring trip DC voltage –SLIC-E/-E2/-S/-S2:
SLIC-P: balance d
SLIC-P: unbalanc ed
0
0
–VBATR/2
30
30
–
Vdc
Vdc
Vdc
DuSLIC
Electri cal Characteristics
Data Sheet 359 2000-07-14
Preliminary
Ring trip detection time
delay –– ––2pe-
riods
Ring off time delay –– ––2pe-
riods
1) can be reduced with current offset error compensation described in Chapter 4.8.2.8
Table 82 DC Characteristics (cont’d)
Parameter Symbol Conditi ons Limit Values Unit
min. typ. max.
DuSLIC
Electri cal Characteristics
Data Sheet 360 2000-07-14
Preliminary
7.7 DuSLIC Timing Characteristics
TA=–40 °C to 85 °C, unless otherwise stated.
7.7.1 MCLK/FSC Timing
Figure 91 MCLK / FSC-Timing
Parameter S ymbol Limit Values Unit
min. typ. max.
Period MCLK1)
512 kH z ± 100 p pM
1536 kH z ± 100 ppM
2048 kH z ± 100 ppM
4096 kH z ± 100 ppM
7168 kH z ± 100 ppM
8192 kH z ± 100 ppM
1) The MCLK frequency must be an integer multiple of the FSC frequency.
tMCLK 1952.93
650.98
488.23
244.116
139.495
122.058
1953.13
651.04
488.28
244.141
139.509
122.070
1953.32
651.11
488.33
244.165
139.523
122.082
ns
MCLK high time tMCLKh 0.4 ×tMCLK 0.5 ×tMCLK 0.6 ×tMCLK µs
Period FSC1) tFSC –125 –µs
FSC setup time tFSC_s 10 50 –ns
FSC hold time tFSC_h 40 50 –ns
FSC (or PCM) jitter
time –0.2 ×tMCLK +0.2×tMCLK ns
t
MCLK
MCLK
FSC
FSC_S
t
MCLKh
t
t
FSC_H
FSC
t
50%
ezm35000.emf
DuSLIC
Electri cal Characteristics
Data Sheet 361 2000-07-14
Preliminary
7.7.2 PCM Interface Timing
7.7.2.1 Single-Clocking Mode
Figure 92 PCM Interface Timing - Single-Clocking Mode
Parameter S ymbol Limit Values Unit
min. typ. max.
Period PCLK1) tPCLK 1/8192 1/(n*64) with
2≤n≤128 1/128 ms
PCLK high time tPCLKh 0.4 ×tPCLK 0.5 ×tPCLK 0.6 ×tPCLK µs
Period FSC1) tFSC –125 –µs
FSC setup time tFSC_s 10 50 –ns
FSC hold time tFSC_h 40 50 –ns
DRA/B setup time tDR_s 10 50 –ns
DRA/B hold time tDR_h 10 50 –ns
DXA/ B delay time2) tdDX 25 –tdDX_min +
0.4 ×CLoad[pF] ns
t
PCLK
PCLK
FSC
DRA/B
DXA/B
FSC_S
t
PCLKh
t
High Imp.
t
DR_S DR_H
t
t
dDX dDXhz
t
t
FSC_H
FSC
t
TCA/B
dTCon
tt
dTCoff
50%
ezm22013.wmf
DuSLIC
Electri cal Characteristics
Data Sheet 362 2000-07-14
Preliminary
7.7.2.2 Double-Clocking Mode
Figure 93 PCM Interface Timing – Double-Clocking Mode
DXA/ B delay time
to high Z tdDXhz 25 –50 ns
TCA/B delay time on tdTCon 25 –tdTCon_min +
0.4 ×CLoad[pF] ns
TCA/B delay time off tdTCoff 25 –tdTCoff_min +
(RPullup[kΩ]×
CLoad[pF])
ns
1) The PCLK frequency must be an integer multiple of the FSC frequency.
2) All delay times are made up by two components: an intrinsic time (min-time), caused by internal processings,
and a second component caused by external circuitry (CLoad, RPullup >1.5kΩ)
Parameter S ymbol Limit Values Unit
min. typ. max.
t
PCLK
PCLK
FSC
DRA/B
DXA/B
FSC_S
t
PCLKh
t
High Imp.
t
DR_S DR_H
t
t
dDX dDXhz
t
t
FSC_H
FSC
t
TCA/B
dTCon
t t
dDTCoff
50%
ezm22014.wmf
DuSLIC
Electri cal Characteristics
Data Sheet 363 2000-07-14
Preliminary
Parame ter Symbol Limit Va l ues Unit
min. typ. max.
Period PCLK1) tPCLK 1/8192 1/(n*64) with
2≤n≤64 1/256 ms
PCLK high time tPCLKh 0.4 ×tPCLK 0.5 ×tPCLK 0.6 ×tPCLK µs
Period FSC1) tFSC –125 –µs
FSC setup time tFSC_s 10 50 –ns
FSC hold time tFSC_h 40 50 –ns
DRA/B setup time tDR_s 10 50 –ns
DRA/B hold time tDR_h 10 50 –ns
DXA/ B delay time2) tdDX 25 –tdDX_min +
0.4 ×CLoad[pF] ns
DXA/B delay time to
high Z tdDXhz 25 –50 ns
TCA/B delay time on tdTCon 25 –tdTCon_min +
0.4 ×CLoad[pF] ns
TCA/B delay time off tdTCoff 25 –tdTCoff_min +
(RPullup[kΩ]×
CLoad[pF])
ns
1) The PCLK frequency must be an integer multiple of the FSC frequency.
2) All delay times are made up by two components: an intrinsic time (min-time), caused by internal processings,
and a second component caused by external circuitry (CLoad, RPullup >1.5kΩ)
DuSLIC
Electri cal Characteristics
Data Sheet 364 2000-07-14
Preliminary
7.7.3 Microco ntroller Interface Timing
Figure 94 Microcontroller Interface Timing
Parameter Symbol Limit Values Unit
min. typ. max.
Period DCLK tDCLK 1/8192 –– ms
DCLK high time tDCLKh –0.5 ×
tDCLK
–µs
CS setup time tCS_s 10 50 –ns
CS hold time tCS_h 30 50 –ns
DIN setup time tDIN_s 10 50 –ns
DIN hold time tDIN_h 10 50 –ns
DOUT delay time1)
1) All delay times are made up by two components: an intrinsic time (min-time), caused by internal processings,
and a second component caused by external circuitry (CLoad)
tdDOUT 30 –tdDOUT_min +
0.4 ×CLoad[pF] ns
DOUT delay time to high Z tdDOUThz 30 –50 ns
DCLK
CS
DIN
DOUT
CS_S
t
High Imp .
t
DIN_S DIN_H
t
t
dDOUT dDOUThz
t
t
DCLKh
DCLK
t
t
CS_h
50%
ezm22015.wmf
DuSLIC
Electri cal Characteristics
Data Sheet 365 2000-07-14
Preliminary
7.7.4 IOM-2 I n terface Ti mi n g
7.7.4.1 Single-Clocking Mode
Figure 95 IOM-2 Interface Timing – Single -C locking Mode
Parameter S ymbol Limit Values Unit
min. typ. max.
Period DCL1)
1) The DCL frequency must be an integer multiple of the FSC frequency.
tDCL –1/2048 –ms
DCL high time tDCLh 0.4 ×tDCL 0.5 ×tDCL 0.6 ×tDCL µs
Period FSC1) tFSC –125 –µs
FSC setup time tFSC_s 10 50 –ns
FSC hold time tFSC_h 40 50 –ns
DD setup time tDD_s 10 50 –ns
DD hold time tDD_h 10 50 –ns
DU delay time2)
2) All delay times are made up by two components: an intrinsic time (min-time), caused by internal processings,
and a second component caused by external circuitry (CLoad, RPullup >1.5kΩ)
tdDX 25 –tdDX_min +
0.4 ×CLoad[pF] ns
DU dela y time to hi gh Z tdDXhz 25 –50 ns
t
DCL
DCL
FSC
DD
DU
FSC_S
t
DCLh
t
High Imp.
t
DD_S DD_H
t
t
dDU dDUhz
t
t
FSC_H
FSC
t
50%
ezm22016.wmf
DuSLIC
Electri cal Characteristics
Data Sheet 366 2000-07-14
Preliminary
7.7.4.2 Double-Clocking Mode
Figure 96 IOM-2 Interface Timing – Double-Clocki ng Mode
Parame ter Symbol Limi t Va l ues Unit
min. typ. max.
Period DCL1)
1) The DCL frequency must be an integer multiple of the FSC frequency.
tDCL –1/4096 –ms
DCL high time tDCLh 0.4 ×tDCL 0.5 ×tDCL 0.6 ×tDCL µs
Period FSC1) tFSC –125 –µs
FSC setup time tFSC_s 10 50 –ns
FSC hold time tFSC_h 40 50 –ns
DD setup time tDD_s 10 50 –ns
DD hold time tDD_h 10 50 –ns
DU delay time2)
2) All delay times are made up by two components: an intrinsic time (min-time), caused by internal processings,
and a second component caused by external circuitry (CLoad, RPullup >1.5kΩ)
tdDX 25 –tdDX_min +
0.4 ×CLoad[pF] ns
DU delay ti m e to h i gh Z tdDXhz 25 –50 ns
t
DCL
DCL
FSC
DD
DU
FSC_S
t
DCLh
t
High Imp.
t
DD_S DD_H
t
t
dDU dDUhz
t
t
FSC_H
FSC
t
50%
ezm22017.wmf
DuSLIC
Application Circuits
Data Sheet 367 2000-07-14
Preliminary
8 Application Circuits
Application circuits are shown for internal ringing with DuSLIC-E/-E2/-S/-P (balanced
and unbalanced) and for external unbalanced ringing with DuSLIC-E/-E2/-S/-S2/-P for
one line. Channel A and the SLIC hav e to be duplicated in the circ uit diagrams to s how
all co m ponents for 2 cha nnels.
8.1 Internal Ringing (Balanced/Unbalanced)
Internal balanced ringing is supported up to 85 Vrms for DuSLIC-E/-E2/-P and up to
45 Vrms for DuSLIC-S. Internal unbalanced ringing is supported for SLIC-P with ringing
amplitudes up to 50 Vrms without any additional external components. Off-hook
detec tion and ring trip de tectio n are also fully inter nal in the D uSLIC chip se t.
DuSLIC
Application Circuits
Data Sheet 368 2000-07-14
Preliminary
8.1.1 Circuit Diagram Internal Ringing
Figure 97 Application Circuit, Internal Ringing (Balanced & Unbalanced)
As sown in Figure 97 both balanced and unbalanced internal ringing uses the same line
circuit.
Note: Only the codec/SLIC combinations shown in Table 1 "DuSLIC Chip Sets" on
Page 16 are possible.
FSC
DCL/PCLK
DD/DRB
DU/DOUT
TS0/DIN
TS1/DCLK
TS2/CS
MCLK
SEL24/DRA
DXA
DXB
RSYNC
ACPA
ACNA
DCPA
DCNA
C1A
C2A
CDCNA
CDCPA
ITACA
ITA
VCMITA
ILA
VCM
VCMS
CREF
GNDR
TEST
C
DC
SLICOFI-2
SLICOFI-2S
(Channel A, B)
C
ITACA
C
VCMITA
R
IT1A
SLIC-E/-E2
SLIC-S
SLIC-P
R
IT2A
R
ILA
ACP
ACN
DCP
DCN
C1
C2
V
DDA
V
DDR
V
DDD
V
DDPLL
C
1
AGND
C
1
AGND
C
1
AGND
C
1
AGND
GNDA GNDD GNDPLL
AGND AGND AGND
C
REF
VCMS
AGND
IL
IT
V
HR
V
DD
V
BATH
V
BATL
C
1
AGND
C
1
BGND
C
1
BGND
BGND AGND CEXT
BGND AGND AGND
C
EXT
RING
TIP
R
STAB
R
STAB
C
STAB
C
STAB
BGND
Protection
Channel A
V
CCA
V
CCA
V
CCA
V
CCA
V
BATH
V
BATL
C
1
BGND
V
H
PE B 3265
PE B 3264
PE B 4265/-2
PE B 4264
PE B 4266
RESET
TCB
TCA
INT
PCM/IOM-2
IO1A
IO3A
IO4A
IO1B
IO2B
IO3B
IO4B
IO2A
V
CCS
C3 IO2A
* optiona l for SL IC -P
*
AGND
AGND
SELCLK
AGND
ezm14042.emf
DuSLIC
Application Circuits
Data Sheet 369 2000-07-14
Preliminary
8.1.2 Protection Circuit for SLIC-E/-E2 and SLIC-S
A typica l overvolt age protect ion circui t for SLIC-E/S i s shown in Figure 98. Other proved
appl ication sc hemes are available on request.
.
Figu re 98 Typ i cal Overvol t ag e Protection fo r SLIC-E /-E2 and SL I C-S
The LCP02 (from STM) protects against overvoltage strikes exceeding VHR and VBATH.
Protection resistors must be rated for lightning pulses. In case of power contact,
protec tion resistors must become high impedanc e or add itional fuses a re needed.
SLIC-E/-E2
PEB 4265/-2
SLIC-S
PEB 4264
30 Ohm
30 Ohm
TIP
RING
VHR
VBATH
LCP02
R
PROT
20 Ohm
fusea ble resistor
Tip
Ring
Gp
Gn
GND
C
P
C
P
C
STAB
C
STAB
R
PROT
20 Ohm
fusea ble resistor
ezm14070.emf
DuSLIC
Application Circuits
Data Sheet 370 2000-07-14
Preliminary
8.1.3 Protection Circuit for SLIC-P
A typical protection circuit for SLIC-P is shown in Figure 99. Other proved application
schemes are ava ilable on request.
Figu re 99 Typi cal Overvoltage Protection for SLIC -P
The ga te trigge r voltag e of the Battrax B 1160CC (T eccor) can be set do wn to the ba ttery
volta ge of VBATR (–150 V).
Protection resistors must be rated for lightning pulses. In case of power contact,
protec tion resistors must become high impedanc e or add itional fuses a re needed.
ezm14048.emf
SLIC-P
PEB 4266
TIP
RING
C
STAB
15nF
C
STAB
15nF
R
STAB
30Ohm
R
STAB
30Ohm
R
PROT
20Ohm
f usable resistor
R
PROT
20Ohm
f usable resistor
BGND
BGND
Protection
B1160CC
VBATR
MB2S
DuSLIC
Application Circuits
Data Sheet 371 2000-07-14
Preliminary
For handlin g higher e lectromag netic comp atibility (EMC) re quirem ents, add itional effort
in the circuit design may be necessary, e.g., a current-compensated choke of 470 µH in
the Ring/Tip lines.
Additionally to the capacitors C1 a 22 µF capacitor per 8 Ring/Tip lines is recommended
for buffering the supply voltages.
8.1.4 Bill of Materials (Including Protection)
Table 83 shows the external passive components needed for a dual channel solution
cons is ting of one SLICOFI-2/-2S and t w o SLIC-E /-E2/-S/-P.
Table 83 External Components in Application Circuit for DuSLIC-E/-E2/-S/-P
No. Symbol Value Unit Tolerance Rating DuSLIC
-E/-E2/-S DuSLIC
-P
2RIT1 470 Ω1% x x
2RIT2 680 Ω1% x x
2RIL 1.6 kΩ1% x x
4RSTAB 30 Ω0.1 % x x
4RPROT 20 Ω0.1 % x x
4CSTAB 15 nF 10 % see 1) xx
2CDC 120 nF 10 % 10 V x x
2CITAC 680 nF 10 % 10 V x x
2CVCMIT 680 nF 10 % 10 V x x
1CREF 68 nF 20 % 10 V x x
2CEXT 470 nF 20 % 10 V x x
12 C1100 nF 10 % x x
2 Battrax B1160CC –– according to
supply voltage
VBATR
x
2 Diode-
bridge MB2S x
2 STM LCP-02 x
4CP220 nF 20 % according to
supply voltage
VBATH and VHR
x
1) according to the highest used battery voltage IVBATRI for SLIC-P and IVHRI or IVBATHI for SLIC-E/-E2/-S
DuSLIC
Application Circuits
Data Sheet 372 2000-07-14
Preliminary
8.2 External Unbalanced Ringing with DuSLIC-E/-E2/-S/-S2/-P
External unbalanced ringing applications are shown for a standard solution (see
Figure 100) an d fo r a soluti o n dedica te d to higher loop le n ghts (see Figure 101).
Note: Only the codec/SLIC combinations shown in Table 1 "DuSLIC Chip Sets" on
Page 16 are possible.
Figure 100 Application Circuit, External Unbalanced Ringing
This c ir cuit senses t he r ing cur r ent on onl y one li n e (Tip li ne). It is th erefo re re str icted t o
applications w i t h low longitud inal influe nc e (s hort lines).
ezm14044.emf
R
STAB
R
STAB
C
STAB
C
STAB
BGND
Protection
External
Ring
Generator
RSYNC / SLICOFI-2
+ 5V
FSC
DCL/PCLK
DD/DRB
DU/DOUT
TS0/DIN
TS1/DCLK
TS2/CS
MCLK
SEL24/DRA
DXA
DXB
RSYNC
ACPA
ACNA
DCPA
DCNA
C1A
C2A
CDCNA
CDCPA
ITACA
ITA
VCMITA
ILA
VCM
VCMS
CREF
GNDR
TEST
C
DC
SLICOFI-2
SLICOFI-2S/-2S2
(Chann el A, B )
C
ITACA
C
VCMITA
R
IT1A
SLIC-E/-E2
SLIC-S/-S2
SLIC-P
R
IT2A
R
ILA
ACP
ACN
DCP
DCN
C1
C2
V
DDA
V
DDR
V
DDD
V
DDPLL
C
1
AGND
C
1
AGND
C
1
AGND
C
1
AGND
GNDA GNDD GNDPLL
AGND AGND AGND
C
REF
VCMS
AGND
IL
IT
V
HR
V
DD
V
BATH
V
BATL
C
1
AGND
C
2
BGND
C
2
BGND
BGND AGND CEXT
BGND AGND AGND
C
EXT
RING
TIP
Channel A
V
CCA
V
CCA
V
CCA
V
CCA
V
BATH
V
BATL
PE B 4265/-2
PE B 4264/-2
PE B 4266
P EB 3265
P EB 3264 /-2
IO1A
IO3A
IO4A
IO1B
IO2B
IO3B
IO4B
IO2A
RESET
TCB
TCA
INT
PCM/IOM-2
V
CCS
IO2AC3
* optional for SLIC-P
*
AGND
SELCLK
AGND
1N4148
1N4148
DuSLIC
Application Circuits
Data Sheet 373 2000-07-14
Preliminary
Figure 101 Application Circuit, External Unbalanced Ringing for Long Loops
For handlin g higher e lectromag netic comp atibility (EMC) re quirem ents, add itional effort
in the circuit design may be necessary, e.g., a current-compensated choke of 470 µH in
the Ring/Tip lines.
This c ircuit se nses the ring current in b oth Tip and Ring lines. Lo ngitudin al influen ce is
cancelled out. This circuit therefore is recomme nded for long line app lications.
PCM/IOM-2
FSC
DCL/PCLK
DD/DRB
DU/DOUT
TS0/DIN
TS1/DCLK
TS2/CS
INT
MCLK
SEL24/DRA
DXA
DXB
TCA
TCB
RSYNC
ACPA
ACNA
DCPA
DCNA
C1A
C2A
CDCNA
CDCPA
ITACA
ITA
VCMITA
ILA
VCM
VCMS
CREF
GNDR
RESET
TEST
C
DC
SLICOFI-2
SLICOFI-2S/-2S2
(Channel A, B)
C
ITACA
C
VCMITA
R
IT1A
SLIC-E/-E2
SLIC-S/-S2
SLIC-P
R
IT2A
R
ILA
ACP
ACN
DCP
DCN
C1
C2
V
DDA
V
DDR
V
DDD
V
DDPLL
C
1
AGND
C
1
AGND
C
1
AGND
C
1
AGND
GNDA GNDD GNDPLL
AGND AGND AGND
C
REF
VCMS
AGND
IL
IT
V
HR
V
DD
V
BATH
V
BATL
C
1
AGND
C
2
BGND
C
2
BGND
BGND AGND CEXT
BGND AGND AGND
C
EXT
RING
TIP
R
STAB
R
STAB
C
STAB
C
STAB
BGND
Protection
Channel A
V
CCA
V
CCA
V
CCA
V
CCA
5V V
BATH
V
BATL
PE B 3265
PE B 326 4/-2
PE B 42 65/-2
PE B 42 64/-2
P EB 4266
+
68k
68k
VCMS/SLICOFI-2/-2S/-2S2
IO3A or IO4A of
SLICOFI-2/-2S/-2S2
Ring
Generator
-48 VDC
80V
RMS
zero crossing signal (TTL level)
RSYNC/SLICOFI-2/-2S/-2S2
+ 5V
RING
TIP
IO1A
IO3A
IO4A
IO1B
IO2B
IO3B
IO4B
-
150Ω
2M
150
Ω
2M
2M 2M
R
PROT
R
PROT
LM358
Relay
C3 IO2
*
*
optional for SLIC-P
AGND
SELCLK
AGND
1N4148
1N4148
ezm35003.emf
DuSLIC
Application Circuits
Data Sheet 374 2000-07-14
Preliminary
8.3 DuSLIC Layout Recommendation
•For each of the supply pins of SLICOFI-2x and SLIC, 100 nF capacitors should be
used. These capacitors should be placed as close as possible to the supply pin of the
asso ciated gr ound/supply pins
•SLICOFI-2x and SLIC shou ld be place d as close to each o th er as possible.
•SLICOFI-2x and SLIC should be placed in s uch way that lines ACP, ACN , DCP, DCN,
IT, ITAC are as short as possible
•ACP/ AC N lines should be placed parallel and s ymm etric al;
via holes should be avoided
ACP/ AC N lines should be run abo ve a GND plane;
•DCP/DCN lines should be placed parallel and symmetrical;
via holes should be avoided
DCP/DCN lines should be run above a GND plane
•VCMITA and VCM should be connected directly (VCMITA via CVCMITA) at resistor
RIT2A (680 Ω)
•VCMITB and VCM should be connected directly (VCMITB via CVCMITB) at resistor
RIT2B (680 Ω)
•Use separate traces for connecting VCM/VCMITA and VCM/VCMITB
these two VCM traces sh ould be conn ected di r ectly at th e VCM pi n of SLICOFI-2x
•In case of a multilayer board it is recommended to use one common ground layer
(AGND, BGND, GNDD, GNDA, GNDB, GNDPLL connected together and share one
ground lay er)
•In case of a two-layer board a common ground should be used for AGND, BGND,
GNDD, GNDA, GNDB and GNDPLL. Ground traces should be layed out as large as
possible. Connections to and from groud pins should be as short as possible. Any
unused area of th e board sho uld be filled with gr ound (cop per pouring)
•The connection of GND, VH and VBAT to the protection devices should be low-
impedance in order to avoid, e.g., a GND shift due to the high impulse currents in case
of an ov erv olt age strik e.
•Tip/ring traces from the SLIC should be symmetrical
DuSLIC
Application Circuits
Data Sheet 375 2000-07-14
Preliminary
Figure 102 DuSLIC Layout Recommendation
S L IC A
S L IC B
SLICOFI-2x
ACNA
ACPA DCNB
DCPB
ITACA
VCMITA
ITA
VCM
ITB
VCMITB
ITACB
DCPB
DCNB
ACNB
ACPB
Parallel/symmetrical
as short as possible
no via holes, should run above a GND plane
Parallel/symmetrical
as short as possible
no via holes, should run above a GND plane
Connection
directly at
resistor
Connection
directly at
SLICOFI-2
IL-A
IT-A
IT-B
IL-B
R
ILA
R
IT1A
R
IT2A
R
ILB
R
IT2B
R
IT1B
C
VCMITA
C
VCMITB
layout_r.emf
DuSLIC
Package Outlines
Data Sheet 376 2000-07-14
Preliminary
9 Package Outlines
Figu re 103 PE B426x (SLIC-S /-S 2, SL I C-E/-E2, SLIC-P)
Note: The SLIC is only available in a P-DSO-20-5 package with heatsink on top. Please
note th at the p in countin g for the P-DS O-20-5 pa ckage is clock wise (top view) in
contrast to similar type packages which mostly count counterclockwise.
P-DSO-20-5
(Pla sti c Dual Small Outlin e)
Gps05755.eps
Top View
Sorts of Packing
Pa ckage outlin es for tubes, trays etc. are contained in our
data book “Package Information”.Dim en sions in mm
SMD = Surf ac e Mounted Dev ic e
DuSLIC
Package Outlines
Data Sheet 377 2000-07-14
Preliminary
Figure 104 PEB 3264, PEB 3264-2, PEB 3265 (SLICOFI-2x)
P-MQFP-64-1
(Pla st ic Metric Quad Flat Package)
Gpm05250.eps
Top View
Sorts of Packing
Pa ckage outlin es for tubes, trays etc. are contained in our
data book “Package Information”.Dim en sions in mm
SMD = Surf ac e Mounted Dev ic e
DuSLIC
Glossary
Data Sheet 378 2000-07-14
Preliminary
10 Glossary
10.1 List of Abbreviations
ACTL Active with VBATL and VBGND
ACTH Active with VBATH and VBGND
ACTR Active with VBATR and VGND or VHR and VBATH
ADC Analog D igit al Convert er
AR Atten uat ion Receiv e
AX Attenuat ion Transm it
BP Band Pass
CMP Compander
Codec Coder Decoder
COP Coefficient Operation
CRAM Coeffi cient RAM
DAC Digital Analog Converter
DSP Digital Signal Processor
DUP Data Upstream Persistence Counter
DuSLIC Dual Chan nel Subscriber Line Int erface Co ncept
EXP Expander
FRR Frequency Response Receive Filter
FRX Frequency Response Transmit Filter
LSSGR Local area transport access Switching System Generic
Requirements
PCM Pulse Code M odulation
PDH Pow er D o w n High Imped ance
DuSLIC
Glossary
Data Sheet 379 2000-07-14
Preliminary
PDRHL Power Down Load Resistive on VBATH and VBGND
PDRRL Power Down Load Resisitve on VBATR and VBGND
PDRH Power Down Resistive on VBATH and VBGND
PDRR Power Down Resistive on VBATR and VBGN
POFI Post Filter
PREF I Anti aliasing Pre Filt er
RECT R ec t if ier (T es t loops, Levelmetering)
SLIC Subscriber Line Interface Circuit (synonym for all versions)
SLIC -S/ -S2 Subsc riber Line Interfac e Circu it St andard F eature Set
PEB 4264/-2
SLIC -E/ -E2 Subsc riber Line Interf ac e C ircuit Enhanc ed Feature Set
PEB 4265/-2
SLIC -P Subscriber Line Interfac e C ircuit Enhanc ed Powe r Ma nagement
PEB 4266
SLICOFI-2x Dual Chan nel Signal Pro cessing Subscriber Line Int erface Co dec
Filter (synonym for all versions)
SLICOF I-2 Dual Channel Sign al Process ing Subscriber Line I nt erf ac e Codec
Filter PEB 32 65
SLICOF I-2S/-2S2 Dual Chan nel Signal Processing Subscriber Line I nt erf ac e Codec
Filter PEB 3264/-2
SOP Status Operation
TG Tone Generat or
TH Trans hy brid Balancing
THFIX Transhy brid Balanc ing Filter (f ix ed)
TS Time Slot
TTX Teletax
DuSLIC
Index
Preliminary
Data Sheet 380 2000-07-14
11 Index
Numerics
170V tech nology 52
A
Activ e 93, 157, 160, 161
Active High 78, 80, 82, 84, 86
Ac tive L ow 78, 80 , 82, 84 , 86
Acti ve Ring 78, 80, 82 , 84, 8 7, 154, 157,
160
Active State 59, 95
Active with HIR 78, 81, 83, 85, 87
Active with HIT 78, 80, 83, 85, 87
Active with Metering 78, 81, 164, 262,
312
B
Bala nc ed ringing 53, 367
Battery feed 33
C
Caller ID 19, 34, 66, 71, 180
Central Office 22
Coding 33
Constant C u rrent Zo ne 42
Cons tant Voltage Zone 44
COP-c omm and 164, 165, 224, 30 8
CRAM coeffi cients 226, 310
D
DC characteristic 45
Digit al Loop Carr ier 22
DTMF 34, 71, 17 8, 198, 200, 228, 294
DTMF deco der 19, 34
DTM F genera to r 19, 34, 6 3
DuSLI COS 33, 224, 308
E
Enhanced Digital Signal Processor 63,
174, 180
MIPS Requirements 71
POP Com m a nds 22 8
Power D iss ipation 340
Exter nal C om ponent s
DuSL IC-P 371
Exter nal c onference 75
Exter nal Ringing 31, 55, 10 7, 192, 289
F
Fiber in t he Loop 22
First Command Byte 163, 264, 265, 314,
315
Frequency r es p onse 33, 34 5
FSK 34
G
Groun d Key 60, 175 , 275
Groun d Start 81
H
Hybrid 33
Hybrid balance 33
I
Imped ance m atching 33, 51
Intelligent NT 22
Internal conference 75
IOM-2 interface 29, 13 8, 145, 262, 26 5,
312, 315
ISDN Terminal Adapters 22
L
Layout R ec omme ndation 374
Levelmeter
AC 117
DC 112
TTX 121
LIN mode 77
LIN16 mode 77
Line Echo Cancellatio n 34, 69, 71, 199
POP Com m a nds 23 9
Line Re s i s tance 102, 12 5
Line Tes t ing 107
DuSLIC
Index
Preliminary
Data Sheet 381 2000-07-14
M
Message w aiting 19, 72
Metering 19, 61, 202, 204, 206, 296, 297
Micro c ontroller in terface 138, 143
Monit or C hannel Op eration 148
Monit or R ec eiver 151
Monitor Transfer Protocol 148
Monit or T r ansmit ter 150
O
Operating Modes
CIDD byte SLICOFI-2 262
CIDD byte SLICOFI-2S/-2S2 312
CIOP byte 164
DuSLIC 78
DuSLIC-E/-E2 84
DuSLIC-P 86
DuSLIC-S/-S2 82
Power M anagem ent 93
SLIC- E 156
SLIC- P 159
SLIC- S 153
Overv olt age prot ection 33
P
PCM ch annel 142
PCM interface 30, 50, 138, 173, 176,
273, 276 , 361
PCM mode 76, 9 2, 210 , 214, 29 8, 300
PCM /µ C interface 76, 138, 194, 291
PCM 16 mode 77
PCM-active 75
PCM-off 75
Polarity Reversal 19, 62
POP command 165, 22 8
Power Dissipation
Operating Modes 93
SLIC 95
SLIC outp ut stage 46
SLIC-E/-E2 326
SLICOFI-2 94, 340
SLICOFI-2/-2 S2 341
SLIC-P 333
SLIC-S /-S2 3 20
Power D own 93, 164 , 190, 262, 312
Power Down High Impedance 78, 80,
156, 159, 160, 164, 193, 262,
290, 312
Power Down Resist ive 78, 80, 82, 84, 86,
153, 156 , 159, 160
Power Down state 6 0, 75, 95, 154 , 16 0,
161, 218, 220, 302, 304
Power Management 17, 19, 80, 93
Privat e Branch E xchange 22
R
Ramp gen erato r 72, 83, 85, 87
Read command 143
Rece ive gain 33
Receive path 50, 199, 218, 220, 222,
302, 304 , 306
Regis te r Descript ion Example 165
Reset 88, 164
Status 177, 277
Resis t iv e Z one 43
Ring on R ing 80, 160
Ring on T ip 8 0, 160
Ring Pause 79, 81, 83, 85 , 87
Ring Trip 52, 81 , 35 8
Ringer Equiva lence Nu m ber 52
Ringing 33, 52, 78, 80, 82, 85, 87, 94,
160, 164 , 262, 312
S
Second Command Byte 143, 165, 264,
265, 314 , 315
Signa ling 33, 59, 65 , 265, 315
Sleep 78, 79, 84, 86 , 164, 262, 312, 340
SLIC Interface 153, 156
Soft reversal 62, 192, 289
SOP- comm and 164, 167, 267
Supervision 33, 59
T
Teleta x Metering 34
DuSLIC
Index
Data Sheet 382 2000-07-14
Test Loops 132
Three-party Con ferencing 74, 194
Time Slot As s ignment 50, 147
TIP/RING interface 138, 152
Transmit gain 33, 346
Transmit path 50, 199, 218, 220, 222,
302, 304 , 306
TTX 33, 61, 81, 19 2, 220, 225, 304, 309
U
Unbalanced ringing 53, 94, 190, 287
Universal Tone Detection 34, 70, 71, 179,
193
POP Com m ands 253
Univ ers al Tone detec tio n 198
V
Voice over IP 22
Voltage rese rv e 41, 47
W
Wireless Lo cal Loop 22
Write comm and 143
http://www.infineon.com
Published by Infineon Technologies AG
Infineon goes for Business Excellence
“Business excellence means intelligent approaches and clearly
defined proces ses, which are both c ons tantly un der review and
ultim at ely lead to goo d operatin g res ults.
Bett er operatin g result s and bus ines s ex cellenc e m ean less
idlen es s and was te fulness f or all of us, m ore profes s ional
success, more accur ate inf or ma t i on, a better overview an d,
thereby, le ss f r us t r at ion and mo re satisfacti on.”
Dr. Ulrich Schumacher
