SAA6588TD-T - NXP Semiconductors / Philips Semiconductors

DATA SH EET

Product speciﬁcation

Supersedes data of 1997 Sep 01

File under Integrated Circuits, IC01

2002 Jan 14

INTEGRATED CIRCUITS

SAA6588

RDS/RBDS pre-processor

2002 Jan 14 2

Philips Semiconductors Product speciﬁcation

RDS/RBDS pre-processor SAA6588

FEATURES

•Integrated switched capacitor filters

•Demodulation of the European Radio Data System

(RDS) or the USA Radio Broadcast Data System

(RBDS) signal

•RDS and RBDS block detection

•Error detection and correction

•Fast block synchronization

•Synchronization control (flywheel)

•Mode control for RDS/RBDS processing

•Different RDS/RBDS block information output modes

(e.g. A-block output mode)

•Fast I2C-bus interface

•Multi-path detector

•Signal quality detector with sensitivity adjustment

•Pause detector with pause level and time adjustment

•Alternatively oscillator frequency: n ×4.332 MHz

(n = 1 to 4)

•UART compatible with 17.328 MHz (n = 4)

•CMOS device

•Single supply voltage

•Extended temperature range (−40 to +85 °C).

GENERAL DESCRIPTION

Today most FM radio stations in Europe and meanwhile

also many FM/AM radio broadcasting stations in the USA

transmit the inaudible European RDS (Radio Data

System) or the USA RBDS (Radio Broadcast Data

System) informations respectively. Likewise nowadays

receivers, most car radios and also some home and

portable radios on the market include at least some of the

RDS features.

The RDS/RBDS system offers a large range of

applications by its many functions to be implemented. For

car radios the most important are:

•Program Service (PS) name

•Traffic Program (TP) identification

•Traffic Announcement (TA) signal

•Alternative Frequency (AF) list

•Program Identification (PI)

•Enhanced Other Networks (EON) information.

The RDS/RBDS pre-processor is a CMOS device that

integrates all RDS/RBDS relevant functions in one chip.

The IC contains filtering and demodulation of the

RDS/RBDS signal, symbol decoding, block

synchronization, error detection, error correction and

additionaldetectorsformulti-path,signalqualityandaudio

signalpauses.Thepre-processedRDS/RBDSinformation

is available via the I2C-bus.

The RDS/RBDS pre-processor replaces a number of ICs

and peripheral components used nowadays in car radio

concepts with RDS or RBDS features. The integration of

the relevant RDS/RBDS data processing functions

provides, in an economic manner, high performance of

RDS/RBDS processing and reduces the real-time

requirements for the main radio microcontroller

considerably. In addition it simplifies the development of

the RDS specific software for the main controller of the

radio set.

Compared with standard radio systems, RDS/RBDS

controlled radio systems additionally require an

RDS/RBDS demodulator with a 57 kHz band-pass filter,

informationaboutthecurrentreceptionsituation(reception

quality, multi-path disturbance etc.), and additional

microcontroller power for RDS/RBDS data processing,

decoding and radio control.

The new RDS/RBDS pre-processor includes all these

specificfunctions and meetsall requirements ofahigh end

RDS/RBDSradio.Moreoverthetimingrequirementsofthe

set controller, regarding RDS/RBDS data processing are

reduced due to the integration of decoder functions, so

that the development of radio control software can be

concentrated specifically on radio set features.

2002 Jan 14 3

Philips Semiconductors Product speciﬁcation

RDS/RBDS pre-processor SAA6588

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

VDDA analog supply voltage 4.5 5.0 5.5 V

VDDD digital supply voltage 4.5 5.0 5.5 V

IDD(tot) total supply current −14.0 −mA

Vi(MPX) RDS input sensitivity at pin MPX 1 −−mV

∆GSQ step size for signal quality input gain −0.6 −dB

CRGSQ control range for signal quality input gain −18.6 −dB

tPON(min) minimum time for pause adjustable in 4 steps 20.2 −161.7 ms

fi(xtal) crystal input frequency n = 1 −4.332 −MHz

n=2 −8.664 −MHz

n=3 −12.996 −MHz

n=4 −17.328 −MHz

TYPE

NUMBER PACKAGE

NAME DESCRIPTION VERSION

SAA6588 DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1

SAA6588T SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

2002 Jan 14 4

Philips Semiconductors Product speciﬁcation

RDS/RBDS pre-processor SAA6588

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BLOCK DIAGRAM

handbook, full pagewidth

MGK535

kΩ

470

kΩ

57 kHz

8th ORDER

BAND-PASS

PAUSE

DETECTOR MULTI-PATH

DETECTOR

CLOCKED

COMPARATOR

SIGNAL QUALITY

DETECTOR

RDS/RDBS

DEMODULATOR

INTERFACE

POWER

SUPPLY

AND RESET

TEST

CONTROL

C10

100 nF

DAVN data

available

pause

output

multi-path

output

71918

SCOUT CIN VDDD

560 pF

OSCILLATOR

AND CLOCK I2C-BUS SLAVE

TRANSCEIVER I2C-BUS

RDS/RDBS

DECODER

multiplex

input

audio

inputs

level

input

SAA6588

TCON MRO

100

100 nF

C11

2.2 nF

330 pF

LVIN

VDDA

AFIN

MPX

2.2 µF

0.47 µF

OSCI

n × 4.332

MHz

n = 1 to 4

OSCO

82 pF

47 pF

1 kΩ

MAD

VSSD

Vref

VSSA

1715

+5 V

PSWN

MPTH

SDA

SCL

Fig.1 Block diagram.

2002 Jan 14 5

Philips Semiconductors Product speciﬁcation

RDS/RBDS pre-processor SAA6588

PINNING

SYMBOL PIN DESCRIPTION

MRO 1 multi-path rectiﬁer output

MPTH 2 multi-path detector output

TCON 3 test control input pin

OSCO 4 oscillator output

OSCI 5 oscillator input

VSSD 6 digital ground (0 V)

VDDD 7 digital supply voltage (5 V)

DAVN 8 data available output (active LOW)

SDA 9 I2C-bus serial data I/O

SCL 10 I2C-bus serial clock input

PSWN 11 pause switch output (active LOW)

MAD 12 slave address (LSB) input

AFIN 13 audio signal input

VDDA 14 analog supply voltage (5 V)

VSSA 15 analog ground (0 V)

MPX 16 multiplex input signal

Vref 17 reference voltage output

SCOUT 18 band-pass ﬁlter output

CIN 19 comparator input

LVIN 20 level input

SYMBOL PIN DESCRIPTION

Fig.2 Pin configuration (DIP20).

handbook, halfpage

MRO

MPTH

TCON

OSCO

OSCI

VSSD

VDDD

SDA

SCL

LVIN

CIN

SCOUT

Vref

VSSA

VDDA

MPX

AFIN

MAD

10 11

SAA6588

MGK533

DAVN

PSWN

Fig.3 Pin configuration (SO20).

handbook, halfpage

MRO

MPTH

TCON

OSCO

OSCI

VSSD

VDDD

SDA

SCL

LVIN

CIN

SCOUT

Vref

VSSA

VDDA

MPX

AFIN

MAD

10 11

MGK534

DAVN

PSWN

SAA6588T

2002 Jan 14 6

Philips Semiconductors Product speciﬁcation

RDS/RBDS pre-processor SAA6588

FUNCTIONAL DESCRIPTION

General

The following functions are performed by the SAA6588:

•Selection of the RDS/RBDS signal from the MPX input

signal

•57 kHz carrier regeneration

•Demodulation of the RDS/RBDS signal

•Symbol decoding

•RDS/RBDS block detection

•Error detection and correction of transmission errors

•Fast block synchronization and synchronization control

•Detection of multi-path distortion and audio signal

pauses

•Determination of the signal quality

•Mode control of processing and RDS/RBDS data output

via I2C-bus interface

•Sensing of pause and multi-path, information via extra

output pins.

The block diagram of the RDS/RBDS pre-processor is

shown in Fig.1. For the application of the device only a few

external components are required. The pre-processors

functional blocks are described in the following sections.

RDS/RBDS signal demodulation

BAND-PASS FILTER

The band-pass filter has a centre frequency of 57 kHz.

It selects the RDS/RBDS sub-band from the multiplex

signal MPX and suppresses the audio signal components.

The filter block contains an analog anti-aliasing filter at the

input followed by an 8th order switched capacitor

band-pass filter and a reconstruction filter at the output.

CLOCKED COMPARATOR

Thecomparator digitizes the output signalfromthe57 kHz

band-pass filter for further processing by the digital

RDS/RBDS demodulator. To attain high sensitivity and to

avoid phase distortion, the comparator input stage

contains an automatic offset compensation.

DEMODULATION

The demodulator provides all functions of the SAA6579

but has improved performance under weak signal

conditions.

The demodulator includes:

•57 kHz carrier regeneration from the two sidebands

(Costas loop)

•Symbol integration over one RDS clock period

•Bi-phase symbol decoding

•Differential decoding

•Synchronization of RDS/RBDS output data with clock.

The RDS/RBDS demodulator recovers and regenerates

the continuously transmitted RDS/RBDS data stream out

of the multiplex signal (MPX) and provides the internal

signals clock (RDCL) and data (RDDA) for further

processing by the RDS/RBDS decoder block.

RDS/RBDS data processing

The RDS/RBDS data processing of the pre-processor

handles the complete processing and decoding of the

continuous serial RDS/RBDS demodulator output data

stream.

Different data processing modes are software controllable

by the external main controller via I2C-bus.

Processed RDS/RBDS data blocks, decoder status

information and signal quality information are also

available via the I2C-bus.

RDS/RBDS DECODER

The RDS/RBDS decoder contains:

•RDS/RBDS block detection

•Error detection and correction

•Synchronization

•Flywheel for synchronization hold

•Bit slip correction

•Data processing control

•RDS/RBDS data output.

2002 Jan 14 7

Philips Semiconductors Product speciﬁcation

RDS/RBDS pre-processor SAA6588

RDS/RBDS block detection

The RDS/RBDS block detection is always active.

For a received sequence of 26 data bits, a valid block and

its offset are identified via syndrome calculation.

Duringsynchronizationsearch,thesyndromeis calculated

with every new received data bit (bit-by-bit) for a received

26-bitsequence.Ifthedecoderissynchronized,syndrome

calculation is activated only after 26 data bits for each new

block received.

Under RBDS reception situation, beside the RDS block

sequenceswith (A,B, C/C', D)offset alsoblocksequences

of 4 blocks with offset E may be received. If the decoder

detects an E-block, this block is marked in the block

identification number BL and is available via an I2C-bus

request. In RBDS processing mode the block is signed as

valid E-block and in RDS processing mode, where only

RDS blocks are expected, signed as invalid E-block

(see Table 13).

This information can be used by the main controller to

detect E-block sequences and identify RDS or RBDS

transmitter stations.

Error detection and correction

The RDS/RBDS error detection and correction recognizes

and corrects potential transmission errors within a

received block via parity-check in consideration of the

offset word of the expected block. Burst errors with a

maximum length of 5 bits are corrected with this method.

After synchronization has been found the error correction

is always active, but cannot be carried out in every

reception situation.

During synchronization search, the error correction is

disabled for detection of the first block and is enabled for

processing of the second block depending on the

pre-selected error correction mode for synchronization

(mode SYNCA to SYNCC, see Table 4).

The processed block data and the status of error

correctionareavailablefordatarequestvia the I2C-busfor

the last two blocks.

Processed blocks are characterized as uncorrectable

under the following conditions:

•During synchronization search, if the burst error is

higher than allowed by the pre-selected correction

mode.

•After synchronization has been found, if the burst error

is higher than 5 bits or if errors are detected but error

correction is not possible.

Synchronization

Thedecoderis synchronizediftwosuccessivevalidblocks

in a valid sequence are detected by the block detection.

For detection of the second block of this sequence, error

correction is also enabled depending on the pre-selected

correction mode (see Table 4). Only valid (correctable)

blocks are accepted for synchronization (see also Section

“Error detection and correction”).

If synchronization is found, the synchronization status flag

(SYNC) is set and available via an I2C-bus request.

The synchronization is held until the flywheel (for

synchronization hold) detects a loss of synchronization

(see Section “Flywheel for synchronization hold”) or an

external restart of synchronization is performed (see

Section “Data processing control”).

Flywheel for synchronization hold

For a fast detection of loss of synchronization the internal

flywheel counter checks the number of uncorrectable

blocks (error blocks). Error blocks increment and valid

blocks decrement the block error counter.

The flywheel counter is only active if the decoder is

synchronized. The synchronization is held until the

flywheel counter detects an error block overflow (loss of

synchronization). The maximum value for the error block

counter is adjustable via the I2C-bus in a range of 0 to 63

(see Table 6).

The value 32 is set after reset and the values 0 and 63

have a special function.

•If the value 0 is programmed then no flywheel is active

•If the value 63 is programmed then the flywheel is

endless and no new start of synchronization is effected

automatically (synchronization hold).

Bit slip correction

During poor reception situation phase shifts of one bit to

the left or right (±1 bit slip) between the RDS/RBDS clock

and data may occur, depending on the lock conditions of

the demodulators clock regeneration.

If the decoder is synchronized and detects a bit slip, the

synchronization is corrected by +1 or −1 bit via block

detection on the respectively shifted expected new block.

2002 Jan 14 8

Philips Semiconductors Product speciﬁcation

RDS/RBDS pre-processor SAA6588

Data processing control

The pre-processor provides different operating modes

selectable via the external I2C-bus. The data processing

control performs the pre-selected operating modes and

controls the requested output of the RDS/RBDS

information.

Restart of synchronization mode:

The ‘restart synchronization’ (NWSY) control mode

immediately terminates the actual synchronization and

restarts a new synchronization search procedure. The

NWSY flag is automatically reset after the restart of

synchronization by the decoder.

This mode is required for a fast new synchronization on

theRDS/RBDS data from a new transmitter station if the

tuning frequency is changed by the radio set.

Restart of synchronization search is furthermore

automatically carried out if the internal flywheel signals

a loss of synchronization (see Section “Flywheel for

synchronization hold”).

Error correction control mode for synchronization:

For error correction and identification of valid blocks

during synchronization search, three different modes

are selectable. (SYM1, SYM0, see Table 4).

RBDS processing mode:

The pre-processor is suitable for receivers intended for

the European (RDS) as well as for the USA (RBDS)

standard. If RBDS mode is selected via the I2C-bus, the

block detection and the error detection and correction

are adjusted to RBDS data processing.

Data available control mode:

The pre-processor provides three different RDS/RBDS

data output processing modes selectable via the ‘data

available’ control mode: (see also Section “RDS/RBDS

data output” and Table 5).

Standard processing mode: if the decoder is

synchronized and a new block is received (every

26 bits), the actual RDS/RBDS information of the last

two blocks is available with every new received block.

Fast PI search mode: during synchronization search

and if a new A-block is received, the actual RDS/RBDS

information of this or the last two A-blocks respectively

is available with every new received A-block. If the

decoderis synchronized,thestandard processingmode

is valid.

Reduced data request processing mode: if the

decoder is synchronized and two new blocks are

received (every 52 bits), the actual RDS/RBDS

information of the last two blocks is available with every

two new received blocks.

The RDS/RBDS pre-processor provides data output of the

block identification, the RDS/RBDS information words and

error detection and correction status of the last two blocks

as well as signal quality indication and general decoder

status information.

Inaddition,thedecoder controlsalsothe datarequestfrom

the external main controller. The pre-processor activates

the ‘data overflow’ status flag DOFL

(see Section “Programming”), if the decoder is

synchronized and a new RDS/RBDS block is received

before the previously processed block was completely

transmitted via I2C-bus. After detection of data overflow

the interface registers are not updated until reset of the

data overflow flag by reading via the I2C-bus.

RDS/RBDS data output

The decoded RDS/RBDS block information and the

current pre-processor status is available via the I2C-bus.

For synchronization of data request between main

controller and pre-processor the additional data available

output signal is used.

If the decoder has processed new information for the main

controller the data available signal (DAVN) is activated

(LOW) under the following conditions (see also Table 5):

•During synchronization search in DAVB mode if a valid

A-block has been detected. This mode can be used for

fast search tuning (detection and comparison of the PI

code contained in the A-block).

•During synchronization search in any DAV mode, if two

blocks in correct sequence have been detected

(synchronization criterion).

•If the pre-processor is synchronized and in mode DAVA

and DAVB a new block has been processed. This mode

is the standard data processing mode, if the decoder is

synchronized.

•If the pre-processor is synchronized and in DAVC mode

two new blocks have been processed.

•If the pre-processor is synchronized and in any DAV

mode loss of synchronization is detected (flywheel

counter overflow and resulting restart of

synchronization).

•In any DAV mode, if a reset condition caused by

power-on or voltage-drop is detected.

2002 Jan 14 9

Philips Semiconductors Product speciﬁcation

RDS/RBDS pre-processor SAA6588

The processed RDS/RBDS data are available for I2C-bus

request for at least 20 ms after the DAVN signal was

activated.

The DAVN signal is always automatically deactivated

(HIGH) after 10 ms or almost after the main controller has

read the RDS/RBDS data via I2C-bus (see Fig.4).

The decoder ignores new processed RDS/RBDS blocks if

the DAVN signal is active or if data overflow occurs

(see Section “Data processing control”).

Multi-path detector

The multi-path detector takes its information from the

unweighted level signal of the FM IF amplifier, input LVIN

(see Fig.1). The part of frequency components around

21 kHz is selected by a band-pass filter and rectified by a

full-wave rectifier. The capacitor at pin MRO is the charge

capacitor. In combination with internal current sources the

time constants of the rectifier are defined.

The analogous output voltage of the multi-path rectifier is

buffered and available via pin MPTH.

Signal quality detector

The signal quality detector takes its information from the

multiplex signal. Disturbances caused by

adjacent-channel reception, noise, or multi-path, generate

highfrequencycomponents(noise)onthemultiplexsignal

besides the audible distortion.

Thesignalquality measurement is provided for fast testing

alternative frequencies as well as for the tuned frequency.

It is a short start/stop procedure. The measuring time is

limited to 850 µs. To attain an average value over a longer

time, multiple measurements are possible with integration

by software processing.

The noise is detected from the frequency spectrum above

90 kHz. The noise voltage is selected by a 4th order

high-pass filter. A full-wave rectifier, controlled by this

noisevoltage,chargesaninitiallydischargedcapacitor(on

chip). The time is measured until the voltage across the

capacitor has reached a defined threshold value. Then

that time equivalent value is stored. The resolution of the

signal quality measurement is 4 bits (16 steps).

For operating the noise detector two modes are provided,

thetriggered mode and the continuous mode. The mode is

defined by the bit SQCM (Signal Quality Continuous

Measurement) as described in Section “Programming”.

The triggered mode is provided for a fast signal quality test

of e.g. an alternative frequency. After the alternative

frequency has been tuned, the signal quality detector has

to be started (triggered) by transmitting the bits SQCM = 0

and TSQD = 1 via the I2C-bus (see Fig.5). This causes a

single shot measurement immediately after the

acknowledgement of this byte.

The bit TSQD is internally reset during the measurement

(TSQD = 0). The result of the measurement is stored and

is available for reading out, as long as no new

measurement is started again e.g. after tuning back to the

previous frequency.

The continuous mode minimizes the required I2C-bus

activities for multiple measurements. After transmission of

SQCM = 1 and TSQD = 1, the signal quality detector

starts a new measurement as described above. But every

time after finishing one measuring procedure the result is

stored (overwrites the previous value within the I2C-bus

buffer SQI3 to SQI0) and a new measurement starts

automatically. If at any time the pre-processor is read out

by his master, the last measured value will be transmitted.

After transmitting the control information SQCM = 0 and

TSQD = 0, the measurement activity will be stopped.

A previously started but not yet finished measurement will

be completed and this last result will also be available.

The control bit combination SQCM = 1 and TSQD = 0

must not be used. It is reserved for later applications.

At a maximum time of 850 µs after triggering or automatic

restart of the signal quality detector, the result of the

measurement (signal quality indication) is available and

representedbythefourbitsSQI3 to SQI0,inavaluerange

of 0 to 15 and is available via the I2C-bus

(see Section “Programming”). The result 0 characterizes

no or less noise/distortion and 15 high noise/distortion.

Tolerances of the signal quality detector as well as

characteristics and tolerances of the FM IF amplifier can

be compensated by adjusting the sensitivity of the signal

quality detector with the control bits SQS0 to SQS4. The

sensitivity can be adjusted over a range of 18.6 dB

(−9.0 to +9.6 dB) in steps of 0.6 dB as given in Table 10.

Pause detector

The pause detector watches the audio modulation for

pauses or very low levels. This function can be used for

performing inaudible RDS AF-tests if the radio is in FM

mode as well as for Automatic Music Search (AMS) if the

radio is in cassette mode.

2002 Jan 14 10

Philips Semiconductors Product speciﬁcation

RDS/RBDS pre-processor SAA6588

The input of the pause detector (AFIN) is low-ohmic and

must be current driven (negative input of an operational

amplifier). This has the following advantages:

•One (MPX) as well as two (left and right) AF channel

application is possible and requires only one pin

•Unwanted crosstalk is avoided if two AF channel

application is chosen

•Matching the input sensitivity is possible by external

resistors.

Forcombined application(RDS and AMS)variations ofthe

switching threshold level as well as the minimum time for

pause detection are possible via I2C-bus control.

The level can be adjusted in four steps of 4 dB by the

control bits PL0 and PL1, see Table 8 (for 1 channel:

R=5kΩ; for 2 channels: R = 10 kΩ).

The corresponding values of FM deviation are calculated

for stereo decoders with an output voltage of 270 mV at

22.5 kHz deviation.

The minimum time for detecting a pause can be adjusted

by the control bits SOSC, PTF0 and PTF1; see Table 9.

The minimum time for detecting ‘no pause’ is fixed to 5 ms

to avoid interruptions of a pause by a short pulse.

The output signal of the pause detector is a digital

switchingsignal(activeLOW).Itisdirectlyavailableviathe

output pin PSWN. A detected pause may initiate an AF

search if required (FM mode).

Oscillator and clock

For good performance of the band-pass and demodulator

stages, the pre-processor requires a crystal oscillator with

a frequency of n ×4.332 MHz. The pre-processor can be

operated with one of four different oscillator frequencies

(n = 1 to 4). The 17.328 MHz frequency (n = 4) is also

UART interface compatible for 8051 based

microcontrollers with a 9600 baud rate (frequency

error = 4.5%), so that a radio set with microcontroller can

run in this case with one crystal only. The pre-processor

oscillator can drive the microcontroller or vice versa.

According to the used oscillator frequency, the mode

control bits PTF1, PTF0 and SOSC have to be set via the

I2C-bus after every reset, see Section “Programming”

The clock generator circuitry generates hereof the

internally used 4.332 MHz system clock and further

derived timing signals.

Power supply and reset

The pre-processor has separate power supply inputs for

the digital and analog parts of the device. For the analog

functions an additional reference voltage (1⁄2VDDA) is

internally generated and available via the output pin Vref.

The I2C-bus interface requires a defined reset condition.

The pre-processor generates a reset signal:

•After the supply voltage VDDD is switched on

•At a supply voltage drop

•If the oscillator frequency is lower than 400 Hz.

Thisinternal reset initializes the I2C-bus interface registers

as well as the I2C-bus slave control and releases the data

line SDA (SDA = HIGH) for input of control mode settings

from the main controller.

If the decoder detects a reset condition, the status

information‘resetdetected’ (RSTD)issetandavailablevia

I2C-bus request. The RSTD flag is deactivated after the

decoder status register was read by the I2C-bus. This

statusinformationis important to signal the main controller

about a voltage drop in the pre-processor IC.

By default, the bits in the write registers (except bit SOSC)

are set to the values in Table 11. If these values are the

required values, no further initialization is necessary.

Programming

I2C-BUS SLAVE TRANSCEIVER

For communication with the external main controller

(master transceiver) the standard I2C-bus is used.

The pre-processors I2C-bus interface acts as a slave

transceiver with fast mode option, that allows a transfer bit

rate up to 400 kbits/s but is also capable of operating at

lower rates (≤100 kbits/s).

The I2C-bus interface is connected to the external I2C-bus

via the serial clock line SCL and the serial data line SDA.

The clock line is supplied by the master and is only input

for the slave transceiver. The data line is a serial 8-bit

oriented bidirectional data transfer line, and acts as input

for control mode settings from the main controller to the

pre-processor, as output for requested RDS/RBDS data

from the pre-processor to the main controller and

acknowledge between pre-processor and main controller.

2002 Jan 14 11

Philips Semiconductors Product speciﬁcation

RDS/RBDS pre-processor SAA6588

The transfer of requested data to the main controller is

synchronized via the additional data available output

signal DAVN to avoid loss of RDS/RBDS data. The DAVN

signal is activated if the pre-processor has provided new

data information for the main controller (see Section

“RDS/RBDS data output”) and can be used for the polling

mode as well as for the interrupt mode of the main

microcontroller.

I2C-BUS INTERFACE REGISTERS

The I2C-bus interface is connected to other blocks of the

pre-processor via internal registers (byte oriented). Those

caneither be written by the pre-processor control and read

by the main controller I2C-bus or vice versa.

The device provides 3 input control registers to which may

be written via the I2C-bus and 7 output registers which

may be read via the I2C-bus.

The decoder control updates the output registers after the

detection of a new RDS/RBDS information block and

reads the new mode control settings of the input control

registers.Both operations mayoccur in thesametime slot,

provided that the read operation is complete before a new

RDS/RBDS data bit is processed by the demodulator.

For the corresponding access the registers are addressed

by two separate register pointers, write-enable and

read-enable signals, which are activated either via the

decoder control or via the I2C-bus interface control.

During a read or write transmission from the I2C-bus the

read/write pointer selects the register of the first byte for

transmission and is auto-incremented by the I2C-bus

control for the transfer of subsequent bytes.

During a write transmission after reception of the device

slave address and write bit, the mode control settings for

the pre-processor have to be send in the protocol

sequence as shown in Table 1 and Fig.5.

During a read cycle after reception of the device slave

address and read bit the requested RDS/RBDS data has

tobe receivedin theprotocolsequence asgiven inTable 2

and Fig.7.

Table 1 Input control registers

Table 2 Output registers

WRITE TRANSMISSION FORMAT

Table 3 Description of initialization and mode control

byte (byte 0W)

DATA FUNCTION

Byte 0Winitialization and mode control setting;

see Table 3

Byte 1Wpause level and ﬂywheel setting;

see Table 6

Byte 2Wpause time/oscillator frequency and

quality detector sensitivity setting;

see Table 7

DATA FUNCTION

Byte 0Rdecoder and data status information;

see Table 12

Byte 1Rlast processed block (HIGH byte);

see Table 15

Byte 2Rlast processed block (LOW byte);

see Table 15

Byte 3Rpreviously processed block (HIGH byte);

see Table 15

Byte 4Rpreviously processed block (LOW byte);

see Table 15

Byte 5Rerror status information; see Table 15

Byte 6Rsignal quality indication; see Table 15

BIT NAME FUNCTION

7 SQCM 0: triggered signal quality measurement

1: signal quality continuous measurement

6 TSQD 0: no determination of signal quality

1: trigger of signal quality detector

measurement

5 NWSY 0: normal processing mode

1: restart of synchronization

4 SYM1 selection of error correction mode for

synchronization search; see Table 4

3 SYM0

2 RBDS 0: RDS processing mode

1: RBDS processing mode

1 DAC1 selection of data output protocol and

indirectly control of data available output

signal (DAVN); see Table 5

0DAC0

2002 Jan 14 12

Philips Semiconductors Product speciﬁcation

RDS/RBDS pre-processor SAA6588

Table 4 Selection of error correction mode for synchronization search

Table 5 Selection of data output protocol and DAVN signal

Table 6 Description of pause level and ﬂywheel setting bytes (byte1W)

Table 7 Description of pause time/oscillator frequency and quality detector sensitivity setting (byte 2W)

Table 8 Control bits PL0 and PL1

SYM1 SYM0 MODE DESCRIPTION

0 0 SYNCA no error correction

0 1 SYNCB error correction of a burst error maximum 2 bits

1 0 SYNCC error correction of a burst error maximum 5 bits

1 1 SYNCD no error correction; no E-E block sequence allowed (for RBDS mode, E-A or D-E

block sequences are still allowed)

DAC1 DAC0 MODE FUNCTION DESCRIPTION

0 0 DAVA standard

processing mode RDS standard output mode;

synchronization search: DAVN = HIGH;

synchronized: block information available and DAVN active after

detection of a new block (every 26 bits)

0 1 DAVB fast PI search

mode synchronization search: for fast PI search, block information

available and DAVN active only if a correct A-block is detected;

synchronized: same as standard DAVA mode

1 0 DAVC reduced data

request

processing mode

synchronization search: DAVN inactive = HIGH;

synchronized: block information available and DAVN active only

after detection of two new blocks (every 52 bits)

11−−−

BIT NAME FUNCTION

7 PL1 level sensitivity for pause detection; see Table 8

6 PL0

5 to 0 FEB5 to FEB0 maximum number of error blocks for synchronization hold ﬂywheel (0 to 63)

BIT NAME FUNCTION

7 PTF1 time criteria for pause (20 to 160 ms); see Table 9

oscillator frequency: n ×4.332 MHz (n = 1 to 4); see Table 9

6 PTF0

5 SOSC 0: set pause time criteria via PFT1 and PFT0

1: select oscillator frequency via PFT1 and PFT0

4 to 0 SQS4 to SQS0 adjustment of signal quality detector sensitivity (−9 to +9.6 dB); see Table 10

PL1 PL0 PAUSE LEVEL

(mV RMS) BELOW DOLBY

LEVEL (dB) FM DEVIATION

(kHz)

0 0 11 30.2 1.0

0 1 17 26.2 1.6

1 0 27 22.2 2.5

1 1 43 18.2 4.0

2002 Jan 14 13

Philips Semiconductors Product speciﬁcation

RDS/RBDS pre-processor SAA6588

Table 9 Control bits SOSC, PTF0 and PTF1

Table 10 Control bits SQS0 to SQS4

SOSC PTF1 PTF0 SOSC = 0 SOSC = 1

MINIMUM TIME

(ms) OSCILLATOR FREQUENCY

(MHz)

0 0 0 20.2 4.332 (n = 1)

0 0 1 40.4 8.664 (n = 2)

0 1 0 80.8 12.996 (n = 3)

0 1 1 161.7 17.328 (n = 4)

SQS CORRECTION

(dB)

SQS4 SQS3 SQS2 SQS1 SQS0 HEX

0000000−9.0

0000101−8.4

0001002−7.8

0001103−7.2

0010004−6.6

0010105−6.0

0011006−5.4

0011107−4.8

0100008−4.2

0100109−3.6

010100A−3.0

010110B−2.4

011000C−1.8

011010D−1.2

011100E−0.6

011110F0

1000010+0.6

1000111+1.2

1001012+1.8

1001113+2.4

1010014+3.0

1010115+3.6

1011016+4.2

1011117+4.8

1100018+5.4

1100119+6.0

110101A+6.6

110111B+7.2

111001C+7.8

111011D+8.4

111101E+9.0

111111F+9.6

2002 Jan 14 14

Philips Semiconductors Product speciﬁcation

RDS/RBDS pre-processor SAA6588

Table 11 Default values of the write register bits after

reset

READ TRANSMISSION FORMAT

Table 12 Description of decoder and data status

information byte (byte 0R)

Table 13 Block identiﬁcation number (last detected block)

Table 14 Processed error correction

Table 15 Bytes 1Rto 6R

BIT VALUE COMMENTS

SQCM 0 triggered signal quality

measurement

TSQD 0 no determination of signal

quality

NWSY 1 restart of synchronization

SYM1 and SYM0 00 no error correction during

synchronization

RBDS 0 RDS processing mode

PL1 and PL0 00 pause level 12 mV

DAC1 and DAC0 00 DAVA modeRDSstandard

output mode

FEB5 to FEB0 100000 ﬂywheel = 32 decimal

PTF1 and PTF0 00 oscillator

frequency = 4.332 MHz

(SOSC = 1);

pause time = 20.2 ms

(SOSC = 0)

SQS4 to SQS0 01111 gain=0dB

BYTE BIT NAME FUNCTION

0R7 to 5 BL2 to BL0 block identiﬁcation number

of last processed block;

see Table 13

4 SYNC 0: not synchronized

1: synchronized

3 DOFL 0: no data overﬂow

1: data overﬂow detected

2 RSTD 0: no reset detected

1: reset detected

1 ELB1 error status of last

processed block;

see Table 14

0 ELB0

BL2/

BP2 BL1/

BP1 BL0/

BP0 BLOCK IDENTIFICATION

0 0 0 block A

0 0 1 block B

0 1 0 block C

0 1 1 block D

1 0 0 block C’

1 0 1 block E (RBDS mode)

1 1 0 invalid block E (RDS mode)

1 1 1 invalid block

ELB1/

EPB1 ELB0/

EPB0 MODE DESCRIPTION

0 0 ERDA no errors detected

0 1 ERDB burst error of maximum

2 bits corrected

1 0 ERDC burst error of maximum

5 bits corrected

1 1 ERDD uncorrectable block

BYTE BIT NAME FUNCTION

1R7 to 0 M15 to

M08 HIGH byte of last

processed block

2R7 to 0 M07 to

M00 LOWbyteof last processed

block

3R7 to 0 PM15 to

PM08 HIGH byte of previously

processed block

4R7 to 0 PM07 to

PM00 LOW byte of previously

processed block

5R7 to 2 BEC5 to

BEC0 number of counted block

errors (0 to 63)

1 EPB1 error status of previously

processed block;

see Table 14

0 EPB0

6R7 to 5 BP2 to

BP0 block identiﬁcation number

of previous processed

block; see Table 13

4−not used (undeﬁned)

3 to 0 SQI3 to

SQI0 signal quality indication

(0 to 15)

2002 Jan 14 15

Philips Semiconductors Product speciﬁcation

RDS/RBDS pre-processor SAA6588

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

Notes

1. Without latching in the entire temperature range.

2. Human body model (equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor).

Except pin 17: −4000 V minimum and +2500 V maximum.

3. Machine model (equivalent to discharging a 200 pF capacitor through a 0 Ωseries resistor and 0.75 µH inductance).

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VDD supply voltage 0 6.5 V

Vnvoltage at pins 1 to 5, 8 to 13, and

16 to 20 with respect to pins 6 and 15 −0.5 VDD + 0.5 ≤6.5 V

Vi(MPX)(p-p) input voltage at pin MPX

(peak-to-peak value) note 1 −6V

iinput current

pins 1 to 5, 8, 10 to 13 and 16 to 20 −10 +10 mA

pin 9 −20 +20 mA

Ilu(prot) latch-up protection current in pulsed

mode Tamb =−40 to +85 °C with

voltage limiting −2 to +10 V −100 +100 mA

Tamb =25°C with voltage

limiting −2 to +12 V −200 +200 mA

Tamb =−40 to +85 °C

without voltage limiting −10 +10 mA

Tamb operating ambient temperature −40 +85 °C

Tstg storage temperature −65 +150 °C

Ves electrostatic handling note 2 −4000 +4000 V

note 3 −250 +250 V

SYMBOL PARAMETER CONDITIONS VALUE UNIT

Rth(j-a) thermal resistance from junction to ambient in free air

SAA6588T (SOT163-1) 85 K/W

SAA6588 (SOT146-1) 62 K/W

2002 Jan 14 16

Philips Semiconductors Product speciﬁcation

RDS/RBDS pre-processor SAA6588

CHARACTERISTICS DIGITAL PART

VDDA =V

DDD =5V; T

amb =25°C; unless otherwise speciﬁed.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

VDDD digital supply voltage 4.5 5.0 5.5 V

IDDD digital supply current −6.0 −mA

Ptot total power dissipation −70 −mW

Inputs

VIL1 LOW-level input voltage at

pins TCON, OSCI and MAD −−0.3VDDD V

VIL2 LOW-level input voltage at

pins SCL and SDA VDDD = 4.5 to 5.0 V −0.5 −+1.5 V

VDDD = 5.0 to 5.5 V −0.5 −+0.3VDDD V

VIH1 HIGH-level input voltage at

pins TCON, OSCI and MAD 0.7VDDD −− V

IH2 HIGH-level input voltage at

pins SCL and SDA VDDD = 4.5 to 5.5 V 3.0 −VDDD + 0.5 V

ILIinput leakage current at

pins TCON, SCL and SDA VMAD =0toV

DDD −−10 µA

Ii(pu) input pull-up current at pin MAD VMAD =V

IL1 −30 −20 −µA

MAD = 3.5 V −−20 −10 µA

Outputs

VOL1 LOW-level output voltage at

pins DAVN, PSWN and OSCO IOL =2mA −−0.4 V

VOL2 LOW-level output voltage at

pin SDA IOL1 = 4.0 mA −−0.4 V

IOL2 = 6.0 mA −−0.6 V

VOH HIGH-level output voltage at

pins DAVN, PSWN and OSCO IOH =−2 mA 4.0 −− V

Crystal parameters

fi(xtal) crystal input frequency n = 1 −4.332 −MHz

n=2 −8.664 −MHz

n=3 −12.996 −MHz

n=4 −17.328 −MHz

∆foscadjustment tolerance of oscillator

frequency −−30 ppm

∆fosc(T)temperature drift of oscillator

frequency Tamb =−40 to +85 °C−−30 ppm

CLload capacitance −30 −pF

Rxtal crystal resonance resistance fosc ≤12.996 MHz −−120 Ω

fosc = 17.328 MHz −−60 Ω

2002 Jan 14 17

Philips Semiconductors Product speciﬁcation

RDS/RBDS pre-processor SAA6588

CHARACTERISTICS ANALOG PART

VDDA =V

DDD =5V; T

amb =25°C; measurements taken in Fig.1; unless otherwise speciﬁed.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

VDDA analog supply voltage 4.5 5.0 5.5 V

VDDA −VDDDvoltage difference between

analog and digital supply −0 0.5 V

IDD(tot) total supply current −14.0 −mA

Vref reference voltage VDDA = 5 V 2.25 2.5 2.75 V

Zo(Vref) output impedance at pin Vref −25 −kΩ

MPX input (signal before the capacitor on pin MPX)

Vi(MPX)(rms) RDS amplitude (RMS value) ∆f=±1.2 kHz RDS signal;

∆f=±3.2 kHz spurious signal 1−−mV

Vi(max)(p-p) maximum input signal capability

(peak-to-peak value) f=57±2 kHz 200 −−mV

f < 50 kHz 1.4 −−V

f < 15 kHz 2.8 −−V

f > 70 kHz 3.5 −−V

i(MPX) input resistance f = 0 to 100 kHz 33 −−kΩ

57 kHz band-pass ﬁlter

fccentre frequency Tamb =−40 to +85 °C 56.5 57.0 57.5 kHz

B−3dB −3 dB bandwidth 2.5 3.0 3.5 kHz

GMPX signal gain f = 57 kHz 17 20 23 dB

αsb stop band attenuation ∆f=±7 kHz 31 −−dB

f < 45 kHz 40 −−dB

f < 20 kHz 50 −−dB

f > 70 kHz 40 −−dB

Ro(SCOUT) output resistance at pin SCOUT f = 57 kHz −30 60 Ω

Comparator input (pin CIN)

Vi(min)(rms) minimum input level

(RMS value) f = 57 kHz −110mV

iinput resistance 70 110 150 kΩ

Multi-path detector (pins LVIN, MPTH and MRO)

Zi(LVIN) input impedance at pin LVIN f = 21 kHz 24 30 36 kΩ

Vi(LVIN) input voltage at pin LVIN 1.0 2.5 4.0 V

fc(MPD) centre frequency of the

multi-path detector band-pass

ﬁlter

20 21 22 kHz

BMPD bandwidth of the multi-path

detector band-pass ﬁlter 3.6 4.0 4.4 kHz

αsb stop band attenuation f = 11 kHz 16 −−dB

f = 31 kHz 12 −−dB

tatt(MRO) attack time of the rectiﬁer C6 = 100 nF; R4 = 470 kΩ− 6.4 −ms

2002 Jan 14 18

Philips Semiconductors Product speciﬁcation

RDS/RBDS pre-processor SAA6588

tdec(MRO) decay time of the rectiﬁer C6 = 100 nF; R4 = 470 kΩ− 50 −ms

Gv(MPTH) rectiﬁer voltage gain; VLVIN(rms) = 0.1 V;

fLVIN = 21 kHz −20 −dB

Zo(MPTH) output impedance at pin MPTH 150 200 250 Ω

Vo(MPTH) output voltage swing at

pin MPTH 0.5 −3.5 V

ZL(MPTH) load impedance at pin MPTH with respect to ground 5 −−kΩ

L(MPTH) load capacitance at pin MPTH with respect to ground −−20 pF

Signal quality detector (pin MPX)

fco cut-off frequency 85 90 95 kHz

PBRR pass-band ripple rejection −−1dB

sb stop band attenuation f = 40 kHz 30 −−dB

VSTEP2-3(rms) input voltage (RMS value) for

transition of signal quality

indication between step 2 and 3

(SQI = 0010 and 0011)

sensitivity=0dB

(SQS = 01111; see Table 10);

f = 100 kHz

−85 −mV

∆GSQ step size for signal quality input

gain 0.4 0.6 0.8 dB

CRGSQ control range for signal quality

input gain 15.6 18.6 21.6 dB

tSQD measuring time after acknowledgement of the

I2C-bus transceiver −−850 µs

Pause detector (pins AFIN and PSWN)

Zi(AFIN) input impedance f = 10 kHz −−10 Ω

VI(AFIN) DC input voltage unloaded −Vref −V

Ith(rms) AC input current for threshold

(RMS value) PL1 = 1; PL0 = 1 3.1 4.4 6.2 µA

THpause(step) step size for pause threshold 345dB

THpause(R) control range for pause

threshold 10 12 14 dB

Ii(offset) input offset current −−0.4 µA

tPON(min) minimum time for pause PT1 = 0; PT0 = 0 −20.2 −ms

PT1 = 0; PT0 = 1 −40.4 −ms

PT1 = 1; PT0 = 0 −80.8 −ms

PT1 = 1; PT0 = 1 −161.7 −ms

tPOFF(min) minimum time for no pause −5−ms

∆t time error (all values) −−1.0 ms

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Gv(MPTH) 20 log VMPTH(DC)

VLVIN(rms)

--------------------------

2002 Jan 14 19

Philips Semiconductors Product speciﬁcation

RDS/RBDS pre-processor SAA6588

I2C-BUS PROTOCOL

I2C-bus format

In communication with the pre-processor two basic types

of I2C-bus protocols are allowed (see Tables 16 and 17).

Every transmission begins with a START condition ‘S’

followed by the 7-bit slave address and the R/W mode bit,

all generated by the external master.

The 6 higher bits of the pre-processors slave address are

fixed to 001000. The least significant bit of the slave

address can be set via the external input pin MAD to

enable a variation if the slave address is already occupied

by another device of the radio set. Data is transferred with

the most significant bit (MSB) first.

Each transmitted byte is followed by an acknowledge bit

‘A’ (SDA = LOW). Every transmission is completed with a

STOP condition ‘P’ generated by the master.

During read or write transfer the master can abridge the

data transfer by generation of a STOP condition. In case

of transmission errors during a write cycle, the

pre-processor can indirectly stop the transfer by

generating no acknowledge (SDA = HIGH) hereafter the

master can send the STOP condition.

Table 16 Transmitting to the pre-processor (write transfer)

Notes

1. S = START condition.

2. Slave address (depends on level at pin MAD) = 0010000 or 0010001.

3. W = write mode.

4. A = acknowledge bit (SDA = LOW).

5. Subsequently data bytes 0W,1

and 2W.

6. P = STOP condition.

Table 17 Receiving from the pre-processor (read transfer)

Notes

1. S = START condition.

2. Slave address (depends on level at pin MAD) = 0010000 or 0010001.

3. R = read mode.

4. A = acknowledge bit (SDA = LOW). Six DATA-acknowledge sequences must occur before the DATA-not

acknowledge sequence.

5. Subsequently data bytes 0Rto 6R.

6. A = no acknowledge (SDA = HIGH).

7. P = STOP condition.

S(1) SLAVE ADDRESS(2) W(3) A(4) DATA(5) A(4) DATA(5) A(4) DATA(5) A(4) P(6)

S(1) SLAVE ADDRESS(2) R(3) A(4) DATA(5) A(4) DATA(5) A(6) P(7)

2002 Jan 14 20

Philips Semiconductors Product speciﬁcation

RDS/RBDS pre-processor SAA6588

Timing data

Table 18 Data available signal (DAVN)

Notes

1. See Fig.4a.

2. See Fig.4b.

SYMBOL PARAMETER TYP. UNIT

tDVL data valid to DAVN LOW 2.0 µs

tTDAV data valid period 21.9 ms

tDV data valid 21.9 ms

tDAVL data available signal is LOW 10.1(1) ms

depends on data request via I2C-bus(2) ms

Fig.4 Data available signal (DAVN).

handbook, full pagewidth

MGK540

tDV

tTDAV

tDAVL

tDVL

DAVN

DATA

handbook, full pagewidth

MGK541

tDV

tTDAV

tDAVL

tDVL

pre-processor

addressed

I2C-BUS

DAVN

DATA

a. No I2C-bus request during DAVN LOW-time (decoder is synchronized).

b. DAVN LOW-time shortened by data-request via I2C-bus (decoder is synchronized).

2002 Jan 14 21

Philips Semiconductors Product speciﬁcation

RDS/RBDS pre-processor SAA6588

PROGRAMMING AND I2C-BUS SUMMARY

Fig.5 RDS pre-processor control commands: mode control and preset settings for the pre-processor.

handbook, full pagewidth

acknowledgement

from slave

acknowledgement

from slave

acknowledgement

from slave

acknowledgement

from slave

MGK538

SQS1 SQS0SQS2SQS3SQS4SOSCPTF0PTF1 AP

byte 2W from master

FEB1 FEB0FEB2FEB3FEB4FEB5PL0PL1 A

byte 1W from master

DAC1 DAC0RBDSSYM0SYM1NWSYTSQDSQCM A

byte 0W from master

MAD 0000100 AS

slave address + write-bit from master

START condition

from master

STOP condition

from master

Fig.6 RDS pre-processor control commands: abridged protocol, for example for immediate restart

synchronization.

handbook, full pagewidth

MGK539

DAC1 DAC0RBDSSYM0SYM11TSQDSQCM AP

byte 0W from master

MAD 0000100 AS

slave address + write-bit from master

acknowledgement

from slave

acknowledgement

from slave

START condition

from master

STOP condition

from master

2002 Jan 14 22

Philips Semiconductors Product speciﬁcation

RDS/RBDS pre-processor SAA6588

Fig.7 Data output protocol (RDS data output).

handbook, full pagewidth

MGK537

SQI1 SQI0SQI2SQI3

not

used

BP0BP1BP2 AP

byte 6R from device

EPB1 EPB0BEC0BEC1BEC2BEC3BEC4BEC5 A

byte 5R from device

lower byte of previous processed block from device

higher byte of previous processed block from device

lower byte of last processed block from device

higher byte of last processed block from device

ELB1 ELB0RSTDDOFLSYNCBL0BL1BL2

M09 M08M10M11M12M13M14M15

M01 M00M02M03M04M05M06M07

PM09 PM08PM10PM11PM12PM13PM14PM15

PM01 PM00PM02PM03PM04PM05PM06PM07

byte 0R from device

MAD 1000100 AS

slave address + read-bit from master

not acknowledged

from master

START condition

from master

STOP condition

from master

2002 Jan 14 23

Philips Semiconductors Product speciﬁcation

RDS/RBDS pre-processor SAA6588

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APPLICATION DIAGRAM

k, full pagewidth

MGK536

270 Ω

(1)

(3)

10 Ω

270 Ω

(1)

(3)

470 Ω

(1)

1 kΩ

R10

470 kΩ

C11

2.2 µFC16

82 pF

C15

47 pF

C17

100 nF

Q1 (4)

(1)

R11 10 Ω

20 1

SAA6588

1 kΩ

47 µF

C12

(1)

C13

2.2 nF

C10

330 pF

470 Ω

C14

100 nF

MRO

MPTH

TCON

OSCO

OSCI

VSSD

VDDD

DAVN

SDA

SCL

LVIN

CIN

SCOUT

Vref

MPX

VSSA

VDDA

AFIN

MAD

C18

1 nF

(1)

1.5 nF

(1)

C51

470 pF

(1)

220 pF

(1)

(3)

1.5 nF

(1)

220 pF

(1)

(3)

10 kΩ

470 nF

10 kΩ

470 nF

(1)

+5 V

S_SDA

S_SCL

S_PSWN

GND

AF1

AF2

MUX

LVL

S_MPTH

+5 V

S_DAVN

560 pF

100 nF

PSWN

HC49/U

L1 (1) (2)

Fig.8 Application diagram.

(1) Components for suppression of electromagnetic emission (EME).

(2) L1 = type EMIFIL, part number BLM21A102S (MURATA) or equivalent.

(3) Values for standard mode I2C-bus. Necessary pull-up resistors of 1.8 kΩ are part of the I2C-bus interface.

(4) Q1: 4.332 MHz, 8.664 MHz, 12.996 MHz or 17.328 MHz.

2002 Jan 14 24

Philips Semiconductors Product speciﬁcation

RDS/RBDS pre-processor SAA6588

PACKAGE OUTLINES

UNIT A

max. 1 2 b1cD E e M

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC EIAJ

inches

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

SOT146-1 95-05-24

99-12-27

min. A

max. bZ

max.

1.73

1.30 0.53

0.38 0.36

0.23 26.92

26.54 6.40

6.22 3.60

3.05 0.2542.54 7.62 8.25

7.80 10.0

8.3 2.04.2 0.51 3.2

0.068

0.051 0.021

0.015 0.014

0.009 1.060

1.045 0.25

0.24 0.14

0.12 0.010.10 0.30 0.32

0.31 0.39

0.33 0.0780.17 0.020 0.13

SC-603MS-001

(e )

seating plane

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

(1)

(1) (1)

DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1

2002 Jan 14 25

Philips Semiconductors Product speciﬁcation

RDS/RBDS pre-processor SAA6588

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZ

ywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC EIAJ

inches

2.65 0.30

0.10 2.45

2.25 0.49

0.36 0.32

0.23 13.0

12.6 7.6

7.4 1.27 10.65

10.00 1.1

1.0 0.9

0.4 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

1.1

0.4

SOT163-1

detail X

0.25

075E04 MS-013

pin 1 index

0.10 0.012

0.004 0.096

0.089 0.019

0.014 0.013

0.009 0.51

0.49 0.30

0.29 0.050

1.4

0.055

0.419

0.394 0.043

0.039 0.035

0.016

0.01

0.25

0.01 0.004

0.043

0.016

0.01

0 5 10 mm

scale

vMA

(A )

SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

97-05-22

99-12-27

2002 Jan 14 26

Philips Semiconductors Product speciﬁcation

RDS/RBDS pre-processor SAA6588

SOLDERING

Introduction

Thistext givesa verybriefinsight toa complextechnology.

A more in-depth account of soldering ICs can be found in

our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).

There is no soldering method that is ideal for all IC

packages. Wave soldering is often preferred when

through-holeandsurfacemountcomponentsaremixedon

one printed-circuit board. Wave soldering can still be used

for certain surface mount ICs, but it is not suitable for fine

pitch SMDs. In these situations reflow soldering is

recommended.

Through-hole mount packages

SOLDERING BY DIPPING OR BY SOLDER WAVE

The maximum permissible temperature of the solder is

260 °C; solder at this temperature must not be in contact

with the joints for more than 5 seconds. The total contact

time of successive solder waves must not exceed

5 seconds.

The device may be mounted up to the seating plane, but

the temperature of the plastic body must not exceed the

specified maximum storage temperature (Tstg(max)). If the

printed-circuit board has been pre-heated, forced cooling

may be necessary immediately after soldering to keep the

temperature within the permissible limit.

MANUAL SOLDERING

Apply the soldering iron (24 V or less) to the lead(s) of the

package, either below the seating plane or not more than

2 mm above it. If the temperature of the soldering iron bit

is less than 300 °C it may remain in contact for up to

10 seconds. If the bit temperature is between

300 and 400 °C, contact may be up to 5 seconds.

Surface mount packages

REFLOW SOLDERING

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

tothe printed-circuit board by screenprinting,stencillingor

pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,

convection or convection/infrared heating in a conveyor

type oven. Throughput times (preheating, soldering and

cooling) vary between 100 and 200 seconds depending

on heating method.

Typical reflow peak temperatures range from

215 to 250 °C. The top-surface temperature of the

packages should preferable be kept below 220 °C for

thick/large packages, and below 235 °C for small/thin

packages.

WAVE SOLDERING

Conventional single wave soldering is not recommended

forsurfacemountdevices(SMDs)or printed-circuitboards

with a high component density, as solder bridging and

non-wetting can present major problems.

To overcome these problems the double-wave soldering

method was specifically developed.

If wave soldering is used the following conditions must be

observed for optimal results:

•Use a double-wave soldering method comprising a

turbulent wave with high upward pressure followed by a

smooth laminar wave.

•For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the

transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the

printed-circuit board.

The footprint must incorporate solder thieves at the

downstream end.

•Forpackageswithleadsonfoursides,the footprintmust

be placed at a 45°angle to the transport direction of the

printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

MANUAL SOLDERING

Fix the component by first soldering two

diagonally-opposite end leads. Use a low voltage (24 V or

less) soldering iron applied to the flat part of the lead.

Contact time must be limited to 10 seconds at up to

300 °C. When using a dedicated tool, all other leads can

be soldered in one operation within 2 to 5 seconds

between 270 and 320 °C.

2002 Jan 14 27

Philips Semiconductors Product speciﬁcation

RDS/RBDS pre-processor SAA6588

Suitability of IC packages for wave, reﬂow and dipping soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package

cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the

Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

2. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.

3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder

cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,

the solder might be deposited on the heatsink surface.

4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

5. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

6. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

MOUNTING PACKAGE SOLDERING METHOD

WAVE REFLOW(1) DIPPING

Through-hole mount DBS, DIP, HDIP, SDIP, SIL suitable(2) −suitable

Surface mount BGA, HBGA, LFBGA, SQFP, TFBGA not suitable suitable −

HBCC, HLQFP, HSQFP, HSOP, HTQFP,

HTSSOP, HVQFN, SMS not suitable(3) suitable −

PLCC(4), SO, SOJ suitable suitable −

LQFP, QFP, TQFP not recommended(4)(5) suitable −

SSOP, TSSOP, VSO not recommended(6) suitable −

2002 Jan 14 28

Philips Semiconductors Product speciﬁcation

RDS/RBDS pre-processor SAA6588

DATA SHEET STATUS

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was

published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

DATA SHEET STATUS(1) PRODUCT

STATUS(2) DEFINITIONS

Objective data Development This data sheet contains data from the objective specification for product

development. Philips Semiconductors reserves the right to change the

speciﬁcation in any manner without notice.

Preliminary data Qualiﬁcation This data sheet contains data from the preliminary specification.

Supplementary data will be published at a later date. Philips

Semiconductors reserves the right to change the speciﬁcation without

notice, in order to improve the design and supply the best possible

product.

Product data Production This data sheet contains data from the product specification. Philips

Semiconductors reserves the right to make changes at any time in order

to improve the design, manufacturing and supply. Changes will be

communicated according to the Customer Product/Process Change

Notiﬁcation (CPCN) procedure SNW-SQ-650A.

DEFINITIONS

Short-form specification  The data in a short-form

specification is extracted from a full data sheet with the

same type number and title. For detailed information see

the relevant data sheet or data handbook.

Limiting values definition Limiting values given are in

accordance with the Absolute Maximum Rating System

(IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device.

These are stress ratings only and operation of the device

atthese oratany otherconditionsabove thosegivenin the

Characteristics sections of the specification is not implied.

Exposure to limiting values for extended periods may

affect device reliability.

Application information  Applications that are

described herein for any of these products are for

illustrative purposes only. Philips Semiconductors make

norepresentationor warrantythatsuchapplicationswill be

suitable for the specified use without further testing or

modification.

DISCLAIMERS

Life support applications  These products are not

designed for use in life support appliances, devices, or

systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips

Semiconductorscustomersusingorsellingthese products

for use in such applications do so at their own risk and

agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Right to make changes  Philips Semiconductors

reserves the right to make changes, without notice, in the

products, including circuits, standard cells, and/or

software, described or contained herein in order to

improve design and/or performance. Philips

Semiconductors assumes no responsibility or liability for

theuseofanyoftheseproducts,conveys nolicence ortitle

under any patent, copyright, or mask work right to these

products,and makes norepresentationsor warranties that

these products are free from patent, copyright, or mask

work right infringement, unless otherwise specified.

2002 Jan 14 29

Philips Semiconductors Product speciﬁcation

RDS/RBDS pre-processor SAA6588

PURCHASE OF PHILIPS I2C COMPONENTS

Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the

components in the I2C system provided the system conforms to the I2C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

2002 Jan 14 30

Philips Semiconductors Product speciﬁcation

RDS/RBDS pre-processor SAA6588

NOTES

2002 Jan 14 31

Philips Semiconductors Product speciﬁcation

RDS/RBDS pre-processor SAA6588

NOTES

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Philips Semiconductors – a world wide company

Contact information

For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825

For sales ofﬁces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.

Printed in The Netherlands 753503/02/pp32 Date of release: 2002 Jan 14 Document order number: 9397 750 09197