FINAL Am79C30A/32A Digital Subscriber Controller (DSC) Circuit DISTINCTIVE CHARACTERISTICS Combines CCITT 1.430 S/T-Interface Transceiv- er, D-Channel LAPD Processor, Audio Proces- sor (DSC device only), and IOM-2 Interface ina single chip Special operating modes allow realization of CCITT 1.430 power-compliant terminal equipment S- or T-interface Transceiver Level 1 Physical Layer Controller Supports point-to-point, short and extended passive bus configurations Provides multiframe support cl Advanced Micro Devices Certified protocol software support available CMOS technology, TTL compatible D-channel processing capability Flag generation/detection CRC generation/checking Zero insertion/deletion Four 2-byte address detectors 32-byte receive and 16-byte transmit FIFOs BLOCK DIAGRAM SBP/IOM-2 interface CAPI CAP? SBIN SOLK BOECHeSTRB ALAA) SBOUT# sFs 4 HSW . A 4 q ve v Q g AREF @ Main Audio . S/T Line > LOUT! 8 a AINB Processor (MAP) Peripheral Port Interface Unit > LOUT2 s E4 EARI (PP) (LIU) Lint [= gy EAR < (Am79C30A LIN2 J 2 LS1 Only) LS24 Bd| Be} Bf Channel B1 Ba B-channel Multiplexer y (MUX) B2 D-Channel Data XTAL1 4 Oscillator Link Controller XTAL2 (OSC) (BLC) Bb Bc MCLK <4 b y Channel ee Microprocessar Interface RESET RD a AAAbABA - & & VvTyvVg v y vv D7 D D5 D4 D3 D2 D1 DO INT A2 Ai AO Microprocessor Interface Note: 09893F-001 *BCL/CH2STRB signal present for PLCC and TQFP packages only. Publication #:09893 Rev.G Amendment 0 Issue Dato: January 1995al AMD DISTINCTIVE CHARACTERISTICS (continued) @ Audio processing capability (DSC circuit only) Registers for implementation of software-based speaker phone algorithms Dual audio inputs Earpiece and loudspeaker drivers Codecffilter with A/i selection Programmable gain and equalization filters Programmabie sidetone level Programmable DTMF, single tone, progress tone, and ringer tone generation Programmable on-chip microphone amplifier @ Pin and software compatible with the Am79C32A ISDN Data Controller (IDC) Circuit. The Am79C32A is used in data-only applications. GENERAL DESCRIPTION The Am79C30A Digital Subscriber Controller (DSC) Circuit and Am79C32A ISDN Data Controller (IDC) Cir- cuit, shown in the Block Diagram, allow the realization of highly-integrated Terminal Equipment for the ISDN. The Am79C30A/32A is fully compatible with the CCITT- I-series recommendations for the S and T reference points, ensuring that the user of the device may design TEs which conform to the international standards. The Am79C30A/32A provides a 192-Kbit/s full duplex digital path over four wires between the TE located on the subscriber's premises and the NT or PABX linecard. All physical layer functions and procedures are imple- mented in accordance with CCITT Recommendation 1.430, including framing, synchronization, maintenance, and multiple terminal contention. Both point-to-point and point-to-multipoint configurations are supported. The Am79C30A/32A processes the ISDN basic rate bit stream, which consists of B1 (64 Kbit/s), B2 (64 Kbit/s), and D (16 Kbit/s) channels. The B channels are routed to and from different sections of the Am79C30A/32A under software control. The D channel is partially processed by the DSC/IDC circuit and is passed to the microprocessor for further processing. The Main Audio Processor (MAP) uses Digital Signal Processing (DSP) to implement a high performance co- decffilter function. The MAP interface supports a loud- speaker, an earpiece, and two separate audio inputs. Programmable on-chip gain is provided to simplify use of low output level microphones. The user may alter fre- quency response and gain of the MAP receive and transmit paths. Tone generators are included to imple- ment ringing, call progress, and DTMF signals. A Peripheral Port (PP) is provided to allow the B chan- nels to be routed off-chip for processing by other peripherals. This port is configurable as either an indus- try-standard IOM-2 port, or as a serial bus port (SBP). The TE design process is simplified by the availability of certified protocol software packages, which provide complete system solutions through OSI Layer 3. 2 Am79C30A/32A Data SheetAMD cl CONNECTION DIAGRAMS Top View 40-Pin DIP iso Chie SY 40 [J Ls1 EAR1 CJ 2 = AREF EAR2 CJ 3 38 LIN4 AINA CJ 4 37 (2s uin2 AINB (1 5 36 D HSW caPt (1 6 35 LOUT1 cap2 C17 34 [2 Lout2 Veco EC] 8 33 [F) Vsg RESET CJ 9 32 [1 sOINT cs 4 10 Am79C30A 31 [) XTAL? RD 14 30 [ XTAL2 WA Cy 12 29 [7 MCLK Vss (FJ 13 23 [J sFs A2 cy 14 27) ~ScCLK Ai Cy] 15 26 [0 ~SBOUT Ao Cj 16 25 [2 SBIN o7 17 24/7) bo be C] 18 23 01 D5 Oo 19 22 (9 pe D4 20 2117 b3 44-Pin PLCC Nn = iL 22255952 22 3 OOOR OORT CAP1 [| 7 39 LOUTI cAP2 [| 8 38 [7] Loute Aveo LL] 9 37 [7] AVss DVce [C] 10 36 [7] DVg5 RESET ([] 11 35 [~j INT cs [12 Am79C30A 34 [7] XTALI AD CC) 13 33 [7] XTAL2 wR [] 14 32 [-}] MCLK DV ss Cl 15 31 4 SFS A2 (] 16 30 mm SCLK Ai ((] 17 29 [_} SBOUT LL ~Z2ReaNRARARA y YOUU UUUUUUo Z588AR B85 BZ 5 a = Qo Note: 3 a Pin 1 is marked for orientation purposes. Am79C30A/32A Data Sheet 3a AMD CONNECTION DIAGRAMS (continued) Top View Note: RSRVD RSRVD AVoc DVce RESET DVs5 A2 Al 40-Pin DIP Ls2 Coie VY 40 (2 1s1 RSRVD CY 2 39 [) RSAVD RASAVD CJ 3 38 (9 LIN1 RSRVD EC] 4 37 (9 tine RSRVD EF] 5 36 [FE Hsw RSRVD (1) 6 35 ( LoumTi RSRVD C7 34 {9 LouT2 Voc C8 33 [2 Vss RESET C4 9 32 1 ~INT CTS (4 10 Am79C32A 31 [2 XTAL! RD Cj 30 [F) XTAL2 wr CJ 12 29 [J MCLK Vss EZ] 13 28 [2 SFs a2 C] 14 27 [) SCLK Ai (] 15 26 [J SBOUT Ao Cy 16 25 [-) SBIN o7 Cy 1? 24[-] Do os Cy 18 23 [J pi os CJ 19 22) p2 D4 CJ] 20 21 [9 D3 44-Pin PLCC Oaqndnaongda eeoenke < = DOO A cl? 30 [J Cl sa 38 [ Cl a 37 C] 10 36 (TJ (J 11 35 [) Cc] 12 Am79C32A 340) Cy 13 33 [7] Cy 14 32 CC] 15 31 [7 CL] 16 30 [TJ C17 29 [7] L ~2PRNANRAAKRAA ) 5 n = Qo ! a 1. Pin 1 is marked for orientation purposes. 2, RSRVD = Reserved pin, should not be connected externally to any signal or supply. LOUT1 LOUT2 AV ss DVss, 4 XTAL1 XTAL2 MCLK SFS SCLK SBOUT 4 Am79C30A/32A Data St ~-tAMD al CONNECTION DIAGRAMS (continued) Top View 44-Pin TQFP MSHI] zNnOC] INN dau (7 isT1 zs1C] Luva [J zuva vNIVC_ aniv SS~y Co 44 43 42 41 40 39 38 37 36 35 34 |) Nn Saxe bEEOL SB COZZEEESE SR NOOO aoa reaannonwta an nnnn NNN NN AY a A & 2 3 2 oo > a : & = bad t+ = oO ~ N UUUUUUUUUUU Oo A Rg2e GRRE oO c mc [] oa me [] za ea [] 8u1SZHO/108 ra } sa ] 90 rj 2a 7] ov 44 43 42 41 40 39 38 37 36 35 34 |) N Ee eg 592%,%2 oO COZZERRESESR HOHOA nono 9XYRSRVeneesee ) g ~ N g 2 q 2 oO Oo Nm @ = E < bat x o o UUUUUUUUUUU aa Q a = gg2age Rez * * xr [J Nias 7} 00 1a rj 20 ] eq [_] SULSZHO/108 va me ~} 9d [4d r] ov Am79C30A/32A Data Sheetal AMD ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. AM79C30A/32A Cc r o- TT - L_ OPTIONAL PROCESSING Blank = Standard Processing TEMPERATURE RANGE C = Commercial (0C to +70C) PACKAGE TYPE J = 44-pin Plastic Leaded Chip Carrier (PL 044) V = 44-pin Thin Plastic Quad Flat Pack (PQT 044) SPEED OPTION Not Applicable Valid Combinations AM79C30A Jc, ve AM79C32A Jc, VC DEVICE NAME/DESCRIPTION Am79C30A/32A Digital Subscriber Controlier (DSC) device ISDN Data Controller (IDC) device Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations, and to check on newly released combinations. Am79C30A/32A Data SheetPIN DESCRIPTION* Line Interface Unit (LIU) HSW Hook-Switch (Input) The HSW signal indicates if the hook-switch is on or off hook. This signal may be generated with a mechanical switch wired to ground with a pull-up resistor to Vec Any change in the HSW state causes an interrupt. LIN1, LIN2 Subscriber Line Input (Differential Inputs) The LIN1 and LIN2 inputs interface to the subscriber (S reference point) via an isolation transformer. LIN2 is the positive input; LIN1 is the negative input. These pins are not TTL compatible. LOUT1, LOUT2 Subscriber Line Output (Differential Outputs) The LOUT1 and LOUT2 line driver output signals inter- face to the subscriber line at the S reference point via an isolation transformer and resistors. LOUT2 is the positive S-interface driver (sources current during a High mark), and LOUT1 is the negative S-interface driver (sources current during Low mark}. For multi- point applications, all TEs must maintain the same polarity on the S Interface. These pins are not TTL compatible. Main Audio Processor (MAP) All MAP pins are analog, and therefore are not TTL compatible. AINA, AINB Analog (Inputs) These analog inputs allow for two separate analog (au- dio) inputs to the transmit path of the codec/filter. Input signals on either of these pins must be referenced to AREF. AREF Analog Reference (Output) This is a nominal 2.25-V reference voltage output for biasing the analog inputs. When the MAP is disabled, this pin is high impedance. CAP1, CAP2 Capacitor/Resistor (CAP1, Input; CAP2, Output) An external resistor and capacitor are connected in series between these pins. These components are needed for the integrator in the Analog-to-Digital Converter (ADC). Note * Alfsignal levels are TTL compatible unless otherwise stated. AMD ct EAR1, EAR2 Earpiece Intertace (Differential Outputs) EAR1 and EAR2 are the outputs from the receive path of the codec/filter. These differential outputs can directly drive a minimum load of 540 ohms. LS1,L$2 Loudspeaker Interface (Differential Outputs) LS1 and LS2 are push-pull outputs which can directly drive a minimum load of 40 ohms. Microprocessor interface (MPI) A2-AG Address Line (inputs) A2, Al, and AO signals select source and destination registers for read and write operations on the data bus. co Chip Select (Input) TS must be Low to read or write to the AM79C30A/32A. Data transfer occurs over the bidirectional data lines (D7-D0). D7-DO Data Bus (Bidirectional with High-Impedance State) The eight bidirectional data bus lines are used to exchange information with the microprocessor. DO isthe least significant bit (LSB) and D7 is the most significant bit (MSB). A High on the data bus line corresponds to a logic 1, and Low corresponds to a logic 0. These lines act as inputs when both WR and CS are active and as outputs when both RD and CS are active. When CS is inactive or both RD and WR are inactive, the D7D0 pins are in a high-impedance state. INT Interrupt (Output) An active Low output on the INT pin informs the external microprocessor that the Am79C30A/32A needs inter- rupt service. INT is updated once every 125 ps. The INT pin remains active until the Interrupt Register (IR) is read or the Am79C30A/32A is reset. RESET Reset (input) Reset is an active High signal which causes the Am79C30A/32A to immediately terminate its present activity and initialize to the reset condition. When reset returns Low, the Am79C30A/32A enters the Idle mode. The MCLK output remains active while RESET is held High. Am79C30A/32A Data Sheet 7il AMD RD Read (Input) The active Low read signal is conditioned by CS and in- dicates that internal information is to be transferred onto the data bus. A number of internal registers are user ac- cessible. The contents of the accessed register are transferred onto the data bus after the High to Low tran- sition of the RD input. WR Write (Input) The active Low write signal is conditioned by CS and in- dicates that external information on the data bus is to be transferred to an internal register. The contents of the data bus are loaded on the Low to High transition of the WR input. Oscillator (OSC) MCLK Master Clock (Output) The MCLK output is available for use as the system clock for the microprocessor, MCLK is derived from the 12.288-MHz crystal via a programmable divider in the Am79C30A4/32A which provides the following MCLK output frequencies: 12.288, 6.144, 4.096, 3.072, 1.536, 0.768, and 0.384 MHz. XTAL1, XTAL2 External Crystal (Output, Input) XTAL1 and XTAL2 are connected to an external parallel resonant crystal for the on-chip oscillator, XTAL2 can also be connected to an external source instead of a crystal, in which case XTAL1 should be left discon- nected. The frequency must be 12.288 MHz, + 80 ppm. Peripheral Port (PP) SBIN Serial Data (Input/Output) When the Peripheral Port is programmed to SBP mode, SBIN operates as an input for serial data. When the Pe- ripheral Portis programmed to |OM-2 mode, SBIN func- tions as the data input except in the special case of IOM-2 Slave mode, when it becomes an open-drain output during part or all of the IOM-2 frame, or when deactivated. SBOUT Serial Data (Input/Output) When the Peripheral Port is programmed to SBP mode, SBOUT operates as an output for serial data. When the Peripheral Port is programmed to {OM-2 mode, SBOUT functions as the data output except in the special case of IOM-2 Slave mode when it becomes an input during part or all of the IOM-2 frame. SCLK Serial Data Clock (Input/Output) When the PP is programmed to SBP mode, SCLK out- puts a 192-kHz data clock, which may be inverted under software control. When the PP is programmed to IOM-2 Master mode, SCLK outputs a 1.536-MHz 2X data clock. In IOM-2 Slave mode, SCLK functions as the clock input. The SCLK pin defaults to a high-impedance state upon reset, but becomes active after any MUX connection is made or if the PP is programmed to |OM-2 Master mode. SFS Serial Frame Sync (Input/Output) In SBP mode, SFS outputs an 8-kHz frame synchro- nization signai. SFS is an output in |OM-2 Master mode, and an input in IOM-2 Slave mode. As an output, SFS is active for 8-bit periods. The SFS pin defaults to a high- impedance state upon reset, but becomes active after any MUX connection is made or if the PP is programmed to IOM-2 Master mode. For SBP mode, the active signal state is Low during Idle and 8 kHz in Active Data Only and Active Voice and Data modes. BCL/CH2STRB Bit Clock/SBP Channel 2 Strobe (Output, Three-state) (present only in PLCC package) In SBP mode, this pin provides a strobe during the 8-bit times of the second 64-kbit/s data channel. In IOM-2 Master mode, this pin provides a 768-kHz bit clock to aid in the connection of non-IOM-2 devices to the port. In 1OM-2 Slave mode, this pin is high-impedance. Power Supply Pins PLCC P. AVcc +5-V analog power supply, +5% (PLCC only) AVss | Analog ground (PLCC only) DVss__ Digital ground (PLCC only) DVcc -+5-V digital power supply, +5% (PLCC only) DIP Packages Voc +5-V power supply, 5% (DIP only) Vss Ground (DIP only) Note: For best performance, decoupling capacitors should be installed between Vcc and Vss as close to the chip as pos- sible. Do not use separate supplies for analog and digital pow- er and ground connections. 8 Am79C30A/32A Data SheetOPERATIONAL DESCRIPTION Overview of Power Modes The minimization of power consumption is a key factor in the design of Terminal Equipment for the ISDN, and the DSC/IDC circuit employs two basic approaches to power management: 1. The power consumption of the DSC/IDC circuit itself is managed by using four basic power modes which allow unused functional blocks to be disabled. The INIT register may be programmed to select Active Voice and Data, Active Data Only, Idle, or Power- Down mode, depending upon which DSC/IDC device resources are required at the time. 2. The power consumption of the controlling micro- processor system may be conirolled by driving the processor clock with the DSC/IDC circuit MCLK out- put. A wide range of MCLK operating frequencies may be selected, and a special Clock Speed-Up function is provided which increases the speed of MCLK upon the occurrence of a key event, without processor intervention. Control of MCLK frequency and Clock Speed-up is accomplished by program- ming the INIT and INIT2 registers, as described later. Active Voice and Data Mode in Active Voice and Data mode ail functional blocks of the DSCADC circuit are available. Device registers may be accessed through the MPI, the LIU and DLC are available, the OSC is running, the Peripheral Port is available, MUX connections may be made, the Second- ary Tone Ringer may be activated. and the MAP is op- erational (DSC circuit only). Active Data Only Mode Active Data Only mode is similar to Active Voice and Data mode, except that the MAP (DSC circuit only) is disabled to reduce system power consumption. This in- creases the amount of power available for the Second- ary Tone Ringer or microprocessor system during the phases of call setup and teardown, or during a data-only telephone call. Idle Mode Idle mode is the RESET default mode of DSC/IDC circuit operation, and represents an operational state in which power consumption is reduced, yet the micro-pro- cessor system is operational to program DSC/IDC cir- cuit registers or perform other required background tasks. Idle mode may also be entered by appropriate programming of the INIT register. In Idle mode, the MCLK output is available to drive the microprocessor system, the MPI is available for pro- gramming of DSC/IDC registers, and the LIU is avail- able to initiate or respond to S/T interface activity. The HSW hookswitch interrupt is also available in Idle mode. AMD at idle mode reduces DSC/IDC circuit power consumption by disabling the MUX, DLC, and MAP functional blocks. The Peripheral Port is also disabled, except that an |OM-2 activation request interrupt is possible, and the SFS and SCLK outputs may still be activated. The SFS and SCLK outputs are high impedance upon RESET, but become active after any MUX connection is pro- grammed. The DLC read-only registers are cleared when the DSC/IDC circuit enters the Idle mode. Power-Down Mode Power-Down mode consumes the least power of all the DSC/IDC power options, and differs from Idle mode in that all clocks, including the XTAL oscillator, are stopped. Most functional blocks are disabled, except for those required to recognize key external events that will force the DSC/IDC circuit to return to Idle mode. The Power-Down mode is not available unless the Power-Down Enable bit is set in the INIT2 register; see the INIT2 register description for further details. Entering the Power-Down Mode The Power-Down mode is entered by appropriate pro- gramming of the INIT and INIT2 registers. Selection of the Power-Down mode causes the DSC/IDC circuit to begin an internal countdown of at least 250 MCLK cycles after which the MCLK and XTAL1 outputs are both stopped and held High, and the XTAL2 input will be disregarded. The purpose of this count- down cycle is to allow the microprocessor time for housekeeping operations before its clock is stopped. If an interrupt causes the DSC INT pin to go Low during the countdown, the Power-Down mode bits in the INIT register will be reset and the countdown will be canceled. If the LIU is enabled and in any state other than F3 at the end of the countdown, MCLK is stopped but the oscilla- tor continues to run. This allows the LIU to identify the incoming signal and either (1) generate an interrupt and force the DSC/IDC circuit to Idle mode when activation is complete, or (2) move to the F3 state and stop the oscillator once the line goes idle. Exiting the Power-Down Mode The DSC/IDC circuit will exit the Power-Down mode and enter the Idle mode if any of the following events occur: The DSC/IDC circuit receives a hardware reset via the RESET pin. The CS and WR pins are both pulled Low at the same time, as would occur during a normal write operation from the microprocessor to the DSC circuit. No data will be transferred by this operation. = The HSW hookswitch pin changes state, and the hookswitch interrupt is enabled. Am79C30A/32A Data Sheet 9a4 amo = The LIU receiver is enabled, detects an incoming sig- nal on the S/T Interface, and achieves activation as indicated by a transition to state F7. Both the INT pin and the F7 transition interrupt must be enabled for Power-Down mode to be exited. If the LIU is enabled, it may restart the oscillator so that it can identify the activity on the interface. If the activity is determined to be noise, the LIU will stop the oscillator and continue to monitor the line without an interrupt or returning to Idie mode. The |OM-2 Interface is enabled as a clock master and the SBIN input pin goes Low. This indicates that a slave device wants to activate the IOM-2 Interface and communicate with the DSC circuit. Both the INT pin and the IOM-2 timing request interrupts must be enabled for Power-Down made to be exited. = The IOM-2 Interface is enabled as a clock slave and the SCLK input pin goes High. This indicates that the master device is activating the 1OM-2 Interface and the DSC circuit must wake up in order to monitor the data. Both the INT pin and the IOM-2 timing re- quest interrupts must be enabled for Power-Down mode to be exited. Ifthe DSCADC circuit is awakened by any condition oth- er than RESET, the MCLK output will be restored to its previously programmed frequency, and will not gener- ate any shortened or spurious output cycles. If the DSC/ IDC circuit is revived by RESET, MCLK will default to its normal 6.144-MHz rate. The DSC/IDC circuit provides a minimum of two MCLK cycles prior to activating the in- terrupt pin when exiting Power-Down mode. MCLK Frequency Control The MCLK frequency selection bits in the INIT register are unchanged from Revision D. However, additional MCLK frequencies are available by programming bits in the INIT2 register. No shortened or spurious clock pulses that might disrupt the external microprocessor will result when the MCLK frequency is changed. In order to reduce the probability of errant software dis- rupting system operation, the INIT2 register requires two consecutive writes before the value will be entered into the register. Note that there will be no MCLK count- down as is the case for entering Power-Down mode if INIT2 is programmed to cause MCLK to STOP, and there will be no shortened or spurious MCLK pulses. MCLK Clock Speed-up Function A programmable automatic MCLK speed-up option is provided that will force a hardware reset of INIT2 bits 3-0, which will cause the MCLK frequency to be re- stored to the vaiue programmed in the INIT register. There are two events that will trigger the clock speed-up function: 1. The DLC receive FIFO threshold has been reached; or. 2. a second packet begins to be received while data from a prior packet is still in the receive FIFO. The second packet case requires provision of an inter- rupt; see the DLC register section for further informa- tion. The clock speed-up function allows the user to program a very slow MCLK frequency using INIT2 when D-channel activity is minimal. If a burst of activity is seen on the D channel and it exceeds the programmed threshold of the receive FIFO or threatens to overrun the receive FIFO status buffers, MCLK will instantly toggle back to the higher frequency programmed in the INIT register. This eliminates the latency incurred if an inter- rupt has to be serviced to change the clock speed, and allows the overall system power to be reduced during typical voice connections. Note that automatic clock speed-up will not function unless at least one of the associated interrupts are enabled sa the processor can be informed that the clock speed has been altered. Global Register Functions INIT Register (INIT) default = OOH Address = Indirect 21 Hex, Read/Write Table 1. INIT Register g = Function Idle mode Active Voice and Data mode Active Data Only mode Power-Down mode INT output enabled INT output disabled MCLK frequency = 6.144 MHz MCLK frequency = 12.288 MHz MCLK frequency = 3,072 MHz MCLK frequency = 6.144 MHz MCLK frequency = 4.096 MHz MCLK frequency = 6.144 MHz MCLK frequency = 6.144 MHz MCLK frequency = 6.144 MHz DLC receiver abort disabled DLC receiver abort enabled DLC transmitter abort disabled DLC transmitter abort enabted oor Ft OO KKK KK Ki OS - Oo KK KKK KK KM KK RK KK KK KIN x xX - O xX KX KK KK KK KK KK KK OD x KX - Or Fe Be He OO OOK KKK KK x ** *- KX +- oO fF oO se OH OK KK KK KI Ww x KK KM RK RK KK KK KK Ht OK KK KN x < KM KK RM KK KK KK KFA FO Ol ~~ eK RK RK mR KK KOK OK KB OH OY 8 x x KK 10 Am79C30A/32A Data SheetINIT2 Register (INIT2) default = 00H Address = Indirect 20 Hex, Read/Write A special write procedure must be followed in order to modify the contents of the INIT2 Register, since the INIT2 Register includes control bits which could result in the stopping of the microprocessor clock. This prace- dure greatly reduces the probability of errant software disabling the system, and is described as follows: AMD cl RESET Operation The Am79C30A/32A can be reset by driving the RESET pin High. When power is first supplied to the DSC/IDC circuit, a reset must be performed. This initializes the DSC/IDC circuit to its default condition as defined in Table 3. Table 3. Reset Pin Conditions 1. Write the INIT2 address to the Command Register. 2. Write to the Data Register (INIT2 is not yet updated). Pin Name State Following RESET 3. Write the INIT2 address to the Command Register. D7-Do High Impedance 4. Write to the Data Register (INIT2 is updated). MCLK 6.144 MHz The writes must take place without any intervening indi- INT Logical 1 rect accesses to the DSC/IDC circuit. SBOUT High Impedance SFS High Impedance Table 2. INIT2 Register SCLK High Impedance LS1, LS2 High Impedance Bit EAR1 High Impedance 7 6 5 4 3 2 1 O|Function EAR2 High Impedance 0 0 X X X X X XI} Reserved, must be written to 0; AREF High Impedance READs are undefined LOUTI High Impedance 00 OX KKK lee NT Rogitrrt nats | (COUT? Fgh Impedance DSCAIDC circuit into Idie mode 0 0 1X X X X X] Power-Down enabled; writing 11 to the INIT Register will put the DSC/IDC circuit into Power- Dawn mode 0 0 X O X X X Xj Muttiframe Interrupt filter disabled 00% 1X X X X|Multiframe Interrupt filter en- abled (see LIU section for de- tailed description) 0 0 X X X X X XI] Clock speed-up option disabled 0 X X O X X X}Clock speed-up option enabled; if set, this register bit will be cleared when the DLC FIFO re- ceive threshold or secand pack- et received interrupt is triggered 0 0 X X 1:0 O OF MCLK frequency determined by INIT Register 1 | MCLK frequency is 1.536 MHz MCLK frequency is 768 kHz MCLK frequency is 384 kHz MCLK stopped in High state Reserved o-oo + 2 Reserved o0oo0UCUOWCcUclUCNUUCUCUUUCUCO oo 0O0090~UdMmhlhlUmw x KKK KOK x KK KK RK OK x <x KK KK OK - = ape st OO 8 - = 00 = + Oo Reserved Receive and Transmit Abort Commands The microprocessor has the option via INIT Register bits 6 and 7 to abort the receive and transmit D-channel packets. When the microprocessor sets one of these bits, the Am79C30A/32A aborts the respective opera- tion. The frame abort sequence is defined in greater detail later. (See the Data Link Controller section on page 38.} Interrupt Handling The Am79C30A/32A generates either no interrupt or only one interrupt every 125 us. Once asserted, INT remains active until the microprocessor responds by interrogating the Am79C30A/32As Interrupt Register (IR) (see Table 4). Reading the IR in response to an acti- vated INT pin deactivates the INT pin and clears the IR. lf an event causing an interrupt occurs while the IR is being read by the microprocessor, the effect of the event is held until the microprocessor has completed its read cycle. A reset clears all conditions causing interrupts. Bits 0, 1. and 4 of the IR, if set, advise the microproces- sor that the respective buffer is ready for reading or writing. If bit 0 is set due to an empty buffer, the D-channe! Transmit buffer must be serviced within 375 us. If bit 1 is set and the D-channel Receive buffer is full, the buffer must be serviced within 425 us. This is to prevent erroneous data transfers causing transmitter underrun and receiver overrun errors. If bit 4 is set then Am79C30A/32A Data Sheet 1at AMD the Bb or Bc buffers must be accessed within 122.4 us. This is to prevent erroneous data transfers. Only one interrupt is used to signal accessibility for both B chan- nels of the S Interface. Since the data transfer must occur synchronously to the S Interface, any data access to either Bb or Be or both must be made within the 122.4 us limit. Note that even though only a single interrupt is issued, either or both S-interface B channels must be serviced. IR bits 2, 3. 5, 6, and 7, if set, indicate that a bit has been set in the associated status or error register. All of the interrupts generated by the Am79C30A/32A can be individually disabled. tn the case of IR bit 7, the interrupt can also be masked by setting PPIER bit 7 to 0. DMR1, DMR2, DMR3, LMR2, MCR4, and MF control the mask conditions that affect the INT pin. The INT pin is activated only by interrupts that are not disabled. The Interrupt Register reflects the status of enabled inter- rupts. The INT pin canbe disabled by setting INIT Regis- ter bit 2 to a logical 1. The Am79C30A/32A has facilities that allow the micro- processor to read the status registers (status update is inhibited during status read) or the IR at any time during functional operation. 12 Am79C30A/32A Data SheetTable 4. Format of the Interrupt Register (IR), Read Only AMD ot Bit | Interrupt Generated/Action Required interrupt Mask 0 D-channel transmit threshold interrupt/oad D-channel Transmit buffer DMR 1 bit 0 1 D-channel receive threshold interrupt/read D-channel Receive buffer DMA 1 bit 1 2 D-channel status interrupt/read DSR1 Source Cause DSR1 bit 0 Valid Address (VA) or End of Address (EQOA) DMR3 bit 0 DSR1 bit 4 When a closing flag is received or a receive error occurs DMR1 bit 3 DSA1 bit 6 When a closing flag is transmitted DMR3 bit 1 3 D-channel error interrupt/read DER and DSR2 bit 2 Source Cause DER bit 0 Current received packet has been aborted DMR2 bit 0 DER bit 1 Non-integer number of bytes received DMR2 bit 1 DER bit 2 Collision abort detected DMR2 bit 2 DER bit 3 FCS error DMR2 bit 3 DER bit 4 Overflow error DMR2 bit 4 DER bit 5 Underflow error DMR2 bit 5 DER bit 6 Overrun error DMR2 bit 6 DER bit 7 Underrun error DMR2 bit 7 DSR2 bit 2 Receive packet lost DMR3 bit 6 4 Bb or Bc byte available or buffer empty interrupt/read or write Bb or Bc buffers MCR4 bit 3 5 LIU status interrupt/read LSR Source Cause LSA bit 3 Change of state to F3 LMR? bit 3 LSR bit 4 Change of state from/to F7 LMR2 bit 6 LSR bit 5 Change of state fromAo F8 LMR2 bit 4 LSR bit 7 HSW change of state LMR2 bit 5 6 D-channel status interrupt/read DSR2 Source Cause DSR2 bit 0 Last byte of received packet DMR3 bit 2 DSR2 bit 1 Receive byte available DMR3 bit 3 DSR2 bit 3 Last byte transmitted DMR3 bit 4 DSR2 bit 4 Transmit buffer available DMR3 bit 5 DSR2 bit 7 Start of second packet EFCR bit 1 7 Multiframe or PP interrupt/read MFSB and PPSR Source Cause MFSB bit 5 S-data available MF bit 1 MFSB bit 6 Q-bit buffer empty MF bit 2 MFSB bit 7 Multiframe change of state {in/out of sync) MF bit 3 PPSR bit 0 Monitor receive, data available PPIER bit 0 PPSR bit 1 Monitor transmit, buffer available PPIER bit 1 PPSR bit 2 Monitor EOM received PPIER bit 2 PPSR bit 3 Monitor abort received PPIER bit 3 PPSR bit 4 C/| channel 0, data change PPIER bit 4 PPSR bit 5 C/l channel 1, data change PPIER bit 5 PPSR bit 6 1OM-2 timing request PPIER bit 6 Am79C30A/32A Data Sheet 13cl AMD FUNCTIONAL DESCRIPTION Microprocessor Interface (MPI) The Am79C30A/32A can be connected to any general purpose 8-bit microprocessor via the MPI. The MCLK from the Am79C30A/32A can be used as the clock for the microprocessor. The MP1 is an interrupt-driven inter- face containing all the circuitry necessary for access to the internal programmable registers, status registers, coefficient RAM, and transmit/receive buffers. MPI External Interface External connections to the MPI are shown in Table 5. Table 5. MPI External Interface Direct Registers Access to the Direct Registers of the Am79C30A/32A is controlled by the state of the CS, RD, WR, A2, At, and AQ input pins, as defined below by Table 6. Indirect Registers To read from or write to any of the Indirect Registers, an indirect address command is first written to the Com- mand Register (CR). One or more data bytes may then be transferred to or from the selected register through the Data Register (DR). Registers within certain groups can be accessed quickly by using internal circuitry which automatically incre- ments the indirect value. In Table 7, the bytes trans- ferred numbers are the number of bytes which are read Name Direction Function or written to the DR after the CR has been loaded. D7-DO Bidirectional Data Bus Whenever the CR is loaded, any previous commands A2-A0 Inputs Address Line are automatically terminated. RD Input Read Enable WR Input Write Enable cs Input Chip Select RESET Input Initialization INT Output Interrupt Table 6. Direct Register Access Guide cs RD WR A2 Al AO | Register(s) Accessed Mode 0 1 0 0 0 Command Register (CR) WwW 0 0 1 0 0 Interrupt Register (IR) R 0 1 0 0 0 1 Data Register (DR) Ww 0 0 1 0 0 1 Data Register (DR} R 0 0 1 0 1 0 D-channel Status Register 1 (DSR1) R 0 0 1 0 1 1 D-channel Error Register (DER) (2-byte FIFO) R 0 1 0 1 0 0 D-channel Transmit buffer (DCTB) (8- or 16-byte FIFO) Ww 0 0 1 1 0 0 D-channel Receive buffer (DCRB) (8- or 32-byte FIFO) R 0 1 0 1 0 1 Bb-channel Transmit buffer (BBTB) WwW 0 0 1 1 0 1 Bb-channel Receive buffer (BBRB) R 0 1 0 1 1 0 Be-channel Transmit buffer (BCTB) WwW 0 0) 4 1 1 0 Be-channel Receive buffer (BCRB) R 0 0 1 1 1 D-channel Status Register 2 (DSR2) R 1 xX X xX xX X No access {X = logical 0 or 1) - Note: The RD and WH signals must never both be Low under normal operating conditions. 14 Am79C304/32A Data SheetTable 7. Indirect Register Access Guide AMD t Operation | Register Register Indirect Mode Address Byte Block Number Name Sequence INIT Initialization Register 1 INIT R/W 21H One byte transferred INIT Initialization Register 2 2 INIT2 R/W 20H One byte transferred LIU LIU Status Register 1 LSR R AIH One byte transferred LIU LIU Priority Register 2 LPR R/W A2H One byte transferred LIU LIU Mode Register 1 3 LMR1 R/W A3H One byte transferred LIU LIU Mode Register 2 4 LMR2 R/w A4H One byte transferred LIU _ 5 Perform 2-4 - ASH LIU Multiframe Register MF RW A6H One byte transferred LIU Multiframe S-bit/Status Register 7 MFSB R A7H One byte transferred LIU Muitiframe Q-bit buffer 8 MFQB Ww A8H One byte transferred MUX MUX Control Register 1 1 MCAR1 RW 41H One byte transferred MUX MUX Control Register 2 2 MCR2 R/W 42H One byte transferred MUX MUX Control Register 3 3 MCR3 RW 43H One byte transferred MUX MUX Control Register 4 4 MCR4 RAW 44H One byte transferred MUX _ 5 Perform 1-4 - 45H MCR1, 2, 3, 4 MAP X tilter Coefficient Register 1 X Coeff. RAW 61H ho LSB, ho MSB...h7 MSB MAP A filter Coefficient Register 2 R Coeff. RAW 62H ho LSB, ho MSB...h7 MSB MAP GX Gain Coefficient Register 3 GX Coeff. R/W 63H LSB, MSB MAP GR Gain Coefficient Register 4 GR Coeff. R/wW 64H LSB, MSB MAP GER Gain Coefficient Register 5 GER Coeff. RiW 65H LSB, MSB MAP Sidetone Gain Coefficient Register 6 STG Coeff. RAV 66H LSB, MSB MAP Frequency Tone Generator Register 1, 2 7 FTGRI1, RW 67H FTGAR1, 2 FTGR2 MAP Amplitude Tone Generator Register 1, 2 8 ATGRi, RAW 68H ATGR1, 2 ATGR2 MAP MAP Mode Register 1 9 MMR1 RAV 69H One byte transferred MAP MAP Mode Register 2 10 MMR2 RAW 6AH One byte transferred MAP _ 11 Perform - 6BH 46 bytes 1-10 loaded 1-10 MAP MAP Mode Register 3 12 MMR3 R/W 6CH One byte transferred Am79C30A/32A Data Sheet 15cl AMD Table 7. Indirect Register Access Guide (continued) Operation | Register Register indirect Mode Address Byte Biock Number Name Sequence MAP Secondary Tone Ringer Amplitude 13 STRA RAV 6DH One byte transferred MAP Secondary Tone Ringer Frequency 14 STRF RAW 6EH One byte transferred MAP Transmit Peak Register 15 PEAKX R 70H One byte transferred MAP Receive Peak Register 16 PEAKR R 71H One byte transferred MAP 17 Perform R 72H One byte _ 15-16 transferred DLC First Received Byte Address Registers 1, 1 FRAR1, 2,3 | RAV 81H FRAR}, 2 2,3 DLC Second Received Byte Address Registers 2 SRAR1, 2,3 | AAV 82H SRAR1, 2 1,2,3 DLC Transmit Address Register 3 TAR RAV 83H LSB, MSB OLC D-channel Receive Byte Limit Register 4 DRLR RAN 84H LSB, MSB DLC D-channel Transmit Byte Count Register 5 DTCR RAV 85H LSB, MSB DLC D-channel Mode Register 4 6 DMR1 RAW 86H One byte transferred DLC D-channel Mode Register 2 7 DMR2 RAW 87H One byte transferred DLC 8 Perform 1-7 - 88H 4 bytes _ loaded 1-7 DLG D-channel Receive Byte Count Register DRCR R 89H LSB, MSB DLC Random Number Generator Register 10 RNGR1 RAV 8AH One byte (LSB) transferred DLC Random Number Generator Register 11 RNGR2 RAV 8BH One byte (MSB) transferred DLC First Received Byte Address Register 4 12 FRAR4 RAV 8CH One byte transferred DLC Second Received Byte Address Register 4 13 SRAR4 RAV 8DH One byte transferred DLC D-channel Mode Register 3 14 DMR3 RAV 8EH One byte transferred OLC D-channel Mode Register 4 15 DMR4 RAV 8FH One byte transferred DLC 16 Pertorm - 90H FRARA4, 12-15 SRAR4, _ DMR3, DMR4 DLC Address Status Register 17 ASR R 91H One byte transferred DLC Extended FIFO Control Register 18 EFCR RAV 92H One byte transferred PP Peripheral Port Control Register 1 1 PPCR1 RAV COH One byte transferred PP Peripheral Port Status Register 2 PPSR R C1H One byte transferred PP Peripheral Port Interrupt Enable Register 3 PPIER RAV C2H One byte transferred PP Monitor Transmit Data Register 4 MTDR Ww C3H One byte transferred 16 Am79C30A/32A Data SheetTable 7. Indirect Register Access Guide (continued) AMD al Operation | Register Register Indirect Mode Address Byte Block Number Name Sequence PP Monitor Receive Data Register 5 MRDR R C3H One byte transferred PP C/l Transmit Data Register 0 6 CITDRO WwW C4H One byte transferred PP C/l Receive Data Register 0 7 CIRDRO R C4H One byte transferred PP C/I Transmit Data Register 1 8 CITDR1 Ww C5H One byte transferred PP C/l Receive Data Register 1 9 CIRDR1 R C5H One byte transferred PP Peripheral Port Control Register 2 10 PPCGR2 RAW C8H One byte transferred PP Peripheral Port Control Register 3 11 PPCR3 RAW CSH One byte transferred Line Interface Unit (LIU) The LIU connects to the four-wire S Interface through a pair of isolation transformers, one for the transmit and one for the receive direction, as shown in Figure 1. The receiver section of the LIU consists of a differential receiver, circuitry for bit timing recovery, circuitry for detecting High and Low marks, and a frame recovery circuit for frame synchronization. The receiver converts the received pseudo-ternary coded signals to binary before delivering them to the other blocks of the Am79C30A/32A. It also performs collision detection (E- and D-bit comparison) per the CCITT recommenda- tions so several TEs can be connected to the same S$ Interface. The transmitter consists of a binary to pseudo-ternary encoder and a differential line driver which meets the CCITT recommendations for the S Interface. The Am79C30A/32A can establish multiframe synchro- nization, receive S bits, and transmit Q_ bits synchronized to the received frame. External Interface The LIU can be connected to both point-to-point and point-to-multipoint configurations at the CCITT S refer- ence point. The point-to-point configuration consists of one TE connected to the NT or PABX linecard. The point-to-multipoint configuration can have multiple TEs connected to one NT. Line Code Pseudo-ternary coding is used for both transmitting and receiving over the S Interface. In this type of coding, a binary 1 is represented by a space (zero voltage), anda binary 0 is represented by a High mark or a Low mark. Two consecutive binary Os are represented by alternate marks to reduce DC offset on the line. A mark followed, either immediately or separated by spaces, by a mark of the same polarity, is defined as a code violation. Code violations are used to identify the boundaries of the frame. Note: The DSC defines Any Signal as any frame with at least three marks above receive threshold. Frame Structures In both transmit and receive directions, the bits are grouped into frames of 48 bits each. The frame structure is identical for both point-to-point and point-to-multipoint configurations. Each frame transmitted at 4 kHz con- sists of several groups of bits. Multiframing If muitiframing is enabled, the Am79C30A/32A re- cognizes and establishes multiframe synchronization based on the monitoring of the F, (Q-bit control} and M (M-bit control) bits. The Am79C30A/32A also receives and compiles S bits, and transmits Q bits synchronized to the received frame. Establishment of Multiframe Synchronization When the enable multiframe synchronization bit (bit 0 of the Multiframe Register) is set and the LIU is in either state F6 or F7, the LIU monitors the F, (Q-bit control) and M (M-bit control) bits. When three consecutive multi- frames with the M bits and F, bits set as defined in Table 8 are received, the multiframe synchronized bit (bit 7 of the Multiframe Register) and multiframe change of state bit (bit 7 of the Multiframe S bit/Status buffer) are set. Note that S-bit data is received, compiled, and transferred to the user after attaining synchronization at the start of the next multiframe. S-Bit Reception The default operation of the DSC/IDC circuit is that the LIU will receive and pass multiframe data to the user in 5-bit increments four times per multiframe, regardless of the value of the data. After multiframe synchroniza- tion has been requested and established, the Am79C30A/32A Data Sheet 17Pa AMD microprocessor can read the Multiframe S bit/Status butter (MFSB) once the S-bit available bit (MFSB bit 5) is set. The S-data available bit is set to a logical 1 when the Am79C30A/32A has received five S bits (one S bit per S-interface frame) synchronized to the setting of the FA-bit to a logical 1 and transferred them into the MFSB. Once the S-bit available bit is set, the MFSB must be accessed within 1.25 ms or succeeding S data will be lost. Subsequent to the original definition of the DSC/ IDC circuit, the CCITT has defined a structure for the 20 multiframe bits, which specifies five 4-bit channels. Furthermore, the idle cade for these channels has been defined as 0000. An enhanced mode of multiframe re- ception has been included, which may be enabled by setting INIT2 bit 4 to a 1. This enhanced mode reduces processor overhead by generating an interrupt only upon the reception of a non-zero S-channel word. INIT2 bit 4 willbe automatically cleared by hardware when the five received data bits inthe MFSB are not all Os, as long as MF bit 1 (interrupt enable) is set. This allows subse- quent valid all-zero words to be received. Furthermore. when the first five S bits of the multiframe are loaded into the MFSB, bit 4 of the MF register will be set, which al- lows identification of the position of received words with- in the multiframe. ; Ss [ Line Drivers Binary | to Pseudo-ternary To Frame Coder MUX |. Recovery ' and DLC t ' 4 Decoder |e Slicer t Timing Bi Balanced Recovery [~ Receiver 09893E002 Figure 1. LIU Block Diagram 18 Am79C30A/32A Data SheetAMD cl Table 8. Multiframing Structures Frame Number NT-to-TE NT-to-TE NT-to-TE TE-to-NT Q Control Bit FA M Bit (M) S Bit (S) F, Bit (Q Bit) 1 1 1 Sci ai 2 0 0 $C21 3 0 0 SC31 4 0 0 S041 5 0 0 SC51 6 1 0 SC12 Q2 7 0 0 SC22 8 0 0 SC32 9 0 0 SC42 10 0 0 SC52 aa} 1 0 $013 Q3 12 0 0 $C23 13 0 0 $C33 14 0 0 $043 15 0 0 SC53 16 1 0 SC14 Q4 17 0 0 $C24 0 18 0 0 SC34 0 19 0 0 $C44 20 0 0 Sc54 1 1 1 Sci Qi 2 0 0 $C21 0 etc. Transmission of Q bits The microprocessor can load the Multiframe Q-bit buffer (MFQB) once the Q-bit buffer empty bit (bit 6 of the Multi- frame S bit/Status buffer) is set. The Q-bit buffer empty bit is set to a logical 1 at reset or when data that has been written to the Multiframe Q-bit buffer is transferred to the LIU. The Q-bit buffer empty bit is cleared to a logical 0 when the Multiframe S-bit/Status buffer is read. After multiframing has been requested and established, the Am79C30A/32A transfers the data written into the Q-bit Register to the LIU, synchronized to the multiframe, irre- spective of the receipt of valid Q-control bits. If the micro- processor does not reload the Q-bit Register for retransmissions, the Q-bit pattern is repeated in the next multiframe. If muitiframing is enabled but multiframe synchroniza- tion is not established, the LIU transmits the value loaded in MFQB bit 4 in all Q bits. The default value of MFQB bit 4 is a logical 0 which satisfies the CCITT rec- ommendations. When synchronization is achieved, the contents of MFQB bits 3 to 0 are transmitted according to Table 8. Loss of Multiframe Synchronization The Am79C30A/32A continuously monitors the F, (Q-bit control) and the M bits to ensure multiframe synchronization. Once muttiframe synchronization is established, multiframe synchronization is lost if three consecutive invalid multiframes are received, or the LIU is no longer in state F6 or F7, or multiframing is disabled. When loss of multiframe synchronization occurs, bit 7 of the Multiframe Register is set to a logical 0, and bit 7 of the Multiframe S bit/Status buffer is set to alogical 1. The Am79C30A/32A also terminates the reception of S bits and transmission of Q bits unti! multiframing synchro- nization is re-established. HSW The hookswitch circuitry on the DSC circuit provides the attached microprocessor with a way of converting an external mechanical hookswitch into a software status condition capable of generating an interrupt. Debounce and glitch rejection are provided internal to the DSC circuit. The logic rejects glitches less than 162 ns and provides debounce of 16 ms. HSW status reporting is disabled after RESET. It is enabled by any of the follow- ing: taking the device out of Idle mode, a write to a MUX Control Register (MCR3-MCR1), or unmasking the HSW interrupt. Am79C30A/32A Data Sheet 19eA amo LIU Registers The LIU contains the registers shown in Table 9. Table 9. LIU Registers Registers No./Registers | Mnemonic LIU Status Register 1 LSR LIU Priority Register 1 LPR LIU Mode Registers 2 LMR1, LMR2 Multiframe Register 1 MF Multiframe S-bit/ 1 MFSB Status Register Multiframe Q-bit buffer 1 MFQB LIU Status Register (LSR), Read Only Address = Indirect A1H The LSR format is shown in Table 10. Table 10. LIU Status Register Generates Interrupt Bit |Logicai1 0-2 | Binary values 000 through No 110 represent the LIU activation circuitry's current state (F2 through F8, respectively) bit 2 is MSB Change of state to F3 Ht LMR2 bit 3 = 4 Change of state from/to F7_| If LMR2 bit 6 = 1 Change of state from/to F8s | If LMR2 bit 4 = 1 HSW state No N OO F&F WwW HSW change of state If LMR2 bit 5 = 1 When the microprocessor reads the LSR, bits 3, 4, 5, and 7 are cleared. The other bits retain the current sta- tus of the LIU. bits 0 to 2 are defined such that state F2 (see CCITT 1.430 state matrix tables) is coded as 0. F3 as 1, F4 as 2, and soon, where bit 0 is the LSB. The LIU interrupts the microprocessor via bit 4 of the LSR when activation has been achieved (that is, when the LIU moves to state F7 upon receipt of INFO 4). During reset the LSR is 0. Even though the LIU Status Register (LSR) is read-only, no default value upon power-up is given due to the uncertain state of bit 6 (Hookswitch State). Following RESET, the LIU State is F2 and the HSW bit reflects the HSW pin, producing a power-up value of either OOH or 40H. LIU D-Channel! Priority Register (LPR), Read/Write The LPR contains the priority level for D-channel ac- cess. its default value after reset is 0. The D-channel access procedure of the Am79C30A/ 32A uses the priority level programmed in the LPR. The priority mechanism defined by the CCITT I-series rec- ommendations is fully implemented if the LPR is pro- grammed via the microprocessor to conform to the priority class of the Layer-2 frame to be transmitted. The LPR has 16 possible programmable priority levels. The priority levels are numbered 0-15. Priority Level 0 corresponds to counting eight 1s in the echo channel. priority Level 1 corresponds to counting ten 1s in the echo channel, priority Level 2 corresponds to counting twelve 1s, etc. The DSC circuit automatically handles transitions between the programmed priority level n and the associated odd value n + 1. The priority is increm- ented following a successfully transmitted packet. and decremented when the higher count has been satisfied. The LPR format is shown in Table 11. Table 11. LIU Priority Register Bits Description 3,2,1,0 D-channel access priority level bit 0 is LSB 7,6,5,4 Reserved, reads logical 0 20 Am79C30A/32A Data SheetAMD at LIU Mode Register (LMR1), Read/Write Address = Indirect A3H LMR1 is defined in Table 12. Table 12. LIU Mode Register 1 Bit | Logical 1 Logical 0 (default value) 0 Enable B1 transmit Disable B1 transmit i Enable B2 transmit Disable B2 transmit 2 Disable F transmit Enable F transmit 3 Disable F, transmit Enable Fy transmit 4 Activation request No activation request 5 Go from F8 to F3 No transition 6 Enable receiver/transmitter Disable receiver/transmitter 7 Reserved; must be set to logical 0 | Reserved; must be set to logical 0 Noies: The Fand F, bits in LMR 1 (bits 2. and 3) should be enabled during the activation procedure so the Am79C30A/32A can respond with INFO 3. LMR! bit 4 is used to transfer the signals PH-AR and Expiry of Timer from the microprocessor to the LIU (see CCITT |.430 state diagramactivation request). PH-AR is defined as bit 4 being a logical 1 and Expiry of Timer is defined as the transition of bit 4 from a logical 1 to a logical 0. This bit must not be set until the LIU, as reflected in the LSR, is in state F3, F6, or F7 and the receiver has been enabled for a minimum of 250 us. LMA 1 bit 6 is primarily used to disable the receiver when the terminal does not require access to the S Interface signals. This bit is cleared by reset and must be written to logical 1 in order to receive activation from the S Interface, or to request activation. LIU Mode Register 2 (LMR2), Read/Write Address = Indirect A4H LMR2 is used to select the operations found in Table 13. Table 13. LIU Mode Register 2 Bit |Logical1 Logical 0 (Default Value) 0 D-channe! loopback at Am78C30A/32A enable D-channel loopback at Am79C30A/32A disable 1 D-channel loopback at LIU enable D-channel loopback at LIU disable 2 D-channel back-off disable D-channel back-off enable 3 F3 change of state interrupt enable F3 change of state interrupt disable 4 F8 change of state interrupt enable F8 change of state interrupt disable 5 HSW interrupt enable HSW interrupt disable 6 F7 change of state interrupt enable F7 change of state interrupt disable 7 Reserved; must be set to logical 0 Reserved; must be set to logical 0 Am79C30A/32A Data Sheet 21al AMD The three D-channel loopback controls defined in LMR2 bits 0, 1, and 2 are explained below: Bit 0, D-channel loopback at Am79C30A/32A enable: Am79C30A NT/PABX This remote loopback is provided for maintenance purposes from the NTs perspective. The NT transmits D-channel bits to the Am79C30A/32A where they are internally looped (with the Data Link Controller) and transmitted back to the NT. The incoming D-channel data can be accessed by the microprocessor; however, the microprocessor cannot send data on the outgoing D channel. Any difference between the transmitted D-channel bits and the received E-channel bits to/from the Am79C30A/32A (normally detected as an error which halts the transmission) is ignored, thereby allowing the transmission to continue. Bit 1, D-channel loopback at LIU enable: Am79C30A NT/PABX Q This local loopback is provided for local testing. Data on the incoming D channelis ignored. The data trom the mi- croprocessor is processed by the DLC and then looped back to the microprocessor in addition to being output to the S Interface. Bit 2, D-channel back-off disabie: DOS D Am79C30A NT/PABX > This loopback is provided for maintenance purposes from the TEs perspective. The Am79C30A/32A trans- mits D-channel bits to the NT where they are looped and transmitted back to the Am79C30A/32A in the E chan- nel. The operation is normal except differences between the D and E channels do not halt the transmission. myo amy 4 Multiframe Register (MF), Read/Write Address = Indirect A6H Table 14. Multiframe Register Bit | Logical 1 Logical 0 (Default Value) Enable S-data available interrupt Enable Q-bit buffer empty interrupt Enable Mukiframe change of state interrupt - worm = First subframe 5,6 | Not used, reads logical 0 7 Multiframe synchronized (read only} Disable interrupt Disable interrupt Disable interrupt Not first subframe Not used, reads logical 0 Multiframe not synchronized (read only) 22 Am79C30A/32A Data SheetMultiframe S-bit/Status Buffer (MFSB), Read Only Address = Indirect A7H Table 15. Multiframe S-Bit/Status Buffer Bit | Description Generates Interrupt 1 S2 No 2 $3 No 3 $4 No 4 $5 No 5 S-data available lf MF bit 1 = 1 6 Q-bit buffer empty If MF bit 2 =1 7 Multiframe change of state | If MF bit 3 = 1 The MFSB reset defauit value is 40H. Multiframe Q-bit Buffer (MFQB), Write Only Address = Indirect ASH Table 16. Multiframe Q-Bit Buffer Bit |Description Q1 (default = 1) Q2 (default = 1) Q3 (default = 1) Q4 (default = 1) Q-bit value when multiframing enabled but syn- chronization not achieved (default = 0) 5,6, 7 | Not used bk OM - O&O Multiplexer (MUX) The MUX contains the registers found in Table 17. Table 17. MUX Registers Register No/Registers | Mnemonic MUX Control 4 MCR1, MCR2, Registers MCR3, MCR4 The Multiplexer is used to selectively route 64-Kbit/s full- duplex B channels between the LIU (Line Interface Unit), MAP (Main Audio Processor), MPI (Microproces- sor Interface), and the PP (Peripheral Port). AMD at The logical channels available at the MUX are shown in Figure 2, They are: 1. From/to the LIU channels B1 and B2 2. From/to the MAP channel Ba 3. From/to the MPI channels Bb and Bc 4. From/to the PP channels Bd, Be, and Bf For any specific application, the MUX can be pro- grammed by the microprocessor to route any three B-channel ports to any other three B-channei ports. Programmable bidirectional bit reversal is provided for both of the MP! data channels Bb and Bc. MUX Control Registers 1, 2, and 3 (MCR1, MCR2, and MCR3), Read/Write Addresses = Indirect 41H, 42H, 43H The MUX can support three bidirectional paths. The contents of the MUX Control Registers MCR1, MCR2, and MCR3 direct the flow of data between the eight MUX logical B channels (see Figure 2). These three MCRs are programmed to connect any two B-channel ports to- gether by writing the appropriate channel code into an MCR. These MCRs have the same format, where bits 7-4 indicate port 1 and bits 30 indicate port 2. In each of these three MCR registers, the channel codes found in Table 18 are used for both ports 1 and 2. Table 18. MCR Register Channel Codes Code | Channel 0000 | No connection (default value) 0001 | B1 (LIU) 0010 | B2 (LIU) 0011 Ba (MAP) 0100 | Bb (MPI) 0101 Bc (MPI) 0110 Bd (PP channel 1) o111 Be (PP channel 2) 1000 | Bf (PP channel 3) For example, to connect B1(LIU) with Bb (MPI) and B2 (LIU) with Ba (MAP), the contents of the MCRs would be: Port 1 | Port 2 Register |7 6 5 4 3 2 1 0| Channel Connection MCR1 0001010 0] Bi (LIU) <> Bb (MPI) MCR2 /001000 1 1]B2 (LIU) <> Ba (MAP) MCR3 000000 0 0} Noconnect <= No connect Am79C30A/32A Data Sheet 23ot amo Peripheral Port Bb <__> MPI B-channel MUX Be <____ +> 3B! LIU > 82 Ba MAP 09893E-003 Figure 2. MUX Logical Channels Therefore, in this example, MCR1 provides a data link from the S Interface and MCR2 sets up a voice connec- tion across the S Interface. To loopback a channel. the same channel code is used for port 1 and port 2. For example, to loopback Bi, B2, and Ba, the MCRs would be: Port 1 | Port 2 Register |7 6 5 4 3 2 1 0| Channel Connection MCR1 0001000 1] B1 (LIU) Loopback MCR2 0016000 1 0] B2 (LIU) Loopback MCR3 [0011061 1]8Ba (MAP) Loopback MCR3 has higher priority than MCR2. MCR2 has higher priority than MCR1. If multiple connections are made to the same port, the data from the connecting ports in the highest priority MCR will overwrite the data from the connecting port in the lower priority MCR, for example: Port 1 | Port 2 Register |7 6 5 4 3 2 1 0| Channel Connection MCRI1 00000000] Noconnect MCR2 000101 0 0]B1{LIU) <~> Bb (MPI) MCR3 0100001 1] B2 (LIU) <~> Ba (MAP) The final data transfers are: B1 (LIU) receives Bb (MPI), Ba (MAP) receives Bb (MPI), Bb (MPI) receives Ba (MAP). Therefore, the data transfer from B1(LIU) to Bo(MPI) is lost in the arrangement proposed in MCR2. 24 Am79C30A/32A Data SheetAMD at MUX Control Register 4 (MCR4), Read/Write Address = Indirect 44H The MUX Control Register 4 (MCR4) can prevent interrupt generation by masking the output of IR bit 4. MCR4 has the format shown in Table 19. Table 19. MUX Control Register 4 Bit | Logical 1 Logical 0 (Default Value) 0-2 | Reserved, must be set to logical 0 Reserved, must be set to logical 0 3 Enable Bb- or Bc-channel byte available interrupt (IR Bit 4) Disable interrupt 4 Reverse bit order of Bb (LSB transmitted/received first) No Bb bit reversal (MSB transmitted/received first) 5 Reverse bit order of Bc (LSB transmitted/received first) No Bc bit reversal (MSB transmitted/received first) 6 Reserved, must be set to logical 0 Reserved, must be set to logical 0 7 Reserved, must be set to logical 0 Reserved, must be set to logical 0 Am79C30A/32A Data Sheet 25oF amo Main Audio Processor (MAP) (Am79C30A only) Overview The MAP, as illustrated in Figure 3, implements audio- band analog-to-digital (ADC) and digital-to-analog (DAC) conversions together with a wide variety of audio support functions. Analog interfaces are provided for a handset earpiece, a handset mouthpiece, a micro- phone, and a loudspeaker. A programmable analog preamplifier is included in front of the A/D converter. The codec and filter functions are implemented using digital signal processing (DSP} techniques to provide opera- tional stability and programmable features. There is one programmable digital gain stage in the transmit path and two in the receive path to allow precise signal level control. Sidetone attenuation is programmable, and programmable equalization filters are present in both the receive and transmit paths in order to modify the fre- quency response of either or both paths. Tone genera- tion capability is included to allow generation of ringing signals, DTMF tones, and call progress signals. MAP operation is described in detail in the following sections. Audio Inputs The audio input port consists of two inputs (AINA and AINB) which are selectable, one at a time, by register programming. Signals applied to these inputs must be AC-coupled. Earpiece and Loudspeaker Drivers The earpiece and loudspeaker drivers each consist of amplifiers with differential, low-impedance outputs. The MAP receive path signal may be routed to either of these outputs, or to both outputs simultaneously. Alternatively, the MAP receive path may be routed to the EAR outputs while the Secondary Tone Ringer (STR) is routed to the LS outputs. The EAR drivers can drive loads >130 ohms between the EAR1 and EAR2 pins, while the LS drivers can drive loads >40 ohms between the LS1 and LS2 pins. The maximum capacitive-loading between EAR1 and EAR2 or between LS1 and LS2 is 100 pF. The EAR outputs are high-impedance when the MAP is disabled. The LS outputs are high impedance when both the MAP and the Secondary Tone Ringer are disabled. CAP1 O_-_,, Co__ CAP2 PEAKX AINA e t 4 } Ba channel! Decimators, BPF . . * to AINB oa> | ADC >| . COMPT Mux _ Digital Transmitter AREF "Loopback 1 ween cee e eee e eee e een nnee Anal \ : q Receiver Naiog ' (A) DTMF t Sidetone | ' GEN. ' Sidetone | \ Gain* porters sss scrsssccccced Digital | + Loopback 2 Ba channel DAC |e STR* Ls2 Notes: Minimum _ Default Maximum Step Gx 0 dB** 008 12 dB 0.5 0B GER -10 dB** 0aB 18 dB 0.5 dB GR -12 dB** 00B 0 dB 0.5 dB STG -18dB** -18dB oaB 0.5 dB GA 0 oB odB 24 dB 6.0 dB ASTG -27 dB** ~ -6 dB 1.5 dB * Programmable Interpolators, LPF HH ea {eer (c) Tone* Tone* (B) i. from MUX y | | PEAKR| Ringer Gen. 09893E-004 These registers can also be programmed for infinite attenuation to break the signal path if desired. Figure 3. Main Audio Processor Block Diagram 26 Am79C30A/32A Data SheetProgrammable Analog Preamplifier A programmable analog preamplifier GA is included in front of the A/D converter and is adjustable in 6-dB increments from 0 dB to +24 dB. The existing GX gain stage in the transmit path may be used for finer adjust- ment of transmit gain. This preamplifier eliminates the need for an external operational amplifier when interfac- ing electret-type handsets to the DSC circuit. Analog Sidetone Analog sidetone takes the analog input to the transmit- ter ADC and sums it into the single-ended input of the EAR output buffer. The summing pointis after the output selection switch. The analog sidetone path has pro- grammable attenuation between 6 and27 dB, plus in- finity (off). Default is infinity. Programming is via four bits in the Extended FIFO Control Register, EFCR.63. The programming values are given in Table 20. Table 20. Analog Sidetone 0000 =co 0100 = 22.5 dB 0001 = -27.0 dB 0101 =-21.0 dB 0010 =-25.5 dB 0110 =-19.5 dB 0011 =-24.0 dB 0111 =-18.0 dB 1000 = -16.5 dB 1100 = -10.5 dB 1001 =-15.0 dB 1101 =-9.0 dB 1010 =-13.5 dB 1110 = -7.5 dB 1011 =-12.0 dB 1111 =-6.0 dB Signal Processing Transmitter The transmitter performs a series of operations as described below. 1. An ADC converts the incoming analog signal at a sampling rate of 512 kHz. 2. The Band Pass filter and a series of decimators reject DC and 50- to 60-Hz line frequencies while reducing the sampling rate to 8 kHz. 3. The X filter is an 8-tap user-programmable filter for tuning the microphone. The default is flat with unity gain. 4. The GX filter is a programmable gain filter that allows the user to program a gain of 0 to +12 dB in 0.5-dB steps. The default value is 0 dB. 5. The u-law or A-law digital compression algorithm converts the linear output of the GX filter to p- or A- law code. The default algorithm is u-law code. The MSB (sign bit) is transferred first to (or from) the MUX. AMD ot Receiver The receiver performs a series of operations described as follows: 1. An expander converts the input A- or p-law data to digital linear data. The most significant bit is trans- ferred from the MUX first. The default value is p-law. 2. The GRiilteris a programmable gain filter that allows the user to program a gain of 12 to 0 dB in 0.5-dB steps. The default value of GR is 0 dB. 3. The GER and Sidetone Gain (STG) are program- mable constant multipliers which allow the user to program a gain of 10 to +18 dB in 0.5-dB steps (default value 0 dB) and -18 to O dB in 0.5-dB steps (default value -18 dB) respectively. The GER provides volume control (for the hearing impaired) and should be programmed to 0 dB fornormal opera- tion. The sidetone gain path provides feedback from the transmitter. 4. The R filter is provided to correct for speaker attenu- ation distortion and is a user-programmable filter similar to the X filter in the transmitter. 5. A series of interpolators increases the sampling frequency. 6. A DAC converts the digital signal to the analog audio output signal. PEAK Hold Registers Logic in the form of two microprocessor accessible peak hold registers will be provided to allow for support of a softwarebased speaker phone solution. These regis- ters, one in the transmit path (PEAKX) and one in the re- ceive path (PEAKR), will provide the compressed maximum (peak) absolute value of the data in the path since the register was last read. With appropriate soft- ware, this can be used to implement a hands-free func- tion. Refer to the MAP block diagram for the location of these registers in the processing path. The following assumptions are made: 1. The GX and GR blocks are used as gain/attenuators, without modification to their range or resolution. 2. The data is presented in compressed A-law format, without the alternate bit inversion. The sign bit is not presented. 3. The data extraction point for the transmit path is after the X filter. 4. The data extraction point for the receive path is im- mediately following the expander. Am79C30A/32A Data Sheet 27at AMD 5. The compressed data from the transmit and receive paths is presented using the same compression algorithm. 6. The peak registers are double-buffered and can be read asynchronously to the operation of the DSP register. They are cleared on read. 7. The peak registers default to dont care values when the part is reset. An initial read operation is re- quired to clear the register before using it for the first time. The PEAKX register is at indirect address 70H, while the PEAKR register is at indirect address 71H. Both may be accessed via back-to-back read data register opera- tions by loading the command register with 72H. Tone Generators The MAP contains three tone generators which can be enabled via MAP Mode Register 2, bits 2, 3, and 4. Only one of the three tone generator bits in the register can be set at a time. If more than one bit is set, all three bits are considered set to zero and tone generation is disabled. The tone generators are: DTMF Generator This generator provides tone injection at a sampling rate of 32 kHz into the transmit and sidetone paths (Figure 3, Block A). The DTMF frequencies generated are guaran- teed to +1.2% deviation. Tone Generation This generator provides call progress tones to the re- ceive path, where it is added to the incoming speech (Figure 3, Block B). Tone Ringer This generator provides tone alert signals output through the receive path to the loudspeaker or earpiece (Figure 3, Block C). To program the DTMF tone generators, two frequency values and two amplitude values must be written to the two 8-bit Frequency Tone Generator Registers (FTGR1, FTGR2) and the two 8-bit Amplitude Tone Generator Registers (ATGR1, ATGR2), respectively. The Tone Generator and the Tone Ringer use the fre- quency programmed in FTGR1. The Tone Generator uses the amplitude programmed in ATGR1 while the Tone Ringer uses the amplitude programmed in ATGR2. Common frequency values are listed in Table 22. The FTGR codes to obtain DTMF dialing output fre- quencies are listed in Table 21. Table 21. DTMF Codes FTGR 2 or 1 9BH ABH BFH D3H [- HEX REG VALUE > FREQ > 1209 1336 1477 1633 FTGR 1 or2 5AH 697 1 2 3 A 63H 770 4 5 6 B 6EH 852 7 8 9 Cc 79H 941 * 0 # D 28 Am79C30A/32A Data SheetThe output frequency of the DTMF tone generator approximately equals : DTMF Frequency in Hz = 64000 integer (8192/i)+1 where is the decimal equivalent of value programmed into the FTGR register. This allows the DTMF generator to supply common dual tone call progress signals such as Busy or Dial tones. Table 22. Tone Ringer and Tone Generator Frequency Coefficients Frequency (Hz) Hex Code 2666 AB 2000 81 16000 67 1333 56 1142 4A 7000 41 889 39 800 34 727 2F 667 2B 615 28 571 25 533 23 500 21 471 1F 444 1D 421 1B 400 1A 381 19 364 18 348 17 333 16 320 15 Notes: These coefficients do not apply to the DTMF generator. AMD ol The ATGR registers allow the user to program a gain of 18 dB to 0 dB in 2-dB steps. Example ATGR codes to obtain amplitude gains are listed in Table 23. 0 dB im- plies a level of +3 dBm0. The gain values are rounded off to the nearest 1 dB. Table 23. Amplitude Gain Coefficients Gain (dB) Hex Code -18 37 -16 32 -14 31 -12 27 -10 22 -8 21 -6 20 4 12 -2 11 0 10 Secondary Tone Ringer A Secondary Tone Ringer is included, which is able to ring the phone using the LS outputs while a voice con- versation is in progress on the EAR outputs. The STR is louder than the Tone Generator, and may be used with or without enabling the MAP in order to provide flexible control of system power consumption. The STR is not available if the INIT register is programmed to Idle or Power-Down mode. The amplitude and frequency of the STR square-wave output waveform is programmable via the STRA and STRF registers, respectively. If both the LS outputs from the MAP receive path and the STR are simultaneously enabled, priority is given to the STR connection. The STR is available for both the DSC and IDC circuits. A legal value must be programmed in the STFF register before the STR is enabled. Programmable Gain Coefficients The GER, GR, GX, and Sidetone gain coefficients are each 16 bits in tength. Two consecutive register loca- tions correspond to one gain coefficient. The LSB is transferred first to (or from) the microprocessor. Sample coefficients for the GER filter are listed in Table 24. The gain values are rounded off to the nearest 0.1 dB. Am79C30A/32A Data Sheet 29ol AMD Table 24. GER Gain Coefficients Gain (dB) Hex Code Gain (d Hex Code LSB MSB -10 4.0 31 -9.5 45 44 -9.0 5.0 43 8.5 5.5 33 -8.0 6.0 40 ~7.5 6.5 11 -7.0 7.0 44 -6.5 75 41 6.0 8.0 31 ~5.5 8.5 55 5.0 9.0 10 4.5 9.5 42 -4.0 10.0 41 3.5 10.5 11 -3.0 11.0 60 2.5 11.5 00 -2.0 12.0 42 -1.5 12.5 40 -1.0 13.0 11 -0.5 13.4 22 0.0 14.0 72 0.5 14.5 42 1.0 15.0 21 1.5 15.5 10 2.0 15.9 22 2.5 16.6 an 3.0 16.9 00 3.5 17.5 21 18.0 00 Note: The coefficient 0008 provides an attenuation of infinity when GER gain is enabled. 30 Am79C30A/32A Data SheetAMD al Example coefficients for the GR, GX, and STG filters Table 26. GR Gain Coefficients are listed in Tables 25, 26, and 27. The gain values are rounded off to the nearest 0.1 dB. Gain Hex Code (dB) MSB LSB Table 25. GX Gain Coefficients -11.5 91 cs -11.0 91 B6 Gain Hex Code -10.5 92 12 (dB) MSB LSB ~10.0 91 A4 0.0 08 08 -9.5 92 22 0.5 4c B2 -9.0 92 32 1.0 3D AC -8.5 92 FB 1.5 2A E5 -8.0 92 AA 2.0 25 33 7.5 993 27 2.5 22 22 7.0 93 B3 3.0 21 22 6.5 94 B3 3.5 1F D3 -6.0 oF 91 4.0 12 A2 5.5 9c EA 45 12 1B -5.0 9B F9 5.0 11 3B ~4.5 9A AC 5.5 0B C3 4.0 9A 4A 6.0 10 F2 -3.5 A2 22 6.5 03 BA -3.0 A2 A2 7.0 02 CA -2.5 AG 8D 7.5 02 1D -2.0 AA A3 8.0 01 5A -1.5 B2 42 8.5 01 22 -1.0 BB 52 9.0 01 12 ~-0.5 CB B2 9.5 00 Ec 0.0 08 08 10.0 00 32 10.5 00 21 11.0 00 13 14.5 00 11 12.0 00 OE Am79C30A/32A Data Sheet 31ol AMD Table 27. STG Gain Coefficients Gain Hex Code (dB) MSB LSB -18.0 8B 76 -17.5 8B 44 -17.0 8B 35 -16.5 8B 2A -16.0 8B 24 -15.5 8B 22 -15.0 91 23 -14.5 91 2E -14.0 91 2A -13.5 4 32 -13.0 1 3B -12.5 91 4B -12.0 91 F9 -11.5 91 C5 -11.0 19 B6 -10.5 92 12 -10.0 91 Ad -9.5 92 22 -9.0 92 32 -8.5 92 FB -8.0 92 AA -7.5 93 27 -7.0 93 B3 -6.5 94 B3 -6.0 9F 91 5.5 9c EA ~5.0 9B F9 -4.5 9A AC -4.0 9A 4A -3.5 A2 22 -3.0 A2 A2 2.5 A6 8D -2.0 AA A3 -1.5 B2 42 -1.0 BB 52 -0.5 CB B2 0.0 08 08 Note: The coefficient 9008 provides an attenuation of infinity when GR, GX, and/or STG are enabled. Overflow/Underflow Precautions When Using Programmable Gains Care must be taken so that at any point in the signal pro- cessing path, the combination of gains and fitters and/or tones does not result in a signal that is larger than full scale. Full scale is defined as the digital representation of the maximum analog signal that is allowed into the transmitter or out of the receiver with all filters and gain stages at their default (0 dB) settings (e.g., in A-Law. the transmitter full scale is + 1.25 V, and the receiver full scale is +2.5 V,). Likewise, it is desirable that the peak signal be kept as close to full scale as pos- sible at any pointin the signal processing path in order to minimize digital truncation effects in the A/D, D/A, and MAP DSP. Consider the following example: STG is programmed for infinite attenuation, GR is programmed to 6 dB while GER is programmed to +12 dB, and the R filter is programmed to exhibit a net gain of -6 dB. Assume the analog full scale out of the receiver is + 2.5 Vp, anda full scale PCM code is possible from the MUX. After GR, the equivalent analog signal will be 2.5 / 2 = +1.25 Vp How- ever, after GER the signal will be 1.25.4, or +5 Vp Even though the R filter will have a net gain of 6 dB, the signal will be clipped after GER and distorted for PCM codes between full scale and 6 dB below full scale due to the intermediate result at the output of GER. Be very careful when programming the tone ringers/ generators. For example, if one of the DTMF tones is programmed to 0 dB, a tone is generated that is equiva- lent to a + full scale signal in the transmit path. This means no headroom is left tor the other DTMF tone. Therefore, the DTMF generator should never be pro- grammed to exceed full scale if signal quality is to be maintained. In the receive path, similar caution should be exercised in order to prevent the combination of Tone Generator, Sidetone, GR, and GER from clipping the signal. Extended Programming Ranges Some applications of the DSC will require greater flexi- bility in the programming of the MAP's internal gain and attenuation blocks. For example, applications such as software-based hands-free utilizing the PEAKX and PEAKR registers may need attenuation as well as gain within the MAP transmit path. The preceding gain tables do not specifically detail this capability, but due to the DSP implementation of these gain and filter blocks, the DSC is capable of performance beyond these recom- mended ranges. (GA and ASTG are not implemented in DSP and are limited to their stated range and step size.) Table 28 lists guaranteed ranges, while Table 29 shows the limits by design. 32 Am79C30A/32A Data SheetTable 28. Recommended Ranges Recommended and guaranteed AMD at where each hj Coefficient Register pair has the following format: Table 29. Design Ranges Limits by design GX -84.3 to 14.0 dB plus infinite in 0.1 dB steps over most of the range GER = -24.1 to 24.1 dB plus infinite in 0.1 dB steps over most of the range GR ~84.3 to 14.0 dB plus infinite in 0.1 dB steps over most of the range STG = -84.3 to 14.0 dB plus infinite in 0.1 dB steps over most of the range As an example, in a hands-free application using an electret requiring 24 dB of gain in the transmit path for optimum performance. The typical implementation would use 18 dB of GA and 6 dB of GX gain. The user would then have a programmable range of +6 dB to ~66 dB utilizing GX. Selection of these gain points is of course, application specific, and will depend on the per- formance requirements of the system. Listings of the optimized programming values for vari- ous levels are included in Appendix A. Values listed in the recommended tables are still correct and will per- form as stated. There is no need to convert to the ex- tended values unless greater resolution is required. Programmable Filter Coefficients and Equations The frequency domain transfer function equation for the X and R filters is: hy = he + hyzo! + haze? + hyzm2 + haz} + e278 + gz + haz? where: Z=cos(wT)+i V sin(wT) i= (-l) 1/2 w = frequency of input signal in Hz - 2pi T = sample period in seconds (0.125 ms) hj G = 0,1,...7) = user-defined coefficients. Each hj coefficient is defined by the following equation: hj = A3 (14+A2[1+AL(1+A0)] } Gx 0 to +12 dB plus infinite in 0.5 dB steps Byte 7 654 3 210 GER = -10to +18 dB plus infinite in 0.5 dB steps LSB $1 M1 So Mo GR 12 to 0 dB plus infinite in 0.5 dB steps MSB $3 M3 $2 M2 STG = -18 to 0 dB plus infinite in 0.5 dB steps and Ai=~-1 Si2 Mi, (j=0,1,2.3), The X and R filter coefficients are programmed using a 16-byte transfer with the format shown in Table 30. Table 30. X/R Filter Format Byte Value 0 ho LSB 1 ho MSB 2 h1 LSB 4 h2 LSB 5 h2 MSB 6 h3 LSB 7 h3 MSB 8 h4 LSB 9 h4 MSB 10 h5 LSB 1 h5 MSB 12 h LSB 13 h MSB 14 h7 LSB 15 h7 MSB Note: AmMAP software, which calculates X and A filter coeffi- cients, is available from Advanced Micro Devices. Contact your local AMD Sales Office for more information. Test Facilities Three capabilities are provided for MAP operation verification. MAP Analog Loopback Signals sent in on AINA or AINB may be sent back out to EAR1/EAR2 or LS1/LS2 by looping the MAP path in the MUX. The MUX should be set up for Ba-to-Ba loop- back by writing 33H to MCR1, MCR2, or MCR3. No oth- er MUX connections overriding Ba-to-Ba should be programmed. This test allows the MAP analog and digital to be tested using a local signal source. MAP Digital Loopback 1 This loopback mode connects the interpolator output to the decimator input in place of the ADC output. This mode allows verification from the S Interface or micro- processor that the MAP digital circuitry is functional. Note that the digital patterns received after loopback will not be identical to the transmitted patterns. The D-D gain is approximately 2.5 dB. Am79C30A/32A Data Sheet 331 amp MAP Digital Loopback 2 This loopback mode connects the analog D/A output path to the analog A/D input path, internal to the DSC cir- cuit. The EAR and LS outputs and both AIN inputs will be disabled. This mode allows veritication from the S Interface or microprocessor that the MAP analog and digital circuitry are functional. The digital patterns received after loopback will not be identical to the transmitted patterns. The bits in the MAP mode Register define the enable/ disable options for the various MAP configurations as follows. MAP Registers The MAP contains the programmable registers found in Table 31. Table 31. Map Registers MAP Register Bytes | Mnemonic X-filter Coefficient Register 16 |X R-filter Coefficient Register 16 |R GX-Gain Coefficient Register 2 GX GR-Gain Coefficient Register 2 GR GER-Gain Coefficient Register 2 GER Sidetone-Gain Coefficient Register 2 STGR Frequency Tone Generator 2 FTGR Register Amplitude Tone Generator Register 2 ATGR MAP mode Ragisters (3) 1 MMR Secondary Tone Ringer Amplitude 1 STRA Reg Secondary Tone Ringer Frequency 1 STRF Reg Transmit Peak Register 1 PEAKX Receive Peak Register 1 PEAKR Note: itis necessary to complete any transfers to the multi-byte MAP registers. For instance, a total of 16 bytes must be transferred to update the X filter. Following reset, the MAP registers FTGR, MMR1, MMR2, MMR3, STRA, and STREF all default to 00 hex. All other MAP registers are not affected by reset and must be programmed by the microprocessor before being enabled. When the registers are disabled, or after reset, the MAP will have the response shown in Table 32. Table 32. Default Values Fitter Default Response X filter Disabled (0 dB, Flat) R filter Disabled (0 dB, Flat) GX filter Disabled (0 dB, Gain) | GR filter Disabled (0 dB, Gain) GER filter Disabled (0 dB, Gain) Sidetone gain Disabled (-18 dB, Gain) 34 Am79C30A/32A Data SheetMAP Mode Register 1 (MMR1) Read/Write Address = Indirect 69H Table 33. Map Mode Register 1 AMD al Bit | Logical 1 Logical 0 (Default Value) 0 A-Law p-Law 1 GX coefficient loaded from register GX bypassed; gain = 0 dB 2 GR coefficient loaded from register GR bypassed; gain = 0 dB 3 GER coefficient loaded from register GER bypassed; gain = 0 dB 4 X coefficient loaded from register X bypassed; response = flat 5 R coefficient loaded from register R bypassed; response = flat 6 Sidetone gain coefficient loaded from register STG gain = -18 dB* 7 Digital loopback at MAP enabled Digital loopback at MAP disabled Note: To ramove the sidetone path completely, it is necassary to enable the STG function by setting MMA1 bit 6 to 1, and program the STGR coefficient to 9008 (hex).34 MAP Mode Register 2 (MMR2) Read/Write Address = Indirect 6AH Table 34. Map Mode Register 2 Bit | Logical 1 Logical 0 (Default Mode) 0 AINB selected AINA selected 1 LS1/LS2 selected EAR1/EAR2 selected 2 DTMF enabled DTMF disabled 3 Tone generator enabled Tone generator disabled 4 Tone ringer enabled Tone ringer disabled 5 High pass filter disabled High pass filter enabled 6 ADC auto-zero function disabled ADC auto-zero function enabled 7 Reserved, must be Logical 0 Reserved, must be Logical 0 Note: For most applications, MMFi2 bits and 6 shauid always be written to logical 0. This enables the 50-60 Hz rejection filter and the internal offset cancellation circuits to operate normally. They can both be disabled when system ar test conditions require the trans- mission of DC or low frequency signals. Am79C30A/32A Data Sheet 35al AMD Map Mode Register 3 (MMR3) Read/Write Address Indirect 6CH Table 35. Map Mode Register 3 Bit 7 6 5 4 3 2 1 0 | Function ) X xX X X X X X | Bit 7 Reserved, must be written to 0 0 Q 0 0 xX XK xX X ]0-dB pre-amplifier gain, 1.250-V maximum peak input voltage 0 0 0 1 xX X x X |+6-dB pre-amplifier gain, 0.625-V maximum peak input voltage 0 0 1 0 X X Xx X |+12-dB pre-amplifier gain, 0.312-V maximum peak input voltage 0 Oo 1 1 x X X X |+18-dB pre-amplifier gain, 0.156-V maximum peak input voltage 0 1 0 0 X X xX X | +24-dB pre-amplifier gain, 0.078-V maximum peak input voltage i) 1 0 1 x x xX X | Reserved; undefined 0 1 1 0 x x xX X | Reserved; undefined 0 1 1 1 x Xx X X | Reserved; undefined 0 Xx X Xx 1 X X X | MUTE ON, AINA and AINB inputs disabled 0) Xx x X 0 X X X |MUTE OFF, AINA or AINB enabled 0 xX x x xX 1 x X | Digital Loopback 2 enabled; D/A output looped to A/D input; EAR, LS, and AIN pin disabled 0 x X X xX 0 X X | Digital Loopback 2 disabled 0 X x xX xX xX 1 X | EAR and LS simultaneously enabled 0 Xx X X xX X 0 X |EAR or LS enabled by MMR2 bit 1 0 Xx X X x X Xx 1 | Secondary Tone Ringer enabled 0 xX X X x xX xX 0 | Secondary Tone Ringer disabled Secondary Tone Ringer Amplitude Register (STRA) Read/Write Address = Indirect 6=DH Table 36. Secondary Tone Ringer Amplitude Bit Peak-to-Peak Approximate 7 6 5 4 3 2 1 0 Output Voltage Relative Output Power into 50 ohms o 0 0.0 0 0 06 0 Silent 00001 0 0 0 0 Reserved o 0 41 0 0 0 0 0 Reserved o 0 1 1 0 0 0 0 Reserved o 100 0 0 0 0 Reserved o 1 0 1 0 0 0 90 Reserved o 1 1 0 0 0 06 0 0.22 V -27 dB 0.25 mW o f 1 1 0 0 0 0 0.31 V 24 dB 0.5 mW 1 0 0 0 0 G0 0 0 0.44 V -21 dB 1.0 mW 1 0 0 1 0 0 0 0 0.62 V -18 dB 2.0 mW 1 0 1 0 0 0 0 0 0.88 V -15 dB 4.0 mW 101 4 0 0 0 0 1.25V -12 dB 8.0 mW 1 1 0 060 0 0 0 #90 1.77V -9 dB 16.0 mW 1 #140 1 0 0 0 0 2.50 V -6 dB 31.25 mW 1 114 0 0 0 0 0 3.53 V -3 dB 62.5 mW 1 14147 1 0 0 0 +0 5.00 V 0 dB 125.0 mW xX X X X 0 0 6 O Bits 0-3 Reserved; must be written to 0 36 Am79C30A/32A Data SheetAMD Pe | Secondary Tone Ringer Frequency Register (STRF), Read/Write; Address = Indirect 6EH STRF is a Read/Write register controlling the frequency of the secondary tone ringer. Hex codes 7F and 00 are reserved and should not be used. The coefficients are defined in Table 37. Table 37. Frequencies for Secondary Tone Ringer Counter Frequency Counter Frequency Counter Frequency Counter Frequency Value (Hz) Value (Hz) Value (Hz) Vatue (Hz) 3F Reserved 3B 727.3 D8 369.2 F7 247.4 1F Reserved 9D 716.4 6C 366.4 FB 246.2 OF 42000.0 4E 705.9 36 363.6 FD 244.9 87 9600.0 27 695.7 1B 360.9 7E 243.7 43 8000.0 13 685.7 8D 358.2 BF 242.4 Ai 6857.1 09 676.1 C6 355.6 5F 241.2 DO 6000.0 04 666.7 E3 352.9 oF 240.0 E8 5333.3 82 657.5 Fi 350.4 97 338.8 F4 4800.0 41 648.7 78 347.8 CB 237.6 7A 4363.6 AQ 640.0 3c 345.3 65 236.5 3D 4000.0 50 631.6 9E 342.9 32 295.3 1E 3692.3 A8 623.4 CF 340.4 99 234.2 8F 3428.6 D4 615.4 E7 338.0 cc 233.0 C7 3200.0 6A 607.6 73 335.7 66 231.9 63 3000.0 BS 600.0 39 333.3 B3 230.8 Bi 2823.5 DA 592.6 9C 331.0 59 229.7 58 2666.7 6D 585.4 CE 328.8 AC 228.6 2c 2526.3 B6 578.3 67 326.5 56 9975 16 2400.0 5B 571.4 33 324.3 >B 296.4 0B 2285.7 AD 564.7 19 322.2 15 225.4 05 2181.8 D6 558.1 8c 320.0 8A 324.4 02 2087.0 6B 551.7 46 317.9 C5 293.3 01 2000.0 35 545.5 A3 315.8 62 302 9 80 1920.0 QA 539.3 Dt 313.7 a4 012 40 1846.2 4D 533.3 68 314.7 128 390.2 20 1777.8 AG 527.5 B4 309.7 oc 3192 10 1714.3 D3 521.7 5A 307.7 06 18.2 88 1655.2 69 516.1 2D 305.7 83 172 C4 1600.0 34 510.6 96 303.8 C4 162 E2 1548.4 1A 505.3 4B 301.9 Eo a163 71 1500.0 oD 500.0 25 300.0 70 5143 38 1454.6 86 494.9 12 298.1 Bs 313.3 1c 1411.8 c3 489.8 89 296.3 5C 124 BE 1371.4 E1 484.9 44 294.5 AE 5115 47 1333.3 FO 480.0 A2 292.7 57 5108 23 1297.3 Fa 475.3 54 290.9 AB 509.6 91 1263.2 7c 470.6 28 289.2 5B 308.7 48 1230.8 BE 466.0 94 287.4 AA 5078 Ad 1200.0 DF 461.5 4A 285.7 DS 506.9 D2 1170.7 6F 457.1 AS 284.0 EA 506 0 EQ 1142.9 B7 452.8 52 282.4 Es 508 4 74 1116.3 DB 448.6 AQ 280.7 . 3A 1090.9 ED 444.4 54 279.1 FA 204.3 1D 1066.7 F6 440.4 2A 277.5 70 203.4 OE 1043.5 7B 436.4 95 275.9 3E 202.5 07 1021.3 BD 432.4 CA 274.3 SF 201.7 03 1000.0 5E 428.6 E5 272.7 4F 200.8 81 979.6 AF 424.8 72 271.2 AT 200.0 co 960.0 D7 421.4 BS 269.7 53 199.2 60 941.2 EB 417.4 DC 268.2 29 198.4 30 923.1 75 413.8 EE 266.7 14 197.5 98 905.7 BA 410.3 77 265.2 OA 196.7 4c 888.9 5D 406.8 BB 263.7 85 195.9 26 872.7 2E 403.4 DD 262.3 42 195.1 93 857.1 17 400.0 6E 260.9 21 194.3 49 842.1 8B 396.7 37 259.5 90 193.6 24 827.6 45 393.4 9B 258.1 cs 192.8 92 813.6 22 390.2 cD 256.7 E4 192.0 cg 800.0 1 387.1 E6 255.3 F2 191.2 64 786.9 08 384.0 F3 254.0 F9 190.5 B2 774.2 84 381.0 79 252.6 FC 189.7 Dg 761.9 C2 378.0 BC 251.3 FE 189.0 EC 750.0 61 375.0 DE 250.0 FF 188.2 76 738.5 Bo 372.1 EF 248.7 Am79C30A/32A Data Sheet 37Pa AMD Data Link Controller (DLC) Overview A 16-Kbit/s D-channel is time-muitiplexed within the frame structure of the S Interface. The data carried by the D channel is encoded using the Link Access Proto- col D-channel (LAPD) format shown in Figure 4. The D channel can be used to carry either end-to-end signaling or low-speed packet data. Further information concerning LAPD protocol can be found in the CCITT recommendations. The LIU controls the multiplexing and demultiplexing of the D-channel data between the S Interface and the DLC. The DLC performs processing of Level-1 and partial Level-2 LAPD protocol, including flag detection and generation, zero deletion and insertion, Frame Check Sequence (FCS) processing for error detection, and some addressing capability. High level protocol proces- sing is done by the external microprocessor. The microprocessor may process the address field in the LAPD frame depending on the programmed state of the DLC. The status of the DLC is held in the status registers and relevant interrupts are generated under user program control. In addition to transmit and receive data FIFOs, the DLC contains a 16-bit pseudo-random number generator (RNG) used in the CCITT D-channel address allocation procedure. D-channel Processing Random Number Generator (RNG) The RNG is accessible by the microprocessor and oper- ates in the following manner. On the Low-to-High transition of the reset signal, the RNG is cleared, then started. The RNG stops when the LSB or MSB of the 16-bit counter is read by the micro- processor, or when the MSB is loaded by the micropro- cessor. Writing to the MSB of the counter loads this byte but does not start the RNG. The RNG starts when the LSB of the counter is loaded by the microprocessor. Frame Abort The DLC aborts an incoming D-channel frame when seven contiguous logical 1s are received. When this occurs, an End-of-Receive-Packet interrupt is issued to the processor. DER bit 0 is set to a logical 1 when the last byte of the aborted packet is read from the D-channel Receive buffer. The Receive-Abort interrupt canbe masked by setting DMR2 bit 0 to a logical 0. With the exception of the Packet-Reception-in-Progress bit, no other bits associated with packet reception are up- dated after a receive packet abort. The receive frame can be aborted at any time by setting INIT bit 6 to logical 1. Similarly, the transmit frame can be aborted by setting INIT bit 7 to a logical 1. When the transmit frame is aborted, seven consecutive 1s are transmitted on the $ Interface followed by a logical 0, and DSR1 bit 7 is set to a logical 1. Seven consecutive 1s followed by a 0 will continue to be transmitted as long as INIT bit 7 is setto 1. DSR1 bit 7 willbe set after each sequence of sevencon- secutive 1s followed by 0. Level-2 Frame Structure The D-channel Level-2 frame structure conforms to one of the formats shown in Figure 4. All frames start and end with the flag sequence consisting of one 0 followed by six 1s followed by one 0. A packet consists of a Lev- ei-2 frame minus the flag bytes. The LSB is transmitted first for all bytes except the FCS. The flag preceding a packet is defined as the opening flag. Therefore, the byte following an opening flag, by definition, cannot be an abort or another flag. A closing flag is defined as a flag that terminates a packet. This flag can be followed by another flag(s), interframe fill consisting of all 1s or flags, or the address field of the next packet. In the latter case, the closing flag of one packet is the opening flag of the next packet. The DLC receiver can recognize interframe fill consisting of logical 1s or flags. The DLC transmitter follows the clos- ing flag with interframe fill consisting of all 1s (mark Idle) if DMR4 bit 4 is set to a logical 0, or all 0's (flag Idle) if DMR4 bit 4 is set to a logical 1. CCITT I-series D-channel access protoco! specifies use of mark Idle. When a collision is detected (mismatch of a D and E bit), a complete frame must be retransmitted. For transfer across the S Interface, the S-interface frame structure is impressed upon the D-channel frame structure (LAPD). Zero Insertion/Deletion When transmitting, the DLC examines the frame con- tent between the opening and closing flags. To ensure that a flag sequence is not repeated within the flag boundaries of the frame, a logical 0 bit is automatically inserted after each sequence of five contiguous logical 1s. When receiving, the DLC examines the frame content between the opening and closing flags and au- tomatically discards the first logical 0 which directly fol- lows five contiguous logical 1s. D-Channel Address Recognition The address field, shown in Figure 4, allows for three types of addresses: 1. 1-byte address signified by the LSB of the first address byte being set to a logical 1 2. 2-byte address signified by the LSB of the first address byte being set to a logical 0, and the LSB of the second address byte being set to a logical 1 3. More than 2-byte address signified by the LSB of both the first and second address bytes being set to a logical 0 38 Am79C30A/32A Data SheetAMD ot 1 2 3 4 5 6 7 8 l I | i | 1 EA=0| C/R SAPI OCTET 2 EA=1 TEI OCTET 3 FLAG ADDRESS CONTROL FCs FLAG 01111110 16 bits 8 bits 16 bits 01111110 Minimum Packet OCTET 1 2,3 o 4 5,6 7 FLAG ADDRESS CONTROL INFORMATION Fcs FLAG General 01711110 16 bits 8 bits N bits 16 bits 01111110 OCTET 1 2,3 4 5... N-1 N Notes: EA = Address Field Extension bit C/R= Command/Response Field bit SAPI= Service Access Point Identifier 09893E-006 TEl= Terminal Endpoint Identifier FCS= Frame Check Sequence Figure 4. Level-2 Frame Structure Formats In the case of the LAPD operating environments, the address is a 2-byte address where the first byte is analo- gous to the Service Access Point Identifier (SAPI} and the second byte is analogous to the Terminal Endpoint Identifier (TEl) as defined by the CCITT recommendations. The DLC is able to recognize D-channel addresses of all of the three types outlined above. Note that only the first two bytes of a more than 2-byte address can be checked by the DLC. There are four First Received Byte Address Registers (FRARs) which hoid the values used to match against the first byte of the incoming address. Similarly, there are four Second Received Byte Address Registers (SRARs) which hold the values used to match against the second byte of the incoming address. FRAR4 defaults to FE hex; SRAR4 defaults to FF hex. This default is analogous to the broadcast address de- fined by the CCITT recommendations. The type of ad- dress recognition which is enabled is shown in Table 38. Table 38. Address Recognition DMR4 DMR1 Bit Bit Bits 7 5 7 6 5 4 Type of address recognition 0 1 xX X x 1 FRAR1 First received byte-only address xX 1 Xx X FRAR3 1 Xx Xx X FRAR4 1 1 xX X x 1 SRAR1 Second received byte-only address X X 1 xX SRAR2 x 1 x xX SRAR3 1 X Xx X SRAR4 xX 0 X x x 1 FRAR1:SRAR1 | 2-byte address Xx X 1 xX FRAR2:SRAR2 X 1 Xx x FRAR3:SRAR3 1 X X X FRAR4:SRAR4 xX xX 0 0 0 0 Address recognition disabled Am79C30A/32A Data Sheet 39\ AMD lf DMR4 bit 6 is set to a logical 0, bit 1 of the FRARs is ignored when matching the first incoming address byte. If DMR4 bit 6 is set to a logical 1, all bits of the FRARs are used when matching the first incoming address byte. FRAR bit 1 is analogous to the C/R bit defined by the CCITT recommendations. The address recognition mechanism for the four FRAR/SRAR addresses can be individually enabled/disabled via DMR1 bits 4-7. First Received Byte-Only Address Recognition If DMR4 bit 5 is set to a logical 1 and DMR4 bit 7 is set to a logical 0. only the first byte of the incoming address is compared with the values stored in the enabled FRARs. An interrupt is generated if there is an address match and the Valid Address interrupt is enabled. If the address matches, the packet will be received. Second Received Byte-Only Address Recognition If DMR4 bits 5 and 7 are set to a logical 1, the DLC compares only the value in the second byte of the in- coming address with values stored in the enabled SRARs. An interrupt is generated if there is an address match and the Valid Address interrupt is enabled. If the address matches, the packet will be received. 2-Byte Address Recognition if DMR4 bit 5 is set to a logical 0, the first byte of the incoming address is compared with the values stored in the enabled FRARs. and the second byte of the in- coming address is compared with the value stored in the corresponding SRAR. An interrupt is generated if a match is found for both incoming address bytes with a FRAR/SRAR pair and the Valid Address interrupt is enabled. If the address matches, the packet will be received. Disabling Address Recognition If DMR1 bits 4, 5, 6, and 7 are all set to logical 0, all address recognition is disabled and all addresses are recognized and received. In this case, the Am79C30A/ 32A receives the first two bytes following the opening flag (the incoming address), and then issues an End of Address interrupt if the End of Address interrupt is enabled. DLC Operation DLC Transmit and Receive FIFOs The DLC Transmit and Receive FIFOs may be config- ured to the Normal or Extended mode of operation. Norma! mode is fully backwards compatible with the Revision D or prior DSC circuit, and is activated upon RESET or if EFCR bit 0 is programmed to logical 0. In Normal mode the Transmit and Receive FIFOs are each 8 bytes in length. The Extended mode of FIFO operation may be activated by programming EFCR bit 0 to a logical 1, increasing the depth of the Transmit and Receive FIFOs to 16 bytes and 32 bytes, respectively. The setting of EFCR bit 0 to logical 1 also alters the available programmable FIFO threshold values set by DMR4 bits 2 and 3. Receiving D-Channel Packets The receiver controls the flow of D-channel data to the D-channel Receive buffer and the termination of a receive packet. Up to two packets can be contained in the D-channe! Receive buffer. After receiving an opening flag (a bit sequence of 01111110) and one byte of data which is not an abort or flagonthe D channel, the DLC sets the Packet-Recep- tion-in-Progress status bit (bit 2) in D-channel Status Register 1 (DSR1). The DLC then receives the first two bytes (the two address bytes). If address recognition is enabled. the Am79C30A/32A issues a Valid Address interrupt if a match between the programmed values and the received address is detected. If no match is detected and address recognition is enabled, the DLC ignores the packet. If address recognition is disabled, the Am79C30A/32A receives the first two bytes, issues an End of Address interrupt, and receives the packet. Both a Valid Address and an End of Address interrupt set Interrupt Register bit 2 to a logical 1 and bit 0 of the D-channel Status Register 1 (DSR1) to a logical 1. The Valid Address/End of Address interrupt can be disabled via DMR3 bit 0. There is an internal 3-byte delay which holds the first of the D-channei address by- tes until the interrupt has been issued. Note that the in- coming address bytes cannot be read however, until the D-channel Receive Byte Available or D-channel Re- ceive Threshold interrupt is set. After the address is received, the DLC continues to receive D-channel bytes into the D-channel Receive buffer FIFO. The DLC issues an interrupt when data is available in the D-channel Receive buffer. This interrupt can be disabled by setting DMR3 bit 3 to a logical 0. The DLC also issues an interrupt when the receive threshold set in DMR4 is reached. This interrupt can be disabled by programming a logical 0 into DMR1 bit 1. By polling, the microprocessor can then read the D-channel bytes. The 3-byte delay incurred during address recognition is maintained. Therefore, the DLC receives the Frame Check Sequence (FCS) before issuing an interrupt to signal the last byte of the packet has been received and appropriate status bits have been up- dated. If DMR3 bit 7 is set, the two FCS bytes at the end of the packet are transferred into the D-channel Receive buffer along with the data. The DLC issues an interrupt when the last byte of the packet is read fram the DCRB. This interrupt can be disabled by setting DMR bit 2 to a logical 0. 40 Am79C30A/32A Data SheetAfter the FCS is received, the DLC receiver detects the closing flag (a bit sequence of 01111110) and then terminates the packet by issuing an End Of Receive Packet interrupt (bit 1 of DSR1) and returns to looking tor opening flags. The DLC also terminates the packet when an abort, anoverflow, or overrun error condition is detected. The End Of Receive Packet interrupt can be disabled by setting DMRA1 bit 3 to a logical 0. The D-channel Receive Byte Count Register (DRCR) is a 16-bit wide, two-word deep FIFO that is used to record the number of bytes in the incoming D-channel packets. Each count is terminated by an end-of-packet condition. Thus, the DRCR informs the microprocessor of the number of bytes, inciuding the address bytes, which have been received. The counter is updated when the last byte of a packet is placed in the D-channel Receive buffer. When the FCS bytes are included in the data transferred to the D-channel Receive buffer, the FCS bytes are included in the byte count; if the FCS bytes are not included in the transfer, they are not included in the byte count. The opening flag and closing flag are not in- cluded in the byte count. The D-channel Error and Address Status Registers are also double buffered. Reading the last byte of a packet causes the DER byte to propagate to the output of the FIFO and updates the D-channel Status and Interrupt Registers accordingly. Reading the MSB of the DRCR causes the next count and associated ASR byte to prop- agate to the output of the FIFOs and updates the D-channel Status and interrupt Registers accordingly. For this reason it is important to read ASR, DER, and DSRi1 prior to reading the DRCR. When a receive error occurs, an End-of-Packet interrupt is generated and the packet is terminated. When the last byte of the associated packet is read from the D-channel Receive buffer, the appropriate DER bits are set and an error interrupt is generated. All error interrupts can be individually masked by setting the corresponding bits in DMR2 to a logical 0. There is one 16-bit D-channel Receive Byte Limit Regis- ter (DRLR). The received byte count is compared with the DRLR. When the byte count of the currently received D-channel packet exceeds the limit value, a receiver overflow is detected, the packet is terminated, and an End-of-Packet interrupt is issued. D-channel Error Reg- ister (DER) bit 4 is setto a logical 1 and an overflow inter- rupt issued when the last byte of the associated packet is read fromthe D-channel Receive buffer. The Overflow Error interrupt can be masked by setting DMR2 bit 4 toa logical 0. The minimum packet length is 5 bytes for a 2-byte address packet (not including flags). If the packet length is less than the above, an interrupt is issued and DER bit 5 is set to a logical 1 when the last byte of the associated packet is read from the D-channel Receive buffer. The error interrupt can be masked by setting DMR2 bit 5 to a logical 0. AMD al If packet reception is in progress and the D-channel Receive buffer is full, the microprocessor has a maxi- mum of 425 us to respond to the D-channel Receive Data Available interrupt. If the microprocessor fails to do so, then an overrun error occurs when the data byte is overwritten. When this happens, the packet is termi- nated. DER bit 6 is set to a logical 1 when the last byte of the associated packet is read from the D-channel Re- ceive buffer. The Overrun Errorinterrupt can be masked by setting DMR2 bit 6 to logical 0. Error indication is given if two packets have been received and not serviced by the user and a third packet is received via DSR2 bit 2. When this error occurs, the third packet is terminated (not received). Error indication is given for a receiver abort (the recep- tion of seven contiguous 1s) by DER bit 0. If the number of bits received between two flags is not an integer multiple of eight (if the received packet does not contain an integral number of bytes), DER bit 1 is set and an interrupt is generated when the last byte of the associated packet is read from the D-channel Receive bufter. The incoming bit stream (including FCS) is run through the FCS generation and compare block. Upon receipt of the closing flag, the result is checked and must be (MSB first} 0001110100001111. Any other pattern indicates an FCS error, and DER bit 3 is set to a logical 1 when the last byte of the associated packet is read from the O-channel Receive buffer. The DLC receiver does not assume the packet to be byte-aligned. The architecture supports shared flags between packets, interframe fill consisting of logical 1s (Mark idle), and interframe fill consisting of flags (Flag idle). Mark idle is defined as at least 15 or more contigu- ous 18. Flag idle is defined as more than two consecu- tive flag characters, not including a closing flag. DSR2 bit 5 is set to a logical 1 while Mark idle is being detected. DSR2 bit 6 is set to a logical 1 while Flag idle is being detected. The receiver D-channel packet can be aborted at any time during reception by setting INIT bit 6. Transmitting D-Channel Packets The DLC Transmitter is activated as soon as the MSB (the second byte) of the 16-bit D-channel Transmit Byte Count Register (DTCR) has been loaded by the microprocessor. Next, the LIU starts counting the number of consecutive 1s on the E-channel until the number of 1s defined by the LIU priority mechanism is detected. After the sequence of fs, the DLC transmitter will begin packet transmission. Am79C30A/32A Data Sheet 41at AMD Address bytes for a transmit packet can be handled in two ways: they can be loaded into the transmit buffer or loaded into the Transmit Address Register (TAR). There is one 16-bit TAR which can be loaded by the microprocessor. The bytes loaded into the TAR are transmitted LSB first followed by MSB. For LAPD opera- tion, the LSB contains the SAPI, and the MSB contains TEI. This 16-bit address (loaded LSB first) is transmitted within the address field of the D-channel packet if enabled by setting DMR1 bit 2 to a logical 1. Ifthe TAR is enabled, the DTCR should be loaded with the number of bytes to be transmitted excluding the address, flags, and FCS. If the TAR is disabled. the DTCR should be loaded with the number of bytes to be transmitted excluding the flags and FCS, and the microprocessor must load the address to be transmitted as the first two bytes of the D-channel packet data. The DLC issues an interrupt when a position is avail- able in the D-channel Transmit buffer. This interrupt can be disabled by setting DMR3 bit 5 to alogical 0. The DLC also issues an interrupt to the microprocessor to request D-channel data bytes when the D-channel Transmit buffer empties to the threshold specified in the D-channel FIFO mode register. This interrupt canbe disabled by setting DMR1 bit 0 to a logical 0. If the D-channel Transmit buffer is empty, the micropro- cessor has up to 375 us to respond to the D-channel transmit buffer interrupt. If the microprocessor fails to load the data bytes in this time frame, an underrun inter- rupt is generated in DER bit 7, and packet transmission is terminated with a transmitted abort. The Underrun interrupt can be masked by setting DMR2 bit 7 to a log- ical.0. Transmission is also terminated when a collision is detected or LIU loss of synchronization occurs. The D-channel Transmit Byte Count Register is decrem- ented each time a byte of data is transferred from the D- channel Transmit buffer to the DLC. The count represents the number of bytes left to be transferred, ex- cluding the FCS and flags. If the transmit abort bit (INIT bit 7) is set, the transmit byte count is frozen and indi- cates the number of bytes left to transter, not the number of bytes transmitted. The last byte of the packet is deter- mined by the D-channe! Transmit Byte Count decre- menting to zero. When this occurs, DSR2 bit3 is set to a logical 7. After the last byte of the packet is transmitted, the DLC adds the FCS and closing flag. Then the DLC issues an interrupt (bit 6 of DSR1) to signify the end of the packet transmission. This interrupt can be masked by setting DMR3 bit 1 to a logical 0, and is reset either by reading DSR1 orwhen the D-channel Transmit Byte Count Reg- ister is loaded for the next packet. Once the D-channel Transmit Byte Count has decrem- ented to 0, a second packet may be loaded into the D-channel Transmit FIFO. If the MSB of the D-channel Transmit Byte Count Register is loaded prior to the end-of-transmit packet interrupt, the second packet is transmitted back-to-back with the previous packet. The End-of-Transmit Packet interrupt is not set be- tween the two packets. If the MSB of the D-channel Transmit Byte Count Register is loaded after the end- of-packet interrupt, the second packet is transmitted once the LIU priority mechanism has been resatisfied. Collision Detection The Network Terminator echoes the transmitted D-channel data back to the DLC in the E-channel bits of the S-interface frame. If there is a difference between the data transmitted and the data echoed back, a coili- sion has occurred. The DLC alerts the microprocessor to this event by asserting the interrupt line (INT) and setting DER bit 2. If a collision occurs during the trans- mission of an abort sequence, the interrupt is still issued. The collision detect interrupt can be masked by setting DMR2 bit 2 to a logical 0. D-Channel Receive and Transmit Errors Non-integer Number of Bytes Anon-integer number of bytes occurs when the number of D-channel bits received between opening and closing flags is not divisible by eight. If a received packet con- sists of anon-integer number of bytes, the DLC sets bit 1 in the D-channel Error Register (DER) to a logical 1 when the last byte of the associated packet is read from the D-channel Receive buffer. Frame Check Sequence Error If a received packet, including its 16-bit Frame Check Sequence. is not received perfectly, the DLC sets DER bit 3 to a logical 1 when the last byte of the associated packet is read from the Receive buffer. Receive Packet Abort If seven contiguous 1s are received while receiving a packet, the packet will be terminated. DER bit 0 will be set to a logical 1 when the last byte of the associated packet is read from the D-channel Receive buffer. Overflow Overflow occurs when the total number of D-channelby- tes within a packet (including, only when enabled, the Frame Check Sequence bytes) exceeds the limit con- tained in the D-channel Receive Byte Limit Register. (See Receiving D-channel Packets section.) When overflow occurs. the DLC terminates the packet, and sets DER bit 4 to a logical 1 when the last byte of the associated packet is read from the D-channel Receive buffer. Underfiow If a received D-channel (including FCS) packet is less than 5 bytes for a 2-byte address packet, an underflow error condition occurs, and the DLC sets DER 42 Am79C30A/32A Data Sheetbit 5 to a logical 1 when the last byte of the associated packet is read from the D-channe! Receive buffer. Overrun A D-channel overrun error occurs when the receiver buffer is full, and another byte is received. This can hap- pen if the D-channel Receive buffer fills. and is not read within 425 us. When this error occurs, the DLC sets DER bit 6 to a logical 1 and terminates the packet. Underrun A D-channel underrun error occurs when an empty D-channel buffer is transmitted. This can happen if the AMD at D-channel Transmit buffer is not loaded within 375 ps of the D-channel Transmit buffer Empty interrupt being asserted (IR bit 0). When this error occurs, the DLC sets DER bit 7 to a logical 1 and terminates the packet. Receive Packet Lost Receive Packet Lost occurs when two outstanding packets have been received and not serviced (the microprocessor has not read the DRCB register}, and a third packet is received. When this error occurs, DSR2 bit 2 is set to a logical 1 and the incoming packet is terminated (not received). DLC Registers The DLC contains the following registers. Registers Number of Registers Mnemonic First Received Byte Address Registers 4 FRAR Second Received Byte Address Registers 4 SRAR Transmit Address Register (16-bit) 1 TAR D-channel Receive Byte Limit Register (16-bit) 1 DRLR D-channel Receive Byte Count Register (16-bit) 4 DRCR (2-word FIFO) D-channel Transmit Byte Count Register (16-bit) 1 DTCR Random Number Generator Registers 2 RNGR D-channel mode registers 4 DMR Address Status Register (2-byte FIFO) 1 ASR Extended FIFO Control Register 1 EFCR D-channel Transmit buffer Register - DCTR D-channel Receive buffer Register - DCRB D-channel Status Register #1 1 DSR1 D-channel Status Register #2 1 DSR2 D-channel Error Register (2-byte FIFO) 1 DER Transmit Address Register (TAR) Read/Write Address = Indirect 83H This register contains the address of the packet to be transmitted if the TAR bit is enabled (DMR1 bit 2). First Received Byte Address Register (FRAR1-FRAR4) Read/Write Address = Indirect FRAR1-FRARS = 81H, FRAR4 = 8CH These registers contain the value to match against the first byte of the incoming address. If DMR1 bits 4~7 are disabled, these registers are ignored. Second Received Byte Address Register (SRAR1-SRAR4) Read/Write Address = Indirect SRAR1i-SRAR3 = 82H, SRAR4 = 8DH These registers contain the value to match against the first byte of the incoming address. If DMRi bits 4~7 are dis- abled, these registers are ignored. D-Channel Receive Byte Count Register (DRCR) Read Address = Indirect 89H This register determines the maximum number of bytes in a received packet. Am79C30A/32A Data Sheet 43a\ AMD D-Channel Receive Byte Limit Register (DRLR) Read/Write Address = Indirect 84H This register contains the total number of received bytes. D-Channel Transmit Byte Count Register (DTCR) Read/Write Address = Indirect 85H This register contains the total number of transferred bytes. Random Number Generator Register (RNGR1, RNGR2) Read/Write Address = Indirect RNGR1 = 8AH, RNGR2 = 8BH These registers contro! the operation of the Random Number Generator. When read, they display the random number generated by the chip. D-Channel Transmit Buffer Register (DCTB) Write D-channel transmit FIFO. D-Channel Receive Buffer Register (DCRB) Read D-channel receive FIFO. D-Channel Mode Register 1 (DMR1) Read/Write Address = Indirect 86H DMR1 controls the enable/disable options for the DLC. It is under sole control of the microprocessor and does not generate any interrupts. DMR_1 is defined in Table 39. Table 39. D-Channel Mode Register 1 Bit | Logical 1 Logical 0 0 Enable D-channel Transmit Threshold interrupt (see IR bit 0) | Disable interrupt (default value) 1 Enable D-channel Receive Threshold interrupt (see IR bit 1) | Disable interrupt (default value) 2 Enable Transmit Address Register Disable Transmit Address Register (defauit value) 3 Enable End of Receive Packet interrupt (see DSR1 bit 1) Disable interrupt (default value) 4 Enable FRAR1/SRAR1 Disable FRAR1/SRAR1 (default value) 5 Enable FRAR2/SRAR2 Disable FRAR2/SRAR2 (default value} 6 Enable FRAR3/SRAR3 Disable FRAR3/SRAR3 (default value} 7 Enable FRAR4/SRAR4 Disable FRAR4/SRAR4 D-Channel Mode Register 2 (OMR2) Read/Write Address = Indirect 87H DMR2 is used to enable/disable the interrupts generated in the DER (see DER definition on page 41). DMR2 is controlled by the microprocessor and does not generate interrupts. DMR2 is defined in Table 40. Table 40. D-Channel Mode Register 2 Bit | Logical 1 Logical 0 (Default Value) 0 Enable Receive Abort interrupt (see DER bit 0) Disable interrupt 1 Enable Non-integer Number of Bytes Received interrupt (see DER bit 1) Disable interrupt 2 Enable Collision Abort Detected interrupt (see DER bit 2) Disabie interrupt 3 Enable FCS Error interrupt (see DER bit 3} Disable interrupt 4 Enable Overflow Error interrupt (see DER bit 4) Disable interrupt 5 Enable Underflow Error interrupt (see DER bit 5) Disable interrupt 6 Enable Overrun Error interrupt (see DER bit 6) Disable interrupt 7 Enable Underrun Error interrupt (see DER bit 7) Disable interrupt 44 Am79C30A/32A Data SheetD-Channel Mode Register 3 (DMR3) Read/Write Address = Indirect 8EH AMD cl Table 41. D-Channeil Mode Register 3 Bit | Logica! 1 Logical 0 (Default Value) 0 Enable Valid Address/End of Address interrupt (default value)(see DSR1 bit 0) | Disable interrupt 1 Enable End of Valid Transmit Packet interrupt (default value)(see DSR1 bit 6) | Disable interrupt 2 Enable Last Byte of Received Packet interrupt (see DSR2 bit 0) Disable interrupt (default value) 3 Enable Receive Byte Available interrupt (see DSR2 bit 1) Disable interrupt (default value) 4 Enable Last Byte Transmitted interrupt (see DSR2 bit 3) Disable interrupt (default value) 5 Enable Transmit buffer Available interrupt (see DSR2 bit 4) Disable interrupt (default value} 6 Enable Received Packet Lost interrupt (see DSR2 bit 2) Disable interrupt (default value) 7 Enable FCS transfer to FIFO Disable FCS transfer to FIFO (default value) D-Channel Mode Register 4 (DMR4) Read/Write Address = Indirect 8FH Table 42. D-Channel Mode Register 4 Bit 7 6 5 43 2 1 Control Function xXx xX X x 0 Receiver Threshold 1 byte (EFCR bit 0 = 0) 1 byte (EFCR bit 0 = 1) Xx X X X X X O 1 2 bytes (EFCR bit 0 = 0) 16 bytes (EFCR bit 0 = 1) Xx X X X X X 1 +0 4 bytes (EFCR bit 0 = 0) 24 bytes (EFCR bit 0 = 1) Xx X X X X X 1 1 8 bytes (EFCR bit 0 = 0) 30 bytes (EFCR bit 0 = 1) X X X X O O X X |Transmitter Threshold 1 byte (EFCR bit 0 = 0) 1 byte (EFCR bit 0 = 1) X X X X 0 1 X X 2 bytes (EFCR bit 0 = 0} 6 bytes (EFCR bit 0 = 1) xX X X X 1:0 X X 4 bytes (EFCR bit 0 = 0) 10 bytes (EFCR bit 0 = 1) xX X X X 1 14 X X 8 bytes (EFCR bit 0 = 0) 14 bytes (EFCR bit 1 = 1) X X X OO X X X = X | Interframe Fill Mark Idle (default value) Xx X X 1 X X X X Flag Idle X X O0 X X X X_~ X | Address Recognition 2-byte (default value) o xX 1X X X X X First Received Byte only 1 X 1X X X X X Second Received Byte only X 0 X X X X X X |C/R Bit Compare Disable FRAR bit 1 compare (default value) X 1 X X X KX KX X Enable FRAR bit 1 compare Note: The receiver and transmitter thresholds can only be changed when the AmM79C30A/32A4 is in Idle mode. Am79C30A/32A Data Sheet 45al AMD Address Status Register (ASR) Read Only Address = Indirect 91H Table 43. Address Status Register Bit | Logical 1 Logical 0 (Default Value) 0 FRAR1/SRAR1 address recognized No FRAR1/SRAR1 address match 1 FRAR2/SRARZ2 address recognized No FRAR2/SRAR2 address match 2 FRAR3/SRARS address recognized No FRAR3/SRAR3 address match 3 FRAR4/SRAR4 address recognized No FRAR4/SRAR4 address match 4-7 | Reserved Reserved D-Channel Status Register 1 (DSR1) Read Only DSR1 has the format shown in Table 44. Table 44. D-Channel Status Register 1 Bit | Logical 1 Logical 0 (Default Value) 0 Valid Address (VA) if the address decode logic is enabled or No valid address End-of-Address (EQOA) if the address decade logic is disabled 1 End of receive packet Not end of packet 2 Packet reception in progress Packet not being received 3 Loopback in operation at Am79C30A/32A No loopback in operation at Am79C30A/32A 4 Loopback in operation at LIU No loopback in operation at LIU 5 D-channel back-off not in operation D-channel back-off in operation 6 End of valid transmit packet No end-of-transmit packet or no transmission 7 Current transmit packet has been aborted No transmit packet abort The DSR1 bits generate interrupts and are set/reset under the conditions shown in Table 45 (in addition to a hardware reset or idle mode). Table 45. DSR1 Interrupts Bit | Generate interrupt Bit Set Bit Reset 0 Yes, if DMR3 bit 0 = 1 Two bytes after an opening flag if a VA is When the microprocessor reads decoded or address recognition is disabled ] DSR1 or associated DRCR 1 Yes, if DMR1 bit 3 = 1 When a clasing flag is received When the microprocessor reads DSA1 or associated DRCR 2 No One byte after the opening flag of any When a flag or an abort is received packet, valid or not 3 No When the operation is in progress When the operation is not in progress 4 No When the operation is in progress When the operation is not in progress 5 No When the operation is in progress When the operation is not in progress 6 Yes, if DMR3 bit 1 = 1 When the closing flag is transmitted When the microprocessor reads DSR1 or when OTCR is loaded 7 No When seven 1s and a 0 have been When the microprocessor reads DSR1 or transmitted when DTCR is loaded 46 Am79C30A/32A Data SheetD-Channel Status Register 2 (DSR2) Read Only DSR2 has the format illustrated in Table 46. AMD Pa Table 46. D-Channel Status Register 2 Bit |Legical 1 Logical 0 (Default Value) 0 Last byte of raceived packet Not last byte of received packet 1 Receive byte available Receive byte not available 2 Receive packet lost Receive packet not lost 3 Last byte transmitted Last byte not transmitted 4 Transmit buffer available Transmit buffer not available* 5 Mark idle detected (15 or more contiguous ts) Mark idle not detected 6 Flag idle detected (more than two contiguous flags) Flag idle not detected 7 Start of second received packet in FIFO Second packet not yet in FIFO Note: "Following RESET, the Transmit buffer Available (bit 4) is set, producing a default value of 10H. The DSR2 bits generate interrupts and are set/reset under the conditions shown in Table 47 (in addition to a hardware reset or Idle mode). Table 47. DSR2 interrupts Bit | Generate Interrupt Bit Set Bit Reset 0 Yes, if DMR3 bit 2 = 1 1 Yes, if DMR1 bit 3 = 1 2 Yes, if DMR3 bit 6 = 1 3 Yes, if DMRS bit 4 = 1 4 Yes, if DMR3 bit 5 = 1 5 No 6 No 7 Yes, if EFCR bit 1 = 1 When last byte of a received packet is read from the DCRB When DCRB contains one or more bytes of data When two outstanding packets are re- ceived and not serviced, and a third packet is received When the last byte of a transmit packet is transferred from the DCTB When the DCTB is available to be loaded with a data byte When 15 contiguous one bits have been detected in the incoming D channel When more than two contiguous flags are detected on the incoming D channels, not including a closing flag When start of second packet is in the receive FIFO When the microprocessor reads the DSR2 When DCRB is empty When the microprocessor reads DSR2 When the microprocessor reads DSR2 When the DCTB is full When the first zero bit is detected on the incoming D channel When a non-flag character is detected on the incoming D channel When second receive packet is not present Am79C30A/32A Data Sheet 47cl AMD D-Channel Error Register (DER) Read Only The DER has the format illustrated in Table 48. Table 48. D-Channel Error Register Bit {Logical 1 Logical 0 (Default Value) 0 Received Packet Abort No abort received 1 Non-integer number of bytes have been received integer number of bytes received 2 Collision Detected No error 3 FCS Error No error 4 Overflow Error No error 5 Underflow Error No error 6 Overrun Error No error 7 Underrun Error No error DER bits 0, 1,3, 4, 5, and 6 are set when the last byte of the associated packet is read from the D-channel Receive buffer. The DER bits generate interrupts and are set/reset under the conditions shown in Table 49 (in addition to a hardware reset). Table 49. DER Interrupts Bit | Generates Interrupt Bit Set Bit Reset 0) Yes, if DMR2 bit 0 =1 When seven consecutive 1s are received | When the microprocessor reads the DER within a packet (DSR? bit 2 = 1) or associated DRCR 1 Yes, if OMR2 bit 1 = 1 Upon errar condition after closing flag When the microprocessor reads the DER has been received or associated DRCR 2 Yes, if DMR2 bit 2 = 1 See section on collision detection When the microprocessor reads the DER or when DTCR is loaded 3 Yes, if DMR2 bit 3 = 1 If error occurs When the microprocessor reads the DER or associated DRCR 4 Yes, if DMR2 bit 4 =1 If errar occurs When the micraprocessor reads the DER or associated DRCR 5 Yes, if DMR2 bit 5 = 1 If error occurs When the microprocessor reads the DER or associated DRCR 6 Yes, if DMR2 bit 6 = 1 If error occurs When the microprocessor reads the DER or associated DRCR 7 Yes, if DMR2 bit 7 = 1 If error occurs When the microprocessor reads the DER or when DTCR is loaded Extended FIFO Control Register (EFCR) Read/Write Address = Indirect 92H Bit 7 6 5 4 3 2 1+ O | Function o X X X X 0 X X |Bits 7 and 2 reserved, must be written to 0 See Table 20. Bits 6-3 control attenuation of the analog sidetone path (ASTG) o X X X X 0 O X | Start of Second Received Packet !n FIFO interrupt disabled o xX X XK X oO 1. X | Start of Second Received Packet In FIFO interrupt enabled oO X X X X a X OO |Normal mode of FIFO operation oO X X X X 90 X 1 | Extended mode of FIFO operation 48 Am79C30A/32A Data SheetPeripheral Port (PP) Overview The purpose of the Peripheral Port is to allow external peripherals to be connected to the DSC/IDC circuit. There are two basic modes of operation, Serial Bus Port mode, and l|OM-2 Terminal mode. Within |OM-2 Termi- nal mode, the DSC/IDC circuit may be configured as any combination of IOM-2 timing/control master or slave. The definition of the Peripheral Port pins depends onthe operating mode of the port, as described in Table 50. Serial Bus Port (SBP) Mode The SBP mode of operation is backwards compatible with the Revision D DSC circuit serial port andis entered either following a device RESET or if programmed in PPCRI1. In SBP mode, the SCLK output provides a 192-kHz 1X data clock of programmable polarity. The SBIN and SBOUT pins support three 8-bit seria! data channels, designated Bd, Be, and Bf. The SFS output provides an 8-kHz serial frame sync pulse eight bit periods in width, coincident with the Bd channel. The SBP mode timing is illustrated in Figure 5. Following a RESET, the SCLK and SFS outputs will default to a high-impedance state, which will be AMD al maintained until any MUX connection is programmed (or until the Peripheral Port is programmed to an [OM-2 mode). SCLK and SFS will remain in a high-impedance State if the Peripheral Port is explicitly disabled. The SCLK and SFS signals are synchronized to the received S-interface frame. If there is no S-interface frame synchronization. the SCLK and SFS signals will free- run at 192 kHz and 8 kHz respectively. lf the DSC/IDC circuit is programmed to Idle mode, the SFS output is driven Low but SCLK continues to run. In Power-Down mode, both the SFS and SCLK outputs are high-impedance. IOM-2 Terminal Mode Overview The IOM-2 Interface standard encompasses both a Li- necard mode and a Terminal made. The Terminal mode was defined to provide four functions, as follows: 1. Connection of multiple Layer-2 devices to a Layer-1 device (in this case, the Layer-1 device is the S/T Interface LIU). Provision for the connection of non-lOM-2 devices is included. 2. Programming and control of Layer-1 or Layer-2 devices that do not have a microprocessor interface, for example, a U-interface transceiver. Table 50. Pin Operation versus Peripheral Port Modes Pin SBP On | Port 1OM-2M |1OM-2M 1OM-2 S* IOM-2 S* IOM-2 S 1{OM-2S Disabled | Activated | Deactivated | Bus Reverse | Bus Reverse | No Bus No Bus : Activated Deactivated | Reverse Reverse Activated Deactivated SBIN IN Z IN IN IN/OD OD OD oD SBOUT OUT Zz oD Zz OD/IN Z iN Z SCLK OUT Z OUT Low IN IN IN IN SFS OUT Zz OUT Low IN IN IN IN BCL/ OUT Zz OUT Low Z Z Z Z CH2STRB IN = Input OUT = Output Z = High Impedance OD = Open Drain Output Note: The Am79C30A is anon-Layer-1 component when operated in the Slave mode; however, it has a microprocessor interface. As a result, it is required to change the direction of its I/O pins at certain times in order to communicate with both the upstream Layer-1 device and any downstream peripheral devices. In the |OM-2 Slave mode, the direction of data flow is reversed with respect to the DSC circuit during Sub-frame 0 and during the deactivated state. The rule is that the upstream Layer-1 device only uses Sub-frame 0 and does not reverse its pins. Any non-Layer-1 component that does not contain a microprocessor interface (i.e., program by the DSC circuit over the Monitor channel in Sub-frame 1) uses Sub-frame 0 to talk to the Layer-1 device and Sub-frame 1 to talk to the DSC circuit. It does not reverse its pins. Am79C30A/32A Data Sheet 49SCLK 192 kHz SBIN or SBOUT 07 D6 DS D4 D3 D2 Bi DO D7 D6 D5 D4 D3 D2 D1 DO D7 D6 DS D4 DB D2 D1 DO je Bd { le Be >< Bf >| SFS 41.7 us 125 ps | 09893E-007 Note: SBIN is sampled on the rising edge of SCLK. SBOUT is changed on the falling edge of SCLK. Figure 5. Serial Bus Port Mode Timing Inter-chip communication between devices on the bus, for instance, data flow between the DSC circuit MAP and an external speech encryption device. Connection of muitiple DLCs to the D channel, including access arbitration. This function is referred to as the TIC channel. The IOM-2 Terminal mode bus consists of three |OM-2 subframes, each containing 32 bits. This 12-byte frame is repeated at 8 kHz, resulting in an aggregate data rate of 768 kbits/s. The frame structure is illustrated in Figure 6, and contains the following channels: Two 64-kbits/s data channels, labeled B1 and B2. Two device programming channels, labeled Monitor 0 and 1. Each channel has an associated pair of MX and MR handshake bits that control data flow. One 16-kbits/s D channel for signaling and data packets. Two Command/indicate channels, labeled C/I0, and C/M, to provide status and command for devices connected via the monitor channels. The Command/indicate channel in the first 1OM-2 subframe consists of four bits, providing 16 states in each direction. In the second subframe the C/I channel is 6 bits, providing 64 states in each direction. Two 64-kbits/s intercommunication channels, labeled [C1 and [C2, to provide additional interdevice communications bandwidth. All data transmitted on the IOM-2 Interface via the SBOUT pin is transmitted MSB first, with the exception of D-channe! data, which is transmitted LSB first. The re- ceiver operates in a compatible way via the SBIN pin. SFS J | MR,MX MR,MX SBIN/ B1 B2 |MONO/D) C/I Ic1 7 IC2 SBOUT MON1 CA TIc IOM channel 0 {OM channel 1 IOM channel 2 09893E-008 Figure 6. |OM-2 Terminal Mode Frame Structure 50 Am79C30A/32A Data SheetDSCADC Circuit |OM-2 Terminal Mode Implementation Data Channels The B1 and B2 channels are physically the first two 8-bit time slots after the frame sync pulse. When making a MUX connection to these channels, |OM-2 channels B1 and B2 correspond to MUX channels Bd and Be, respectively. When in an }OM-2 mode, a MUX connec- tion to channel Bf provides access to one of the two intercommunication channels as selected in PPCR1. Command/indicate Channels The Peripheral Port supports the C/I channels of the first and second IOM-2 subframes. The Peripheral Port monitors these two channels, and generates an inter- rupt any time the received data changes and is stable for two frames. The received data is read from C/I Receive Data Register 0 or 1, and C/l transmit data is written to C/l Transmit Data Register 0 or 1. When the TIC bus fea- ture is enabled, C/I0 transmit access to the IOM-2 Inter- face is controlled by CITDRO bit 7, Bus Access Request. D Channel \f the peripheral Port is configured as 1OM-2 master with TIC bus disabled, the DLC will transmit and receive D- channel data to and from the S Interface through the AMD at LIU. The D-channel data received from the S Interface is also output on the IOM-2 interface. D-channel data re- ceived from the IOM-2 Interface is disregarded. If, how- ever, TIC bus is enabled, the TIC bus control logic will arbitrate D-channel data flow between the S Interface and either the DLC or IOM-2 Interface based on TIC bus access procedures. When the Peripheral Port is configured as |OM-2 slave, the DLC will transmit and receive D-channel data to and from the |IOM-2 Interface. This will be a dedicated path if the TIC bus feature is disabled, or with DLC access arbi- trated according to TIC bus access procedures if the TIC bus feature is enabled. The LIU is not used in this situa- tion, so there is no D-channel data flow between the DLC and LIU. Monitor Channels Support for the two Monitor channels is provided on a one-at-a-time basis. A bit in Peripheral Port Control Register 1 selects which one of the two Monitor chan- nels is utilized at any time. Tic Bus The |OM-2 TIC bus control bits reside in the last byte to the 1OM-2 Terminal mode frame (channel 2, byte 4). The bits and their definitions are shown in Figure 7. Data Upstream (output) 1 1 BAC|TBA2|TBA1|/TBAO| 1 1 Data Downstream (input) E E S8/G | AB 1 1 1 1 BAC bit (Bus Accessed): indication to other devices that the TIC bus is being accessed. When 0 the bus is accessed, when 1 it is free. This bit is driven to zero by the device that gets an address match on the TBA2-0 bits. TBA2-0 bits (TIC Bus Address): address bit used for arbitration of TIC bus control. Assumes OpenDrain bus such that de- vice with highest zero content in its address has the highest priority. Lowest priority address, which is also the default, is 111. E-bits (Echo): D-channel Echo bits from the S-bus. Will not be supported by the DSC. S/G bit (Stop/Go): used to indicate availability of the S-bus D- channel. When 0, the D-channel is clear for transmission. When 1, D-channel transmission should be haited. A bit (Available/Blocked): supplementary bit for D-channel control. 1 indicates D-channel available, 0 O-channel blocked. Optional, will not be supported by the DSC. Figure 7. TIC Bus Control Bits and Definitions Am79C30A/32A Data Sheet 51cl AMD MASTER Mode DSC is the timing master (FSC and SCLK are outputs) TIC bus provides D and C/I0 access to all downstream and control master (can communicate with downstream devices. For control slave applications, the DSC can devices). The configuration of timing master and control disable all IOM-2 channel 1 communications. slave is covered within this mode. The presence of the | fo 0 Ve | SBOUT \ Ur | upstream Dsc I | SBIN_ | <_ | | L.__J DD t Downstream #1 DU > DD <t Downstream #2 DU > downstream Figure 8. IOM-2 Master Mode Operation 52 Am79C30A/32A Data SheetAMD at SLAVE Mode - Bus Reversal Enabled DSC is the timing slave (FSC and SCLK are inputs) and stream devices via MONI and C/I). D and C/l0 arbitra- control master (can communicate with other down- tion provided by TIC bus capability. U- transceiver res 7 | IC1, 12, MON1, crit | ey A DU | faa TTaae Voy | | psc spout! 4 < upstream it sBin | | ! Lt DD Downstream ~< #1 DU > DD Downstream <= #2 DU > downstream Figure 9. IOM-2 Slave Mode Operation with Bus Reversal Am79C30A/32A Data Sheet 53Pa | AMD SLAVE Mode - Bus Reversal Disabled DSC is the timing slave (FSC and SCLK are inputs) and stream devices). D and C/I0 arbitration provided by TIC control master (cannot communicate with other down- bus capability. DSC Master oo SBOUT A sBIN CT 7 | B1, B2, D, MONO, C/lO, | {| 1C1, C2, MON1, C/I1, S/G(in), TIC(out} | | ee re ee ee ee ee ee ee SBOUT |__| psc r# | upstream ff SBIN | I > L_ DD Downstream < #1 DU > DD Downstream DU > downstream Figure 10. IOM-2 Slave Mode Operation without Bus Reversal 54 Am79C30A/32A Data SheetIntelligent NT Either Slave mode can be used to implement the intelli- gent NT configuration. The diagram below depicts this configuration using DSC Slave mode with bus reversal disabled. The U-transceiver operates as the IOM-2 master de- vice, programmed to TE mode and outputting at 1536-kHz DCL. The DSC indicates a D-channel request according to the TIC bus procedure using the BAC bit on the DU line (BAC=0). The S-transceiver surveys the re- ceived D channel and if it is idle, enables the DSC to AMD al send its D-channel frame to the U-transceiver on DU by driving S/G low on DD. The S-transceiver also sets its transmitted E-channei bits on the S-Interface to zero (in- version of received D bits) to prevent all connected TEs from transmitting data into the D-channel. When the DSC compietes its D-channel transmission, it releases the TIC bus by setting BAC=1. The S-transceiver then mirrors the incoming D bits into the E-channel, thus be- having as a normal NT with transparent D-channel handling. U-transceiver Master _ _ DOUTIOD y DIN/DU FO 7 | B1, B2, D, MONO, C/O, | | 11, 1C2, MON1, C/I, S/G{in), TIC(out) | PRT TTT psc Seo" S ! upstream , | IN SB t > | | D-channel DD perm | Te conc S-transceiver ~~ E-channel DU <<__ ~ downstream S Interface Figure 11. 1IOM-2 Intelligent NT Configuration Am79C30A/32A Data Sheet 55cl AMD Monitor Channel Procedures The Monitor channel operates on an event-driven basis; although data transfers on the bus are synchro- nized to the frame sync, the flow of data is controlled by a handshake procedure using the outgoing MX and incoming MR bits. Thus, the actual data rate is not fixed, but is dependent upon the response speed of transmit- ter and receiver. Figure 12 illustrates the sequence of events in the monitor handshake procedure. Idle State The outgoing MX and incoming MR bits held inactive for two or more frames indicates that the Monitor channel is Idle in the outgoing direction. Start of Transmission The PPCR1 register is programmed to select one of the two monitor channels. Data is then loaded into the moni- tor Transmit Data Register, causing the first data byte to be presented to the bus as well as an inactive-to-active transition of outgoing MX. The Monitor channel transmit buffer available interrupt is also generated when data is placed on the bus, indicating that the next data byte may be written to the buffer. Outgoing MX remains active, and the data is repeated until an inactive-to- active transition of the incoming MR is received. Subsequent Transmission Following detection of the first inactive-to-active transi- tion of incoming MR, all following bytes to be transmitted will be presented to the bus coincident with an active- to-inactive transition of outgoing MX. The IOM-2 specification defines a general case (Figure 12a) in which the transmitter waits for an inactive-to-active transition of incoming MR, and a maximum speed case (Figure 12c) in which the transmitter achieves a higher transmission rate by anticipating the falling edge of incoming MR. The DSC/IDC circuit Monitor channel transmitter implements the maximum speed case as follows: the second byte is placed onto the bus at the start of the frame following the transition of incoming MR (High to Low), and a Monitor channel transmit buffer available interrupt is generated. Simultaneously, outgoing MX is returned inactive for one frame, then reactivated. Note that two frames of outgoing MX inactive signifies the end of a message. Outgoing MX and the data byte remain valid until incoming MR goes inactive. The next byte is transmitted during the next frame, meaning one frame after incoming MR goes inactive. In this manner, the transmitter is anticipating incoming MR returning active, which it will do one frame time after it is deactivated, unless an abort is signaled from the receiver. After the jast byte of data has been transmitted, indicated by the Monitor Transmit Data Register being empty and the end-of-transmission (EOM) bit being set in PPCR1, outgoing MX is deactivated in response to incoming MR going inactive, and left inactive. First Byie Reception At the time the receiver sees the first byte, indicated by the inactive-to-active transition of incoming MX, out- going MR is by definition inactive. Outgoing MR is activated in response to the activation of incoming MX, the data byte on the bus is loaded into the Monitor Receive Data Register, and a Monitor channel receive data available interrupt is generated. Outgoing MR remains active until the next byte is received or an end- of-message is detected (incoming MX held inactive for two or more frames). Subsequent Reception Data is received into the buffer on each falling edge of incoming MX, and a Monitor channel receive data available interrupt is generated. Note that the data was actually valid at the time incoming MX became inactive, one frame prior to becoming active. Outgoing MR is deactivated at the time data is read and reactivated one frame later. The reception of data is terminated by reception of an end-of-message indication, which is incoming MX remaining inactive for two or more frames. End-of-Transmission (EOM) The transmitter sends an EOM in response to the EOM request bit being set in PPCR1. Once the EOM bit is set, the EOM is transmitted as soon as the Monitor Transmit Data Register becomes empty. This is normally done when the last byte of a message has been transmitted. The DSC/IDC circuit transmits an EOM simply by not reactivating MX after deactivating it in response to MR going inactive. The EOM request bit in PPCR1 is auto- matically cleared when the EOM has been transmitted, indicating that the monitor transmitter is available for a new message. Abort An abott is a signal from the receiver to the transmitter indicating that data has been missed. The receiver sends an abort by holding MR inactive for two or more frames in response to MX going active. An interrupt is generated when an abort is received. Flow Control The transmitter is held off until the Monitor Receive Data Register is read, since MR is held active until the receive byte is read. The transmitter will not start the next transmission cycle until MR goes inactive. 56 Am79C30A/32A Data SheetTransmitter Receiver Transmitter Receiver Transmitter Receiver MX MR MX MR MX WX AMD at . t t a t I ' 1 I i t ' A . ' ' t 1 ' a ee ee ' ' 4 ' ' 4 ' ' ,OM, ' a! ' 1 1 ' ' ' 14 1 1 r ' First Byte ' , New Byte 1 Last Byte , ' 1 1 1 ' t ' ' 1 F ' ' t t 1 ' ' ' e ' q ' , ' ' 1 ' ' : 1 1 & & ' cf 1 ACK a Jeo ACK + ACK 1 t I I a . t cy i . t t 4 : t t i 1 _?> > 1 1 1 , 1 I n- 125 LS 125 us ' ' ' t 1 1 t ' a. General Case 1 , i , a a ' ' ' . ' EOM yo NewByl@ yy on ' 1 t t t I 1 t ' ' ' ' ' t 1 ' a ' 1 1 1 i 1 a ee ee el , J t I 1 I t ' r 1 . - 1 ' 1 Abort Il t 1 1 ' Request 1 1 ' t ' 1 a ' ' b. Abort Request from the Receiver 4 t cy t a 1 F a i ' a | Doo 4 , EOM | 1 f ' ' 1 First Byte " Second Byte Third'Byte ; 1 ' s 1 4 ' te a ' ' ' 1 ' f I a 1 ' t I v a . t 1 ' ' t cy 1 t . ACK ACK ' First Byte ' Second Byte | Third Byte | ' t i 4 t t t t t I c. Maximum Speed Case 09893E-009 Figure 12. Monitor Handshake Timing Am79C30A/32A Data Sheet 57al AMD IOM-2 Activation/Deactivation The IOM-2 Interface includes an activation/deactivation capability (see Figure 13). Activation and deactivation can be initiated from either upstream or downstream components on the bus. When deactivated, the upstream device holds all the clock outputs Low, and the downstream devices force their open drain data outputs to a High-Z state (seen as a High on the system bus due to the external pullup resistor). The activation/ deactivation procedure is a combination of software handshakes via the C/I channel, and hardware indica- tions via the clock and data lines. The IOM-2 specifica- tion describes both the hardware and software protocols in detail; the hardware operation supported by the Am79C30A IOM-2 implementation is outlined in Figure 13. DSC/IDC Circuit as Upstream Device (Clock Master) Deactivation Deactivation of the IOM-2 Interface from the Am79C30A operating as an upstream device is initiated and con- trolled by the microprocessor. A series of software hand- shakes via the C/t channel must be performed before the hardware deactivation can take place. The upstream device must issue a deactivation request command on the C/I channel and wait for a deactivation indication from all downstream units. Once this is received, a deactivation confirmation command must be sent on the C/I channel by the upstream device. The upstream device will then stop all clocks and hold them Low. On the Am78C30A, the IOM-2 clocks (SCLK, SFS, and BCL/CH2STRB) are stopped and forced Low SBIN goes Low Timing Request Interrupt generated Idle (clks off) Software clears Activation bit clk pend (clks off) Software sets Activation bit ACTIVE (clks on) Software sets Activation bit a. Am79C30A as Upstream Device Software sets Activation bit SBIN output forced Low (SBIN = 0) (clks off) Clock received from upstream; Timing Request interrupt generated (SBIN = 0) (clks on) Software clears Activation bit (clks off) (SBIN = Z) ACTIVE (clks on) (SBIN = data) SBIN output forced to Z Timeout (clks off) Clocks stopped by upstream device b. Am79C30A as Downstream Device Notes: This diagram shows only the portions of the 1OM-2 activation/deactivation procedures that are affected by the Am79C30A hardware. The C/l-channel software handshakes are not shown. 09893E-010 Figure 13. [OM-2 Activation/Deactivation 58 Am79C30A/32A Data Sheetwhen the microprocessor clears the activation/deactiva- tion bit in the Peripheral Port Control Register Number 1 (PPCR1). When this bit is cleared, the data output pin (SBOUT) is also forced to High-Z (seen as a High on the system bus due to the external pullup resistor), and the Am79C30A begins monitoring the data input pin (SBIN) for the presence of a timing request from any down- stream units. Activation Activation can be initiated locally by the processor or remotely by one of the downstream units. To activate locally, the processor sets the activation/deactivation bit in PPCR1 (starting the clocks), and then proceeds through the software activation protocol on the C/I channel. For remote activation, the upstream device re- ceives a request from the downstream device via the data input pin. When the data input pin (SBIN) goes Low, Am79C30A will generate an |OM-2 timing-request inter- rupt, bit 6 in the Peripheral Port Status Register (PPSR). The processor must respond to this interrupt, and restart the IOM-2 clocks by setting the activation/ deactivation bit in PPCR1. Once the clocks are running, the downstream device can request full activation via the C/l channel using the |OM-2 software protocol. DSC/IDC Circuit as a Downstream Device (Clock Slave) Deactivation Deactivation is normally initiated by the upstream device as described above. When the deactivation request is received by the downstream device over the C/l channel, the processor must respond by sending the deactivation indication over the C/i channel. The upstream device will then send the deactivation con- firmation command over the C/I channel and stop the IOM-2 clocks. The Am79C30A will detect that the clock has stopped (defined as no clock pulse received for 650 ns) and force itself to the deactivated state. In the deactivated state, SBIN, and SBOUT are both forced to a High-Z state, and the SCLK input is monitored for any rising edge that would indicate an activation request from the upstream device. Activation Once again, activation can originate from either the upstream or the downstream device. To activate the interface from the downstream device, the processor sets the activation/deactivation bit in the PPCR1 regis- ter. This will force the Am79C30A to pull its data output pin (SBIN in this case, since the I/O pin definition is reversed when talking to the upstream device) Low, causing the upstream device to start the 1OM-2 clocks. Once the clocks are running, as indicated by SCLK input going High, the Am79C30A wili generate an [OM-2 timing request interrupt (bit 6 in PPSR). The processor must respond to the interrupt by loading the proper C/I command response into C/ITRDO, then clearing the ac- AMD Pa tivation/deactivation bit in PPCR1. This will release the data output pin (SBIN) from being held Low and allow the processor to complete the activation procedure by sending the proper commands over the C/l channel. When the activation is originated from the upstream device, the AmM79C30A will generate an IOM-2 timing request interrupt (bit 6 in PPSR) when the IOM-2 clocks become active as indicated by the SCLK input pin going High. The Am79C30A will begin normal IOM-2 transmission/reception as soon as SCLK appears; no intervention from the microprocessor is required. How- ever, the processor must respond to the interrupt and perform the normal C/I channel software handshakes before activation will be complete. TIC Bus Operation CAO Channel Arbitration Software control for the IOM-2 Bus Accessed (BAC) bit will be added at bit 7 of CITDRO, which is currently re- served. It will be referred to as the BAR, Bus Access Request bit. This bit will be used to gain access to the CAQ channel when TIC bus support is enabled (PPCR3.3=1). The BAR bit should be set whenever the DSC has C/l0 data available to transmit. When CITDRO.7=1, the TIC bus will arbitrate access to the C/O channel with other devices on the IOM-2 interface using the TIC address programmed into PPCR3.2-0. The TIC bus control Jogic will check to see if the BAC bit on the line is 0 or 1 to determine if another downstream device currently owns the bus. If zero, the DSC will wait. Once a one is detected in BAC, the logic will place the DSC's TIC bus address on the open drain output. It will then sample this output with the |OM-2 received data strobe timing to check for conflict with other downstream devices. If the received TiC address and the contents of PPCR3.2-0 match, the logic will set the BAC output to O indicating to other downstream devices that the DSC has taken control of the D and C/I0 channels. After it sets its BAC output to 0, the logic will compare the TIC address on the line with PPCR3.20 in one more frame to ensure ownership of the bus. If a mis-compare occurs, the DSC will set its BAC output to 1 and return to the beginning of arbitration. Once access is gained, the D and C/i0 channels are the possession of the DSC. This allows the DSC to com- plete C/l0 communication with the Layer 1 device with- out interruption from other downstream devices. (Since the TIC bus is used for arbitration of both D and C/lO channel communication, gaining access for one implicit- ly gives you access to the other). After the DSC com- pletes C/I0 communication, software should set CITDRO.7=6 to aliow other downstream devices access to the D and C/l0 channels. The logic wiil set the BAC bit output of the DSC back to 1, as long as the DSC has no D-channel communications also in progress. Am79C30A/32A Data Sheet 59cl AMD A priority scheme is included to prevent the DSC from dominating the bus. A new bus access will not be al- towed until the device detects BAC bit set to 1 in two successive frames. Care must be taken in use of the Bus Access Request bit (CITDRO.7). As stated above, once access is gained through use of this bit, the DSC will control the D and C/lO channels as long as it remains set. Software must remember to clear this bit to allow other devices access. D-Channel Arbitration When the TIC bus feature is enabled (PPCR3.3=1), the DLC will automatically request TIC bus access without software intervention. The access procedure is much the same as the C/I0 channel above. The TIC bus control logic will check to see if the BAC bit on the line is 0 or 1 to determine if another downstream device currently owns the bus. !f zero, the DSC will wait. Once a one is detected in BAC, the logic will place the DSCs TIC bus address on the open drain output. It will then sample this output at the IOM-2 received data strobe point to check for conflict with other downstream devices. If the received TIC address and the contents of PPCR3.2-0 match, the logic will set the BAC output to 0 indicating to other downstream devices that the DSC has taken control of the D and C/O channels. After is sets its BAC output to 0, the logic will compare the TIC address on the line with PPCR3.2-0 in one more frame to ensure ownership of the bus. If a mis-compare occurs, the DSC will set its BAC output to 1 and retum to the beginning of arbitration. Once access is gained, the D and C/l0 channels are the possession of the DSC. This allows the DSC to com- plete D-channel communications with the Layer 1 de- vice without interruption from other downstream devices. After the DSC completes D-channel commu- nication, logic will set the DSCs BAC bit output back to 1, as long as the BAC request bit (CITDRO.7) is not set. This allows other downstream devices access to the D and C/l0 channels. If CITDRO.7=1, the device assumes C/O communication is still in progress and the BAC out- put remains 0 until software clears CITDRO.7. A priority scheme is included to prevent the DSC from dominating the bus. A new bus access will not be al- lowed until the device detects BAC bit set to 1 in two successive frames. 60 Am79C30A/32A Data SheetPeripheral Port Registers The PP contains the following registers: AMD cl Registers # of Registers Mnemonic Peripheral Port Control Register 3 PPCR1, PPCR2, PPCR 3 Peripheral Port Status Register 1 PPSR Peripheral Port Interrupt Enable Register 1 PPIER Monitor Transmit Data Register 1 MTDR Monitor Receive Data Register 1 MRDR C/l Transmit Data Register 2 CITDRO, CITDR1 C/l Receive Data Register 2 CIRDRO, CIRDR1 Peripheral Port Control Register 1 (PPCR1) Default = 01 Hex Address = Indirect CO Hex, Read/Write 7 6 5 4 3 2 1 9 IOM 2 ACTV/ DEACT MONTR CHANL SELECT MONTR IC CHANL RQST SELECT MONTR ABORT RQST MONTR ENABL Bit Function Monitor Channel Abort RequestThis bit is automatically cleared during RESET or manually by software as follows: to send an ABORT message, software should set this bit, wait at least two frames, then clear the bit. Monitor Channel EnableThis bit only affects 1OM-2 operation. When set, the selected monitor channel is enabled. When cleared, both monitor channels are disabled. Whenever the monitor channel is disabled, the Monitor Transmit and Receive Data Register (MTDR, MRDR) are updated to their default states: MTDR = FFH, MRDR = 00H. Monitor Channel SelectThis bit only affects |OM-2 operation. When set, Monitor channel 1 is used (second subframe). When cleared, Monitor channel 0 is used (first subframe). Monitor End-of-Message RequestWhen set, this bit forces the Monitor channel transmitter to send an EOM once all data written into the Monitor Transmit Data Register has been transmitted. This tells the receiving device that the message is complete. The bit is cleared by hardware when the EOM is sent by reset or by software. IC Channel SelectThis bit only affects |OM-2 operation. When set, the IC2 time slot is used (sixth octet after the frame sync). When cleared, the {C1 time slot is used (fifth octet after the frame sync). The unused channel is always placed in a high-impedance state. 1OM-2 Activation/Deactivation BitThis bit only affects 1OM-2 operation. Note that this bit controls only the start- ing and stopping of SCLK, BCL/CH2STRB, SFS, and the state of the SBIN/SBOUT pins; this alone does not consti- tute activation or deactivation of the IOM-2 bus. The activation/deactivation procedure involves the exchange of a series of commands and indications over the C/I channel. This procedure, including a state diagram, is detailed in the IOM-2 specification. IOM-2 Master modeThis bit is set by software. When deactivated, the master will turn on SCLK, BCL/CH2STRB, and SFS clocks via software by setting this bit when the SBIN pin is pulled Low, indicating that a downstream device wishes to communicate over the interface. The |OM-2 activation/deactivation bit is cleared by software or reset. When cleared, the clocks are stopped, and SBIN is monitored for the reactivation request from the slave (SBIN held Low). [Reset defaults the Peripheral Port to SBP operation.] |OM-2 Slave modeThis bit is set by software to initiate an activation request to the master. When set, the SBIN pin is driven Low, and held Low until the activation/deactivation bit is cleared by software. In response to SBIN going Low the master will start SCLK, which generates a timing request interrupt in the DSC circuit. The activation/ deactivation bit is cleared by software in response to this interrupt. Am79C30A/32A Data Sheet 61O14 aw Peripheral Port Control Register 1 (PPCR1) (continued) Bit Function 1-0 Port Mode Select FieldThese two bits select the configuration of the Peripheral Port as follows. Bit 10 Function 0 0 Port disabled om | SBP mode enabled 1 0 |OM-2 Slave mode enabled 1 $1 IOM-2 Master mode enabled When the port is disabled, SBOUT, SBIN, and all port-related clocks are placed in a high-impedance state. When the DSC circuit is reset, this bit field is set to 01, and the port is not enabled until a MUX MCR register is writ- ten to. If this bit is cleared prior to such a path being programmed, the port will remain disabled until the bit is set via a software write operation. Peripheral Port Status Register (PPSR) Default = Bit 1 = 1, Bits 6-2 and 0 = 0, Bit 7 is Indeterminate Address = Indirect C1 Hex, Read 7 6 5 4 3 2 1 0 CHNG | CHNG MONTR | MONTR |OM-2 ik iN MONTR | MONTR on AONTE RSRVD aM ons Cio ABORT EOM BUFFR DATA RQST DATA DATA RECVD | RECVD AVAIL AVAIL The Peripheral Port Status Register presents various status conditions to the user, and is only used in the lOM-2 mode. Each of these conditions can generate an interrupt to the user. The interrupts are enabled via the Peripheral Port interrupt Enable Register. The state of the respective interrupt enable bits does not affect the setting of bits in this register. Bits 6, 3, and 2 are cleared when this register is read. Bit 1 is cleared when the Data Register is written, and bit 0 is cleared when the Data Register is read. In addition, bits 3, 2, 1, and O are cleared when the Monitor channel is disabled (via bit 6 of the PPCR1 Register). Because bit 7 is reserved, the default value of this register is either O2H or 82H. Bit Function 6 1OM-2 Timing RequestWhen the DSC circuit is the upstream device (master made), this bit is set by hardware to indi- cate that a downstream device has requested the starting of the |OM-2 clocks. The clocks are started by software. This bit does not indicate the receipt of an activation request on the C/I channel. When the DSC circuit is the downstream compo- nent (slave mode), this bit is set in response to SCLK starting (going High) when the bus is deactivated. Notes: The DSC circuit will not exit Power-Down mode in response to either a timing request or the clocks being started if this interrupt is masked. It is essential that an interrupt be generated when the DSC circuit leaves Power-Down mode. Other- wise, power consumption could increase significantly without the processor's knowledge. 5 Change in C/l1 Channel StatusThis bit is set by hardware to indicate that the contents on the receive side of C/l channel 1 have changed since the C/I Receive Data Register was last read. 4 Change in CAO Channel StatusThis bit is set by hardware to indicate that the contents on the receive side of C/l channel 0 have changed since the C/I Receive Data Register was last read. 3 Monitor Channel Abort Request ReceivedThis bit is set by hardware to indicate that an abort request has been re- ceived on the monitor channel. This indicates that the receiver on the other end of the Monitor channel has failed to re- ceive the transmitted data correctly and wishes that the current transmission be discontinued and the data transmission repeated via software. 2 Monitor Channel End-of-Message Indication ReceivedThis bit is set by hardware to indicate that an EOM has been received on the monitor channel. This indicates that the message currently being received has concluded. 1 Monitor Channel Transmit Buffer AvailableThis bit is set by hardware to indicate that a new byte of data can be loaded into the Monitor Transmit Data Register. 0 Monitor Channel Receive Data AvailableThis bit is set by hardware to indicate that a byte of data has been received on the monitor channel and is available in the Monitor Receive Data Register. 62 Am79C30A/32A Data SheetPeripheral Port Interrupt Enable Register (PPIER) = 1 Default = Write = 00 Hex, Read = Bit 7 = 1, Bits 6-0 = 0 Address = Indirect C2 Hex, Read/Write 7 6 5 4 3 2 1 0 ENABL ENABL ENABL ENABL ENABL CHNG CHNG ENABL ENABL MONTR | MONTR PP/MF 1OM 2 MONTR | MONTR IN IN XMIT RECV INT EN TIME cit C/o ABORT EOM BUFFR DATA ROQST RECVD RECVD DATA DATA AVAIL AVAIL The Peripheral Port Interrupt Enable Register provides an individual interrupt-enable bit corresponding with each of the status conditions in the Peripheral Port Status Register. When set, the interrupt is enabled. Clearing the bit disables the interrupt. These bits are set and cleared by software. Bit Function 7 PP/MF Interrupt EnableWhen set, this bit enables the Peripheral Port and Multiframing interrupts. When cleared, the PP and MF interrupts are disabled. Notes: To ensure proper interrupt reporting, software must disable PP/MF interrupts when the interrupt routine is entered and enable them when exiting. Monitor Transmit Data Register (MTDR) Default = FF Hex Address = Indirect C3 Hex, Write 7 6 5 4 3 2 1 0 pare DATA DATA DATA DATA DATA DATA BATA (MsB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 4 (so) The Monitor Transmit Data Register is the user-visible portion of the Monitor channel Transmitter Data buffer. Data is written into this register by the user in response to a monitor transmit buffer available interrupt. It is then transmitted to the receiver on the other side of the IOM-2 bus. The MTDR is emptied when the PP is reset. Monitor Receive Data Register (MRDR) Default = 00 Hex Address = Indirect C3 Hex, Read 7 6 5 4 3 2 1 0 para DATA DATA DATA DATA DATA DATA pa , (MsB) BIT 6 BITS BIT 4 BIT 3 BIT 2 BIT 1 ise The Monitor Receive Data Register is the user-visible portion of the Monitor channel Receiver Data buffer. Data is written into this register by the hardware as it is received over the monitor channel. A monitor data available interrupt is generated when the register is loaded. The register is overwritten by hardware only after the register has been read. The default on reset is 00 hex. Am79C30A/32A Data Sheet 63cl AMD CA Transmit Data Register 0 (CATDRO) Default = OF Hex Address = Indirect C4 Hex, Write 7 6 5 4 3 2 1 0 clo Clo Clo cio Bus Access | asryp RSRVD RSRVD DATA DATA DATA DATA Request BIT 3 BIT 2 BIT 1 BIT 0 (MSB) (LSB) The C/l Transmit Data Register 0 is the user-visible portion of the C/I channel O transmitter. Data can be written into this register by the user at any time and is transmitted continuously during each subsequent frame until changed. The register is set to its default value, OF hex (C/I channet idle), by reset or disabling of the Peripheral Port. Bus access request bitWhen set, the DSC will attempt to gain access to the C/lO0 channel if TIC bus is enabled. C/l Receive Data Register 0 (CARDRO) Default = XF Hex Address = Indirect C4 Hex, Read 7 6 5 4 3 2 1 0 CIO C/o Clo Clo RSRVD RSRVD RSRVD RSRVD DATA DATA DATA DATA (use) BIT 2 BIT 1 (se) The C/l Receive Data Register 0 contains data valid for two frames from C/l Receive channel 0. The register is set to its default value of XF hex by a reset or the disabling of the Peripheral Port. C/l Transmit Data Register 1 (CATDR1) Default = 3F Hex Address = Indirect C5 Hex, Write 7 6 5 4 3 2 1 0 CA Chi cit ci c/l1 cil RSRVD RSRVD DATA DATA DATA DATA DATA Dara (HSB) BIT 4 BIT 3 BIT 2 BIT 4 (so) The C/ Transmit Data Register 1 is the user-visible portion of the C/ channel 1 transmitter. Data can be written into this register by the user at any time. It is transmitted continuously during each subsequent frame until changed. The regis- ter is set to its default value, 3F hex (C/I channel idle), by reset or disabling of the Peripheral Port. C/l Receive Data Register 1 (C/IRDR1) Default = Bits 7 and 6 are Indeterminate, Bits 5-0 = 1 Address = Indirect C5 Hex, Read 7 6 5 4 3 2 1 0 CA cyt cit Cit cit cM RSRVD RSRVD DAT 5 DATA DATA DATA DATA aaa (Mss) BIT 4 BIT 3 BIT 2 BIT 1 eS The C/I Receive Data Register 1 contains the data (valid for two frames) from C/I Receive channel 1. The register is set to its default value by a reset or the disabling of the Peripheral Port. 64 Am79C30A/32A Data SheetAMD at Peripheral Port Control Register 2 (PPCR2) Default = Bits 7, 6, and 0 = 0, Bit 5 = 1, Bits 41 are Indeterminate* Address = Indirect C8 Hex, Read/Write 7 6 5 4 3 2 1 0 REV REV REV SCLK CODE CODE CODE RSRVD RSRVD ASRVD RSRVD INVAT BIT 2 BIT 1 BIT 0 ENABL (MSB) (LSB) The Peripheral Port Control Register 2 controls the inversion of the SCLK output in SBP mode. This provides flexibility in the connection of peripheral devices to the DSC circuit. The hardware revision code is also contained in this register, which allows software to identity the revision of the hardware. Note: * The default value is revision-level dependent. Revision E will report a hardware revision code of 001. Bit Function 7-5 Hardware Revision CodeThis read-only fieid reports the hardware revision level. Revision E of the DSC circuit will report a hardware revision code of 010. SCLK Inversion EnableWhen set, the SCLK output is inverted in SBP mode. When cleared, the SCLK output is identi- cal to the Revision D DSC circuit. This bit should not be changed while SCLK is enabled. Peripheral Port Control Register 3 (PPCR3) Default = Bits 7-5 are Indeterminate, Bit 4=1, Bit 3=0, Bits 2-0= 1 Address = Indirect C9 Hex, Read/Write 7 6 5 4 3 2 1 0 SLAVE RESERVED| RESERVED | RESERVED | MODE BUS| nage | ADDHESS | ADDRESS | AGBEESS REVERSAL Bit Function 7-5 RESERVED 4 SLAVE Mode Bus ReversalPPCR3.4 controls the bus reversal function of the DSCs IOM-2 SLAVE mode. By default (PPCR3.4=1) the Slave bus reverses to ensure backwards compatibility with previous revisions. When PPCR3.4=0 the 1OM-2 bus will not reverse in SLAVE mode. This assures slave compatibility of the control function and allows use with devices such as the ISAC-S. 3 TIC Bus EnablePPCR3.3 controls enabling and disabling of TIC bus operation. When PPCR3.3=0 which is the default condition, the IOM-2 bus will not support the TIC bus feature to ensure backwards compatibility with previous IOM-2 capable revisions of the 79C30A. The TIC bus control logic features are only enabled if PPCR3.3=1. Features enabled when PPCR3.3=1 S/G bit . When the DSC is in IOM-2 MASTER mode the CTS output of the LIU is used to drive the transmitted S/G bit. This signal indicates D-channel Clear To Send status and is set when the LIU collision detection logic fulfills the pro- grammed priority level requirements. When in IOM-2 SLAVE mode the received S/G bit is used as the Clear To Send input into the DLC block. IT ress Bus an ccessed Refer to TIC bus operation section. 2-0 TIC Bus AddressDevice address to be used on TIC bus. Default is 111. Am79C30A/32A Data Sheet 65at AMD APPLICATIONS ISDN Feature Phone This basic feature phone is the ISDN equivalent to the common analog phone. The keypad can be a simple four-by-four single-pole switch-matrix or a larger-matrix to provide full-key system features. The display option illustrated in Figure 14 can be included in any of the applications shown in this section. ISDN Feature Phone with Parallel and Serial Data Ports Plus Other Peripherals Access to the CCITT R reference interface is provided via both the serial and parallel ports in Figure 15. This application may easily have voice capability added by using a DSC circuit in place of the IDC circuit. Figure 16 illustrates applications with increased B-channel data processing requirements. Am79C30A DSC Circuit ere Audio Telephone Processor B-Channel |_| Surge [3 st s- pp MUX = LIU Protection =) oT Interface Hook Switc D-Channel OSC MPI DLC MCLK Interrupt RAM ROM y y Power Reversal Interrupt Power . lp ee Controller Microcontroller L__ 7 5V Ba Bd BS LCD Displ Keypad splay 09893E-011 Figure 14. ISDN Telephone 66 Am79C30A/32A Data SheetAMD cl Terminal Interface YA Speaker PSB2110 ISDN Terminal Adaptor Circuit V.110 Processor Am79C32A IDC Circuit Serial E} eS Terminal |_| Port} ty + Liv Surge | S/T interface Port pp B-Channel Protection . MUX | 3 UART HDLC | | osc MPI D-Channel DLC FIFO FIFO Microprocessor Interface MCLK Power Reversal Interrupt Interrupts 3h vy y RAM ROM Power Microcontroller Controller + | ~ 5Yy 09893E-012 Figure 15. Terminal Adapter (V.110/V.120) With Voice Upgrade Capability Am79C30A/32A Data Sheet 67al AMD Analog Telephone Interface AmB5C30 or PSBB2525 Am79C30A DSC Circuit Audio Data Link Data Link Processor Controller Controller [7 B-Channel |_| LIU Surge [3 f -| PP Pt mux Protection SIT Microprocessor Interface 3 | MPI p-channel DMA Controller 80188 DMA Dual-Port | Dual-Port Optional Timers RAM RAM ROM DRAM | Program Controller] Interface Controller Memory Interrupts et CPU Am85C30/PSB82525 |+___ > Chip DSC Circuit PC Bus Selects Interface Memory Clock PC Bus 09893E-015 Figure 16. PC Add-On Board (1 or 2 Data Channels) 68 Am79C30A/32A Data SheetELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Storage temperature ............. 65C to +150C Ambient temperature with power applied .............. -55C to +125C Supply voltage to ground, potential continuous ................. OVto+7.0V Lead temperature (soldering, 10 sec) ........ 300C Maximum power dissipation ................ 1.5 W Voltage from any PINTO Vss oe ee eee eee ee Vss 0.5 V to Veo + 0.5 V DC input/output current (except LS1,LS2) .................0.008. 10mA DC output current, LS1, LS2 only........... 100 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum rat- ings for extended periods may affect device reliability. AMD il Operating Ranges Commercial (C) devices Operating Vcc range with respect tO Veg oe cece cee eee eee eens 4.75 V to 5.25 V Ambient temperature (T,).........-... OC to +70C Operating Ranges define those limits between which the functionality of the device is guaranteed. DC Characteristics over Commercial Operating Ranges (unless otherwise specified) Preliminary Parameter Parameter Descriptions Test Conditions Min Max Unit Symbol Vin Input High Level, except XTAL2 2.0 Veco + 25 Vv Vine Input High Level XTAL2 0.80 Voc Veco + 25 Vv Vit Input Low Level Vsg 0.25 0.80 v Vor Output Low Level, except SBOUT | lo. = 2 mA 0.40 Vv Output Low Level, SBOUT only lop = 7 mA 0.40 Von Output High Level lon = 400 pA 2.4 Vv =-10 yA 0.90 Vee lon Output Leakage Current 0 < Vout < Voc +10 pA Output in High-Z State li Input Leakage Current O< Vin < Veco Digital Inputs 10 LA LIN1/LIN2 + 200 pA XTAL2 5.5 (TYP) pA Cy Input Capacitance Temp = 25C 10 (TYP) pF Digital Input Freq = 1 MHz Co Output Capacitance Temp = 25C 10 (TYP) pF Digital Input/Output Freq = 1 MHz Am79C30A/32A Data Sheet 69at AMD Table 51. Revision E Power Specifications for CCITT-Restricted Mode Phone Operation Preliminary Parameter Symbol | Parameter Descriptions Test Conditions Typ Max Unit Veco Supply Current Voc = 5.25 V: Vin = Voc: Vit = Vssi mode = loc 0 Power-Down; Clocks & Oscillator Stopped; LIU 4 5 mw (Power-Down mode) Receiver Enabled; S Interface Silent (INFO 0) Voc Supply Current Vec = 5.25 Vi Vin = Veci Vit = Vgsi mode = Idle; lec fuctx = 384 kHz; LIU Receiver Enabled; 20 25 mw (Idle mode) S Interface Silent (INFO 0) Vee = 5.25 V; Vin = Voc} Vi. = Vssi mode = Active, Vec Supply Current Data Only; fick = 3.072 MHz; LIU Receiver loc2 and Transmitter Enabled; S Interface Activated 80 105 mw (Active; Call Set-Up) with Data on D-channel Only; S-interface Load = 50 ohms Voc = 5.25 Vi Vin = Veci Vit = Vssi mode = Active Voice & Data: fucix = 384 MHz; LIU Receiver Voc Supply Current and Transmitter Enabled; S Interface Activated 155 190 mw lees with Data on D-channel and one B-channei; (Active; Voice mode) S-interface Load = 50 ohms; AINA = 15 dBm0, 1-kHz Sine Wave; EAR1/EAR2 = -15 dBm0, 1-kHz Tone Driving 600 ohms Vec = 5.25 V; Vin = Voci Vi = Ves; mode = Active, Data Only; fuct = 384 kHz; LIU Receiver loc4 Vcc Supply Current and Transmitter Enabled; S Interface Activated 125 150 mW (Active; Ringing, No Load") with Data on D-channel Only; S-interface Load = 50 ohms; Secondary Tone Ringer Enabled at 0 dB, 400 Hz, No Load Note: All power measurements assume PP disabled or in |OM-2 Deactivated mode. *Power consumption with the output loaded will be Iccd + Nour peak) peak) (Vee) LOAD For Rioap = 50 ohms and Voy; = ~12 dB (625 mV, peak), the maximum power consumption will be 215 mW. AC Characteristics Voc = 5 V 5%; Ves = OV; Ty = 0C to 70C; MCLK = 3.072 MHz Table 52. MAP Analog Characteristics (Am79C30A only) Preliminary Parameter Symbol | Parameter Descriptions Test Conditions Min Typ Max | Unit Analog Input Impedance 1.25 V <Vin <4+1.25V 2 Zw AINA or AINB to AREF fin <4 KHz 00 Kohm Allowable Offset Voltage . : Vios at AINA or AINB with respect to AREF pin -5 +5 mV Rioap > 40 ohms Lis Allowable Load LS1 to LS2 and Cioap < 100 pF Rioap > 540 ohms Lear Allowable Load EAR1 to EAR2 and Croan < 100 pF Rioap > 1 Kohm Lancer Allowable Load AREF to Vsg or Voc and Cioap < 100 pF Varner Analog Reference Voltage 2.1 2.25 2.4 Vv 70 Am79C30A/32A Data SheetMAP Transmission Characteristics (Am79C30A only) The codec is designed to meet CCIIT Recommendation G.714 requirements for signal to distortion, gain track- ing, frequency response, and idle channel noise specifi- cation as defined in Table 53. Verification of conformance to G.714 is by device characterization. Production testing of individual parts includes those pa- rameters shown in Table 54. Half-channel parameters are specified from AINA or AINB input pins to a B channel for the transmit path, and AMD at from a B channel to EAR1/EAR2 or LS1/LS2 pins mea- sured differentially for the receive path. These parame- ters are applicable for both A- or p-law conversion. (A-law assumes psophometetric filtering, and p-law as- sumes C-message weighting). All parameters are speci- fied with the GR, X, R, GX and GER filters disabled; STG filter is enabled but programmed for infinite attenuation. All values are for Vec=5V +5%, TA = 0-70C, and pro- grammable filters/gains disabled (0 dB, flat) unless otherwise indicated. Table 53. MAP Transmission Characteristics (Am79C30A only) Preliminary Parameter Symbo! | Parameter Descriptions Test Conditions Min Typ Max Unit *50 Hz-60 Hz 24.0 dB < 300 Hz -0.25 dB Transmit Frequency Response 0.3 kHz-3.0 kHz -0.25 +0.25 dB TXF (Attenuation vs Frequency Relative to 3.0 kHz--3.4 kHz 0.25 +0.9 dB -10 dBm0 at 1020 Hz)see Figure 17 | 3.4 kHz-3.6 kHz -0.25 dB 3.6 kHz-3.9 kHz 0.0 dB 3.9 kHz4.0 kHz 9.0 dB < 300 Hz 0.25 dB Receive Frequency Response 0.3 kHz-3.0 kHz -0.25 + 0.25 dB RXF (Attenuation vs Frequency Relative to 3.0 kKHz-3.4 kHz 0.25 +0.9 dB ~10 dBm0 at 1020 Hz)-see Figure 21 | 3.4 kHz-3.6 kHz -0.25 dB 3.6 kHz-3.9 kHz 0.0 dB 3.9 kHz-4.0 kHz 9.0 dB Transmit Group Delay Variation 500 Hz-600 Hz 750 ys TxD vs Frequency at -10 dBm0 Relative 600 Hz~1000 Hz 380 ys to Minimum Delay Frequencysee 1.0 kHz2.6 kHz 130 Hs Figure 18 2.6 kHz2.8 kHz 750 us Receive Group Delay Variation 500 Hz600 Hz 750 ps RXD vs Frequency at 10 dBm0 Relative 600 Hz~1000 Hz 380 us to Minimum Delay Frequencysee 1.0 kHz-2.6 kHz 130 us Figure 22 2.6 KHz-2.8 kHz 750 us Transmit Signal/Total Distortion vs 0 to -30 dBmO 35.0 dB TXSTD Level; CCITT Method 2, 1020 Hz 40 dBm0 29.0 dB {Transmit Gain = 0dB)see Figure 20 | -45 dBm0O 24.0 dB Receive Signal/Total Distortion vs 0 to -30 dBmo 35.0 dB RXSTD | Level; CCITT Method 2, 1020 Hz ~40 dBmO 29.0 dB (Transmit Gain = 0dB)see Figure 24 | -45 dBm0 24.0 dB Transmit Gain Tracking vs Level; +3 to 40 dBm0 -0.3 + 0.3 dB TXGT CCITT Method 2, 1020 Hz (Transmit 40 to -50 dBmo -0.6 +06 dB Gain = 0 dB)see Figure 19 -50 to -55 dBmo -1.6 +16 dB Receive Gain Tracking vs Level; +3 to 40 dBm0 -0.3 +0.3 dB RXGT CCITT Method 2, 1020 Hz (Receive -40 to -50 dBm0 -0.6 + 0.6 dB Gain = 0 dB)see Figure 23 50 to -55 dBm0 ~1.6 + 1.6 dB GX = 0 dB, GA=0 dB -82 ~78 dBmo Transmit Idle channel Noise GX = 6 dB, GA=0dB -79 -76 dBm0 TXICN AINA or AINB Connected GX = 6 dB, GA = 6 dB -76 -72 dBmo to AREF GX = 6 dB, GA = 12 dB -73 -69 dBmo GX =6 dB, GA= 18 dB -70 -66 dBmo . : GR = 0 dB, GER = 0 dB -90 85 dBmo RXICN Receive Idle channel Noise GR = -12 dB, GER = 0 4B 80 _75 dBmo Note: *Measured with the high pass filter and auto-zero enabled in MMR2. Am79C30A/32A Data Sheet 71il AMD Table 54. Codec Performance Specifications (Am79C30A Only) Symbol | Description Test Conditions Min Max Unit TXG Transmit absolute gain 0 dBm0; 1020 Hz; Vec=5V +5%, TA = 0.50 +0,50 dB 0C-70C; over all GA RXGE Receive absolute gain at EAR1/EAR2 0 dBm0; 1020 Hz; Vec=5V +5%, TA = 0.50 +0.50 dB (nominal) 0C-70C; Rload = 540 ohms RXGL Receive absolute gain 0 dBm0; 1020 Hz; Vcc=5V +5%, TA = 0.80 +0.80 dB 0C-70C; Rload = 40 ohms TXSTD | Transmit signal/total distortion; CCITT | -10 dBm0 35 dB method 2, 1020 Hz (Tx gain = 0) 45 dBmo 24 RXSTD_ | Receive signal/total distortion; CCITT -10 dBmo 35 dB method 2, 1020 Hz (Rx gain = 0) -45 dBmo 24 TXGT Transmit gain tracking; CCITT method | -45 0.60 +0.60 dB 2. 1020 Hz (Tx gain = 0) RXGT Receive gain tracking; CCITT method =| -45 0.60 +0.60 dB 2, 1020 Hz (Rx gain = 0) TXICN | Transmit Idle channel Noise AINA con- | GX=6 dB, GA=18 dB -66 dB nected to AREF RXICN | Receive Idle channel Noise GR=-12 dB, GER = 0 dB ~75 dB Notes: The following test conditions apply to aif MAP tests: 1. Anexternal 1-Kohm+ 5% resistor and 2200-pF + 10% capacitor are connected in series between the CAP1 and CAP2 pins for all transmit tests. a Rw performance may occur if used single ended rather than differential. Transmitter 0-dB Reference Point: All tests are half-channel with the sidetone path enabled but programmed for infinite attenuation (STG = 9008 hex). Transmit specs are tested and guaranteed with the input signal source referenced to AREF; see test circuit below. Receive specs are guaranteed for both EAR1/EAR2 and LS1/LS2 outputs measured differentially. Some degradation in Transmit specs are guaranteed for both AINA and AINB inputs with the auto-zero and high-pass filters enabled in MMR2. Nominal input voltage at AINA or AINB will produce a 0-dBm, 1-kHz digital code at the transmit output with all transmit gains at 0 dB. A law ut law = 625mV rms = 620 mV rms Receiver 0-dB Reference Point: Nominal output voltage between EAR 1/EAR2 or LS1/LS2 resulting from a 0-dBm, 1-kHz digital code at the receive input with all receive A law p law gains at 0 dB. = 1.25V rms = 1.2V rms Transmit Test Circuit with Input Source Referenced to AREF 0.1 LF AINA or AINB 100K AREF 72 Am79C30A/32A Data SheetAMD cl 24 0B - y 9dB 7 co Mf} 0.9 Perf prc ccc crt r ttre ster e sere eee 47-4 A] A: - | ; S va ' 5 a ' 3 | 5 LL] : < LL] 02-1. VALASSIS LLLLLL LLL oe i ob<--s weer eee O- ----------------------- enh <p LT : : ' ; | 4 0.25 an 7 TTT A 50 60 300 1020 3000 34003600 3900 Frequency (Hz) TO 09893E-016 Figure 17. Attenuation/Frequency Distortion (Transmit) | 750 L..---L4,--------- eee eee 1 OD ' 3 t > + 3 = ' 9 ' 2 380 , 9 ' 9 ' 130 ' |} 2600 2800 Frequency (Hz) __<$___> 09893E-017 Figure 18. Group Delay Variation with Frequency (Transmit) Am79C30A/32A Data Sheet 73Gain Variation (dB) ~- | rN | T T 40 -10 +3 > , Input Level (dBm0) _____ 09893E-018 Figure 19. Gain Tracking Error (Transmit) (CCITT Method 2 at 1020 Hz) 74 Am79C30A/32A Data SheetSignai-to-Total Distortion Ratio (dB) AMD cl Fo ee ag PT occ f ' 24 Fe <c reece cree 1 : ; 1 9 + T T 45 40 -30 -10 0 Input Level (dBm0) 09893E-019 Figure 20. Signal-to-Total Distortion Ratio (Transmit) (CCITT Method 2 at 1020 Hz) 0.9 o = c s o 3 = o = zt 0.25 0 0.25 9 dB 7 a LZ 4 L LL7 Zz pm r vores oo SS See eens : * e 7 ' 1 4 ' c a : 1 300 1020 3000 3400 3600 3900 Frequency (Hz) =O 09893E-020 Figure 21. Attenuation/Frequency Distortion (Receive) Am79C30A/32A Data Sheet 75al AMD 750 JL eee Pe) ee ee eee eee eg A: A 3 s t o A 3 380 A 3 3 to a3 Oo ' 1 4 : 130 P-.--- tedeeeee Lo Lf fe ' my : to Li i jt 500 600 1000 2600 2800 Frequency (Hz) _______ 09893E-021 Figure 22. Group Delay Variation with Frequency (Receive) 1 ' 0.6 ao . 7 ' YY ogb----t--s------ L222 Zz | z tot z | | 4 | c Tr I Y 1 2 -55 -50 40 ~10 + 5 ' ! ' ' = 03 }- = 2 ber tonne ee TTIW 77 77 7 & 06 ----1-- : Input Level (dBmQ) ______________ -16 J----] | 09893E-022 Figure 23. Gain Tracking Error (Receive) (CCITT Method 2 at 1020 Hz) 76 Am79C30A/32A Data SheetSignal-to-Total Distortion Ratio (dB) AMD lt | -10 0 Oman rr rr ce et er ee ee eee ee ee ee eee ~45 40 eo input Level (dBm0) Figure 24. Signal-to-Total-Distortion Ratio (Receive) (CCITT Method 2 at 1020 Hz) 09893E-023 Am79C30A/32A Data Sheet 77at AMD LIU Characteristics All of the parameters below are measured at the chip terminals and are consistent with 2:1 transformers. Preliminary Parameter Symbol | Parameter Descriptions Min Typ Max Unit Viour Output mark amplitude measured between LOUT2 and LOUT1 (Note 1) | 2.210 2.326 2.442 Vv Receivable input level measured between LIN2 and LIN1, with noise Vu added as specified by CCITT 1.430 section 8.6.2.1 (Note 2) 530 1800 mv Zour Output impedance measured between LOUT2 and LOUT1 20 Kohm spacing condition Zin Input impedance measured between LIN2 and LIN1 20 Kohm J Timing extraction jitter on LOUT -7 +7 % PD Total phase deviation (LOUT with respect to LIN) -7 +15 % PU Pulse unbalanced measured between LOUT2 and LOUT1 (Note 1) -5 +5 % PW Output pulse width measured between LOUT2 and LOUT1 (Note 1) 4.7 5.2 5.7 us Notes: 1. See the equivalent test load circuit and pulse template in Figures 26 and 27. 2. The 530-mV receive input level is equivalent to 9.0 dB of attenuation from a nominal transmit level when measured at the LIN pins. Allowing 0.5-dB loss in the isolation transformer, and 1.0-dB loss in the input isolation resistors, this level will guarantee compliance to the CCITT receiver sensitivity spec of 7.5 dB when measured at the S reference point. 3. Typical receiver performance is 220 mV. 78 Am79C30A/32A Data SheetAMD zl Ro 2:1 LOUT2 + ANA o tT O+ Viour 3 z Ri T. Cc. Vs-reference) LOUT1 - Wy + oO Ry Rs 2:1 LINt AW T 0 3 t zn, T Cc. Vis-reference) LIN2 WA + O Ay 09893E-024 Notes: 1. 2. RF, is the termination impedance at the S interface. 3. 4. Fi, and Rp are the transmitter output series resistors; their value depends upon the characteristics of the pulse transformer Vis.intertace): Transmitter output at the S-interface reference point. C, is the effective capacitance at the S interface. (see Figure 28). R; and Ry are required for multipoint operation to prevent loading of the line when power is removed from the terminal. Figure 25. System Interface to LIU High Mark 50 ohms LOUT2 +] 50% LOUTT Low Mark 50 ohms b c 09893E-025 Pu _ High Mark ~ 6 Low Mark a b 09893E-026 Figure 26. Equivalent Test Figure 27. Differential Output Signals Load Conditions Between LOUT2, and LOUT1 (Using the Test Circuit in Figure 24) Am79C30A/32A Data Sheet 79at AMD lLour 2 > A Rsec Ferm @ N2 Rcoro * N LOUT2 + MAN Wy WN Vout A, N2 LOUT1 - Ny Ry 09893E-027 Notes: 1. Asec is the DC impedance of the transformer secondary (IC side of transformer). FApaim is the DC impedance of the transformer primary (line side of transformer). Fooro is the DC impedance of the TE connecting cord: typically 4-6 ohms. N is the transformer turns ratio (N = 2 for Am79C30A/32A). F, is the S-interface line impedance (50 ohms). hour is the desired load current for the CCITT transmission templates (7.5 mA for 50-ohm line). V.our is the nominal output voltage from the DSC/ADC line driver. N22 OR & Figure 28. Equivalent DC Circuit at LOUT Pins for calculation of R, and R, Series Resistor Calculations Equation 1 Tour = Viour R, + Ri + Reec + (Ream N) + (Ry N*) + (Reoro * N*) Equation 2 R,+R:= (Vout) Rsec ~ (Renin N?) -(Re N?) ~ (Reorp N?) (ILour) Equation 3 Let Ri = R: Equation 4 V, > R,=R:= 4 Rsec (Ream N?) ~(Ri N?) (Reorv * N*) } 2 Tout Notes: N=2 R, = 50 ohms Viout = 2.326 Vv hour = 7.5 mA Equation 5 R, = R, = 55.067 1/2 { Rsec + (4 Reria) + (4 Reorp) } Equation 5 should be used to determine the value of R, and R, for the particular transformer used by each customer. 80 Am79C30A/32A Data SheetAMD et Microprocessor Read/Write Timing Microprocessor Read Timing Parameter Parameter Symbol Description Min Max Units fata RD Pulse Width 200 ns TAHAL Read Recovery Time (Notes 1. 2) 200 ns tava Address Valid to RD Low 20 ns tay Address Hold After RD High 10 ns taHcH RD High to CS High (Note 7) 0 ns tracc Read Access Time (Nate 3) 80 ns tanpz RD High to Data Hi-Z . 50 ns tapcs RD Low to CS Low (Note 4) 30 ns Microprocessor Write Timing Parameter Parameter Symbol Description Min Max Units twowH WR Pulse Width 200 ns twHwe Write Recovery Time (Note 1) 200 ns tavwe Address Valid to WR Low 20 ns taHwH Address Hold After WR High (Note 8) 10 ns twrcr WR High to CS High (Note 7) 0 ns toswu Data Setup to WR High 100 ns toHwH Data Hold After WR High 10 ns twacs WR Low to CS Low (Note 4) 30 ns Notes: 1. The read/write recovery time of 200 ns holds in all cases except when a write command register operation is followed by a read data register operation when accessing the MAP coefficient RAM. This operation requires a minimum recovery time of 450 ns. 2. Successive reads of the D-Channel Receive Buffer require a minimum cycle time (eau + tanp.) of 480 ns. 3. Read access time is measured from the falling edge of CS or the falling edge of RD. whichever occurs last. 4. CS may go Low before either AD or WR goes Low. 5. in minimal systems, CS may be tied Low. 6. Read and write indirect register operations cannot be mixed without at least one write command register operation between them. 7.TS may go High before either RD or WR goes High. 8. IfCS goes High before WR goes High, the minimum Address Hold time becomes 12 ns. 9. RD andWR pulse width, Address setup and hold, and Data setup and hold timing are measured from the points where bothTS and RD or WR are Low simultaneously. Am79C30A/32A Data Sheet 81i AMD ApOR tavAL <> lee} tare tavwe o> me CO > trocs > twrcs cs \ + tRHcH > twren e ternH phe taHAL tre ROWR N Read / Read Write trace ele terHnz e toHwH DATA CS 09893E--028 Figure 29. Microprocessor Read/Write Timing Interrupt Timing Parameter Parameter Symbol Description Min Max Units tintc INT Cycle Time 125 us trec INT Recovery Time 500 ns tntc > INT Figure 30. INT Timing 09893E-029 82 Am79C30A/32A Data SheetAMD al Reset and Hookswitch Timing Reset Timing Parameter Parameter Symbol Description Min Max Units. tres Reset Pulse Width 1 us teyAc Power Stable to Reset Low 1 HS tr Reset Transition Fall Time 1 ms ta Reset Transition Rise Time 20 ps Hookswitch Timing Parameter Parameter Symbol Description Min Max Units ts Debounce Time 16 16.25 ms ty HSW Detected to INT Delay ) 370 us Note: Due to clock start-up times, the hookswitch Min and Max Debounce times are approximately 3 ms greater in Power-Down Mode. 4.75V V ee a teyAL > Ve oF Vi RESET he tres p E 09893E-030 Figure 31. Reset Timing " LN 09893E-031 Figure 32. Hookswitch Debounce Timing Am79C30A4/32A Data Sheet 83il AMD OSC (XTAL2) Timing Parameter Parameter Test Symbol Description Conditions Min Max Units teteL Oscillator Period 81.374 81.387 ns tou High Time 33 ns tet Low Time 33 ns teicH Rise Time 10 ns tence Fail Time 10 ns Note: Frequency = 12.288 MHz +80 ppm. MCLK Timing Parameter Parameter Test Symbol Description Conditions Min Max Units to XTAL2 Voc/2 to MCLK Load < 80pF 60 ns MCLK Voc /2 taiser Rise Time MCLK Load < 80pF 15 ns 0.5 V to (Vgc-0.5V) trise2 Rise Time MCLK Load < 40pF 5 ns 1.0Vto3.5V teauui Fall Time MCLK Load < 80pF 15 ns (Vec~-0.5V) to 0.5 V trate Fall Time MCLK Load < 40pF 5 ns 3.5Vto10V tewy High Pulse 12.288 MHz MCLK Load < 80pF 33 ns Width 6.144 MHz 73 ns 4.069 MHz 114 ns 3.072 MHz 155 ns 1.536 MHz 317 ns 768 kHz 643 ns 384 kHz 1.294 ps tewL Low Pulse 12.288 MHz MCLK Load < 80pF 33 ns Width 6.144 MHz 73 ns 4.096 MHz 114 ns 3.072 MHz 155 ns 1.536 MHz 317 ns 768 kHz 643 ns 384 kHz 1.294 pS } torch -< tenc. k 0.5V NPY NK < tcl _> bg $$ tcc Eee Note: *Not TTL Vin 09893E-032 Figure 33. External Clock Driver (XTAL2) Timing 84 Am79C30A/32A Data SheetAMD at + tb so tT VS VS VS ANS NSN NN NS Osc Vec/2 ovary: F LS LS VS VSL LVS VY VA 12.288 MHz Divide by 2 F \ fo VS LYS NL TL 6.144 MHz Divide by 3 K \ ff 7" 4.096 MHz tra 12 w]le >|be trise 12 Divide by4__f 4 f 3.072 MHz eto, -| | __ tps < teLk 09893E-033 Figure 34. OSC/MCLK Timing SBP Mode Timing Parameter Parameter Test Symbol Description Conditions Min Max Units Tp" SCLK 5.025 5.392 ps Ta High time 2.594 2.615 ps Tb* Low time 2.431 2.777 us trise SCLK rise time SCLK Load < 80pF 20 ns tau SCLK fall time SCLK Load < 80pF 20 ns tucsc MCLK to SCLK MCLK Load < 80pF 60 ns @6.144 MHz SCLK Load < 80pF tours SCLK High to 50 250 ns frame sync tcLpo SBOUT SBOUT/SFS 50 250 ns Data available Load = 80 pF toicH SBIN set-up time 200 ns teHoz SBIN hold time 0 ns Noie: *The frequency of SCLK is fyraiz /64. Tp and Tb are based on this SCLK frequency but include a +163-ns allowance for internal-phase lock-loop correction. Am79C30A/32A Data Sheet 85at AMD Ta Th Tp le he ie sox J UU UU U UU UU UU UU UU Ue sBIN or spout. XX XX XX XXX XXX XXX XXX XXX KOO | Bd >|__ Be +|+_. Bt >| srs | [ }+ 11 -| |+ 11 >| 09893E-034 Notes: 1, ForPPCR2(0) = 0, SBIN data is sampled on the rising edge of SCLK; SBOUT data is changed on the falling edge of SCLK. For PPCR2(0) = 1, SBIN data is sampled on the falling edge of SCLK; SBOUT data is changed on the rising edge of SCLK. 2. T1 width is eight SCLK periods. Figure 35. SBP Mode Timing MCLK (6.144 MHz) tuesc SCLK(192KHz)__ NY 232 \ tours 4) tours Rt *SFS (8 KHz) NO tetpo @ap| tciv0 SBOUT toicu tonpz SBIN 09893E-035 Notes: 1. CH2STRB timing is identical to SFS timing but delayed by eight SCLK cycles. 2. This timing diagram reflects SCLK for PPCR2(0)=0. For PPCR2(0)=1, the diagram is identical except that the SCLK waveform should be inverted. Figure 36. SBP Mode MCLK/SCLK/SFS Timing 86 Am79C30A/32A Data SheetIOM-2 Master Mode Timing AMD at Parameter Signal Abbr Consition Min Max Units Data Clock Rise/Fall SCLK tate C, = 150 pF 50 ns Clock Period SCLK tse. 1.536 MHz 487 815 ns +100 PPM 163 ns* Pulse Width SCLK twH. 260 ns tw. Frame Sync SFS trite C_ = 150 pF 50 ns Frame Sync Setup/Clock SFS tse C_ = 150 pF 50 ns Frame Sync Delay/Clock SFS teo C, = 150 pF 0 ns Frame Sync Hold/Clock SFS tey C. = 150 pF 50 tw. + 50 ns Frame Delay SFS tor C, = 150 pF twe 50 ns Data Delay/Clock SBOUT tosc C, = 150 pF 100 ns Data Hold/Clock SBOUT tone C, = 150 pF 70 ns Data Setup SBIN tso tw + 20 ns Data Hold SBIN tub 50 ns IOM-2 Slave Mode Timing Parameter Signal Abbr Min Max Units Data Clock Rise/Fall SCLK tate 60 ns Clock Frequency (1/period) SCLK T/tscik 1.536 MHz Hz +100 PPM +163 ns* Clock Delay High/Low BCL tety. tent 30 ns Pulse Width SCLK twa. twe 240 ns Frame Sync Rise/Fall SFS tate 60 ns Frame Set-up SFS tsp 70 ns Frame Hold/Clock SFS ten 20 ns Frame Delay/Clock SFS treo 0 ns Frame Width High SF5S twen 130 ns Frame Width Low SFS tweL tscuk ns Data Delay/Clock SBOUT tosc 100" ns Data Hold/Clock SBOUT touc 70 ns Data Set-up SBIN tsp twr + 20 ns Data Hold SBIN typ 50 ns Notes: *The +163-ns value can occur once per frame for digital phase lock loop correction. *C, = 150 pF Am79C30A/32A Data Sheet 87al AMD BCL i | ! j l __I | 1 J | | I | | SCLK | | J | | I | | ] { J L_J | | l I | | - | SFS T f | | EON < Bit 32 | x Bit 0 x | Bit 1 x Bit 2 Lo 4 Detail A BCL SCLK tgcu tro > A o>F ll SFS* tse thn tor > at <$<$___ twen p tonic SBOUT a r _tosc SBIN Detail A tsp | Note: * In Master Mode, SFS is 16 SCLK cycles + set-up time + hold time in length. Figure 37. |\OM-2 Timing Transmitter Side Receiver Side 09893E-036 88 Am79C30A/32A Data SheetAMD cl Switching Test Conditions (Input) 2.4V 2.0V 20V Test Points < 0.45V 08V 08V 09893E-037 Note: AC testing inputs are driven at 2.4 V fora logical 1, and 0.45 V for a logical 0. Timing measurements are made at 2.0 Vand 0.8 Vfora logical 1, and a logical 0, respectively. Figure 38. Switching Test Input/Output Waveform Device under - C, = 80 pF C, Includes Jig Capacitance Includes Jig Capac 09893E-038 Figure 39. Switching Test Load Circuit Am79C30A/32A Data Sheet 89AMD at APPENDIX A Table 1. Coefficients for GX, GR, and STG Attenuators Gain Hex Gain Hex Gain Hex (dB) MSB LSB (dB) MSB LSB (dB) MSB LSB 84.3 87 87 -42.0 90 E6 36.0 90 D6 ~78.3 86 87 ~41.9 90 E5 ~35.9 90 DS ~72.2 SF 8D 41.8 8F 53 -35.8 8E 52 66.2 84 87 41.7 SF 51 35.7 8E 4B 60.2 8F 8B 41.6 90 E4 35.6 80 D4 54.2 91 OF 41.5 8F 42 ~35.5 BE 42 50.7 8F 92 -41.4 8F 41 ~35.3 8E 41 49.3 90 FB ~41.2 8F 3D -35.2 8 3c 48.7 90 FC 41.1 90 E3 -36.1 90 D3 48.4 90 FD 41.0 8F 33 35.0 8E 33 48.3 90 FE ~-40.9 8F 32 34.9 8E 32 48.2 8E 91 40.7 8F 31 34.6 8E 31 48.1 90 F7 40.4 8F 2B 34.4 8E 2B 48,0 90 F6 ~40.3 8F 2D -34.3 8E 2c ~47.9 90 F5 -40.2 90 E2 ~34.2 90 D2 47.6 90 F4 40.1 8F 24 34.1 8E 24 -47.1 90 F3 ~40.0 8F 23 34.0 8E 23 46.2 90 F2 -39.8 8F 22 33.8 8E 22 45.4 8F A2 -39.4 8E A2 33.4 8D A2 -45.0 8F A3 -~39.0 8E A3 33.0 8D A3 44.8 8F A4 -38.8 8E A4 -32.8 8D A4 44.7 8F AS ~38.7 8E AS -32.7 8D AS 44.6 90 F1 -38.6 8D 92 ~32.6 8D A6 ~44.5 8F AG 38.5 8F 15 -32.5 8E 415 44.3 8F AB 38.4 8E AC 32.4 8E 14 43.9 8F Bi -33.3 8F 13 32.2 8E 13 43.6 8F B2 -37.9 8E Bi -31.9 8D Bi -43.5 8F B3 ~37.6 BE B2 -31.6 8D B2 -43.4 8F B4 -37.4 8E B3 31.4 8D B3 43.3 90 EB ~-37.3 8E BS -31.3 8D B4 43.2 8F BB -37.2 BE Bc ~31.2 8D BC 43.0 8F C1 -37.1 8E BB -31.1 8D BB 42.9 8F C2 -37.0 8E C1 ~31.0 8D C1 42.8 8F C3 ~36.8 8E c2 30.8 8D C2 -42.7 90 EC -36.7 90 DC -30.7 8D C3 -42.6 8F D1 36.6 8E CB -30.6 8D CB 42.5 8F D2 36.5 8E Di ~30.5 8D D1 42.4 90 ED 36.4 90 bo 30.4 8D D2 42.3 8E 96 36.3 BE E2 -30.3 8D E14 42.2 8F Ft -36.2 8E Fi -30.2 8c 96 ~42.1 8D 91 -36.1 8c 91 30.1 91 0B Am79C30A/32A Data Sheet A-11 amp Table 1. Coefficients for GX, GR, and STG Attenuators (continued) Gain Hex Gain Hex Gain Hex (dB) MSB LSB (dB) MSB LSB (dB) MSB LSB -30.0 90 C7 24.1 8A 91 -18.3 91 15 29.9 8D 5C -24.0 90 B7 -18.2 8B E2 -29.8 90 C5 -23.9 90 B -18.1 8A 97 29.7 8D 4A 23.8 90 B5 -18.0 91 1F -29.6 90 C4 -23.7 8c 4A -17.9 91 1E -29.5 8D 43 23.6 90 B4 -17.8 91 10 -29.4 8D 42 ~-23,5 8c 43 -17.7 8B 4A -29.3 8D 3A -23.4 8C 42 -17.6 8B 4D ~29.2 8D 3B 23,3 8c 3A -17.5 90 A4 ~29.1 90 c3 23,2 8c 3B -17.4 8B 42 29.0 8D 33 23.1 90 B3 -~17.3 8B 41 -28.8 8D 32 -23.0 8c 34 -17.2 8B 3B -28.6 8D 2A -22.9 8c 33 -17.1 8B 3D ~28.4 8D 2B 22.8 8c 32 -17.0 90 A3 28.3 8D 2c 22.6 8c 31 -16.9 8B 33 28.2 8c Al ~22.4 8C 2B ~-16.8 8B 32 -28.1 8D 24 -22.3 8c 2c ~16.6 8B 2A 28.0 8D 23 22.2 8C 2E ~16.3 8B 2B -27.7 8D 22 ~22.1 90 B2 ~16.2 8B 2E -27.3 8c A2 22.0 8c 24 -16.1 BA Al -27.0 8c A3 -21.9 8C 23 ~16.0 8B 24 -26.8 8c A4 21.7 8c 22 -15.9 8B 23 26.7 8c AS -21.3 8B A2 -15.7 88 22 ~26.6 8c AG -20.9 8B A3 -15.3 91 22 ~26.5 8D 15 -20.7 8B A4 -14.9 91 23 26.4 8C AC -20.6 8B A6 -14.7 8A A4 -26.2 8D 13 ~20.5 8C 15 -14.6 8A AS ~25.9 8c B1 20.4 8B AC -14.5 89 92 25.6 8c B2 -20.2 8C 13 ~14.4 91 2D 25.4 8G B3 -19.9 8B B1 ~14.2 91 2B ~25.3 8C B4 -19.5 8B B2 -13.8 8A B1 25.2 8B 93 -19.4 8B B3 -13.5 8A B2 ~25.1 8C BB 19.3 8B B4 -13.4 91 33 24.9 8c Ci ~19.2 8A 93 -13.3 91 34 24.8 8c C2 -19.1 8B BB -13.2 91 35 24.7 8c C3 -18.9 8B C1 -13.1 91 3C 24.6 90 BC -18.8 8B c2 -13.0 91 3B 24.5 8C D1 -18.7 8B C3 -12.9 91 41 24.4 8c D2 -18.6 91 14 -12.7 8A C2 24.3 8c E4 -18.5 8B Di -12.6 91 44 24.2 90 BE -18.4 8B D2 12.5 94 4B A-2 Am79C30A/32A Data SheetAMD cl Table 1. Coefficients for GX, GR, and STG Attenuators (continued) Gain Hex Gain Hex Gain Hex (dB) MSB LSB (dB) MSB LSB (dB) MSB LSB 12.4 BA D2 77 92 Ag -3.6 9A 22 ~12.3 AO 05 -76 93 22 -3.5 9A 1A -12.2 91 61 -7.5 93 23 3.4 9A 1B ~124 8A FA 7.4 93 2A -3.3 A2 67 ~12.0 08 "1 -7.3 89 83 3.2 A2 E? 11.9 30 96 -7.2 93 E7 3.1 9A 12 11.8 rT DA -74 AO 2D -3.0 Ag 1c -11.7 a1 D3 -7.0 AO 2B ~2.9 Ag 57 -11.6 91 D1 -6.9 94 13 -2.8 99 BA 11.5 90 94 -6.8 93 A3 -2.7 Ad FC 11.4 4 C2 6.7 AO 32 2.6 AS FB -11.3 94 C1 6.6 94 D7 -2.5 AF AT 11 91 BB 6.5 93 94 -2.4 AE 3F -11.0 AO 0B 6.4 89 D1 2.3 AC 5F 10.9 91 B3 -6.3 96 C7 2.2 99 3c 10.8 91 B2 -6.2 96 DS 2.4 AB F6 10.5 92 12 -6.1 97 A7 -2.0 99 2A 10.3 4 AB -6.0 oF 54 1.9 99 2B 10.2 92 14 -5.9 oF 27 1.8 AA 7F 10.1 a9 At 5.8 9D 74 -1.7 AA 2B ~10.0 92 1D -5.7 9D 47 -1.6 AA 21 -9.9 92 1B 5.6 89 4B 1.5 B2 FE -9.7 91 A2 5.5 9c FD -1.4 Ag AA -9.5 92 22 5.4 9D 01 1.3 B3 57 -9.4 92 23 -5.3 9c 1B -1.2 BF 6B -9.3 92 24 5.2 9 12 14 BE B7 9.2 92 2c 5.1 ag 3c -1.0 | BB 6F 9.1 92 2A -5.0 9B 87 0.9 rer FF 9.0 92 32 -4.9 89 33 0.8 BB ot 8.9 92 33 -4.8 9c 01 -0.7 c2 FE 8.8 92 3B -4.7 9B 22 0.6 CE 3F 8.7 92 42 -4.6 9B 1c -0.5 cD C7 -8.6 AO 15 ~4.5 9B 13 -0.4 CA 7F -8.5 92 F7 4.4 9B 12 0.3 DC D7 8.4 94 95 -4.3 39 28 0.2 DB 6F -8.3 AO iC 4,2 9B 0B 0.1 EB E7 -8.2 92 BB 4.4 oA 77 0.0 00 80 8.1 92 B4 -4.0 89 24 0.1 6A F7 8.0 93 12 -3.9 9B 02 0.2 5B E7 -7.9 93 13 -3.8 9A 2A 0.3 5C 5F -7.8 AO 21 -3.7 89 22 0.4 4A 7F Am79C30A/32A Data Sheet A-36A amo Table 1. Coefficients for GX, GR, and STG Attenuators (continued) Gain Hex Gain Hex Gain Hex (dB) MSB LSB (dB) MSB LSB (dB) MSB LSB 0.5 4c D7 46 12 12 8.7 01 ic 0.6 4 57 47 11 C1 8.8 01 14 0.7 42 FE 4.8 10 96 8.9 00 AB 0.8 41 FF 493 20 04 9.0 00 AA 0.9 3B 6F 5.0 09 93 9.1 00 B2 1.0 3D C7 5.1 11 2c 9.2 00 BB 1.1 33 57 5.2 11 22 9.3 ao BA 1.2 29 AA 5.3 0A Al 9.4 00 CA 1.3 32 FE 5.4 10 AS 9.5 00 08 1.4 2B 01 5.5 0A 93 9.6 00 69 1.5 2A 7F 5.6 0B A2 9.7 00 4A 1.6 19 2A 5.7 0A 91 9.8 00 3A 1.7 2B F6 5.8 oc Al 9.9 00 3B 1.8 2c 5F 5.9 oD Al 10.0 00 32 1.9 2E B7 6.0 00 90 10.1 00 2A 2.0 24 FG 6.1 05 91 10.2 00 2B 2.1 23 D7 6.2 10 4F 10.3 600 23 2.2 23 57 6.3 04 B7 10.4 00 22 2.3 1A 12 6.4 03 Al 10.6 00 1A 2.4 22 67 6.5 03 B1 10.7 00 1B 2.5 1A 1A 6.6 03 77 10.8 00 1c 2.6 og 22 6.7 02 Al 10.9 00 15 2.7 1B 02 6.8 01 92 11.0 00 13 2.8 1A 77? 6.9 02 B1 11.2 00 12 2.9 og 2B 7.0 02 C1 11.5 00 1 3.0 1c 00 7.1 02 41 11.8 00 0B 3.1 1B 67 7.2 02 31 11.9 00 oc 3.2 1B E7 7.3 01 Al 12.0 00 10 3.3 1c FD 7.4 01 A2 12.1 00 05 3.4 1D 47 7.5 01 A3 12.2 00 04 3.5 17 A7 7.6 01 B1 12.3 00 03 3.6 16 B7 7.7 01 B2 12.6 oo 2 3.7 14 F5 7.8 01 Cl 13.1 00 01 3.8 20 2B 7.9 01 D1 14.0 00 00 3.9 13 E7 8.0 01 51 4.0 20 21 8.1 01 3B -inf. 08 10 44 1 93 8.2 01 32 4.2 12 F7 8.3 01 2B 4.3 12 2A 8.4 01 23 4.4 12 22 8.5 01 22 4.5 09 Al 8.6 01 1A A-4 Am79C30A/32A Data Sheetamo of Table 2. Coefficients for GER Attenuators Gain Hex Gain Hex Gain Hex (dB) MSB LSB (dB) MSB LSB (dB) MSB LSB -24.1 99 99 -11.4 47 99 6.8 7D c9 -20.6 AQ 99 -11.3 DA AQ 6.7 9E C7 -19.2 99 9B -11.2 99 54 -6.6 6E cg -18.6 cg 99 -11.1 FA AQ 6.5 69 CF ~18.3 Dg 99 -11.0 AQ 91 -6.4 5F cg -18.2 E9 99 -10.9 36 99 -6.3 66 9c -18.1 99 OF -10.8 9A BB -6.2 59 DE -18.0 99 97 -10.7 cg 92 6.1 59 OF -17.9 99 96 -10.5 34 99 -6.0 57 9D -17.8 99 95 -10.4 D9 92 5.9 56 9D -17.5 49 99 -10.2 E9 92 6.8 49 DF -17.0 39 99 -10.0 99 72 -5.7 D9 74 ~16.1 29 99 9.8 25 99 5.6 55 9E -15,7 BA 99 9.7 FB AQ 6.5 E9 64 ~15.1 99 AC 9.6 79 AB 6.4 55 69 -148 DA 99 -9.5 69 AB 6.3 F9 54 -14.7 99 AE 9.4 BA 95 ~5.2 66 49 -14.6 99 AF ~9.2 9A CE 5.1 E9 73 -14,5 19 99 9.1 9A CF -5.0 37 OF ~14.4 AQ 96 -9.0 CA 97 -4.9 36 OF -14.3 59 SA -8.9 ED AQ 4.8 36 79 -14.0 AQ 94 8.8 19 9D 4.7 AS A7 -13.8 99 BC -8.7 DA 97 4.6 92 C7 -13.5 39 9A -8.6 F9 91 4.5 AA 55 -13.3 EB 99 -8.5 79 AF ~4.4 92 cs -13.2 99 cc -8.4 77 9A 4,3 D3 93 -13.1 79 9B -8.3 FA 95 4.2 2F F9 -12.9 Bg 95 -8.2 BB 96 4.1 27 OF -12.7 99 CE -8.1 49 AE ~4.0 91 A3 -12.6 DD 99 -8.0 9B cD 3.9 77 29 -12.5 cg 97 -7.9 AQ 74 3.8 D4 92 -12.4 99 OF -7.8 FC B9 -3.7 7A BE -12.3 EE 99 7.7 29 AB 3.6 6F BA -12.2 FE 99 7.6 EA AA ~3.5 A7 B7 12.1 79 SE 7.5 FD BQ -3.4 66 AB -12.0 ag 99 7.4 37 9A 3.3 7A cD -11.9 59 SE ~7.3 39 BB -3.2 6D CA -11.8 59 OF 7.2 79 BE -3.1 6E CA ~11.7 57 99 7A 6F BO -3.0 A3 A3 -11.6 99 65 -7.0 BO 76 -2.9 5F CA -11.5 55 99 -6.9 DB 94 -2.8 7B BC Am79C30A/32A Data Sheet A-5al AMD Table 2. Coefficients for GER Attenuators (continued) Gain Hex Gain Hex Gain Hex (dB) MSB LSB (dB) MSB LSB (dB) MSB LSB 2.7 56 AC 1.4 EC 62 5.6 CF 06 2.6 5A DE 1.5 34 7F 5.6 BB 02 -2.5 7B BD 1.6 C2 F5 5.7 BE 03 2.4 66 AE 1.7 FD 33 5.8 CE 04 2.3 4A DF 1.8 D2 E5 5.9 DF 05 -2.2 4A EE 1.9 FE 62 6.0 EE 05 -2.1 5B BF 2.0 E2 F5 6.1 og 70 -2.0 47 AF 2.1 D2 F4 6.2 96 00 -1.9 6D cB 2.2 E2 E4 6.3 09 50 -1.8 65 5A 2.3 F2 F4 6.4 FC 03 -1.7 6B CE 2.4 24 7E 6.5 AC 01 -1.6 6B DD 2.5 a4 6F 6.6 DE 03 -1.5 5B CF 2.6 D2 F3 6.7 BE 02 -1.4 5B DD 27 E2 E3 6.8 AD 01 -1.3 6C cD 2.8 C1 D7 6.9 AE 01 ~-1.2 B7 D6 2.9 C1 E7 7.0 FA 01 -1.1 67 BE 3.0 FC 71 7.1 cD 02 -1.0 66 BF 3.1 D1 D6 7.2 BB 01 -0.9 4E EB 3.2 C1 F5 7.3 CE 02 -0.8 5D bc 3.3 FD 61 7.4 DD 02 0.7 5C DE 3.4 Di E5 75 DE 02 0.6 5D DD 3.5 16 6D 7.6 FD 02 -0.5 Al A3 3.6 El F5 7.7 EE 02 -0.4 5D DE 3.7 E2 F2 7.8 EF 02 ~0.3 4E EC 3.8 EE 41 7.9 E7 20 0.2 EA 42 3.9 15 6F 8.0 F 20 0.1 90 E7 4.0 17 4F 8.1 E5 20 0.0 67 EF 4.1 16 4F 8.2 D4 20 0.1 90 F6 4.2 BB 04 8.3 20 E4 0.2 90 F5 43 E1 F3 8.4 F4 20 0.3 55 EE 4.4 FF 31 8.5 10 B6 0.4 D4 E5 45 09 13 8.6 B5 10 0.5 90 C3 4.6 BC 05 8.7 20 B2 0.6 ED 44 4.7 DB 06 8.8 3 20 0.7 D4 F4 4.8 CB 04 8.9 1 F2 0.8 EE 44 4.9 FB 06 9.0 C7 10 0.9 D3 E5 5.0 CG 06 9.1 10 C6 1.0 E3 F 5.1 BD 04 9.2 c5 10 1.1 D3 E4 5.2 AD 02 9.3 20 C2 1.2 BS F4 5.3 AE 02 9.4 D6 10 1.3 EE 43 5.4 cc 04 95 10 30 Am79C30A/32A Data SheetAMD a Table 2. Coefficients for GER Attenuators (continued) Gain Hex Gain Hex (dB) MSB LSB (dB) MSB LSB 9.6 10 F6 13.8 EO 20 9.7 E5 10 13.9 FO 20 9.8 E2 20 14.0 72 00 9.9 10 E4 14.1 13 10 10.0 10 C3 14.2 52 00 10.1 40 AO 14.4 1B 00 10.2 46 10 14.5 42 00 10.3 10 D3 15.0 oc o1 10.4 10 E3 15.3 oD 01 10.5 10 F3 15.4 OE 01 10.6 10 Al 15.5 OF 01 10.7 BE 00 15.6 0A 00 10.8 BF 00 15.7 61 00 10.9 B7 00 15.8 50 10 11.0 00 B6 15.9 22 00 11.1 00 B5 16.1 40 10 11.2 01 D2 16.6 30 10 11.3 01 E2 16.9 BO 00 11.4 F2 01 17.5 02 10 11.5 00 C7 17.8 DO 00 11.6 00 C6 17.9 EO 00 11.7 00 cs 18.0 FO 00 11.8 D7 00 18.1 70 00 11.9 00 B3 18.2 60 00 12.0 00 90 18.3 50 00 12.1 F6 00 18.6 40 00 12.2 00 E5 19.1 10 10 12.3 00 D4 20.0 02 00 12.4 00 E4 21.6 00 10 12.5 00 C3 24.1 00 00 12.6 47 00 12.7 46 00 inf. 00 08 12.8 00 B2 12.9 00 E3 13.0 F3 00 13.1 00 Al 13.2 16 10 13.3 15 10 13.4 22 10 13.6 14 10 13.7 DO 20 Am79C30A/32A Data Sheet A-7APPENDIX B KEY DESIGN HINTS FOR THE DSC/IDC CIRCUIT Due to the high level of integration of the Am79C30A/ 32A DSC/IDC circuit, it is easy to overlook important design information when reading the data sheet. The following list of key design hints has been compiled to streamline the design process. A comprehensive series of ISDN application notes and tutorials is available from Advanced Micro Devices; please contact an AMD sales office or factory for current information. @ The AREF pin must be used to bias the AINA and AINB inputs. There is a datasheet parameter, Vios, which states that the analog inputs must be biased to within 5 mV of AREF. AREF is nominally2.4 V; normal device-to-device variation will exceed the 5-mV Vios specification. lf a voltage other than AREF is used, transmission performance at very low signal levels will be degraded. @ The recommended method of biasing the AINA and AINB inputs is to use a 15-100 Kohm resistor be- tween the input and AREF. The signal source should be AC-coupled to the analog input. Take care that the RC formed by the biasing resistor and blocking ca- pacitor does not distort the input signai. = The AREF output must not be loaded with a capacitor since it may cause the intemal buffer amplifier to be- come unstable. For some applications involving significant gain external to the DSC circuit, the AREF output may require a simple RC noise filter. In this case, the AREF output should be isolated from the capacitor by a resistance of greater than 1 Kohm to ensure stability. @ The analog gain selection value (in MMR3) should be written before the MAP is enabled. = The MAP auto-zero function (MMR2) should be enabled before the MAP is enabied. The DSC/IDC circuit should be provided with de- coupling capacitors, situated as close as possible to the package power leads. In general, 0.1-4F ceramic capacitors are sufficient, but bulk decoupling capaci- tors will be required if the LS1 and LS2 loudspeaker outputs are driving a heavy load. = The DSC/IDC circuit is constructed on a single substrate, and therefore the device power pins must not be from separate supplies. If there is a DC off- set between the analog and digital power-supply pins, excessive current may flow through the device substrate. TheLS1,LS2, EAR1, and EAR? outputs are intended to be used differentially. Although it is possible to use only a single output, the rejection of power-supply noise and internal digital noise is improved if the outputs are used differentially. AMD at Observe the maximum loading specification for the LS and EAR outputs. When used differentially, the EAR outputs must see a minimum of 540 ohms be- tweenthem. Similarly, the LS outputs must see a mini- mum of 40 ohms. The maximum capacitive loading in either case is 100 pF. @ The LS and EAR outputs need not be matched to the load. The LS and EAR outputs are voltage drivers and do not assume the presence of any particular load im- pedance. If the maximum loading specification is met, the LS and EAR outputs will function satisfactorily. In some cases, an external resistor may be used to center the desired output volumefor instance, while driving a 150-ohm earpiece with the EAR outputs. @ If using an EAR or LS output in a single-ended fash- ion, AC-couple the pin to the load. If not, the excessive DC current will cause signal distortion. & When using programmable gains and fitters in the MAP, consider the dynamic range effects such as truncation error and clipping. In case of questions in any particular application, please contact the AMD applications staff for assistance. @ All MAP tone generators are referenced with respect to the +3-dBm0 overload voltagethat is, a0-dBtone yields a +3-dBm0 output. Take care to avoid clipping when adding tones to signals as, for example, when generating DTMF waveforms. @ The RC connected to CAP1/CAP2 must be situated as close as possible to the DSC circuit package to re- duce the amount of noise coupled in from other signal traces. @ Observe the XTAL2 frequency accuracy requirement of 12.288 MHz + 80 ppm. Since crystals from different manufacturers will vary, the DSC circuit oscillator out- put frequency at the MCLK pin must be measured and, if necessary, the value of the crystal load capaci- tors should be adjusted as part of the initial design procedure. An application note of oscillator consider- ations is available from AMD (ISDN Systems Engi- neering Application Note, order #12557). @ If driving the XTAL2 pin with the external oscillator, is necessary to observe the datasheet input voltage and rise/fall time requirements. Note that the XTAL2 levels are not TTL-compatible. Take care in board layout of the DSC circuit, as with any sensitive analog device. An application note of DSC circuit board layout hints is available from AMD (ISDN Systems Engineering Application Note, order #12557). a The sidetone path defaults to -18-dB attenuation. If disabling the sidetone path is desired, the sidetone block must be enabled and programmed for infinite attenuation. Consider the LiU transformers, series resistors, and IC LIU output drivers as a functional unit. Transform- ers that meet CCITT 1.430 requirements with other transceivers are not necessarily appropriate for use with the DSC circuit, and vice versa. Am79C30A/32A Data Sheet B-1al AMD Interrupts should be masked when reading or writing any indirect or multibyte DSC circuit registers to prevent the possibility of an interrupt occurring and destroying the contents of the Command Register. @ If the MAP and secondary tone ringer are disabled, the EAR, AREF, and LS outputs are high-impedance. lf the MAP is enabled, the unselected audio output is high-impedance. = The MAP should not be enabled until after the LIU has achieved synchronization. This will eliminate the possibility of audible distortion when the internal device timing is resynchronized to the S Interface. = To make optimum use of the MAP digital signal pro- cessing chain, use digital gain (GX) for fine adjust- ment, and analog gain (GA) for coarse adjustment. The user must program the Secondary Tone Ringer Frequency Register (STFR) with a legal value before enabling the secondary tone ringer. Trademarks Copyright 1995 Advanced Micro Devices, All rights reserved. AMD is a registered trademark of Advanced Micro Devices, Inc. 8 in order to exit Power-Down Mode due to LIU activation, both the F7 interrupt and the DSC/ADC circuit interrupt pin must be enabled. In order to exit Power-Down Mode due to IOM-2 activation, both the IOM-2 Timing Request interrupt and the DSC/IDC circuit interrupt pin must be enabled. The MAP auto-zero function must be enabled prior to enabling the MAP. For ail normal applications, the auto-zero function should always be enabled. To ensure proper operation of the filters (X and R} and gains (GX, GR, GER, STGR, and ATGR), these regis- ter blocks should not be accessed more frequently than 128-s intervals. This allows the internal buffers to the map to operate properly, since they are updated only once per frame. AmMAP, Digital Subscriber Controller, DSC, and IDC are trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. B-2 Am79C30A/32A Data SheetFo] (tm Ohi lett) North American ALABAMA... .. (205) 830-9192 ARIZONA .... .. (602) 242-4400 CALIFORNIA, Culver City cece teeneceesatcseereneenetaneeeees (310) 645-1524 UPVING ones . (714) 450-7500 Sacramento( Roseville) .. {918) 786-6700 San Diego. .. (619) 560-7030 San Jose... -. (408) 922-0300 Woodland Hills 00.0... cee eer erate (818) 878-9988 CANADA, Ontario, KAMARA ooo cence ee eecnscse re ceesenesaasaseevesevseeeneares (613) 592-0060 Willowdale .... .. (416) 222-7800 COLORADO .. .. (303) 741-2900 CONNECTICUT ... . (203) 264-7800 FLORIDA, Boca Raton... .. (407) 361-0050 Clearwater .... -. (813) 530-9971 Orlando (Longwood) .... GEORGIA ... (407) 862-9292 .. (404) 449-7920 .. (208) 377-0393 TOKYO oe eccrine TEL ... (03) 3346-7550 . (03) 3346-5197 KOREA, Seoul ou... (82) 2-784-0030 (82) 2-784-8014 SINGAPORE ...... ee (65) 3481188 seve (65) 9480161 SWEDEN, Stockhoim area........... TEL... ....(08) 98 61 80 (Bromma) FAX. .... (08) 98 09 06 TAIWAN, Taipei ......... TEL. .. (886) 2-7153536 FAX woe rectsees (886) 2-7122182 UNITED KINGDOM, London area... TEL... ... (0483) 740440 (Woking) FAX. (0483) 756196 Manchester area TEL. (0925) 830380 (Warrington) FAX.... ... (0925) 830204 North American Representatives ___ CANADA Burnaby, B.C. DAVETEK MARKETING......... (604) 430-3680 Kanata, Ontario - VITEL ELECTRONICS...... (613) 592-0090 Mississauga, Ontario ~ ILLINGIS, VITEL ELECTRONICS ooccccccsesccsccsssnsseeeeeteeenen (905) 564-9720 Chicago (Itasca) .. (708) 773-4422 Lachine, Quebec VITEL ELECTRONICS..... (514) 636-5951 Naperville .. (708) 505-9517 ILLINOIS KENTUCKY ... .. (606) 281-1533 Skokie INDUSTRIAL MARYLAND... .. (410) 981-3790 REPRESENTATIVES, ING 0. cee cece (708) 967-8430 MASSACHUSETTS .. (617) 273-3970 IOWA MINNESOTA .. (612) 938-0004 LORENZ SALES ooo ecccccecccesecreceesetesceeetsneeeenee (319) 377-4666 NEW JERSEY, KANSAS Cherry Hill .... .. (609) 662-2900 Merriam - LORENZ SALES .(913) 469-1312 Parsippany ... .. (201) 299-0002 Wichita LORENZ SALES.. . (318) 721-0500 NEW YORK MEXICO Brewster, (914) 279-8323 Chula Vista - SONIKA ELECTRONICA............ (619) 498-8340 Rochester - (746) 425-8050 Guadalajara SONIKA ELECTRONICA . . (523) 647-4250 : . Mexico City SONIKA ELECTRONICA ...........(525) 754-6480 NORTH CAROLINA Monterrey SONIKA ELECTRONICA _(528) 358-9280 Charlotte . .. (704) 875- 3091 MICHIGAN onnaleish wes . (919) 878- 8111 Brighton COM-TEK SALES, INC... (810) 227-0007 : Holland - COM-TEK SALES, INC .(616) 335-8418 Columbus (Westerville) .. (614) 891-6455 MINNESOTA ) Dayton... - (513) 439-0268 MEL FOSTER TECH. SALES, INC.. v0.0.0... (612) 941-9790 OREGON .... .. (503) 245-0080 MISSOURI . PENNSYLVANIA .... 0. serene essences (610) 398-8006 LORENZ SALES ooocecccccccccccccccetescc ttesesteerevsenease (314) 997-4558 TEXAS, NEBRASKA .. (512) 346-7830 LORENZ SALES wicecccccseccssseessssneesstnmsnseeeseeseeeenes (402) 475-4660 .. (214) 934-9099 NEW MEXICO HOUSTON 00... cec cee ccnsanescee eres ee seseteceseeenaeesseree (713) 376-8084 THORSON DESERT STATES 00. ceccccccccececeeessees (505) 883-4343 . NEW YORK International Hauppauge COMPONENT BELGIUM, Antwerpan..... TEL ....ccccccsececeeees (03) 248 43 00 CONSULTANTS, INC oe.cccecsssssseescccescsssesstetttsssaee (516) 273-5050 FAX... ... (03) 248 46 42 East Syracuse NYCOM .(315) 437-8343 FRANCE, Paris ......-cs0- TEL... .. (1) 49-75-10-10 Fairport - NYCOM (716) 425-5120 (1) 49-75-10-13 OHIO GERMANY, Centerville ~ DOLFUSS ROOT & CO (513) 433-6776 Bad Homburg.............. TEL... - (06172)-92670 Westlake DOLFUSS ROOT & CO oe (216) 899-9370 ; FAX. . {06172)-23195 PENNSYLVANIA MUNCHEN ..oeeesess see reseees TEL - (088) 450530 RUSSELL F. CLARK CO.ING. oecccccccsuecsenen (412) 635-9500 (089) 406490 PUERTO RICO HONG KONG, _. (852) 956-0388 ureome REP ASSOC, INC (809) 746-6550 Kowloon (852) 956-0588 FRONT RANGE MARKETING ....0...0cccscssseecneees (801) 288-2500 . WASHINGTON ITALY, Milano {02) 3390541 ELECTRA TECHNICAL SALES ... (208) 821-7442 FAX. .... (02) 38103458 JAPAN, WISCONSIN OSAKA occcscccccceeeereseseeee TEL cooccesccssssseseeeenseeee (06) 243-3250 Brookfield INDUSTRIAL FAX (06) 243-3253 REPRESENTATIVES, ING o.....ccsccccsesssssseutseneeceecee (414) 574-9393 Advanced Micro Devices, inc. One AMD Place, P.O. Box 3453, Sunnyvale, CA 94088, USA 098936 GV Tet: (408) 732-2400 TWX: 910-339-9280 * TELEX: 34-6306 TOLL FREE: (800) 538-8450 Con-7.3M-1/98-0 ee APPLICATIONS HOTLINE & LITERATURE ORDERING TOLL FREE: (800) 222-9323 + (408) 749-5703 RECYCLED & * UK & Europe 44-0-256-811101 * France 0590-8621 Germany 0130-813875 Italy 1678-77224 RECYCLABLE