Kinetis KL03 32 KB Flash
48 MHz Cortex-M0+ Based Microcontroller
Supports ultra low power 48 MHz devices with up to 32 KB
Flash.
World's smallest MCU based on ARM® technology. Ideal
solution for Internet of Things edge nodes design with ultra small
form factor and ultra low power consumption. The products
offers:
• Tiny footprint packages, including 1.6 x 2.0 mm2 WLCSP
• Run power consumption as low as 50 µA/MHz
• Static power consumption as low as 2.2 µA with 7.5 µs
wakeup time for full retention and lowest static mode down
to 77 nA in deep sleep
• Highly integrated peripherals, including new boot ROM and
high accurate internal voltage reference, etc
Core
• ARM® Cortex®-M0+ core up to 48 MHz
Memories
• Up to 32 KB program flash memory
• 2 KB SRAM
• 8 KB ROM with build-in bootloader
• 16 bytes regfile
System peripherals
• Nine low-power modes to provide power optimization
based on application requirements
• COP Software watchdog
• Low-leakage wakeup unit
• SWD debug interface and Micro Trace Buffer
• Bit Manipulation Engine
Clocks
• 48 MHz high accuracy internal reference clock
• 8/2 MHz low power internal reference clock
• 32 kHz to 40 kHz crystal oscillator
• 1 kHz LPO clock
Operating Characteristics
• Voltage range: 1.71 to 3.6 V
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range (ambient): -40 to 105°C for QFN
packages; -40 to 85°C for WLCSP packages
Human-machine interface
• General-purpose input/output up to 22
Communication interfaces
• One 8-bit SPI module
• One LPUART module
• One I2C module supporting up to 1 Mbit/s, with
double buffer
Analog Modules
• 12-bit SAR ADC with internal voltage reference, up
to 818 ksps and 7 channels
• High-speed analog comparator containing a 6-bit
DAC and programmable reference input
• 1.2 V voltage reference (Vref)
Timers
• Two 2-channel Timer/PWM modules
• One low-power timer
• Real time clock
Security and integrity modules
• 80-bit unique identification number per chip
MKL03ZxxVFG4
MKL03ZxxVFK4
MKL03Z32CAF4R
MKL03Z32CBF4R
16-pin QFN (FG)
3 x 3 x 0.65 Pitch 0.5
mm
24-pin QFN (FK)
4 x 4 x 0.65 Pitch 0.5
mm
20 WLCSP
2 x 1.61 x 0.56 Pitch 0.4 mm(AF) 2 x 1.61 x
0.32 Pitch 0.4 mm (BF)
NXP Semiconductors Document Number: KL03P24M48SF0
Data Sheet: Technical Data Rev. 5.1 08/2017
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Ordering Information1
Part Number Memory Maximum number of I\O's
Flash (KB) SRAM (KB)
MKL03Z8VFG4(R) 8 2 14
MKL03Z16VFG4(R) 16 2 14
MKL03Z32VFG4(R) 32 2 14
MKL03Z32CAF4R 32 2 18
MKL03Z32CBF4R 32 2 18
MKL03Z8VFK4(R) 8 2 22
MKL03Z16VFK4(R) 16 2 22
MKL03Z32VFK4(R) 32 2 22
1. To confirm current availability of ordererable part numbers, go to http://www.nxp.com and perform a part number search.
Related Resources
Type Description Resource
Selector Guide The Solution Advisor is a web-based tool that features interactive
application wizards and a dynamic product selector.
Solution Advisor
Product Brief The Product Brief contains concise overview/summary information to
enable quick evaluation of a device for design suitability.
KL03PB1
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
KL03P24M48SF0RM1
Data Sheet The Data Sheet includes electrical characteristics and signal
connections.
KL03P24M48SF01
Chip Errata The chip mask set Errata provides additional or corrective
information for a particular device mask set.
KL03Z_xN86K2
Package
drawing
Package dimensions are provided in package drawings. QFN 16-pin: 98ASA00525D1
QFN 24-pin: 98ASA00602D1
WLCSP 20-pin: 98ASA00676D1
WLCSP 20-pin (ultra thin):
98ASA00964D1
1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.
2. To find the associated resource, go to http://www.nxp.com and perform a search using this term with the “x” replaced by
the revision of the device you are using.
Figure 1 shows the functional modules in the chip.
2Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017
NXP Semiconductors
Memories and
Memory Interfaces
Program
flash
RAM
Analog Timers Communication
Interfaces
SPI
x1
Clocks
LPO
Core
SWD
interfaces
Interrupt
controller
Human-Machine
Interface (HMI)
System
Internal
watchdog
reference
Internal
clocks
oscillator
Low
frequency
Low power
UART
x1
Cortex-M0+ARM
with
GPIOs
interrupt
Low Power
Timer
MTB
BME
comparator
with
x1
Analog
Security
and Integrity
Unique ID
ROM
Register
file
RTC
6-bit DAC
VREF
Kinetis KL03 Family
x1
IC
2
Timers
2x2ch
12-bit ADC
x1
Figure 1. Functional block diagram
Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 3
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Table of Contents
1 Ratings....................................................................................5
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings.......................................................5
1.4 Voltage and current operating ratings............................. 6
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................7
2.2.1 Voltage and current operating requirements....... 7
2.2.2 LVD and POR operating requirements................7
2.2.3 Voltage and current operating behaviors.............8
2.2.4 Power mode transition operating behaviors........ 9
2.2.5 Power consumption operating behaviors............ 10
2.2.6 EMC radiated emissions operating behaviors.....24
2.2.7 EMC Radiated Emissions Web Search
Procedure boilerplate.......................................... 25
2.2.8 Capacitance attributes.........................................25
2.3 Switching specifications...................................................25
2.3.1 Device clock specifications..................................25
2.3.2 General switching specifications......................... 26
2.4 Thermal specifications.....................................................26
2.4.1 Thermal operating requirements......................... 26
2.4.2 Thermal attributes................................................27
3 Peripheral operating requirements and behaviors.................. 27
3.1 Core modules.................................................................. 27
3.1.1 SWD electricals .................................................. 28
3.2 System modules.............................................................. 29
3.3 Clock modules................................................................. 29
3.3.1 MCG-Lite specifications.......................................29
3.3.2 Oscillator electrical specifications........................30
3.4 Memories and memory interfaces................................... 31
3.4.1 Flash electrical specifications..............................31
3.5 Security and integrity modules........................................ 33
3.6 Analog............................................................................. 33
3.6.1 ADC electrical specifications............................... 33
3.6.2 CMP and 6-bit DAC electrical specifications....... 37
3.6.3 Voltage reference electrical specifications.......... 39
3.7 Timers..............................................................................40
3.8 Communication interfaces............................................... 40
3.8.1 SPI switching specifications................................ 41
3.8.2 Inter-Integrated Circuit Interface (I2C) timing...... 45
3.8.3 UART...................................................................47
4 Dimensions............................................................................. 47
4.1 Obtaining package dimensions....................................... 47
5 Pinout......................................................................................48
5.1 KL03 signal multiplexing and pin assignments................48
5.2 KL03 pinouts....................................................................49
6 Ordering parts......................................................................... 51
6.1 Determining valid orderable parts....................................51
7 Part identification.....................................................................51
7.1 Description.......................................................................51
7.2 Format............................................................................. 52
7.3 Fields............................................................................... 52
7.4 Example...........................................................................52
8 Terminology and guidelines.................................................... 53
8.1 Definition: Operating requirement....................................53
8.2 Definition: Operating behavior......................................... 53
8.3 Definition: Attribute.......................................................... 54
8.4 Definition: Rating............................................................. 54
8.5 Result of exceeding a rating............................................ 55
8.6 Relationship between ratings and operating
requirements....................................................................55
8.7 Guidelines for ratings and operating requirements..........55
8.8 Definition: Typical value...................................................56
8.9 Typical value conditions.................................................. 57
9 Revision history.......................................................................57
4Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017
NXP Semiconductors
1 Ratings
1.1 Thermal handling ratings
Table 1. Thermal handling ratings
Symbol Description Min. Max. Unit Notes
TSTG Storage temperature –55 150 °C 1
TSDR Solder temperature, lead-free — 260 °C 2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Table 2. QFN packages moisture handling ratings
Symbol Description Min. Max. Unit Notes
MSL Moisture sensitivity level — 3 — 1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
Table 3. WLCSP packages moisture handling ratings
Symbol Description Min. Max. Unit Notes
MSL Moisture sensitivity level — 1 — 1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Table 4. ESD handling ratings
Symbol Description Min. Max. Unit Notes
VHBM Electrostatic discharge voltage, human body model –2000 +2000 V 1
VCDM Electrostatic discharge voltage, charged-device
model
–500 +500 V 2
ILAT Latch-up current at ambient temperature of 105 °C –100 +100 mA 3
Ratings
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NXP Semiconductors
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
1.4 Voltage and current operating ratings
Table 5. Voltage and current operating ratings
Symbol Description Min. Max. Unit
VDD Digital supply voltage –0.3 3.8 V
IDD Digital supply current — 120 mA
VIO IO pin input voltage –0.3 VDD + 0.3 V
IDInstantaneous maximum current single pin limit (applies to
all port pins)
–25 25 mA
VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
80%
20%
50%
VIL
Input Signal
VIH
Fall Time
High
Low
Rise Time
Midpoint1
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
All digital I/O switching characteristics, unless otherwise specified, assume the output
pins have the following characteristics.
• CL=30 pF loads
General
6Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017
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• Slew rate disabled
• Normal drive strength
2.2 Nonswitching electrical specifications
2.2.1 Voltage and current operating requirements
Table 6. Voltage and current operating requirements
Symbol Description Min. Max. Unit Notes
VDD Supply voltage 1.71 3.6 V
VDDA Analog supply voltage 1.71 3.6 V —
VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V —
VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V —
VIH Input high voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
0.75 × VDD
—
—
V
V
—
VIL Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
—
VHYS Input hysteresis 0.06 × VDD — V —
IICIO IO pin negative DC injection current—single pin
• VIN < VSS–0.3V –5 — mA
1
IICcont Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents of 16
contiguous pins
• Negative current injection –25 — mA
—
VRAM VDD voltage required to retain RAM 1.2 — V —
1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN
greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If
this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting
resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|.
General
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2.2.2 LVD and POR operating requirements
Table 7. VDD supply LVD and POR operating requirements
Symbol Description Min. Typ. Max. Unit Notes
VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V —
VLVDH Falling low-voltage detect threshold — high
range (LVDV = 01)
2.48 2.56 2.64 V —
VLVW1H
VLVW2H
VLVW3H
VLVW4H
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV = 00)
• Level 2 falling (LVWV = 01)
• Level 3 falling (LVWV = 10)
• Level 4 falling (LVWV = 11)
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
1
VHYSH Low-voltage inhibit reset/recover hysteresis —
high range
— ±60 — mV —
VLVDL Falling low-voltage detect threshold — low
range (LVDV=00)
1.54 1.60 1.66 V —
VLVW1L
VLVW2L
VLVW3L
VLVW4L
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV = 00)
• Level 2 falling (LVWV = 01)
• Level 3 falling (LVWV = 10)
• Level 4 falling (LVWV = 11)
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
1
VHYSL Low-voltage inhibit reset/recover hysteresis —
low range
— ±40 — mV —
VBG Bandgap voltage reference 0.97 1.00 1.03 V —
tLPO Internal low power oscillator period — factory
trimmed
900 1000 1100 μs —
1. Rising thresholds are falling threshold + hysteresis voltage
2.2.3 Voltage and current operating behaviors
Table 8. Voltage and current operating behaviors
Symbol Description Min. Max. Unit Notes
VOH Output high voltage — Normal drive pad (except
RESET)
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –2.5 mA
VDD – 0.5
VDD – 0.5
—
—
V
V
1, 2
VOH Output high voltage — High drive pad (except
RESET)
VDD – 0.5
VDD – 0.5
—
—
V
V
1, 2
Table continues on the next page...
General
8Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017
NXP Semiconductors
Table 8. Voltage and current operating behaviors (continued)
Symbol Description Min. Max. Unit Notes
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –20 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –10 mA
IOHT Output high current total for all ports — 100 mA —
VOL Output low voltage — Normal drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 2.5 mA
—
—
0.5
0.5
V
V
1
VOL Output low voltage — High drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA
—
—
0.5
0.5
V
V
1
IOLT Output low current total for all ports — 100 mA —
IIN Input leakage current (per pin) for full temperature
range
— 1 μA 3
IIN Input leakage current (per pin) at 25 °C — 0.025 μA 3
IIN Input leakage current (total all pins) for full
temperature range
— 41 μA 3
IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA —
RPU Internal pullup resistors 20 50 kΩ 4
1. I/O have both high drive and normal drive capability selected by the associated PTx_PCRn[DSE] control bit. All other
GPIOs are normal drive only.
2. The reset pin only contains an active pull down device when configured as the RESET signal or as a GPIO. When
configured as a GPIO output, it acts as a pseudo open drain output.
3. Measured at VDD = 3.6 V
4. Measured at VDD supply voltage = VDD min and Vinput = VSS
2.2.4 Power mode transition operating behaviors
All specifications except tPOR and VLLSx→RUN recovery times in the following
table assume this clock configuration:
• CPU and system clocks = 48 MHz
• Bus and flash clock = 24 MHz
• HIRC clock mode
VLLSx→RUN recovery uses LIRC clock mode at the default CPU and system
frequency of 8 MHz, and a bus and flash clock frequency of 4 MHz.
General
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NXP Semiconductors
Table 9. Power mode transition operating behaviors
Symbol Description Min. Typ. Max. Unit Note
tPOR After a POR event, amount of time from the
point VDD reaches 1.8 V to execution of the first
instruction across the operating temperature
range of the chip.
— — 300 μs 1
• VLLS0 → RUN
—
152
166
μs
—
• VLLS1 → RUN
—
152
166
μs
—
• VLLS3 → RUN
—
93
104
μs
—
• VLPS → RUN
—
7.5
8
μs
—
• STOP → RUN
—
7.5
8
μs
—
1. Normal boot (FTFA_FOPT[LPBOOT]=11).
2.2.5 Power consumption operating behaviors
Table 10. KL03 QFN packages power consumption operating behaviors
Symbol Description Min. Typ. Max.1Unit Notes
IDDA Analog supply current — — See note mA 2
IDD_RUNCO Running CoreMark in flash in compute operation
mode—48M HIRC mode, 48 MHz core / 24 MHz
flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
—
—
5.49
5.62
5.71
5.84
mA
3
IDD_RUNCO Running While(1) loop in flash in compute
operation mode—48M HIRC mode, 48 MHz
core / 24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
—
—
5.16
5.27
5.37
5.48
mA
3
IDD_RUN Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock disable
48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
—
—
6.03
6.16
6.27
6.41
mA
3
IDD_RUN Run mode current—48M HIRC mode, running
CoreMark in flash all peripheral clock disable,
24 MHz core/12 MHz flash, VDD = 3.0 V
3
Table continues on the next page...
General
10 Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017
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Table 10. KL03 QFN packages power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max.1Unit Notes
• at 25 °C
• at 105 °C
—
—
3.71
3.81
3.86
3.96
mA
IDD_RUN Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock disable
12 MHz core/6 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
—
—
2.47
2.58
2.57
2.68
mA
3
IDD_RUN Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock enable 48
MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
—
—
6.43
6.56
6.69
6.82
mA
3
IDD_RUN Run mode current—48M HIRC mode, running
While(1) loop in flash all peripheral clock
disable, 48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
—
—
5.71
5.82
5.94
6.05
mA
—
IDD_RUN Run mode current—48M HIRC mode, running
While(1) loop in Flash all peripheral clock
disable, 24 MHz core/12 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
—
—
3.3
3.4
3.43
3.54
mA
—
IDD_RUN Run mode current—48M HIRC mode, Running
While(1) loop in Flash all peripheral clock
disable, 12 MHz core/6 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
—
—
2.28
2.38
2.37
2.48
mA
—
IDD_RUN Run mode current—48M HIRC mode, Running
While(1) loop in Flash all peripheral clock
enable, 48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
—
—
6.1
6.22
6.34
6.47
mA
—
IDD_RUN Run mode current—48M HIRC mode, running
While(1) loop in SRAM all peripheral clock
disable, 48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
—
—
3.14
3.27
3.23
3.36
mA
—
IDD_RUN Run mode current—48M HIRC mode, running
While(1) loop in SRAM all peripheral clock
enable, 48 MHz core/24 MHz flash, VDD = 3.0 V
—
—
3.54
3.67
3.63
3.76
mA
—
Table continues on the next page...
General
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Table 10. KL03 QFN packages power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max.1Unit Notes
• at 25 °C
• at 105 °C
IDD_VLPRCO Very-low-power run While(1) loop in flash in
compute operation mode— 2 MHz LIRC mode,
2 MHz core/0.5 MHz flash, VDD = 3.0 V
• at 25 °C
—
500
750
μA
—
IDD_VLPRCO Very-low-power-run While(1) loop in SRAM in
compute operation mode— 8 MHz LIRC mode,
4 MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C
—
188
217
μA
—
IDD_VLPRCO Very-low-power run While(1) loop in SRAM in
compute operation mode:—2 MHz LIRC mode,
2 MHz core / 0.5 MHz flash, VDD = 3.0 V
• at 25 °C
—
82
123
μA
—
IDD_VLPR Very-low-power run mode current— 2 MHz
LIRC mode, While(1) loop in flash all peripheral
clock disable, 2 MHz core / 0.5 MHz flash, VDD
= 3.0 V
• at 25 °C
—
503
754
μA
—
IDD_VLPR Very-low-power run mode current— 2 MHz
LIRC mode, While(1) loop in flash all peripheral
clock disable, 125 kHz core / 31.25 kHz flash,
VDD = 3.0 V
• at 25 °C
—
60
90
μA
—
IDD_VLPR Very-low-power run mode current— 2 MHz
LIRC mode, While(1) loop in flash all peripheral
clock enable, 2 MHz core / 0.5 MHz flash, VDD =
3.0 V
• at 25 °C
—
516
774
μA
—
IDD_VLPR Very-low-power run mode current— 8 MHz
LIRC mode, While(1) loop in SRAM in all
peripheral clock disable, 4 MHz core / 1 MHz
flash, VDD = 3.0 V
• at 25 °C
—
209
350
μA
—
IDD_VLPR Very-low-power run mode current— 8 MHz
LIRC mode, While(1) loop in SRAM all
peripheral clock enable, 4 MHz core / 1 MHz
flash, VDD = 3.0 V
• at 25 °C
—
229
370
μA
—
IDD_VLPR Very-low-power run mode current—2 MHz LIRC
mode, While(1) loop in SRAM in all peripheral
clock disable, 2 MHz core / 0.5 MHz flash, VDD
= 3.0 V
• at 25 °C
—
93
140
μA
—
IDD_VLPR Very-low-power run mode current—2 MHz LIRC
mode, While(1) loop in SRAM all peripheral
clock disable, 125 kHz core / 31.25 kHz flash,
VDD = 3.0 V
—
31
81
μA
—
Table continues on the next page...
General
12 Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017
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Table 10. KL03 QFN packages power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max.1Unit Notes
• at 25 °C
IDD_VLPR Very-low-power run mode current—2 MHz LIRC
mode, While(1) loop in SRAM all peripheral
clock enable, 2 MHz core / 0.5 MHz flash, VDD =
3.0 V
• at 25 °C
—
103
154
μA
—
IDD_WAIT Wait mode current—core disabled, 48 MHz
system/24 MHz bus, flash disabled (flash doze
enabled), all peripheral clocks disabled,
MCG_Lite under HIRC mode, VDD = 3.0 V
—
1.4
1.94
mA
—
IDD_WAIT Wait mode current—core disabled, 24 MHz
system/12 MHz bus, flash disabled (flash doze
enabled), all peripheral clocks disabled,
MCG_Lite under HIRC mode, VDD = 3.0 V
—
1.02
1.24
mA
—
IDD_VLPW Very-low-power wait mode current, core
disabled, 4 MHz system/ 1 MHz bus and flash,
all peripheral clocks disabled, VDD = 3.0 V
— 121 181 μA —
IDD_VLPW Very-low-power wait mode current, core
disabled, 2 MHz system/ 0.5 MHz bus and flash,
all peripheral clocks disabled, VDD = 3.0 V
— 59 97 μA —
IDD_VLPW Very-low-power wait mode current, core
disabled, 125 kHz system/ 31.25 kHz bus and
flash, all peripheral clocks disabled, VDD = 3.0 V
— 28 42 μA —
IDD_PSTOP2 Partial Stop 2, core and system clock disabled,
12 MHz bus and flash, VDD = 3.0 V
—
1.53
2.03
mA
—
IDD_PSTOP2 Partial Stop 2, core and system clock disabled,
flash doze enabled, 12 MHz bus, VDD = 3.0 V
—
0.881
1.18
mA
—
IDD_STOP Stop mode current at 3.0 V
• at 25 °C and below
• at 50 °C
• at 85 °C
• at 105 °C
—
—
—
—
158
164
187
219
175.7
179.48
199.54
236.43
μA
—
IDD_VLPS Very-low-power stop mode current at 3.0 V
• at 25 °C and below
• at 50 °C
• at 85 °C
• at 105 °C
—
—
—
—
2.2
3.9
13.9
28.4
2.71
6.63
18.25
36.59
μA
—
IDD_VLPS Very-low-power stop mode current at 1.8 V
• at 25 °C and below
• at 50 °C
—
—
2.2
3.8
2.674
6.44
—
Table continues on the next page...
General
Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 13
NXP Semiconductors
Table 10. KL03 QFN packages power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max.1Unit Notes
• at 85 °C
• at 105 °C
—
—
13.2
27.8
17.37
35.54
μA
IDD_VLLS3 Very-low-leakage stop mode 3 current, all
peripheral disable, at 3.0 V
• at 25 °C and below
• at 50 °C
• at 85 °C
• at 105 °C
—
—
—
—
1.08
1.4
3.45
7.02
1.17
1.52
3.96
8.19
μA
—
IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC
current, at 3.0 V
• at 25 °C and below
• at 50 °C
• at 85 °C
• at 105 °C
—
—
—
—
1.47
1.82
3.93
7.6
1.56
1.94
4.44
8.77
μA
—
IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC
current, at 1.8 V
• at 25 °C and below
• at 50 °C
• at 85 °C
• at 105 °C
—
—
—
—
1.33
1.65
3.56
6.92
1.42
1.77
4.07
8.09
μA
—
IDD_VLLS1 Very-low-leakage stop mode 1 current all
peripheral disabled at 3.0 V
• at 25 °C and below
• at 50°C
• at 85°C
• at 105 °C
—
—
—
—
566
788
2270
4980
690
839
2600
5820
nA
—
IDD_VLLS1 Very-low-leakage stop mode 1 current RTC
enabled at 3.0 V
• at 25 °C and below
• at 50°C
• at 85°C
• at 105 °C
—
—
—
—
969
1200
2740
5610
1059
1251
3070
6450
nA
—
IDD_VLLS1 Very-low-leakage stop mode 1 current RTC
enabled at 1.8 V
• at 25 °C and below
• at 50°C
• at 85°C
• at 105 °C
—
—
—
—
826
1040
2400
4910
916
1091
2730
5750
nA
—
Table continues on the next page...
General
14 Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017
NXP Semiconductors
Table 10. KL03 QFN packages power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max.1Unit Notes
IDD_VLLS0 Very-low-leakage stop mode 0 current all
peripheral disabled (SMC_STOPCTRL[PORPO]
= 0) at 3.0 V
• at 25 °C and below
• at 50 °C
• at 85 °C
• at 105 °C
—
—
—
—
265
467
1920
4540
373
512.9
2256
5395
nA
—
IDD_VLLS0 Very-low-leakage stop mode 0 current all
peripheral disabled (SMC_STOPCTRL[PORPO]
= 1) at 3 V
• at 25 °C and below
• at 50 °C
• at 85 °C
• at 105 °C
—
—
—
—
77
255
1640
4080
350
465.70
1994
4956
nA
4
1. The maximum values represent characterized results equivalent to the mean plus three times the standard deviation
(mean + 3 sigma).
2. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.
See each module's specification for its supply current.
3. MCG_Lite configured for HIRC mode. CoreMark benchmark compiled using IAR 7.10 with optimization level high,
optimized for balanced.
4. No brownout
Table 11. KL03 WLCSP package power consumption operating behaviors
Symbol Description Min. Typ. Max.1Unit Notes
IDDA Analog supply current — — See note mA 2
IDD_RUNCO Running CoreMark in flash in compute
operation mode—48M HIRC mode, 48 MHz
core / 24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 85 °C
—
—
5.49
5.59
5.71
5.81
mA
3
IDD_RUNCO Running While(1) loop in flash in compute
operation mode—48M HIRC mode, 48 MHz
core / 24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 85 °C
—
—
5.16
5.24
5.37
5.45
mA
3
IDD_RUN Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock disable
48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 85 °C
—
—
6.03
6.13
6.27
6.38
mA
3
Table continues on the next page...
General
Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 15
NXP Semiconductors
Table 11. KL03 WLCSP package power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max.1Unit Notes
IDD_RUN Run mode current—48M HIRC mode, running
CoreMark in flash all peripheral clock disable,
24 MHz core/12 MHz flash, VDD = 3.0 V
• at 25 °C
• at 85 °C
—
—
3.71
3.78
3.86
3.93
mA
3
IDD_RUN Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock disable
12 MHz core/6 MHz flash, VDD = 3.0 V
• at 25 °C
• at 85 °C
—
—
2.47
2.55
2.57
2.65
mA
3
IDD_RUN Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock enable
48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 85 °C
—
—
6.43
6.53
6.69
6.79
mA
3
IDD_RUN Run mode current—48M HIRC mode, running
While(1) loop in flash all peripheral clock
disable, 48 MHz core/24 MHz flash, VDD = 3.0
V
• at 25 °C
• at 85 °C
—
—
5.71
5.79
5.94
6.02
mA
—
IDD_RUN Run mode current—48M HIRC mode, running
While(1) loop in Flash all peripheral clock
disable, 24 MHz core/12 MHz flash, VDD = 3.0
V
• at 25 °C
• at 85 °C
—
—
3.3
3.37
3.43
3.50
mA
—
IDD_RUN Run mode current—48M HIRC mode, Running
While(1) loop in Flash all peripheral clock
disable, 12 MHz core/6 MHz flash, VDD = 3.0 V
• at 25 °C
• at 85 °C
—
—
2.28
2.35
2.37
2.44
mA
—
IDD_RUN Run mode current—48M HIRC mode, Running
While(1) loop in Flash all peripheral clock
enable, 48 MHz core/24 MHz flash, VDD = 3.0
V
• at 25 °C
• at 85 °C
—
—
6.1
6.19
6.34
6.44
mA
—
IDD_RUN Run mode current—48M HIRC mode, running
While(1) loop in SRAM all peripheral clock
disable, 48 MHz core/24 MHz flash, VDD = 3.0
V
—
—
3.14
3.24
3.23
3.33
mA
—
Table continues on the next page...
General
16 Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017
NXP Semiconductors
Table 11. KL03 WLCSP package power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max.1Unit Notes
• at 25 °C
• at 85 °C
IDD_RUN Run mode current—48M HIRC mode, running
While(1) loop in SRAM all peripheral clock
enable, 48 MHz core/24 MHz flash, VDD = 3.0
V
• at 25 °C
• at 85 °C
—
—
3.54
3.64
3.63
3.73
mA
—
IDD_VLPRCO Very-low-power run While(1) loop in flash in
compute operation mode— 2 MHz LIRC mode,
2 MHz core/0.5 MHz flash, VDD = 3.0 V
• at 25 °C
—
500
750
μA
—
IDD_VLPRCO Very-low-power-run While(1) loop in SRAM in
compute operation mode— 8 MHz LIRC mode,
4 MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C
—
188
217
μA
—
IDD_VLPRCO Very-low-power run While(1) loop in SRAM in
compute operation mode:—2 MHz LIRC mode,
2 MHz core / 0.5 MHz flash, VDD = 3.0 V
• at 25 °C
—
82
123
μA
—
IDD_VLPR Very-low-power run mode current— 2 MHz
LIRC mode, While(1) loop in flash all peripheral
clock disable, 2 MHz core / 0.5 MHz flash, VDD
= 3.0 V
• at 25 °C
—
503
754
μA
—
IDD_VLPR Very-low-power run mode current— 2 MHz
LIRC mode, While(1) loop in flash all peripheral
clock disable, 125 kHz core / 31.25 kHz flash,
VDD = 3.0 V
• at 25 °C
—
60
90
μA
—
IDD_VLPR Very-low-power run mode current— 2 MHz
LIRC mode, While(1) loop in flash all peripheral
clock enable, 2 MHz core / 0.5 MHz flash, VDD
= 3.0 V
• at 25 °C
—
516
774
μA
—
IDD_VLPR Very-low-power run mode current— 8 MHz
LIRC mode, While(1) loop in SRAM in all
peripheral clock disable, 4 MHz core / 1 MHz
flash, VDD = 3.0 V
• at 25 °C
—
209
350
μA
—
IDD_VLPR Very-low-power run mode current— 8 MHz
LIRC mode, While(1) loop in SRAM all
peripheral clock enable, 4 MHz core / 1 MHz
flash, VDD = 3.0 V
• at 25 °C
—
229
370
μA
—
IDD_VLPR Very-low-power run mode current—2 MHz
LIRC mode, While(1) loop in SRAM in all
—
Table continues on the next page...
General
Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 17
NXP Semiconductors
Table 11. KL03 WLCSP package power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max.1Unit Notes
peripheral clock disable, 2 MHz core / 0.5 MHz
flash, VDD = 3.0 V
• at 25 °C
— 93 140 μA
IDD_VLPR Very-low-power run mode current—2 MHz
LIRC mode, While(1) loop in SRAM all
peripheral clock disable, 125 kHz core / 31.25
kHz flash, VDD = 3.0 V
• at 25 °C
—
31
81
μA
—
IDD_VLPR Very-low-power run mode current—2 MHz
LIRC mode, While(1) loop in SRAM all
peripheral clock enable, 2 MHz core / 0.5 MHz
flash, VDD = 3.0 V
• at 25 °C
—
103
154
μA
—
IDD_WAIT Wait mode current—core disabled, 48 MHz
system/24 MHz bus, flash disabled (flash doze
enabled), all peripheral clocks disabled,
MCG_Lite under HIRC mode, VDD = 3.0 V
—
1.4
1.94
mA
—
IDD_WAIT Wait mode current—core disabled, 24 MHz
system/12 MHz bus, flash disabled (flash doze
enabled), all peripheral clocks disabled,
MCG_Lite under HIRC mode, VDD = 3.0 V
—
1.02
1.24
mA
—
IDD_VLPW Very-low-power wait mode current, core
disabled, 4 MHz system/ 1 MHz bus and flash,
all peripheral clocks disabled, VDD = 3.0 V
— 121 181 μA —
IDD_VLPW Very-low-power wait mode current, core
disabled, 2 MHz system/ 0.5 MHz bus and
flash, all peripheral clocks disabled, VDD = 3.0
V
— 59 97 μA —
IDD_VLPW Very-low-power wait mode current, core
disabled, 125 kHz system/ 31.25 kHz bus and
flash, all peripheral clocks disabled, VDD = 3.0
V
— 28 42 μA —
IDD_PSTOP2 Partial Stop 2, core and system clock disabled,
12 MHz bus and flash, VDD = 3.0 V
—
1.53
2.03
mA
—
IDD_PSTOP2 Partial Stop 2, core and system clock disabled,
flash doze enabled, 12 MHz bus, VDD = 3.0 V
—
0.881
1.18
mA
—
IDD_STOP Stop mode current at 3.0 V
• at 25 °C and below
• at 50 °C
• at 85 °C
—
—
—
158
164
187
175.7
179.48
199.54
μA
—
IDD_VLPS Very-low-power stop mode current at 3.0 V
• at 25 °C and below
—
—
2.2
3.9
2.71
6.63
—
Table continues on the next page...
General
18 Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017
NXP Semiconductors
Table 11. KL03 WLCSP package power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max.1Unit Notes
• at 50 °C
• at 85 °C
— 13.9 18.25 μA
IDD_VLPS Very-low-power stop mode current at 1.8 V
• at 25 °C and below
• at 50 °C
• at 85 °C
—
—
—
2.2
3.8
13.2
2.674
6.44
17.37
μA
—
IDD_VLLS3 Very-low-leakage stop mode 3 current, all
peripheral disable, at 3.0 V
• at 25 °C and below
• at 50 °C
• at 85 °C
—
—
—
1.08
1.4
3.45
1.17
1.52
3.96
μA
—
IDD_VLLS3 Very-low-leakage stop mode 3 current with
RTC current, at 3.0 V
• at 25 °C and below
• at 50 °C
• at 85 °C
—
—
—
1.47
1.82
3.93
1.56
1.94
4.44
μA
—
IDD_VLLS3 Very-low-leakage stop mode 3 current with
RTC current, at 1.8 V
• at 25 °C and below
• at 50 °C
• at 85 °C
—
—
—
1.33
1.65
3.56
1.42
1.77
4.07
μA
—
IDD_VLLS1 Very-low-leakage stop mode 1 current all
peripheral disabled at 3.0 V
• at 25 °C and below
• at 50°C
• at 85°C
—
—
—
566
788
2270
690
839
2600
nA
—
IDD_VLLS1 Very-low-leakage stop mode 1 current RTC
enabled at 3.0 V
• at 25 °C and below
• at 50°C
• at 85°C
—
—
—
969
1200
2740
1059
1251
3070
nA
—
IDD_VLLS1 Very-low-leakage stop mode 1 current RTC
enabled at 1.8 V
• at 25 °C and below
• at 50°C
• at 85°C
—
—
—
826
1040
2400
916
1091
2730
nA
—
IDD_VLLS0 Very-low-leakage stop mode 0 current all
peripheral disabled
(SMC_STOPCTRL[PORPO] = 0) at 3.0 V
—
265
373
—
Table continues on the next page...
General
Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 19
NXP Semiconductors
Table 11. KL03 WLCSP package power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max.1Unit Notes
• at 25 °C and below
• at 50 °C
• at 85 °C
—
—
467
1920
512.9
2256
nA
IDD_VLLS0 Very-low-leakage stop mode 0 current all
peripheral disabled
(SMC_STOPCTRL[PORPO] = 1) at 3 V
• at 25 °C and below
• at 50 °C
• at 85 °C
—
—
—
77
255
1640
350
465.70
1994
nA
4
1. The maximum values represent characterized results equivalent to the mean plus three times the standard deviation
(mean + 3 sigma).
2. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
3. MCG_Lite configured for HIRC mode. CoreMark benchmark compiled using IAR 7.10 with optimization level high,
optimized for balanced.
4. No brownout
Table 12. Low power mode peripheral adders — typical value
Symbol Description Temperature (°C) Unit
-40 25 50 70 85 1051
ILIRC8MHz 8 MHz internal reference clock (LIRC)
adder. Measured by entering STOP or
VLPS mode with 8 MHz LIRC enabled,
MCG_SC[FCRDIV]=000b,
MCG_MC[LIRC_DIV2]=000b.
68 68 68 68 68 68 µA
ILIRC2MHz 2 MHz internal reference clock (LIRC)
adder. Measured by entering STOP
mode with the 2 MHz LIRC enabled,
MCG_SC[FCRDIV]=000b,
MCG_MC[LIRC_DIV2]=000b.
27 27 27 27 27 27 µA
IEREFSTEN32KHz External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN
and EREFSTEN] bits. Measured by
entering all modes with the crystal
enabled.
• VLLS1
• VLLS3
• VLPS
• STOP
340
340
340
340
410
410
420
420
460
460
480
480
470
490
570
570
480
530
610
610
600
600
850
850
nA
ILPTMR LPTMR peripheral adder measured by
placing the device in VLLS1 mode with
LPTMR enabled using LPO.
30
30
30
85
100
200
nA
Table continues on the next page...
General
20 Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017
NXP Semiconductors
Table 12. Low power mode peripheral adders — typical value (continued)
Symbol Description Temperature (°C) Unit
-40 25 50 70 85 1051
ICMP CMP peripheral adder measured by
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and a
single external input for compare.
Includes 6-bit DAC power consumption.
15 15 15 15 15 15 µA
IRTC RTC peripheral adder measured by
placing the device in VLLS1 mode with
external 32 kHz crystal enabled by
means of the RTC_CR[OSCE] bit and
the RTC ALARM set for 1 minute.
Includes ERCLK32K (32 kHz external
crystal) power consumption.
340 440 440 480 520 620 nA
IUART UART peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source waiting
for RX data at 115200 baud rate.
Includes selected clock source power
consumption.
• LIRC8M (8 MHz internal
reference clock)
• LIRC2M (2 MHz internal
reference clock)
85
28
85
28
85
28
85
28
85
28
85
28
µA
ITPM TPM peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source
configured for output compare
generating 100 Hz clock signal. No load
is placed on the I/O generating the
clock signal. Includes selected clock
source and I/O switching currents.
• LIRC8M (8 MHz internal
reference clock)
• LIRC2M (2 MHz internal
reference clock)
93
35
93
35
93
35
93
35
93
35
93
35
µA
IBG Bandgap adder when BGEN bit is set
and device is placed in VLPx or VLLSx
mode.
45 45 45 45 45 45 µA
IADC ADC peripheral adder combining the
measured values at VDD and VDDA by
placing the device in STOP or VLPS
mode. ADC is configured for low power
mode using the internal clock and
continuous conversions.
340 340 340 340 340 340 µA
1. For QFN packages only.
General
Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 21
NXP Semiconductors
2.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG-Lite in HIRC for run mode, and LIRC for VLPR mode
• No GPIOs toggled
• Code execution from flash
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA
4.00E-03
5.00E-03
6.00E-03
7.00E-03
Current Consumption on VDD (A)
Run Mode Current vs Core Frequency
ALLOFF
Temperature=25, VDD=3, MCG Mode=HIRC, while loop located in Flash
All Peripheral CLK Gates
000.00E+00
1.00E-03
2.00E-03
3.00E-03
'1-1 '1-1 '1-1 '1-1 1-1 '1-2
3 6 8 12 24 48
Current Consumption on VDD (A)
ALLON
CLK Ratio
Flash - Core
Core Freq (MHz)
Figure 3. Run mode supply current vs. core frequency (loop located in flash)
General
22 Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017
NXP Semiconductors
2.00E-03
2.50E-03
3.00E-03
3.50E-03
4.00E-03
Current Consumption on VDD (A)
Run Mode Current vs Core Frequency
ALLOFF
Temperature=25, VDD=3, MCG Mode=HIRC, while loop located in SRAM
All Peripheral CLK Gates
000.00E+00
500.00E-06
1.00E-03
1.50E-03
'1-1 '1-1 '1-1 '1-1 1-1 '1-2
3 6 8 12 24 48
Current Consumption on VDD (A)
ALLON
CLK Ratio
Flash - Core
Core Freq (MHz)
Figure 4. Run mode supply current vs. core frequency (loop located in SRAM)
General
Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 23
NXP Semiconductors
150.00E-06
200.00E-06
250.00E-06
Current Consumption on VDD (A)
VLPR Mode Current vs Core Frequency
ALLOFF
All Peripheral CLK Gates
Temperature=25, VDD=3, MCG=LIRC8M, while loop in SRAM
000.00E+00
50.00E-06
100.00E-06
'1-1 '1-2 '1-4
1 2 4
Current Consumption on VDD (A)
ALLON
CLK Ratio
Flash - Core
Figure 5. VLPR mode current vs. core frequency (loop in SRAM)
2.2.6 EMC radiated emissions operating behaviors
Table 13. EMC radiated emissions operating behaviors for 24-pin QFN package
Symbol Description Frequency
band
(MHz)
Typ. Unit Notes
VRE1 Radiated emissions voltage, band 1 0.15–50 5 dBμV 1, 2
VRE2 Radiated emissions voltage, band 2 50–150 7 dBμV
VRE3 Radiated emissions voltage, band 3 150–500 5 dBμV
VRE4 Radiated emissions voltage, band 4 500–1000 5 dBμV
VRE_IEC IEC/SAE level 0.15–1000 N — 2, 3
1. Determined according to IEC 61967-2 (and SAE J1752/3) radiated radio frequency (RF) emissions measurement
standard. Typical Configuration: Appendix B: DUT Software Configuration—2. Typical Configuration.
2. VDD = 3.3 V, TA = 25 °C, firc48m = 48 MHz, fSYS = 48 MHz, fBUS = 24 MHz
3. IEC/SAE Level Maximums: N≤12 dBµV, M≤18 dBµV, L≤24 dBµV, K≤30 dBµV, I ≤ 36 dBµV, H ≤ 42 dBµV, G≤48 dBµV.
General
24 Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017
NXP Semiconductors
2.2.7 EMC Radiated Emissions Web Search Procedure boilerplate
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.nxp.com.
2. Perform a keyword search for "EMC design"
2.2.8 Capacitance attributes
Table 14. Capacitance attributes
Symbol Description Min. Max. Unit
CIN Input capacitance — 7 pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 15. Device clock specifications
Symbol Description Min. Max. Unit
Normal run mode
fSYS System and core clock — 48 MHz
fBUS Bus clock — 24 MHz
fFLASH Flash clock — 24 MHz
fLPTMR LPTMR clock — 24 MHz
VLPR and VLPS modes1
fSYS System and core clock — 4 MHz
fBUS Bus clock — 1 MHz
fFLASH Flash clock — 1 MHz
fLPTMR LPTMR clock2— 24 MHz
fERCLK External reference clock — 16 MHz
fERCLK External reference clock — 32.768 kHz
fLPTMR_ERCLK LPTMR external reference clock — 16 MHz
fTPM TPM asynchronous clock — 8 MHz
fUART0 UART0 asynchronous clock — 8 MHz
General
Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 25
NXP Semiconductors
1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN
or from VLPR.
2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.
2.3.2 General switching specifications
These general-purpose specifications apply to all signals configured for GPIO and
UART signals.
Table 16. General switching specifications
Description Min. Max. Unit Notes
GPIO pin interrupt pulse width (digital glitch filter disabled) —
Synchronous path
1.5 — Bus clock
cycles
1
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100 — ns 2
GPIO pin interrupt pulse width — Asynchronous path 16 — ns 2
Port rise and fall time — 36 ns 3
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. 75 pF load
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 17. Thermal operating requirements of WLCSP package
Symbol Description Min. Max. Unit Note
TJDie junction temperature –40 95 °C
TAAmbient temperature –40 85 °C 1
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to
determine TJ is: TJ = TA + RθJA × chip power dissipation.
Table 18. Thermal operating requirements of other packages
Symbol Description Min. Max. Unit Note
TJDie junction temperature –40 125 °C
TAAmbient temperature –40 105 °C 1
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to
determine TJ is: TJ = TA + RθJA × chip power dissipation.
General
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2.4.2 Thermal attributes
Table 19. Thermal attributes
Board type Symbol Description 16 QFN 20
WLCSP
24 QFN Unit Notes
Single-layer (1S) RθJA Thermal resistance, junction to
ambient (natural convection)
64.2 69.8 60.7 °C/W 1,2
Four-layer (2s2p) RθJA Thermal resistance, junction to
ambient (natural convection)
53.3 57.5 48.5 °C/W 1,2,3
Single-layer (1S) RθJMA Thermal resistance, junction to
ambient (200 ft./min. air speed)
55.4 62.03 51.0 °C/W 1,3
Four-layer (2s2p) RθJMA Thermal resistance, junction to
ambient (200 ft./min. air speed)
48.9 54.3 43.6 °C/W 1,3
— RθJB Thermal resistance, junction to
board
33.5 51.64 30.4 °C/W 4
— RθJC Thermal resistance, junction to
case
20.9 0.73 9.8 °C/W 5
—ΨJT Thermal characterization
parameter, junction to package
top outside center (natural
convection)
0.2 0.2 0.2 °C/W 6
—ΨJB Thermal characterization
parameter, junction to package
bottom outside center (natural
convection)
22.4 ―21.8 °C/W 7
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
3. Per JEDEC JESD51-6 with the board horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is
written as Psi-JT.
7. Thermal characterization parameter indicating the temperature difference between package bottom center and the
junction temperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JB.
3 Peripheral operating requirements and behaviors
3.1 Core modules
Peripheral operating requirements and behaviors
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3.1.1 SWD electricals
Table 20. SWD full voltage range electricals
Symbol Description Min. Max. Unit
Operating voltage 1.71 3.6 V
J1 SWD_CLK frequency of operation
• Serial wire debug
0
25
MHz
J2 SWD_CLK cycle period 1/J1 — ns
J3 SWD_CLK clock pulse width
• Serial wire debug
20
—
ns
J4 SWD_CLK rise and fall times — 3 ns
J9 SWD_DIO input data setup time to SWD_CLK rise 10 — ns
J10 SWD_DIO input data hold time after SWD_CLK rise 0 — ns
J11 SWD_CLK high to SWD_DIO data valid — 32 ns
J12 SWD_CLK high to SWD_DIO high-Z 5 — ns
J2
J3 J3
J4 J4
SWD_CLK (input)
Figure 6. Serial wire clock input timing
Peripheral operating requirements and behaviors
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J11
J12
J11
J9 J10
Input data valid
Output data valid
Output data valid
SWD_CLK
SWD_DIO
SWD_DIO
SWD_DIO
SWD_DIO
Figure 7. Serial wire data timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
3.3.1 MCG-Lite specifications
Table 21. HIRC48M specification
Symbol Description Min. Typ. Max. Unit Notes
VDD Supply voltage 1.71 — 3.6 V —
IDD48M Supply current — 400 500 μA —
firc48m Internal reference frequency — 48 — MHz —
Δfirc48m_ol_lv total deviation of IRC48M frequency at low voltage
(VDD=1.71V-1.89V) over temperature
—
± 0.5
±1.5
%firc48m
—
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Table 21. HIRC48M specification (continued)
Symbol Description Min. Typ. Max. Unit Notes
Δfirc48m_ol_hv total deviation of IRC48M frequency at high voltage
(VDD=1.89V-3.6V) over temperature
—
± 0.5
±1.0
%firc48m
—
Jcyc_irc48m Period Jitter (RMS) — 35 150 ps —
tirc48mst Startup time — 2 3 μs 1
1. IRC48M startup time is defined as the time between clock enablement and clock availability for system use. Enable the
clock by setting MCG_MC[HIRCEN] = 1. See reference manual for details.
Table 22. LIRC8M/2M specification
Symbol Description Min. Typ. Max. Unit Notes
VDD Supply voltage 1.08 — 1.47 V —
T Temperature range -40 — 125 °C —
IDD_2M Supply current in 2 MHz mode — 14 17 µA —
IDD_8M Supply current in 8 MHz mode — 30 35 µA —
fIRC_2M Output frequency — 2 — MHz —
fIRC_8M Output frequency — 8 — MHz —
fIRC_T_2M Output frequency range (trimmed) — — ±3 %fIRC VDD≥1.89 V
fIRC_T_8M Output frequency range (trimmed) — — ±3 %fIRC VDD≥1.89 V
Tsu_2M Startup time — — 12.5 µs —
Tsu_8M Startup time — — 12.5 µs —
3.3.2 Oscillator electrical specifications
3.3.2.1 Oscillator DC electrical specifications
Table 23. Oscillator DC electrical specifications
Symbol Description Min. Typ. Max. Unit Notes
VDD Supply voltage 1.71 — 3.6 V —
IDDOSC Supply current — low-power mode
• 32 kHz
—
500
—
nA
1
CxEXTAL load capacitance — — — 2, 3
CyXTAL load capacitance — — — 2, 3
RFFeedback resistor — low-frequency, low-power
mode
— — — MΩ 2, 4
RSSeries resistor — low-frequency, low-power
mode
— — — kΩ —
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Table 23. Oscillator DC electrical specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
Vpp5Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
— 0.6 — V —
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using either the integrated capacitors or by using external components.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
3.3.2.2 Oscillator frequency specifications
Table 24. Oscillator frequency specifications
Symbol Description Min. Typ. Max. Unit Notes
fosc_lo Oscillator crystal or resonator frequency — low
frequency mode
32 — 40 kHz —
tdc_extal Input clock duty cycle (external clock mode) 40 50 60 % —
tcst Crystal startup time — 32 kHz low-frequency,
low-power mode
— 750 — ms 1, 2
1. Proper PC board layout procedures must be followed to achieve specifications.
2. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
3.4 Memories and memory interfaces
3.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
3.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps
are active and do not include command overhead.
Table 25. NVM program/erase timing specifications
Symbol Description Min. Typ. Max. Unit Notes
thvpgm4 Longword Program high-voltage time — 7.5 18 μs —
thversscr Sector Erase high-voltage time — 13 113 ms 1
thversall Erase All high-voltage time — 52 452 ms 1
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1. Maximum time based on expectations at cycling end-of-life.
3.4.1.2 Flash timing specifications — commands
Table 26. Flash command timing specifications
Symbol Description Min. Typ. Max. Unit Notes
trd1sec1k Read 1s Section execution time (flash sector) — — 60 μs 1
tpgmchk Program Check execution time — — 45 μs 1
trdrsrc Read Resource execution time — — 30 μs 1
tpgm4 Program Longword execution time — 65 145 μs —
tersscr Erase Flash Sector execution time — 14 114 ms 2
trd1all Read 1s All Blocks execution time — — 0.5 ms —
trdonce Read Once execution time — — 25 μs 1
tpgmonce Program Once execution time — 65 — μs —
tersall Erase All Blocks execution time — 61 500 ms 2
tvfykey Verify Backdoor Access Key execution time — — 30 μs 1
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3.4.1.3 Flash high voltage current behaviors
Table 27. Flash high voltage current behaviors
Symbol Description Min. Typ. Max. Unit
IDD_PGM Average current adder during high voltage
flash programming operation
— 2.5 6.0 mA
IDD_ERS Average current adder during high voltage
flash erase operation
— 1.5 4.0 mA
3.4.1.4 Reliability specifications
Table 28. NVM reliability specifications
Symbol Description Min. Typ.1Max. Unit Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles 5 50 — years —
tnvmretp1k Data retention after up to 1 K cycles 20 100 — years —
nnvmcycp Cycling endurance 10 K 50 K — cycles 2
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40 °C ≤ Tj ≤ 125 °C.
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3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
3.6 Analog
3.6.1 ADC electrical specifications
All ADC channels meet the 12-bit single-ended accuracy specifications.
3.6.1.1 12-bit ADC operating conditions
Table 29. 12-bit ADC operating conditions
Symbol Description Conditions Min. Typ.1Max. Unit Notes
VDDA Supply voltage Absolute 1.71 — 3.6 V —
ΔVDDA Supply voltage Delta to VDD (VDD – VDDA) -100 0 +100 mV 2
ΔVSSA Ground voltage Delta to VSS (VSS – VSSA) -100 0 +100 mV 2
VREFH ADC reference
voltage high
1.13 VDDA VDDA V3
VREFL ADC reference
voltage low
VSSA VSSA VSSA V3
VADIN Input voltage VREFL — VREFH V —
CADIN Input
capacitance
• 8-bit / 10-bit / 12-bit
modes
— 4 5 pF —
RADIN Input series
resistance
— 2 5 kΩ —
RAS Analog source
resistance
(external)
12-bit modes
fADCK < 4 MHz
—
—
5
kΩ
4
fADCK ADC conversion
clock frequency
≤ 12-bit mode 1.0 — 18.0 MHz 5
Crate ADC conversion
rate
≤ 12-bit modes
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
20.000
—
818.330
Ksps
6
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
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3. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to
VSSA.
4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
RAS
VAS CAS
ZAS
VADIN
ZADIN
RADIN
RADIN
RADIN
RADIN
CADIN
Pad
leakage
due to
input
protection
INPUT PIN
INPUT PIN
INPUT PIN
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
ADC SAR
ENGINE
Figure 8. ADC input impedance equivalency diagram
3.6.1.2 12-bit ADC electrical characteristics
Table 30. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol Description Conditions1. Min. Typ.2Max. Unit Notes
IDDA_ADC Supply current 0.215 — 1.7 mA 3
fADACK
ADC
asynchronous
clock source
• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1
1.2
2.4
3.0
4.4
2.4
4.0
5.2
6.2
3.9
6.1
7.3
9.5
MHz
MHz
MHz
MHz
tADACK =
1/fADACK
Sample Time See Reference Manual chapter for sample times
TUE Total
unadjusted error
• 12-bit modes
• <12-bit modes
—
—
±6
±3
—
±6
LSB45
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Table 30. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description Conditions1. Min. Typ.2Max. Unit Notes
DNL Differential non-
linearity
• 12-bit modes
• <12-bit modes
—
—
±0.9
±0.4
–1.1 to
+1.9
–0.3 to 0.5
LSB45
INL Integral non-
linearity
• 12-bit modes
• <12-bit modes
—
—
±1.5
±0.5
–2.7 to
+1.9
–0.7 to
+0.5
LSB45
EFS Full-scale error • 12-bit modes
• <12-bit modes
—
—
5
2
—
3
LSB4VADIN =
VDDA5
EQQuantization
error
• 12-bit modes — — ±0.5 LSB4
EIL Input leakage
error
IIn × RAS mV IIn =
leakage
current
(refer to
the MCU's
voltage
and
current
operating
ratings)
Temp sensor
slope
Across the full temperature range
of the device
1.55 1.62 1.69 mV/°C 6
VTEMP25 Temp sensor
voltage
25 °C 706 716 726 mV 6
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with
1 MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. ADC conversion clock < 3 MHz
Table 31. 12-bit ADC characteristics (VREFH = VREFO, VREFL = VSSA)
Symbol Description Conditions1. Min. Typ.2Max. Unit Notes
IDDA_ADC Supply current 0.215 — 1.7 mA 3
fADACK
ADC
asynchronous
clock source
• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1
1.2
2.4
3.0
4.4
2.4
4.0
5.2
6.2
3.9
6.1
7.3
9.5
MHz
MHz
MHz
MHz
tADACK =
1/fADACK
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Table 31. 12-bit ADC characteristics (VREFH = VREFO, VREFL = VSSA) (continued)
Symbol Description Conditions1. Min. Typ.2Max. Unit Notes
Sample Time See Reference Manual chapter for sample times
TUE Total
unadjusted
error
• 12-bit modes
• <12-bit modes
—
—
±4
±1.4
±6.8
±2.1
LSB45
DNL Differential non-
linearity
• 12-bit modes
• <12-bit modes
—
—
±0.7
±0.2
–1.1 to
+1.9
–0.3 to
0.5
LSB45
INL Integral non-
linearity
• 12-bit modes
• <12-bit modes
—
—
±1.0
±0.5
–2.7 to
+1.9
–0.7 to
+0.5
LSB45
EFS Full-scale error • 12-bit modes
• <12-bit modes
—
—
–4
–1.4
–5.4
–1.8
LSB4VADIN =
VDDA5
EQQuantization
error
• 12-bit modes — — ±0.5 LSB4
EIL Input leakage
error
IIn × RAS mV IIn =
leakage
current
(refer to
the MCU's
voltage
and
current
operating
ratings)
Temp sensor
slope
Across the full temperature range
of the device
1.55 1.62 1.69 mV/°C 6
VTEMP25 Temp sensor
voltage
25 °C 706 716 726 mV 6
1. All accuracy numbers assume the ADC is calibrated with VREFH = VREFO
2. Typical values assume VREFO = 1.2 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1
MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. ADC conversion clock < 3 MHz
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ADC Clock Frequency (MHz)
0 2 4 6 8 10 12 14 16 18 2220
Hardware Averaging Disabled
Averaging of 8 samples
Averaging of 32 samples
10
10.1
10.3
10.2
10.4
10.5
10.6
10.7
10.8
10.9
11
11.1
11.3
11.2
11.4
11.5
11.6
11.7
11.8
11.9
ENOB
Typical ADC 12-bit Single Ended ENOB vs ADC Clock
100Hz, 90% FS Sine Input
Figure 9. Typical ENOB vs. ADC_CLK for 12-bit single-ended mode
3.6.2 CMP and 6-bit DAC electrical specifications
Table 32. Comparator and 6-bit DAC electrical specifications
Symbol Description Min. Typ. Max. Unit
VDD Supply voltage 1.71 — 3.6 V
IDDHS Supply current, High-speed mode (EN=1,
PMODE=1)
— — 200 μA
IDDLS Supply current, low-speed mode (EN=1, PMODE=0) — — 20 μA
VAIN Analog input voltage VSS – 0.3 — VDD V
VAIO Analog input offset voltage — — 20 mV
VHAnalog comparator hysteresis1
• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
—
—
—
—
5
10
20
30
—
—
—
—
mV
mV
mV
mV
VCMPOh Output high VDD – 0.5 — — V
VCMPOl Output low — — 0.5 V
tDHS Propagation delay, high-speed mode (EN=1,
PMODE=1)
20 50 200 ns
tDLS Propagation delay, low-speed mode (EN=1,
PMODE=0)
80 250 600 ns
Analog comparator initialization delay2— — 40 μs
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Table 32. Comparator and 6-bit DAC electrical specifications (continued)
Symbol Description Min. Typ. Max. Unit
IDAC6b 6-bit DAC current adder (enabled) — 7 — μA
INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3
DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
00
01
10
HYSTCTR
Setting
0.1
10
11
Vin level (V)
CMP Hystereris (V)
3.12.82.5
2.2
1.91.61.3
1
0.70.4
0.05
0
0.01
0.02
0.03
0.08
0.07
0.06
0.04
Figure 10. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
Peripheral operating requirements and behaviors
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00
01
10
HYSTCTR
Setting
10
11
0.1 3.12.82.5
2.2
1.91.61.3
1
0.70.4
0.1
0
0.02
0.04
0.06
0.18
0.14
0.12
0.08
0.16
Vin level (V)
CMP Hysteresis (V)
Figure 11. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
3.6.3 Voltage reference electrical specifications
Table 33. VREF full-range operating requirements
Symbol Description Min. Max. Unit Notes
VDDA Supply voltage 1.71 3.6 V —
TATemperature Operating temperature
range of the device
°C —
CLOutput load capacitance 100 nF 1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature
range of the device.
Table 34 is tested under the condition of setting VREF_TRM[CHOPEN],
VREF_SC[REGEN] and VREF_SC[ICOMPEN] bits to 1.
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Table 34. VREF full-range operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
Vout Voltage reference output with factory trim at
nominal VDDA and temperature=25C
1.1915 1.195 1.1977 V 1
Vout Voltage reference output — factory trim 1.1584 — 1.2376 V 1
Vout Voltage reference output — user trim 1.193 — 1.197 V 1
Vstep Voltage reference trim step — 0.5 — mV 1
Vtdrift Temperature drift (Vmax -Vmin across the full
temperature range: 0 to 70°C)
— — 50 mV 1
Ac Aging coefficient — — 400 uV/yr —
Ibg Bandgap only current — — 80 µA 1
Ilp Low-power buffer current — — 360 uA 1
Ihp High-power buffer current — — 1 mA 1
ΔVLOAD Load regulation
• current = ± 1.0 mA
—
200
—
µV 1, 2
Tstup Buffer startup time — — 100 µs —
Vvdrift Voltage drift (Vmax -Vmin across the full voltage
range)
— 2 — mV 1
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 35. VREF limited-range operating requirements
Symbol Description Min. Max. Unit Notes
TATemperature 0 50 °C —
Table 36. VREF limited-range operating behaviors
Symbol Description Min. Max. Unit Notes
Vout Voltage reference output with factory trim 1.173 1.225 V —
3.7 Timers
See General switching specifications.
3.8 Communication interfaces
Peripheral operating requirements and behaviors
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3.8.1 SPI switching specifications
The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master
and slave operations. Many of the transfer attributes are programmable. The following
tables provide timing characteristics for classic SPI timing modes. See the SPI chapter
of the chip's Reference Manual for information about the modified transfer formats
used for communicating with slower peripheral devices.
All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted,
as well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins.
Table 37. SPI master mode timing on slew rate disabled pads
Num. Symbol Description Min. Max. Unit Note
1 fop Frequency of operation fperiph/2048 fperiph/2 Hz 1
2 tSPSCK SPSCK period 2 x tperiph 2048 x
tperiph
ns 2
3 tLead Enable lead time 1/2 — tSPSCK —
4 tLag Enable lag time 1/2 — tSPSCK —
5 tWSPSCK Clock (SPSCK) high or low time tperiph – 30 1024 x
tperiph
ns —
6 tSU Data setup time (inputs) 22 — ns —
7 tHI Data hold time (inputs) 0 — ns —
8 tvData valid (after SPSCK edge) — 10 ns —
9 tHO Data hold time (outputs) 0 — ns —
10 tRI Rise time input — tperiph – 25 ns —
tFI Fall time input
11 tRO Rise time output — 25 ns —
tFO Fall time output
1. For SPI0, fperiph is the bus clock (fBUS).
2. tperiph = 1/fperiph
Table 38. SPI master mode timing on slew rate enabled pads
Num. Symbol Description Min. Max. Unit Note
1 fop Frequency of operation fperiph/2048 fperiph/2 Hz 1
2 tSPSCK SPSCK period 2 x tperiph 2048 x
tperiph
ns 2
3 tLead Enable lead time 1/2 — tSPSCK —
4 tLag Enable lag time 1/2 — tSPSCK —
Table continues on the next page...
Peripheral operating requirements and behaviors
Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 41
NXP Semiconductors
Table 38. SPI master mode timing on slew rate enabled pads (continued)
Num. Symbol Description Min. Max. Unit Note
5 tWSPSCK Clock (SPSCK) high or low time tperiph – 30 1024 x
tperiph
ns —
6 tSU Data setup time (inputs) 96 — ns —
7 tHI Data hold time (inputs) 0 — ns —
8 tvData valid (after SPSCK edge) — 52 ns —
9 tHO Data hold time (outputs) 0 — ns —
10 tRI Rise time input — tperiph – 25 ns —
tFI Fall time input
11 tRO Rise time output — 36 ns —
tFO Fall time output
1. For SPI0, fperiph is the bus clock (fBUS).
2. tperiph = 1/fperiph
(OUTPUT)
2
8
6 7
MSB IN2
LSB IN
MSB OUT2 LSB OUT
9
5
5
3
(CPOL=0)
4
11
11
10
10
SPSCK
SPSCK
(CPOL=1)
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
1. If configured as an output.
SS1
(OUTPUT)
(OUTPUT)
MOSI
(OUTPUT)
MISO
(INPUT) BIT 6 . . . 1
BIT 6 . . . 1
Figure 12. SPI master mode timing (CPHA = 0)
Peripheral operating requirements and behaviors
42 Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017
NXP Semiconductors
<<CLASSIFICATION>>
<<NDA MESSAGE>>
38
2
6 7
MSB IN2
BIT 6 . . . 1
MASTER MSB OUT2 MASTER LSB OUT
5
5
8
10 11
PORT DATA PORT DATA
310 11 4
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
9
(OUTPUT)
(CPOL=0)
SPSCK
SPSCK
(CPOL=1)
SS1
(OUTPUT)
(OUTPUT)
MOSI
(OUTPUT)
MISO
(INPUT) LSB IN
BIT 6 . . . 1
Figure 13. SPI master mode timing (CPHA = 1)
Table 39. SPI slave mode timing on slew rate disabled pads
Num. Symbol Description Min. Max. Unit Note
1 fop Frequency of operation 0 fperiph/4 Hz 1
2 tSPSCK SPSCK period 4 x tperiph — ns 2
3 tLead Enable lead time 1 — tperiph —
4 tLag Enable lag time 1 — tperiph —
5 tWSPSCK Clock (SPSCK) high or low time tperiph – 30 — ns —
6 tSU Data setup time (inputs) 3 — ns —
7 tHI Data hold time (inputs) 7 — ns —
8 taSlave access time 23 tperiph ns 3
9 tdis Slave MISO disable time 23 tperiph ns 4
10 tvData valid (after SPSCK edge) — 25.7 ns —
11 tHO Data hold time (outputs) 0 — ns —
12 tRI Rise time input — tperiph – 25 ns —
tFI Fall time input
13 tRO Rise time output — 25 ns —
tFO Fall time output
1. For SPI0, fperiph is the bus clock (fBUS).
2. tperiph = 1/fperiph
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
Peripheral operating requirements and behaviors
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Table 40. SPI slave mode timing on slew rate enabled pads
Num. Symbol Description Min. Max. Unit Note
1 fop Frequency of operation 0 fperiph/4 Hz 1
2 tSPSCK SPSCK period 4 x tperiph — ns 2
3 tLead Enable lead time 1 — tperiph —
4 tLag Enable lag time 1 — tperiph —
5 tWSPSCK Clock (SPSCK) high or low time tperiph – 30 — ns —
6 tSU Data setup time (inputs) 2 — ns —
7 tHI Data hold time (inputs) 7 — ns —
8 taSlave access time — tperiph ns 3
9 tdis Slave MISO disable time — tperiph ns 4
10 tvData valid (after SPSCK edge) — 122 ns —
11 tHO Data hold time (outputs) 0 — ns —
12 tRI Rise time input — tperiph – 25 ns —
tFI Fall time input
13 tRO Rise time output — 36 ns —
tFO Fall time output
1. For SPI0, fperiph is the bus clock (fBUS).
2. tperiph = 1/fperiph
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
2
10
6 7
MSB IN
BIT 6 . . . 1
SLAVE MSB SLAVE LSB OUT
11
5
5
3
8
4
13
NOTE: Not defined
12
12
11
SEE
NOTE
13
9
see
note
(INPUT)
(CPOL=0)
SPSCK
SPSCK
(CPOL=1)
SS
(INPUT)
(INPUT)
MOSI
(INPUT)
MISO
(OUTPUT)
LSB IN
BIT 6 . . . 1
Figure 14. SPI slave mode timing (CPHA = 0)
Peripheral operating requirements and behaviors
44 Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017
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2
6 7
MSB IN
BIT 6 . . . 1
MSB OUT SLAVE LSB OUT
5
5
10
12 13
312 13
4
SLAVE
8
9
see
note
(INPUT)
(CPOL=0)
SPSCK
SPSCK
(CPOL=1)
SS
(INPUT)
(INPUT)
MOSI
(INPUT)
MISO
(OUTPUT)
NOTE: Not defined
11
LSB IN
BIT 6 . . . 1
Figure 15. SPI slave mode timing (CPHA = 1)
3.8.2 Inter-Integrated Circuit Interface (I2C) timing
Table 41. I2C timing
Characteristic Symbol Standard Mode Fast Mode Unit
Minimum Maximum Minimum Maximum
SCL Clock Frequency fSCL 0 10010 4002kHz
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tHD; STA 4 — 0.6 — µs
LOW period of the SCL clock tLOW 4.7 — 1.25 — µs
HIGH period of the SCL clock tHIGH 4 — 0.6 — µs
Set-up time for a repeated START
condition
tSU; STA 4.7 — 0.6 — µs
Data hold time for I2C bus devices tHD; DAT 033.454050.93µs
Data set-up time tSU; DAT 2506— 1004, 7— ns
Rise time of SDA and SCL signals tr— 1000 20 +0.1Cb8300 ns
Fall time of SDA and SCL signals tf— 300 20 +0.1Cb7300 ns
Set-up time for STOP condition tSU; STO 4 — 0.6 — µs
Bus free time between STOP and
START condition
tBUF 4.7 — 1.3 — µs
Pulse width of spikes that must be
suppressed by the input filter
tSP N/A N/A 0 50 ns
1. The PTB3 and PTB4 pins can support only the Standard mode.
2. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can be achieved only when using the
normal drive pins and VDD ≥ 2.7 V.
Peripheral operating requirements and behaviors
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3. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
4. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
5. Input signal Slew = 10 ns and Output Load = 50 pF
6. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
7. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU;
DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.
8. Cb = total capacitance of the one bus line in pF.
To achieve 1MHz I2C clock rates, consider the following recommendations:
• To counter the effects of clock stretching, the I2C baud Rate select bits can be
configured for faster than desired baud rate.
• Use high drive pad and DSE bit should be set in PORTx_PCRn register.
• Minimize loading on the I2C SDA and SCL pins to ensure fastest rise times for the
SCL line to avoid clock stretching.
• Use smaller pull up resistors on SDA and SCL to reduce the RC time constant.
Table 42. I 2C 1Mbit/s timing
Characteristic Symbol Minimum Maximum Unit
SCL Clock Frequency fSCL 0 11MHz
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
tHD; STA 0.26 — µs
LOW period of the SCL clock tLOW 0.5 — µs
HIGH period of the SCL clock tHIGH 0.26 — µs
Set-up time for a repeated START condition tSU; STA 0.26 — µs
Data hold time for I2C bus devices tHD; DAT 0 — µs
Data set-up time tSU; DAT 50 — ns
Rise time of SDA and SCL signals tr20 +0.1Cb120 ns
Fall time of SDA and SCL signals tf20 +0.1Cb2120 ns
Set-up time for STOP condition tSU; STO 0.26 — µs
Bus free time between STOP and START condition tBUF 0.5 — µs
Pulse width of spikes that must be suppressed by
the input filter
tSP 0 50 ns
1. The maximum SCL clock frequency of 1 Mbit/s can support 200 pF bus loading when using the normal drive pins and
VDD ≥ 2.7 V.
2. Cb = total capacitance of the one bus line in pF.
Peripheral operating requirements and behaviors
46 Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017
NXP Semiconductors
SDA
HD; STA tHD; DAT
tLOW
tSU; DAT
tHIGH
tSU; STA SR PS
S
tHD; STA tSP
tSU; STO
tBUF
tftr
tftr
SCL
Figure 16. Timing definition for devices on the I2C bus
3.8.3 UART
See General switching specifications.
4Dimensions
4.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to nxp.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package Then use this document number
16-pin QFN 98ASA00525D
24-pin QFN 98ASA00602D
20-pin WLCSP 98ASA00676D
20-pin WLCSP (ultra thin) 98ASA00964D
Dimensions
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NXP Semiconductors
Pinout
5.1 KL03 signal multiplexing and pin assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
NOTE
PTB3 and PTB4 are true open drain pins. The external pullup
resistor must be added to make them output correct values in
using I2C, GPIO, and LPUART0.
24
QFN
20
WLC
SP
16
QFN
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5
1 — — PTB6/
IRQ_2/
LPTMR0_ALT3
DISABLED PTB6/
IRQ_2/
LPTMR0_ALT3
TPM1_CH1 TPM_CLKIN1
2 — — PTB7/
IRQ_3
DISABLED PTB7/
IRQ_3
TPM1_CH0
3 B5 1 VDD VDD VDD
4 C5 2 VSS VSS VSS
5 C4 3 PTA3 EXTAL0 EXTAL0 PTA3 I2C0_SCL I2C0_SDA LPUART0_TX
6 C3 4 PTA4 XTAL0 XTAL0 PTA4 I2C0_SDA I2C0_SCL LPUART0_RX CLKOUT
7 D3 5 PTA5/
RTC_CLK_IN
DISABLED PTA5/
RTC_CLK_IN
TPM0_CH1 SPI0_SS_b
8 D5 6 PTA6 DISABLED PTA6 TPM0_CH0 SPI0_MISO
9 — — PTB10 DISABLED PTB10 TPM0_CH1 SPI0_SS_b
10 — — PTB11 DISABLED PTB11 TPM0_CH0 SPI0_MISO
11 D4 7 PTA7/
IRQ_4
DISABLED PTA7/
IRQ_4
SPI0_MISO SPI0_MOSI
12 C1 8 PTB0/
IRQ_5/
LLWU_P4
ADC0_SE9 ADC0_SE9 PTB0/
IRQ_5/
LLWU_P4
EXTRG_IN SPI0_SCK I2C0_SCL
13 D1 9 PTB1/
IRQ_6
ADC0_SE8/
CMP0_IN3
ADC0_SE8/
CMP0_IN3
PTB1/
IRQ_6
LPUART0_TX LPUART0_RX I2C0_SDA
14 B1 10 PTB2/
IRQ_7
VREF_OUT/
CMP0_IN5
VREF_OUT/
CMP0_IN5
PTB2/
IRQ_7
LPUART0_RX LPUART0_TX
15 D2 — PTA8 ADC0_SE3 ADC0_SE3 PTA8 I2C0_SCL SPI0_MOSI
16 C2 — PTA9 ADC0_SE2 ADC0_SE2 PTA9 I2C0_SDA SPI0_SCK
5
Pinout
48 Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017
NXP Semiconductors
24
QFN
20
WLC
SP
16
QFN
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5
17 A1 11 PTB3/
IRQ_10
DISABLED PTB3/
IRQ_10
I2C0_SCL LPUART0_TX
18 B2 12 PTB4/
IRQ_11
DISABLED PTB4/
IRQ_11
I2C0_SDA LPUART0_RX
19 A2 13 PTB5/
IRQ_12
NMI_b ADC0_SE1/
CMP0_IN1
PTB5/
IRQ_12
TPM1_CH1 NMI_b
20 B3 — PTA12/
IRQ_13/
LPTMR0_ALT2
ADC0_SE0/
CMP0_IN0
ADC0_SE0/
CMP0_IN0
PTA12/
IRQ_13/
LPTMR0_ALT2
TPM1_CH0 TPM_CLKIN0 CLKOUT
21 A3 — PTB13/
CLKOUT32K
DISABLED PTB13/
CLKOUT32K
TPM1_CH1 RTC_CLKOUT
22 A4 14 PTA0/
IRQ_0/
LLWU_P7
SWD_CLK ADC0_SE15/
CMP0_IN2
PTA0/
IRQ_0/
LLWU_P7
TPM1_CH0 SWD_CLK
23 B4 15 PTA1/
IRQ_1/
LPTMR0_ALT1
RESET_b PTA1/
IRQ_1/
LPTMR0_ALT1
TPM_CLKIN0 RESET_b
24 A5 16 PTA2 SWD_DIO PTA2 CMP0_OUT SWD_DIO
5.2 KL03 pinouts
The following figures show the pinout diagrams for the devices supported by this
document. Many signals may be multiplexed onto a single pin. To determine what
signals can be used on which pin, see KL03 signal multiplexing and pin assignments.
Pinout
Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 49
NXP Semiconductors
24
23
22
PTA2
PTA1/IRQ_1/LPTMR0_ALT1
PTA0/IRQ_0/LLWU_P7
PTA12/IRQ_13/LPTMR0_ALT2
PTB5/IRQ_12
21
20
19
PTB13/CLKOUT32K
PTA9
PTA8
16
15
PTB4/IRQ_11
PTB3/IRQ_10
18
17
PTB2/IRQ_7
PTB1/IRQ_6
14
13
PTB0/IRQ_5/LLWU_P4
PTA7/IRQ_4
PTB11
PTB10
12
11
10
9
PTA6 8
PTA5/RTC_CLK_IN 7
PTA4
PTA3
VSS
VDD
PTB7/IRQ_3
PTB6/IRQ_2/LPTMR0_ALT3
6
5
4
3
2
1
Figure 17. KL03 24-pin QFN pinout diagram
1234
A
5
PTB5
B
PTB13
PTA12
PTA4
C
PTA0
PTA1
PTA3
PTA7
DPTA8
PTA9
PTA5
PTB1
PTB0
PTB2
PTA2
VDD
VSS
PTA6
PTB3
PTB4
Figure 18. KL03 20-pin WLCSP pinout diagram
Pinout
50 Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017
NXP Semiconductors
1VDD
2VSS
3PTA3
4PTA4
5PTA5/RTC_CLK_IN
6PTA6
7PTA7/IRQ_4
8PTB0/IRQ_5/LLWU_P4
9PTB1/IRQ_6
10 PTB2/IRQ_7
11 PTB3/IRQ_10
12 PTB4/IRQ_11
13 PTB5/IRQ_12
14 PTA0/IRQ_0/LLWU_P7
15 PTA1/IRQ_1/LPTMR0_ALT1
16 PTA2
Figure 19. KL03 16-pin QFN pinout diagram
6Ordering parts
6.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable
part numbers for this device, go to nxp.com and perform a part number search.
7Part identification
7.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
Ordering parts
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NXP Semiconductors
7.2 Format
Part numbers for this device have the following format:
Q KL## A FFF R T PP CC N
7.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Table 43. Part number fields description
Field Description Values
Q Qualification status • M = Fully qualified, general market flow(full
reels for WLCSP)
• P = Prequalification
• K = Fully qualified, general market flow, 100
pieces reels (WLCSP only)
KL## Kinetis family • KL03
A Key attribute • Z = Cortex-M0+
FFF Program flash memory size • 8 = 8 KB
• 16 = 16 KB
• 32 = 32 KB
R Silicon revision • (Blank) = Main
• A = Revision after main
T Temperature range (°C) • V = –40 to 105
• C = –40 to 85
PP Package identifier • FG = 16 QFN (3 mm x 3 mm)
• AF = 20 WLCSP (2 mm x 1.61 mm x 0.56
mm)
• BF = 20 WLCSP (2 mm x 1.61 mm x 0.32
mm)
• FK = 24 QFN (4 mm x 4 mm)
CC Maximum CPU frequency (MHz) • 4 = 48 MHz
N Packaging type • R = Tape and reel
• (Blank) = Trays
7.4 Example
This is an example part number:
Part identification
52 Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017
NXP Semiconductors
MKL03Z32VFK4
Terminology and guidelines
8.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation
and possibly decreasing the useful life of the chip.
8.1.1 Example
This is an example of an operating requirement:
Symbol Description Min. Max. Unit
VDD 1.0 V core supply
voltage
0.9 1.1 V
8.2 Definition: Operating behavior
Unless otherwise specified, an operating behavior is a specified value or range of
values for a technical characteristic that are guaranteed during operation if you meet
the operating requirements and any other specified conditions.
8.2.1 Example
This is an example of an operating behavior:
Symbol Description Min. Max. Unit
IWP Digital I/O weak pullup/
pulldown current
10 130 µA
8
Terminology and guidelines
Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 53
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8.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
8.3.1 Example
This is an example of an attribute:
Symbol Description Min. Max. Unit
CIN_D Input capacitance:
digital pins
— 7 pF
8.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
•Operating ratings apply during operation of the chip.
•Handling ratings apply when the chip is not powered.
8.4.1 Example
This is an example of an operating rating:
Symbol Description Min. Max. Unit
VDD 1.0 V core supply
voltage
–0.3 1.2 V
Terminology and guidelines
54 Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017
NXP Semiconductors
8.5 Result of exceeding a rating
40
30
20
10
0
Measured characteristic
Operating rating
Failures in time (ppm)
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
8.6 Relationship between ratings and operating requirements
–∞
- No permanent failure
- Correct operation
Normal operating range
Fatal range
Expected permanent failure
Fatal range
Expected permanent failure
∞
Operating rating (max.)
Operating requirement (max.)
Operating requirement (min.)
Operating rating (min.)
Operating (power on)
Degraded operating range Degraded operating range
–∞
No permanent failure
Handling range
Fatal range
Expected permanent failure
Fatal range
Expected permanent failure
∞
Handling rating (max.)
Handling rating (min.)
Handling (power off)
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
8.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
Terminology and guidelines
Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 55
NXP Semiconductors
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
8.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
8.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol Description Min. Typ. Max. Unit
IWP Digital I/O weak
pullup/pulldown
current
10 70 130 µA
8.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
Terminology and guidelines
56 Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017
NXP Semiconductors
0.90 0.95 1.00 1.05 1.10
0
500
1000
1500
2000
2500
3000
3500
4000
4500
5000
150 °C
105 °C
25 °C
–40 °C
VDD (V)
I(μA)
DD_STOP
TJ
8.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Table 44. Typical value conditions
Symbol Description Value Unit
TAAmbient temperature 25 °C
VDD 3.3 V supply voltage 3.3 V
9 Revision history
The following table provides a revision history for this document.
Table 45. Revision history
Rev. No. Date Substantial Changes
3.1 07/2014 Initial public release.
4 08/2014 Changed pinout signal names ADC0_SE5, ADC0_SE6, and
ADC0_SE12 to ADC0_SE8, ADC0_SE9 and ADC0_SE15 respectively.
Table continues on the next page...
Revision history
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NXP Semiconductors
Table 45. Revision history (continued)
Rev. No. Date Substantial Changes
5 07/2017 • Added new part of MKL03Z32CBF4R and its package
information.
• Updated the Resource and its footnote to the Chip Errata in the
front page
• Updated the descriptions to the VLPW to be very low power wait
mode in the Power consumption operating behaviors
• Added a note to the TA in the Thermal operating requirements
• Updated the foot note to the Typ. of the Table 31 to be VREFO =
1.2 V
• Added I2C 1 Mbit/s timing specifications in Inter-Integrated Circuit
Interface (I2C) timing
• Updated Determining valid orderable parts
• Updated the 20-pin WLCSP package (AF) size in Fields
5.1 08/2017 Updated the Max. of MSL for WLCSP packages to 1 in the Moisture
handling ratings
Revision history
58 Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017
NXP Semiconductors
How to Reach Us:
Home Page:
nxp.com
Web Support:
nxp.com/support
Information in this document is provided solely to enable system and software
implementers to use NXP products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits based
on the information in this document. NXP reserves the right to make changes
without further notice to any products herein.
NXP makes no warranty, representation, or guarantee regarding the suitability of
its products for any particular purpose, nor does NXP assume any liability arising
out of the application or use of any product or circuit, and specifically disclaims
any and all liability, including without limitation consequential or incidental
damages. “Typical” parameters that may be provided in NXP data sheets and/or
specifications can and do vary in different applications, and actual performance
may vary over time. All operating parameters, including “typicals,” must be
validated for each customer application by customerʼs technical experts. NXP
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Document Number KL03P24M48SF0
Revision 5.1 08/2017