SiR610DP
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N-Channel 200 V (D-S) MOSFET
FEATURES
• ThunderFET® technology optimizes balance
of RDS(on), Qg, Qsw and Qoss
• 100 % Rg and UIS tested
• Material categorization:
for definitions of compliance please see
www.vishay.com/doc?99912
APPLICATIONS
•Fixed telecom
•DC/DC converter
• Primary and secondary side switch
• Synchronous rectification
•LED lighting
• Power supplies
• Class D amplifier
Notes
a. Package limited.
b. Surface mounted on 1" x 1" FR4 board.
c. t = 10 s.
d. See solder profile (www.vishay.com/doc?73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed
and is not required to ensure adequate bottom side solder interconnection.
e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum under steady state conditions is 54 °C/W.
g. TC = 25 °C.
PRODUCT SUMMARY
VDS (V) 200
RDS(on) max. () at VGS = 10 V 0.0319
RDS(on) max. () at VGS = 7.5 V 0.0334
Qg typ. (nC) 20
ID (A) 35.4
Configuration Single
PowerPAK® SO-8 Single
Top View
1
6.15 mm
5.15 mm
Bottom View
4
G
3
S
2
S
1
S
D
8
D
6
D
7
D
5
N-Channel MOSFET
G
D
S
ORDERING INFORMATION
Package PowerPAK SO-8
Lead (Pb)-free and halogen-free SiR610DP-T1-RE3
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
PARAMETER SYMBOL LIMIT UNIT
Drain-source voltage VDS 200 V
Gate-source voltage VGS ± 20
Continuous drain current (TJ = 150 °C)
TC = 25 °C
ID
35.4
A
TC = 70 °C 28.3
TA = 25 °C 8.6 b, c
TA = 70 °C 6.9 b, c
Pulsed drain current (t = 100 μs) IDM 80
Continuous source-drain diode current TC = 25 °C IS
35.4
TA = 25 °C 5.6 b, c
Single pulse avalanche current L = 0.1 mH IAS 30
Single pulse avalanche energy EAS 45 mJ
Maximum power dissipation
TC = 25 °C
PD
104
W
TC = 70 °C 66.6
TA = 25 °C 6.25 b, c
TA = 70 °C 4 b, c
Operating junction and storage temperature range TJ, Tstg -55 to +150 °C
Soldering recommendations (peak temperature) c260
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL TYPICAL MAXIMUM UNIT
Maximum junction-to-ambient bt 10 s RthJA 15 20 °C/W
Maximum junction-to-case (drain) Steady state RthJC 0.9 1.2
SiR610DP
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Notes
a. Pulse test; pulse width 300 μs, duty cycle 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-source breakdown voltage VDS VGS = 0 V, ID = 250 μA 200 - - V
VDS temperature coefficient VDS/TJID = 10 mA - 173 - mV/°C
VGS(th) temperature coefficient VGS(th)/TJID = 250 μA - -7.1 -
Gate-source threshold voltage VGS(th) VDS = VGS, ID = 250 μA 2 - 4 V
Gate-source leakage IGSS VDS = 0 V, VGS = ± 20 V - - 100 nA
Zero gate voltage drain current IDSS
VDS = 200 V, VGS = 0 V - - 1 μA
VDS = 200 V, VGS = 0 V, TJ = 70 °C - - 15
On-state drain current aID(on) VDS 10 V, VGS =10 V 30 - - A
Drain-source on-state resistance aRDS(on)
VGS =10 V, ID = 10 A - 0.0239 0.0319
VGS = 7.5 V, ID = 10 A - 0.0249 0.0334
Forward transconductance agfs VDS = 15 V, ID = 10 A - 27 - S
Dynamic b
Input capacitance Ciss
VDS = 100 V, VGS = 0 V, f = 1 MHz
- 1380 -
pFOutput capacitance Coss - 142 -
Reverse transfer capacitance Crss -11-
Total gate charge Qg
VDS = 100 V, VGS = 10 V, ID = 10 A - 25 38
nCVDS = 100 V, VGS = 7.5 V, ID = 10 A
-2030
Gate-source charge Qgs -6.4-
Gate-drain charge Qgd -6.8-
Output charge Qoss VDS = 100 V, VGS = 0 V - 52 -
Gate resistance Rgf = 1 MHz 0.6 2.1 4
Turn-on delay time td(on)
VDD = 100 V, RL = 10 , ID 10 A,
VGEN = 10 V, Rg = 1
-918
ns
Rise time tr-2040
Turn-off delay time td(off) -2040
Fall time tf-2448
Turn-on delay time td(on)
VDD = 100 V, RL = 10 , ID 10 A,
VGEN = 7.5 V, Rg = 1
-1122
Rise time tr-2754
Turn-off delay time td(off) -1836
Fall time tf-2448
Drain-Source Body Diode Characteristics
Continuous source-drain diode current ISTC = 25 °C - - 35.4 A
Pulse diode forward current ISM --80
Body diode voltage VSD IS = 5 A, VGS = 0 V - 0.77 1.1 V
Body diode reverse recovery time trr
IF = 10 A, dI/dt = 100 A/μs, TJ = 25 °C
- 100 200 ns
Body diode reverse recovery charge Qrr - 400 800 nC
Reverse recovery fall time ta-80-
ns
Reverse recovery rise time tb-20-
SiR610DP
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Output Characteristics
On-Resistance vs. Drain Current and Gate Voltage
Gate Charge
Transfer Characteristics
Capacitance
On-Resistance vs. Junction Temperature
10
100
1000
10000
0
30
60
90
120
150
03691215
Axis Title
1st line
2nd line
2nd line
ID- Drain Current (A)
VDS - Drain-to-Source Voltage (V)
2nd line
V
GS
= 10 V thru 7 V
V
GS
= 6 V
V
GS
= 4 V
V
GS
= 5 V
10
100
1000
10000
0.020
0.023
0.026
0.029
0.032
0.035
0 1632486480
Axis Title
1st line
2nd line
2nd line
RDS(on) - On-Resistance (Ω)
ID- Drain Current (A)
2nd line
VGS = 7.5 V
VGS = 10 V
10
100
1000
10000
0
2
4
6
8
10
0 5 10 15 20 25
Axis Title
1st line
2nd line
2nd line
VGS - Gate-to-Source Voltage (V)
Qg- Total Gate Charge (nC)
2nd line
VDS = 50 V, 100 V, 150 V
ID= 10 A
10
100
1000
10000
0
16
32
48
64
80
0246810
Axis Title
1st line
2nd line
2nd line
ID- Drain Current (A)
VGS - Gate-to-Source Voltage (V)
2nd line
TC= 25 °C
TC=-55 °C
TC= 125 °C
10
100
1000
10000
0
600
1200
1800
2400
3000
0 20406080100
Axis Title
1st line
2nd line
2nd line
C - Capacitance (pF)
VDS - Drain-to-Source Voltage (V)
2nd line
Crss
Coss
Ciss
10
100
1000
10000
0.5
1.0
1.5
2.0
2.5
3.0
-50 -25 0 25 50 75 100 125 150
Axis Title
1st line
2nd line
2nd line
RDS(on) - On-Resistance (Normalized)
TJ- Junction Temperature (°C)
2nd line
ID= 10 A
VGS = 10 V
VGS = 7.5 V
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
Threshold Voltage
Single Pulse Power, Junction-to-Ambient
Safe Operating Area, Junction-to-Ambient
10
100
1000
10000
0.001
0.01
0.1
1
10
100
0 0.2 0.4 0.6 0.8 1.0 1.2
Axis Title
1st line
2nd line
2nd line
IS- Source Current (A)
VSD - Source-to-Drain Voltage (V)
2nd line
TJ= 150 °C
TJ= 25 °C
10
100
1000
10000
0
0.03
0.06
0.09
0.12
0.15
345678910
Axis Title
1st line
2nd line
2nd line
RDS(on) - On-Resistance (Ω)
VGS - Gate-to-Source Voltage (V)
2nd line
TJ= 25 °C
TJ= 125 °C
ID= 10 A
10
100
1000
10000
-1.5
-1.1
-0.7
-0.3
0.1
0.5
-50-25 0 255075100125150
Axis Title
1st line
2nd line
2nd line
VGS(th) - Variance (V)
TJ- Temperature (°C)
2nd line
ID= 5 mA
ID= 250 µA
10
100
1000
10000
0
60
120
180
240
300
0.001 0.01 0.1 1 10
Axis Title
1st line
2nd line
2nd line
Power (W)
Time (s)
2nd line
10
100
1000
10000
0.01
0.1
1
10
100
0.01 0.1 1 10 100 1000
Axis Title
1st line
2nd line
2nd line
ID- Drain Current (A)
VDS - Drain-to-Source Voltage (V)
(1) VGS > minimum VGS at which RDS(on) is specified
IDM limited
Limited by RDS(on) (1)
TC= 25 °C
Single pulse BVDSS limited
100 ms
10 ms
1 ms
100 µs
10 s
DC
1s
IDlimited
SiR610DP
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S17-0132-Rev. A, 19-Jan-17 5Document Number: 75855
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Current Derating a
Power, Junction-to-Case Power, Junction-to-Ambient
Note
a. The power dissipation PD is based on TJ max. = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the
package limit.
10
100
1000
10000
0
8
16
24
32
40
0255075100125150
Axis Title
1st line
2nd line
2nd line
ID- Drain Current (A)
TC- Case Temperature (°C)
2nd line
10
100
1000
10000
0
25
50
75
100
125
0 25 50 75 100 125 150
Axis Title
1st line
2nd line
2nd line
Power (W)
TC- Case Temperature (°C)
2nd line
10
100
1000
10000
0
0.6
1.2
1.8
2.4
3.0
0255075100125150
Axis Title
1st line
2nd line
2nd line
Power (W)
TA- Ambient Temperature (°C)
2nd line
SiR610DP
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S17-0132-Rev. A, 19-Jan-17 6Document Number: 75855
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Normalized Thermal Transient Impedance, Junction-to-Ambient
Normalized Thermal Transient Impedance, Junction-to-Case
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?75855.
10
100
1000
10000
0.01
0.1
1
0.0001 0.001 0.01 0.1 1 10 100 1000
Axis Title
1st line
2nd line
Normalized Effective Transient
Thermal Impedance
Square Wave Pulse Duration (s)
2nd line
0.1
0.05
0.02 Single pulse
Duty Cycle = 0.5
0.2
P
DM
t
1
t
2
1. Duty cycle, D =
2. Per unit base = R
thJA
= 54 °C/W
3. T
JM
-T
A
= P
DM
Z
thJA (t)
4. Surface mounted
t
1
t
2
Notes:
10
100
1000
10000
0.01
0.1
1
0.0001 0.001 0.01 0.1 1 10
Axis Title
1st line
2nd line
Normalized Effective Transient
Thermal Impedance
Square Wave Pulse Duration (s)
2nd line
0.1
0.05
0.02
Single pulse
Duty Cycle = 0.5
0.2
Package Information
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Revison: 13-Feb-17 1Document Number: 71655
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PowerPAK® SO-8, (Single/Dual)
DIM. MILLIMETERS INCHES
MIN. NOM. MAX. MIN. NOM. MAX.
A 0.97 1.04 1.12 0.038 0.041 0.044
A1 - 0.05 0 - 0.002
b 0.33 0.41 0.51 0.013 0.016 0.020
c 0.23 0.28 0.33 0.009 0.011 0.013
D 5.05 5.15 5.26 0.199 0.203 0.207
D1 4.80 4.90 5.00 0.189 0.193 0.197
D2 3.56 3.76 3.91 0.140 0.148 0.154
D3 1.32 1.50 1.68 0.052 0.059 0.066
D4 0.57 typ. 0.0225 typ.
D5 3.98 typ. 0.157 typ.
E 6.05 6.15 6.25 0.238 0.242 0.246
E1 5.79 5.89 5.99 0.228 0.232 0.236
E2 3.48 3.66 3.84 0.137 0.144 0.151
E3 3.68 3.78 3.91 0.145 0.149 0.154
E4 0.75 typ. 0.030 typ.
e 1.27 BSC 0.050 BSC
K 1.27 typ. 0.050 typ.
K1 0.56 - - 0.022 - -
H 0.51 0.61 0.71 0.020 0.024 0.028
L 0.51 0.61 0.71 0.020 0.024 0.028
L1 0.06 0.13 0.20 0.002 0.005 0.008
0° - 12° 0° - 12°
W 0.15 0.25 0.36 0.006 0.010 0.014
M 0.125 typ. 0.005 typ.
ECN: S17-0173-Rev. L, 13-Feb-17
DWG: 5881
3. Dimensions exclusive of mold flash and cutting burrs.
1.
Notes
2
Inch will govern.
Dimensions exclusive of mold gate burrs.
Backside View of Single Pad
Backside View of Dual Pad
Detail Z
D
D1
D2
c
θ
A
θ
E1
θ
D1
E2
D2
e
b
1
2
3
4
H
4
3
2
1
θ
1
2
3
4
b
L
D2
D3 (2x)
Z
A1
K1
K
D
E
W
L1
D5
E3
D4
E4
E4
KL
HE2
D4
D5
M
E3
2
2
VISHAY SILICONIX
Power MOSFETs Application Note AN821
PowerPAK® SO-8 Mounting and Thermal Considerations
APPLICATION NOTE
Revision: 16-Mai-13 1Document Number: 71622
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www.vishay.com
by Wharton McDaniel
MOSFETs for switching applications are now available with
die on resistances around 1 m and with the capability to
handle 85 A. While these die capabilities represent a major
advance over what was available just a few years ago, it is
important for power MOSFET packaging technology to keep
pace. It should be obvious that degradation of a high
performance die by the package is undesirable. PowerPAK
is a new package technology that addresses these issues.
In this application note, PowerPAK’s construction is
described. Following this mounting information is presented
including land patterns and soldering profiles for maximum
reliability. Finally, thermal and electrical performance is
discussed.
THE PowerPAK PACKAGE
The PowerPAK package was developed around the SO-8
package (figure 1). The PowerPAK SO-8 utilizes the same
footprint and the same pin-outs as the standard SO-8. This
allows PowerPAK to be substituted directly for a standard
SO-8 package. Being a leadless package, PowerPAK SO-8
utilizes the entire SO-8 footprint, freeing space normally
occupied by the leads, and thus allowing it to hold a larger
die than a standard SO-8. In fact, this larger die is slightly
larger than a full sized DPAK die. The bottom of the die
attach pad is exposed for the purpose of providing a direct,
low resistance thermal path to the substrate the device is
mounted on. Finally, the package height is lower than the
standard SO-8, making it an excellent choice for
applications with space constraints.
Fig. 1 PowerPAK 1212 Devices
PowerPAK SO-8 SINGLE MOUNTING
The PowerPAK single is simple to use. The pin arrangement
(drain, source, gate pins) and the pin dimensions are the
same as standard SO-8 devices (see figure 2). Therefore, the
PowerPAK connection pads match directly to those of the
SO-8. The only difference is the extended drain connection
area. To take immediate advantage of the PowerPAK SO-8
single devices, they can be mounted to existing SO-8 land
patterns.
Fig. 2
The minimum land pattern recommended to take full
advantage of the PowerPAK thermal performance see
Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs. Click on the PowerPAK SO-8 single in the index
of this document.
In this figure, the drain land pattern is given to make full
contact to the drain pad on the PowerPAK package.
This land pattern can be extended to the left, right, and top
of the drawn pattern. This extension will serve to increase
the heat dissipation by decreasing the thermal resistance
from the foot of the PowerPAK to the PC board and
therefore to the ambient. Note that increasing the drain land
area beyond a certain point will yield little decrease
in foot-to-board and foot-to-ambient thermal resistance.
Under specific conditions of board configuration, copper
weight and layer stack, experiments have found that
more than about 0.25 in2 to 0.5 in2 of additional copper
(in addition to the drain land) will yield little improvement in
thermal performance.
Standard SO-8 PowerPAK SO-8
PowerPAK
®
SO-8 Mounting and Thermal Considerations
APPLICATION NOTE
Application Note AN821
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Revision: 16-Mai-13 2Document Number: 71622
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PowerPAK SO-8 DUAL
The pin arrangement (drain, source, gate pins) and the pin
dimensions of the PowerPAK SO-8 dual are the same as
standard SO-8 dual devices. Therefore, the PowerPAK
device connection pads match directly to those of the SO-8.
As in the single-channel package, the only exception is the
extended drain connection area. Manufacturers can likewise
take immediate advantage of the PowerPAK SO-8 dual
devices by mounting them to existing SO-8 dual land
patterns.
To take the advantage of the dual PowerPAK SO-8’s
thermal performance, the minimum recommended land
pattern can be found in Application Note 826,
Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs. Click on the
PowerPAK 1212-8 dual in the index of this document.
The gap between the two drain pads is 24 mils. This
matches the spacing of the two drain pads on the
PowerPAK SO-8 dual package.
REFLOW SOLDERING
Vishay Siliconix surface-mount packages meet solder reflow
reliability requirements. Devices are subjected to solder
reflow as a test preconditioning and are then
reliability-tested using temperature cycle, bias humidity,
HAST, or pressure pot. The solder reflow temperature profile
used, and the temperatures and time duration, are shown in
figures 3 and 4.
For the lead (Pb)-free solder profile, see
www.vishay.com/doc?73257.
Fig. 3 Solder Reflow Temperature Profile
Fig. 4 Solder Reflow Temperatures and Time Durations
Ramp-Up Rate + 3 °C /s max.
Temperature at 150 - 200 °C 120 s max.
Temperature Above 217 °C 60 - 150 s
Maximum Temperature 255 + 5/- 0 °C
Time at Maximum
Temperature 30 s
Ramp-Down Rate + 6 °C/s max.
260 °C
3 °C(max) 6 ° C/s (max.)
30 s
217 °C
150 s (max.)
Reflow Zone
60 s (min.)
Pre-Heating Zone
150 - 200 °C
Maximum peak temperature at 240 °C is allowed.
PowerPAK
®
SO-8 Mounting and Thermal Considerations
APPLICATION NOTE
Application Note AN821
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Revision: 16-Mai-13 3Document Number: 71622
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THERMAL PERFORMANCE
Introduction
A basic measure of a device’s thermal performance
is the junction-to-case thermal resistance, RthJC, or the
junction-to-foot thermal resistance, RthJF This parameter is
measured for the device mounted to an infinite heat sink and
is therefore a characterization of the device only, in other
words, independent of the properties of the object to which
the device is mounted. Table 1 shows a comparison of
the DPAK, PowerPAK SO-8, and standard SO-8. The
PowerPAK has thermal performance equivalent to the
DPAK, while having an order of magnitude better thermal
performance over the SO-8.
Thermal Performance on Standard SO-8 Pad Pattern
Because of the common footprint, a PowerPAK SO-8
can be mounted on an existing standard SO-8 pad pattern.
The question then arises as to the thermal performance
of the PowerPAK device under these conditions. A
characterization was made comparing a standard SO-8 and
a PowerPAK device on a board with a trough cut out
underneath the PowerPAK drain pad. This configuration
restricted the heat flow to the SO-8 land pads. The results
are shown in figure 5.
Fig. 5 PowerPAK SO-8 and Standard SO-0 Land Pad Thermal
Path
Because of the presence of the trough, this result suggests
a minimum performance improvement of 10 °C/W by using
a PowerPAK SO-8 in a standard SO-8 PC board mount.
The only concern when mounting a PowerPAK on a
standard SO-8 pad pattern is that there should be no traces
running between the body of the MOSFET. Where the
standard SO-8 body is spaced away from the pc board,
allowing traces to run underneath, the PowerPAK sits
directly on the pc board.
Thermal Performance - Spreading Copper
Designers may add additional copper, spreading copper, to
the drain pad to aid in conducting heat from a device. It is
helpful to have some information about the thermal
performance for a given area of spreading copper.
Figure 6 shows the thermal resistance of a PowerPAK SO-8
device mounted on a 2-in. 2-in., four-layer FR-4 PC board.
The two internal layers and the backside layer are solid
copper. The internal layers were chosen as solid copper to
model the large power and ground planes common in many
applications. The top layer was cut back to a smaller area
and at each step junction-to-ambient thermal resistance
measurements were taken. The results indicate that an area
above 0.3 to 0.4 square inches of spreading copper gives no
additional thermal performance improvement. A
subsequent experiment was run where the copper on the
back-side was reduced, first to 50 % in stripes to mimic
circuit traces, and then totally removed. No significant effect
was observed.
Fig. 6 Spreading Copper Junction-to-Ambient Performance
TABLE 1 - DPAK AND POWERPAK SO-8
EQUIVALENT STEADY STATE
PERFORMANCE
DPAK PowerPAK
SO-8
Standard
SO-8
Thermal
Resistance RthJC 1.2 °C/W 1 °C/W 16 °C/W
Si4874DY vs. Si7446DP PPAK on a 4-Layer Board
SO-8 Pattern, Trough Under Drain
Pulse Duration (sec)
)
s
ttaw/
C
( e
cn
adep
m
I
0.0001
0
1
50
60
10
100000.01
40
20
Si4874DY
Si7446DP
100
30
R
th vs. Spreading Copper
(0 %, 50 %, 100 % Back Copper)
Spreading Copper (sq in)
)sttaw/C(
ecn
adep
m
I
0.00
56
51
46
41
36
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
0 %
50 %
100 %
PowerPAK
®
SO-8 Mounting and Thermal Considerations
APPLICATION NOTE
Application Note AN821
www.vishay.com Vishay Siliconix
Revision: 16-Mai-13 4Document Number: 71622
For technical questions, contact: powermosfettechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SYSTEM AND ELECTRICAL IMPACT OF
PowerPAK SO-8
In any design, one must take into account the change in
MOSFET RDS(on) with temperature (figure 7).
Fig. 7 MOSFET RDS(on) vs. Temperature
A MOSFET generates internal heat due to the current
passing through the channel. This self-heating raises the
junction temperature of the device above that of the PC
board to which it is mounted, causing increased power
dissipation in the device. A major source of this problem lies
in the large values of the junction-to-foot thermal resistance
of the SO-8 package.
PowerPAK SO-8 minimizes the junction-to-board thermal
resistance to where the MOSFET die temperature is very
close to the temperature of the PC board. Consider two
devices mounted on a PC board heated to 105 °C by other
components on the board (figure 8).
Fig. 8 Temperature of Devices on a PC Board
Suppose each device is dissipating 2.7 W. Using the
junction-to-foot thermal resistance characteristics of the
PowerPAK SO-8 and the standard SO-8, the die
temperature is determined to be 107 °C for the PowerPAK
(and for DPAK) and 148 °C for the standard SO-8. This is a
2 °C rise above the board temperature for the PowerPAK
and a 43 °C rise for the standard SO-8. Referring to figure 7,
a 2 °C difference has minimal effect on RDS(on) whereas a
43 °C difference has a significant effect on RDS(on).
Minimizing the thermal rise above the board temperature by
using PowerPAK has not only eased the thermal design but
it has allowed the device to run cooler, keep rDS(on) low, and
permits the device to handle more current than the same
MOSFET die in the standard SO-8 package.
CONCLUSIONS
PowerPAK SO-8 has been shown to have the same thermal
performance as the DPAK package while having the same
footprint as the standard SO-8 package. The PowerPAK
SO-8 can hold larger die approximately equal in size to the
maximum that the DPAK can accommodate implying no
sacrifice in performance because of package limitations.
Recommended PowerPAK SO-8 land patterns are provided
to aid in PC board layout for designs using this new
package.
Thermal considerations have indicated that significant
advantages can be gained by using PowerPAK SO-8
devices in designs where the PC board was laid out for
the standard SO-8. Applications experimental data gave
thermal performance data showing minimum and
typical thermal performance in a SO-8 environment, plus
information on the optimum thermal performance
obtainable including spreading copper. This further
emphasized the DPAK equivalency.
PowerPAK SO-8 therefore has the desired small size
characteristics of the SO-8 combined with the attractive
thermal characteristics of the DPAK package.
0.8 °C/W
107 °C
PowerPAK SO-8
16 C/W
148 °C
Standard SO-8
PC Board at 105 °C
Application Note 826
Vishay Siliconix
Document Number: 72599 www.vishay.com
Revision: 21-Jan-08 15
APPLICATION NOTE
RECOMMENDED MINIMUM PADS FOR PowerPAK® SO-8 Single
0.174
(4.42)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.260
(6.61)
0.024
(0.61)
0.154
(3.91)
0.150
(3.81)
0.050
(1.27)
0.050
(1.27)
0.032
(0.82)
0.040
(1.02)
0.026
(0.66)
Return to Index
Return to Index
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www.vishay.com Vishay
Revision: 01-Jan-2019 1Document Number: 91000
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