FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-
3.3V LVPECL/LVCMOS SYNTHESIZER ICS843001I-23
IDT™ / ICS™ 3.3V L VPECL/ LVCMOS FREQUENCY SYNTHESIZER 1 ICS843001BGI-23 REV. B FEBRUARY 19, 2009
PRELIMINARY
GENERAL DESCRIPTION
The ICS843001I-23 is a highly versatile, low phase
noise LVPECL/LVCMOS Synthesizer which can
generate low jitter reference clocks for a variety of
communication applications and is a member of
the HiPerClocksTM family of high performance clock
solutions from IDT. The dual crystal interface
allows the synthesizer to support up to three communication
standards in a given application (i.e. SONET with a 19.44MHz
crystal, 1Gb/10Gb Ethernet and Fibre Channel using a 25MHz
crystal). The rms phase jitter performance is typically less than
1ps, thus making the device acceptable for use in demanding
applications such as OC48 SONET, GbE/10Gb Ethernet
and SAN applications. The ICS843001I-23 is packaged in
a small 24-pin TSSOP package.
FEATURES
• One 3.3V LVPECL output pair and
one LVCMOS/LVTTL REF_OUT output
• Selectable crystal oscillator interfaces
or LVCMOS/LVTTL single-ended input
• Crystal and CLK range: 17.5MHz - 29.54MHz
• Able to generate GbE/10GbE/12GbE, Fibre Channel
(1Gb/4Gb/10Gb), PCI-E and SATA from a 25MHz crystal
• VCO range: 1.12GHz - 1.3GHz
• Supports the following applications:
SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV
• RMS phase jitter @ 622.08MHz (12kHz - 20MHz):
0.9ps (typical) @ 3.3V
• Supply modes:
VCC/VCCO
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
HiPerClockS™
ICS
PIN ASSIGNMENT
11
10
01
00
00
01
10
11
Phase
Detector VCO
000 ÷44
001 ÷45
010 ÷48
011 ÷50
100 ÷51
111 ÷64
(default)
N
000 ÷2
001 ÷4
010 ÷5
011 ÷6
100 ÷8
(default)
101 ÷10
110 ÷12
111 ÷16
M
3
3
OSC
OSC
Q
nQ
REF_OUT
N2:N0
M2:M0
SEL0
SEL1
XTAL_IN0
XTAL_OUT0
XTAL_IN1
XTAL_OUT1
CLK
MR
OE_REF
Pulldown
Pulldown
Pullup
Pulldown
Pulldown
Pulldown
ICS843001I-23
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
VCCO_LVCMOS
N0
N1
N2
VCCO_LVPECL
Q
nQ
VEE
VCCA
VCC
XTAL_OUT1
XTAL_IN1
1
2
3
4
5
6
7
8
9
10
11
12
REF_OUT
VEE
OE_REF
M2
M1
M0
MR
SEL1
SEL0
CLK
XTAL_IN0
XTAL_OUT0
24
23
22
21
20
19
18
17
16
15
14
13
BLOCK DIAGRAM
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ 3.3V L VPECL/ LVCMOS FREQUENCY SYNTHESIZER 2 ICS843001BGI-23 REV. B FEBRUARY 19, 2009
ICS843001I-23
FEMTOCLOCK™ CR YSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
rebmuNemaNepyTnoitpircseD
1V
SOMC_OCC
rewoP .tuptuoTUO_FERLTTVL/SOMCVLrofnipylppustuptuO
3,21N,0NtupnInwodlluP .C3elbaTeeS.sniptcelesredividtuptu
O
.slevelecafretniLTTVL/SOMCVL
42NtupnIpulluP
5V
LCEPVL_OCC
rewoP.tuptuoLCEPVLrofnipylppustuptuO
7,6Qn,QtupuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
32,8V
EE
rewoP.nipylppusevitageN
9V
ACC
rewoP.nipylppusgolanA
01V
CC
rewoP.nipylppuseroC
11
21
,1TUO_LATX
1NI_LATX tupnI ,tuptuoehtsi1TUO_LATX.ecafretnilatsyrctnanoserlellaraP
.t
upniehtsi1NI_LATX
31
41
,0TUO_LATX
0NI_LATX tupnI ,tuptuoehtsi0TUO_LATX.ecafretnilatsyrctnanoserlellaraP
.tu
pniehtsi0NI_LATX
51KLCtupnInwodlluP.tupnikcolcLTTVL/SOMCVL
71,611LES,0LEStupnInwodlluP.slevelecafretniLTTVL/SOM
CVL.sniptcelesXUMtupnI
81RMtupnInwodlluP
erasredividlanretnieht,HGIHcigolnehW.teseRretsaMHGIHevitcA
otQntup
tuodetrevniehtdnawologotQtuptuoeurtehtgnisuacteser
erastuptuoehtdnasredividlanretnieht,WOLcigolnehW.hg
ihog
.slevelecafretniLTTVL/SOMCVL.delbane
12,02,912M,1M,0MtupnIpulluP .B3elbaTeeS.sniptcelesredividkcabdeeF
.slevelecafretniLTTVL/SOMCVL
22FER_EOtupnInwodlluP .E3elbaTeeS.woLtluafeD.elbanetuptuokcolcecnerefeR
.slevelecafretniLTTVL/SOMCVL
42TUO_FERtuptuO .slevelecafretniLTTVL/SOMCVL.tuptuokcolcecnerefeR
:ETON
nwodlluPdnapulluP
.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotrefer
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
ecnaticapaCtupnI 4Fp
C
DP
noitapissiDrewoP
ecnaticapaC Fp
R
NWODLLUP
rotsiseRnwodlluPtupnI 15kΩ
R
PULLUP
rotsiseRpulluPtupnI 15kΩ
R
tuo
ecnadepmItuptuOTUO_FER02Ω
IDT™ / ICS™ 3.3V L VPECL/ LVCMOS FREQUENCY SYNTHESIZER 3 ICS843001BGI-23 REV. B FEBRUARY 19, 2009
ICS843001I-23
FEMTOCLOCK™ CR YSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER PRELIMINARY
TABLE 3A. COMMON CONFIGURATIONS TABLE
tupnI kcabdeeF
rediviD )zHM(OCVeulaVrediviDN ycneuqerFtuptuO
)zHM( noitacilppA
)zHM(tupnILATX
724488116152.47VTDH
57.428488116152.47VTDH
44.914661.44218 25.551TENOS
44.914661.44212 80.226TENOS
44.914661.44214 40.113TENOS
5205052101521EgiG
520505218 52.651EgiG01
520505215 052EgiG
520505214 5.213IIMGX
520505212 526EgiG01
525452116 5.781EgiG21
5284002121001sserpxEICP
528400218 051ATAS
528400216157ATAS
521557212152.601lennahCerbiF
521557218 573.951lennahCerbiFgiG01
521557216 5.212lennahCerbiFgiG4
TABLE 3B. PROGRAMMABLE M OUTPUT DIVIDER
FUNCTION TABLE
TABLE 3C. PROGRAMMABLE N OUTPUT DIVIDER
FUNCTION TABLE
stupnI tupnIecnerefeRedoMLLP
1LES0LES
00 0LATXevitcA
01 1LATXevitcA
10 KLCevitcA
11 KLCssapyB
TABLE 3D. BYPASS MODE FUNCTION TABLE
stupnI eulaVediviDN
2N1N0N
000 2
00 1 4
010 5
011 6
10 0 8
)tluafed(
10 1 01
110 21
111 61
TABLE 3E. OE_REF OUTPUT FUNCTION TABLE
stupnI rediviDM
eulaV
ycneuqerFtupnI
2M1M0MmuminiMmumixaM
000 445.5245.92
00 1 549.4288.82
010 843.3280.72
011 054.220.62
10 0 150.2294.52
11146
)tluafed(
5.7113.02
stupnItuptuO
FER_EOTUO_FER
0Z-iH
1evitcA
IDT™ / ICS™ 3.3V L VPECL/ LVCMOS FREQUENCY SYNTHESIZER 4 ICS843001BGI-23 REV. B FEBRUARY 19, 2009
ICS843001I-23
FEMTOCLOCK™ CR YSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
CC 4.6V
Inputs, VI-0.5V to VCC + 0.5V
Outputs, IO (LVPECL)
Continuous Current 50mA
Surge Current 100mA
Outputs, VO (LVCMOS) -0.5V to V
CCO_LVCMOS + 0.5V
Package Thermal Impedance, θJA 82.3°C/W (0 mps)
Storage Temperature, T
STG -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO_LVPECL, VCCO_LVCMOS = 3.3V±5%, VEE = 0V, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
CC
egatloVylppuSeroC531.33.3564.3V
V
ACC
egatloVylppuSgolanAV
CC
50.0–3.3V
CC
V
V
LCEPVL_OCC
egatloVylppuStuptuO531.33.3564.3V
V
SOMCVL_OCC
egatloVylppuStuptuO531.33.3564.3V
I
EE
tnerruCylppuSrewoP 501Am
I
ACC
tnerruCylppuSgolanA 5Am
I
OCC
tnerruCylppuStuptuO 5Am
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
CC
egatloVylppuSeroC 531.33.3564.3V
V
ACC
egatloVylppuSgolanAV
CC
50.0–3.3V
CC
V
V
LCEPVL_OCC
egatloVylppuStuptuO 573.25.2526.2V
V
SOMCVL_OCC
egatloVylppuStuptuO 573.25.2526.2V
I
EE
tnerruCylppuSrewoP 501Am
I
ACC
tnerruCylppuSgolanA 5Am
I
OCC
tnerruCylppuStuptuO 5Am
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, VCCO_LVPECL, VCCO_LVCMOS = 2.5V±5%, VEE = 0V, TA = -40°C TO 85°C
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO_LVPECL, VCCO_LVCMOS = 2.5V±5%, VEE = 0V, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
CC
egatloVylppuSeroC 573.25.2526.2V
V
ACC
egatloVylppuSgolanAV
CC
50.0–5.2V
CC
V
V
LCEPVL_OCC
egatloVylppuStuptuO 573.25.2526.2V
V
SOMCVL_OCC
egatloVylppuStuptuO 573.25.2526.2V
I
EE
tnerruCylppuSrewoP 001Am
I
ACC
tnerruCylppuSgolanA 5Am
I
OCC
tnerruCylppuStuptuO 5Am
IDT™ / ICS™ 3.3V L VPECL/ LVCMOS FREQUENCY SYNTHESIZER 5 ICS843001BGI-23 REV. B FEBRUARY 19, 2009
ICS843001I-23
FEMTOCLOCK™ CR YSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER PRELIMINARY
TABLE 4E. LVPECL DC CHARACTERISTICS, VCC = VCCO_LVPECL = 3.3V±5%, VEE = 0V, TA = -40°C TO 85°C
TABLE 4D. LVCMOS / LVTTL DC CHARACTERISTICS, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnI V
CC
V3.3=2V
CC
3.0+V
V
CC
V5.2=7.1V
CC
3.0+V
V
LI
egatloVwoLtupnI V
CC
V3.3=3.0-8.0V
V
CC
V5.2=3.0-7.0V
I
HI
tupnI
tnerruChgiH
,1LES,0LES,KLC
1N,0N,RM,FER_EO
V
CC
V=
NI
V564.3=
V526.2ro 051Aµ
2M:0M,2N V
CC
V=
NI
V564.3=
V526.2ro 5Aµ
I
LI
tupnI
tnerruCwoL
,1LES,0LES,KLC
1N,0N,RM,FER_EO
V
CC
,V526.2roV564.3=
V
NI
V0= 5-Aµ
2M:0M,2N V
CC
,V526.2roV564.3=
V
NI
V0= 051-Aµ
V
HO
hgiHtuptuO
1ETON;egatloV TUO_FER V
SOMCVL_OCC
V564.3=6.2V
V
SOMCVL_OCC
V526.2=8.1V
V
LO
woLtuptuO
1ETON;egatloV TUO_FER V
SOMCVL_OCC
V564.3=
V526.2ro 5.0V
Δ/V ΔTetaRegdEtupnIKLC%08-%02DBTsn/V
05htiwdetanimrettuptuO:1ETON ΩVot
SOMCVL_OCC
,noitceSnoitamrofnItnemerusaeMretemaraPeeS.2/
.smargaid"margaiDtiucriCtseTdaoLtuptuO"
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HO
1ETON;egatloVhgiHtuptuOV
LCEPVL_OCC
4.1-V
LCEPVL_OCC
9.0-V
V
LO
1ETON;egatloVwoLtuptuOV
LCEPVL_OCC
0.2-V
LCEPVL_OCC
7.1-V
V
GNIWS
gniwSegatloVtuptuOkaeP-ot-kaeP6.00.1V
05htiwdetanimretstuptuO:1ETON ΩVot
LCEPVL_OCC
.V2-
TABLE 5. CRYSTAL CHARACTERISTICS
retemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
noitallicsOfoedoM latnemadnuFzHM
ycneuqerF 5.7145.92zHM
)RSE(ecn
atsiseRseireStnelaviuqE 05 Ω
ecnaticapaCtnuhS 7Fp
leveLevirD 1Wm
.latsyrctnanoserlellarapFp81nagnisudeziretcar
ahC:ETON
TABLE 4F. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5% or 2.5V±5%, VCCO_LVPECL = 2.5V±5%, VEE = 0V, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HO
1ETON;egatloVhgiHtuptuOV
LCEPVL_OCC
4.1-V
LCEPVL_OCC
9.0-V
V
LO
1ETON;egatloVwoLtuptuOV
LCEPVL_OCC
0.2-V
LCEPVL_OCC
5.1-V
V
GNIWS
gniwSegatloVtuptuOkaeP-ot-kaeP4.00.1V
05htiwdetanimretstuptuO:1ETON ΩVot
LCEPVL_OCC
.V2-
IDT™ / ICS™ 3.3V L VPECL/ LVCMOS FREQUENCY SYNTHESIZER 6 ICS843001BGI-23 REV. B FEBRUARY 19, 2009
ICS843001I-23
FEMTOCLOCK™ CR YSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER PRELIMINARY
TABLE 6A. AC CHARACTERISTICS, VCC = VCCO_LVPECL, VCCO_LVCMOS = 3.3V±5%, VEE = 0V, TA = -40°C TO 85°C
TABLE 6B. AC CHARACTERISTICS, VCC = 3.3V±5%, VCCO_LVPECL, VCCO_LVCMOS = 2.5V±5%, VEE = 0V, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
TUO
ycneuqerFtuptuO 65056zHM
t
DP
noitagaporP
1ETON,yaleD
otKLC
TUO_FER 5.2sn
t
)Ø(tij ;)modnaR(,rettiJesahPSMR
3,2ETON )zHM02-zHk21(zHM80.2269.0sp
f
OCV
egnaRkcoLOCVLLP 21.13.1zHG
Lt
LES_
emiTtceleS sm
Lt
M_
emiTkcoLLLP sm
t
R
t/
F
tuptuO
emiTllaF/esiR
Qn/Q%08ot%02003sp
TUO_FER%08ot%02005sp
cdoelcyCytuDtuptuO Qn/Q05%
TUO_FER05%
dehsilbatsesihcihw,eg
narerutarepmetgnitarepotneibmadeificepsehtrevodeetnaraugerasretemaraplacirtcelE:ETON
teemlliwecivedehT
.mpfl005nahtretaergwolfriaesrevsnartdeniatniamhtiwtekcostsetanidetnuomsiecivedehtnehw
.snoitidnoceseht
rednudehcaerneebsahmuirbiliuqelamrehtretfasnoitacificeps
VehtmorfderusaeM:1ETON
CC
Vottupniehtfo2/
SOMCVL_OCC
.tuptuoehtfo2/
.latsyrcztrauqzHM44.91agnisuderusaemrettijesahP:2ETON
.56dradnatSCEDEJhtiwecnadroccanide
nifedsiretemarapsihT:3ETON
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
TUO
ycneuqerFtuptuO 65056zHM
t
DP
noitagaporP
1ETON,yaleD
otKLC
TUO_FER 5.3sn
t
)Ø(tij ;)modnaR(,rettiJesahPSMR
3,2ETON )zHM02-zHk21(zHM80.2261sp
f
OCV
egnaRkcoLOCVLLP 21.13.1zHG
Lt
LES_
emiTtceleS sm
Lt
M_
emiTkcoLLLP sm
t
R
t/
F
tuptuO
emiTllaF/esiR
Qn/Q%08ot%02003sp
TUO_FER%08ot%02005sp
cdoelcyCytuDtuptuO Qn/Q05%
TUO_FER05%
dehsilbatsesihcihw,eg
narerutarepmetgnitarepotneibmadeificepsehtrevodeetnaraugerasretemaraplacirtcelE:ETON
teemlliwecivedehT
.mpfl005nahtretaergwolfriaesrevsnartdeniatniamhtiwtekcostsetanidetnuomsiecivedehtnehw
.snoitidnoceseht
rednudehcaerneebsahmuirbiliuqelamrehtretfasnoitacificeps
VehtmorfderusaeM:1ETON
CC
Vottupniehtfo2/
SOMCVL_OCC
.tuptuoehtfo2/
.latsyrcztrauqzHM44.91agnisuderusaemrettijesahP:2ETON
.56dradnatSCEDEJhtiwecnadroccanide
nifedsiretemarapsihT:3ETON
IDT™ / ICS™ 3.3V L VPECL/ LVCMOS FREQUENCY SYNTHESIZER 7 ICS843001BGI-23 REV. B FEBRUARY 19, 2009
ICS843001I-23
FEMTOCLOCK™ CR YSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER PRELIMINARY
TABLE 6C. AC CHARACTERISTICS, VCC = VCCO_LVPECL, VCCO_LVCMOS = 2.5V±5%, VEE = 0V, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
TUO
ycneuqerFtuptuO 65056zHM
t
DP
noitagaporP
1ETON,yaleD
otKLC
TUO_FER 3sn
t
)Ø(tij ;)modnaR(,rettiJesahPSMR
3,2ETON )zHM02-zHk21(zHM80.2261.1sp
f
OCV
egnaRkcoLOCVLLP 21.13.1zHG
Lt
LES_
emiTtceleS sm
Lt
M_
emiTkcoLLLP sm
t
R
t/
F
tuptuO
emiTllaF/esiR
Qn/Q%08ot%02003sp
TUO_FER%08ot%02005sp
cdoelcyCytuDtuptuO Qn/Q05%
TUO_FER05%
dehsilbatsesihcihw,eg
narerutarepmetgnitarepotneibmadeificepsehtrevodeetnaraugerasretemaraplacirtcelE:ETON
teemlliwecivedehT
.mpfl005nahtretaergwolfriaesrevsnartdeniatniamhtiwtekcostsetanidetnuomsiecivedehtnehw
.snoitidnoceseht
rednudehcaerneebsahmuirbiliuqelamrehtretfasnoitacificeps
VehtmorfderusaeM:1ETON
CC
Vottupniehtfo2/
SOMCVL_OCC
.tuptuoehtfo2/
.latsyrcztrauqzHM44.91agnisuderusaemrettijesahP:2ETON
.56dradnatSCEDEJhtiwecnadroccanide
nifedsiretemarapsihT:3ETON
IDT™ / ICS™ 3.3V L VPECL/ LVCMOS FREQUENCY SYNTHESIZER 8 ICS843001BGI-23 REV. B FEBRUARY 19, 2009
ICS843001I-23
FEMTOCLOCK™ CR YSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
3.3V CORE/2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT
2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT
3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT
SCOPE
Qx
nQx
LVPECL
VEE
2V
-1.3V±0.165V
2.5V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
VCC,
VCCO_LVPECL
3.3V CORE/2.5V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
SCOPE
Qx
LVCMOS
GND
1.65V±5%
-1.65V±5%
VCC,
VCCO_LVCMOS
SCOPE
Qx
nQx
LVPECL
V
EE
2.8V±0.04V
-0.5V±0.125V
SCOPE
Qx
GND
LVCMOS
1.25V±5%
-1.25V±5%
SCOPE
Qx
nQx
LVPECL
VEE
2V
-0.5V±0.125V
SCOPE
Qx
LVCMOS
GND
1.25V±5%
-1.25V±5%
VCCO_LVPECL VCCO_LVCMOS
2V 2.05V±5%
2V
VCCA
1.65V±5%
VCCA
VCC,
VCCO_LVPECL
VCC,
VCCO_LVCMOS
VCCA
VCCA
VCC
2.05V±5%
2.8V±0.04V
VCCA
VCC
2V
VCCA
1.25V±5%
IDT™ / ICS™ 3.3V L VPECL/ LVCMOS FREQUENCY SYNTHESIZER 9 ICS843001BGI-23 REV. B FEBRUARY 19, 2009
ICS843001I-23
FEMTOCLOCK™ CR YSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER PRELIMINARY
t
PW
t
PERIOD
t
PW
t
PERIOD
odc = x 100%
Q
RMS PHASE JITTER
nQ
Phase Noise Mas
k
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise Power
LVPECL OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
20%
80% 80%
20%
t
R
t
F
V
SWING
OUTPUT RISE/FALL TIME
tPERIOD
tPW
tPERIOD
odc = x 100%
V
CCO_LVCMOS
2
tPW
REF_OUT
LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
tPD
VCC
2
V
CCO_LVCMOS
2
REF_OUT
CLK
PROPAGATION DELAY
Q,
REF_OUT
nQ
IDT™ / ICS™ 3.3V L VPECL/ LVCMOS FREQUENCY SYNTHESIZER 10 ICS843001BGI-23 REV. B FEBRUARY 19, 2009
ICS843001I-23
FEMTOCLOCK™ CR YSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER PRELIMINARY
APPLICATION INFORMATION
INPUTS:
CRYSTAL INPUTS
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
CLK INPUT
For applications not requiring the use of a clock input, it can be
left floating. Though not required, but for additional protection, a
1kΩ resistor can be tied from the CLK input to ground.
LVCMOS CONTROL PINS
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVCMOS OUTPUT
The unused LVCMOS output can be left floating. There should
be no trace attached.
LVPECL OUTPUT
The unused LVPECL output pair can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or terminated.
FIGURE 1. POWER SUPPLY FILTERING
10Ω
VCCA
10μF
.01μF
3.3V or 2.5V
.01μF
VCC
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perfor-
mance, power supply isolation is required. The ICS843001I-23
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCA, and VCCO_X
should be individually connected to the power supply
plane through vias, and 0.01µF bypass capacitors should be used
for each pin.
Figure 1
illustrates this for a generic VCC pin and
also shows that VCCA requires that an additional10Ω resistor
along with a 10µF bypass capacitor be connected to the VCCA pin.
IDT™ / ICS™ 3.3V L VPECL/ LVCMOS FREQUENCY SYNTHESIZER 11 ICS843001BGI-23 REV. B FEBRUARY 19, 2009
ICS843001I-23
FEMTOCLOCK™ CR YSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER PRELIMINARY
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram
is shown in
Figure 3.
The XTAL_OUT pin can be left floating.
The input edge rate can be as slow as 10ns. For LVCMOS
signals, it is recommended that the amplitude be reduced from
full swing to half swing in order to prevent signal interference
with the power rail and to reduce noise. This configuration
requires that the output impedance of the driver (Ro) plus the
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
series resistance (Rs) equals the transmission line impedance.
In addition, matched termination at the crystal input will
attenuate the signal in half. This can be done in one of two
ways. First, R1 and R2 in parallel should equal the transmission
line impedance. For most 50Ω applications, R1 and R2 can be
100Ω. This can also be accomplished by removing R1 and
making R2 50Ω.
R2
Zo = 50
VDD
Ro
Zo = Ro + Rs
R1
VDD
XTAL_IN
XTAL_OUT
.1uf
Rs
FIGURE 2. CRYSTAL INPUT INTERFACE
CRYSTAL INPUT INTERFACE
The ICS843001I-23 has been characterized with 18pF
parallel resonant crystals. The capacitor values shown in
Figure 2
below were determined using an 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
ICS84332
XTAL_IN
XTAL_OUT
X1
18pF Paral lel Crys tal
C2
22p
C1
22p
IDT™ / ICS™ 3.3V L VPECL/ LVCMOS FREQUENCY SYNTHESIZER 12 ICS843001BGI-23 REV. B FEBRUARY 19, 2009
ICS843001I-23
FEMTOCLOCK™ CR YSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER PRELIMINARY
V
CC
- 2V
50Ω50Ω
RTT
Z
o
= 50Ω
Z
o
= 50Ω
FOUT FIN
RTT = Z
o
1
((V
OH
+ V
OL
) / (V
CC
– 2)) – 2
3.3V
125Ω125Ω
84Ω84Ω
Z
o
= 50Ω
Z
o
= 50Ω
FOUT FIN
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion.
Figures 4A and 4B
show two different layouts
which are recommended only as guidelines. Other suitable
clock layouts may exist and it would be recommended that the
board designers simulate to guarantee compatibility across all
printed circuit and clock component process variations.
TERMINATION FOR LVPECL OUTPUTS
FIGURE 4B. LVPECL OUTPUT TERMINATIONFIGURE 4A. LVPECL OUTPUT TERMINATION
IDT™ / ICS™ 3.3V L VPECL/ LVCMOS FREQUENCY SYNTHESIZER 13 ICS843001BGI-23 REV. B FEBRUARY 19, 2009
ICS843001I-23
FEMTOCLOCK™ CR YSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER PRELIMINARY
TERMINATION FOR 2.5V LVPECL OUTPUTS
Figure 5A
and
Figure 5B
show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating
50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground
level. The R3 in Figure 5B can be eliminated and the termination
is shown in
Figure 5C.
FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE
FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
R2
62.5
Z o = 50 Ohm
R1
250
+
-
2.5V
2, 5V LVPEC L
Driver R4
62.5
R3
250
Z o = 50 Ohm
2.5V
VCC=2.5V
R1
50
R3
18
Zo = 50 Ohm
Zo = 50 Ohm
+
-
2, 5V LVPEC L
Driver
VCC=2.5V 2.5V
R2
50
2, 5V LVPECL
Driver
VCC=2.5V
R1
50 R2
50
2.5V
Z o = 50 Ohm
Z o = 50 Ohm
+
-
IDT™ / ICS™ 3.3V L VPECL/ LVCMOS FREQUENCY SYNTHESIZER 14 ICS843001BGI-23 REV. B FEBRUARY 19, 2009
ICS843001I-23
FEMTOCLOCK™ CR YSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843001I-23.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843001I-23 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 105mA = 363.8mW
•Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 363.8mW + 30mW = 393.8mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA
must be used. Assuming no air
flow and a multi-layer board, the appropriate value is 82.3°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.394W * 82.3°C/W = 117.4°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (multi-layer).
θθ
θθ
θJA by Velocity (Meters per Second)
TABLE 7. THERMAL RESISTANCE θθ
θθ
θJA FOR 24-PIN TSSOP, FORCED CONVECTION
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 82.3°C/W 78.0°C/W 75.9°C/W
IDT™ / ICS™ 3.3V L VPECL/ LVCMOS FREQUENCY SYNTHESIZER 15 ICS843001BGI-23 REV. B FEBRUARY 19, 2009
ICS843001I-23
FEMTOCLOCK™ CR YSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER PRELIMINARY
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 6
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V
CCO
- 2V.
• For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(VCCO_MAX - VOH_MAX
) = 0.9V
• For logic low, VOUT = VOL_MAX = VCCO_MAX
– 1.7V
(VCCO_MAX - VOL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX
– (VCCO_MAX
- 2V))/R
L
] * (VCCO_MAX
- VOH_MAX) = [(2V - (V
CCO_MAX - VOH_MAX
))/R
L
] * (VCCO_MAX
- VOH_MAX) =
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX
– (VCCO_MAX
- 2V))/R
L
] * (VCCO_MAX
- VOL_MAX) = [(2V - (V
CCO_MAX - VOL_MAX
))/R
L
] * (VCCO_MAX
- VOL_MAX) =
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
VCCO - 2V
Q1
VOUT
RL
50
VCCO
IDT™ / ICS™ 3.3V L VPECL/ LVCMOS FREQUENCY SYNTHESIZER 16 ICS843001BGI-23 REV. B FEBRUARY 19, 2009
ICS843001I-23
FEMTOCLOCK™ CR YSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER PRELIMINARY
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS843001I-23 is: 4165
TABLE 8. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP
θθ
θθ
θJA by Velocity (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 82.3°C/W 78.0°C/W 75.9°C/W
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP TABLE 9. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MO-153
LOBMYS sretemilliM
muminiMmumixaM
N42
A--02.1
1A50.051.0
2A08.050.1
b91.003.0
c90.002.0
D07.709.7
ECISAB04.6
1E03.405.4
eCISAB56.0
L5
4.057.0
α°0°8
aaa--01.0
PACKAGE OUTLINE AND DIMENSIONS
IDT™ / ICS™ 3.3V L VPECL/ LVCMOS FREQUENCY SYNTHESIZER 17 ICS843001BGI-23 REV. B FEBRUARY 19, 2009
ICS843001I-23
FEMTOCLOCK™ CR YSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER PRELIMINARY
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
TABLE 10. ORDERING INFORMATION
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32-IGB10034832IB100348SCIPOSSTdaeL42ebutC°58otC°04-
T32-IGB10034832IB100348SCIPOSSTdaeL42leer&epat0052C°58otC°04-
FL32-IGB100348L32IB10034SCIPOSST"eerF-daeL"dae
L42ebutC°58otC°04-
TFL32-IGB100348L32IB10034SCIPOSST"eerF-daeL"daeL42leer&epat0052C°58otC°04-
.tnailpmocSHoRe
radnanoitarugifnoceerF-bPehterarebmuntrapehtotxiffus"FL"nahtiwderedroeratahtstraP:ETON
ICS843001I-23
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS FANOUT BUFFER PRELIMINARY
Innovate with IDT and accelerate your future networks. Cont act:
www.IDT.com
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800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
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For Tech Support
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+480-763-2056
Corporate Headquarters
Integrated Device Technology , Inc.
6024 Silver Creek V alley Road
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United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
© 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, th e IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
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