High Voltage, Isolated Gate Driver with
Internal Miller Clamp, 2 A Output
Data Sheet
ADuM4121/ADuM4121-1
Rev. 0 Document Feedback
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FEATURES
2 A peak output current (<2 Ω RDSON)
2.5 V to 6.5 V input
4.5 V to 35 V output
Undervoltage lockout (UVLO) at 2.5 V VDD1
Multiple UVLO options on VDD2
Grade A: 4.4 V (typical) UVLO on VDD2
Grade B: 7.3 V (typical) UVLO on VDD2
Grade C: 11.3 V (typical) UVLO on VDD2
Precise timing characteristics
53 ns maximum isolator and driver propagation delay
CMOS input logic levels
High common-mode transient immunity: >150 kV/µs
High junction temperature operation: 125°C
Default low output
Internal Miller clamp
Safety and regulatory approvals (pending)
UL recognition per UL 1577
5 kV rms for 1-minute withstand
CSA Component Acceptance Notice 5A
VDE certificate of conformity (pending)
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
VIORM = 849 V peak
Wide-body, 8-lead SOIC
APPLICATIONS
Switching power supplies
Isolated IGBT/MOSFET gate drives
Industrial inverters
Gallium nitride (GaN)/silicon carbide (SiC) power devices
GENERAL DESCRIPTION
The ADuM4121/ADuM4121-11 are 2 A isolated, single-channel
drivers that employ Analog Devices, I n c .’s iCoupler® technology
to provide precision isolation. The ADuM4121/ADuM4121-1
provide 5 kV rms isolation in the wide-body, 8-lead SOIC package.
Combining high speed CMOS and monolithic transformer
technology, these isolation components provide outstanding
performance characteristics superior to alternatives such as the
combination of pulse transformers and gate drivers.
The ADuM4121/ADuM4121-1 operate with an input supply
ranging from 2.5 V to 6.5 V, providing compatibility with lower
voltage systems. In comparison to gate drivers that employ high
voltage level translation methodologies, the ADuM4121/
ADuM4121-1 offer the benefit of true, galvanic isolation
between the input and the output.
The ADuM4121/ADuM4121-1 include an internal Miller clamp
that activates at 2 V on the falling edge of the gate drive output,
supplying the driven gate with a lower impedance path to reduce
the chance of Miller capacitance induced turn on.
Options exists to allow the thermal shutdown to be enabled or
disabled. As a result, the ADuM4121/ADuM4121-1 provide
reliable control over the switching characteristics of insulated
gate bipolar transistor (IGBT)/metal oxide semiconductor field,
effect transistor (MOSFET) configurations over a wide range of
switching voltages.
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
1 Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,239. Other patents pending.
ENCODE DECODE
AND
LOGIC
V
DD1
V
I
+
GND
1
V
DD2
V
OUT
CLAMP
GND
2
ADuM4121/
ADuM4121-1
UVLO
UVLO TSD
V
I
–
2V
1
2
3
4
8
7
6
5
14967-001
ADuM4121/ADuM4121-1 Data Sheet
Rev. 0| Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics ............................................................. 3
Regulatory Information ............................................................... 4
Package Characteristics ............................................................... 4
Insulation and Safety-Related Specifications ............................ 5
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics .............................................................................. 5
Recommended Operating Conditions ...................................... 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution...................................................................................6
Pin Configuration and Function Descriptions ..............................7
Typical Performance Characteristics ..............................................8
Theory of Operation ...................................................................... 11
Applications Information .............................................................. 12
Printed Circuit Board (PCB) Layout ....................................... 12
Propagation Delay-Related Parameters ................................... 12
Undervoltage Lockout ............................................................... 12
Output Load Characteristics ..................................................... 13
Power Dissipation....................................................................... 13
Insulation Lifetime ..................................................................... 14
Typical Applications ................................................................... 14
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
10/2016—Revision 0: Initial Version
Data Sheet ADuM4121/ADuM4121-1
Rev. 0 | Page 3 of 16
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Low-side voltages referenced to GND1. High side voltages referenced to GND2; 2.5 V ≤ VDD1 ≤ 6.5 V; 4.5 V ≤ VDD2 ≤ 35 V, TJ = −40°C to
+125°C. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical
specifications are at TJ = 25°C, VDD1 = 5.0 V, V DD2= 15 V.
Table 1.
Parameter
Symbol
Min
Max
Unit
Test Conditions/Comments
DC SPECIFICATIONS
High Side Power Supply
VDD2 Input Voltage VDD2 4.5 35 V
V
DD2
Input Current, Quiescent
I
DD2(Q)
2.7
mA
Logic Supply
VDD1 Input Voltage VDD1 2.5 6.5 V
Input Current IDD1 3.6 5 mA VI+ = high, VI− = low
Logic Inputs (VI+, VI−)
Input Current II+, II− −1 0.01 +1 µA
Input Voltage
Logic High VIH 0.7 × VDD1 V 2.5 V ≤ VDD1 ≤ 5 V
3.5 V VDD1 > 5 V
Logic Low VIL 0.3 × VDD1 V 2.5 V ≤ VDD1 ≤ 5 V
1.5 V VDD1 > 5 V
UVLO
VDD1
Positive-Going Threshold
V
VDD1UV+
2.5
V
Negative-Going Threshold VVDD1UV− 2.3 2.35 V
Hysteresis VVDD1UVH 0.1 V
VDD2
Grade A
Positive Going Threshold VVDD2UV+ 4.4 4.5 V
Negative Going Threshold VVDD2UV− 4.1 4.2 V
Hysteresis VVDD2UVH 0.2 V
Grade B
Positive Going Threshold VVDD2UV+ 7.3 7.5 V
Negative Going Threshold VVDD2UV− 6.9 7.1 V
Hysteresis VVDD2UVH 0.2 V
Grade C
Positive Going Threshold VVDD2UV+ 11.3 11.6 V
Negative Going Threshold VVDD2UV− 10.8 11.1 V
Hysteresis VVDD2UVH 0.2 V
Thermal Shutdown (TSD) The ADuM4121-1 does not have TSD
Positive Edge TTSD_POS 155 °C
Hysteresis
T
TSD_HYST
°C
Internal NMOS Gate Resistance RDSON_N 0.6 1.6 Ω Tested at 250 mA, VDD2 = 15 V
0.6 1.6 Ω Tested at 1 A, VDD2 = 15 V
Internal PMOS Gate Resistance
R
DSON_P
1.8
Ω
Tested at 250 mA, V
DD2
= 15 V
0.8 1.8 Ω Tested at 1 A, VDD2 = 15 V
Internal Miller Clamp Resistance RDSON_MILLER 0.8 2 Ω Tested at 200 mA, VDD2 = 15 V
Miller Clamp Voltage Threshold VCLP_TH 1.75 2 2.25 V Referenced to GND2, VDD2 = 15 V
Peak Current IPK 2.3 A VDD2 = 12 V, 4 Ω gate resistance
SWITCHING SPECIFICATIONS
Pulse Width
PW
50
ns
CL = 2 nF, VDD2 = 15 V, RGON 1 = RGOFF1 = 5 Ω
Propagation Delay
Rising Edge2 tDLH 22 32 42 ns CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5 Ω
Falling Edge2 tDHL 30 38 53 ns CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5 Ω
ADuM4121/ADuM4121-1 Data Sheet
Rev. 0| Page 4 of 16
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Skew3 tPSK 22 ns CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5 Ω
Falling Edge4 tPSKHL 12 ns CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5 Ω
Rising Edge5 tPSKLH 15 ns CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5 Ω
Pulse Width Distortion tPWD 7 13 ns CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5 Ω
Output Rise/Fall Time (10% to 90%) tR/tF 11 18 26 ns CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5 Ω
Common-Mode Transient Immunity (CMTI) |CM|
Static CMTI6 150 kV/µs VCM = 1500 V
Dynamic CMTI7
150
kV/µs
V
CM
= 1500 V
1 RGON and RGOFF are the external gate resistors in the test.
2 tDLH propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 10% threshold of the VOUT signal. tDHL propagation
delay is measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VOx signal. See Figure 24 for waveforms of the propagation delay
parameters.
3 tPSK is the magnitude of the worst case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions. See Figure 24 for waveforms of the propagation delay parameters.
4 tPSKHL is the magnitude of the worst case difference in tDHL that is measured between units at the same operating temperature, supply voltages, and output load within
the recommended operating conditions. See Figure 24 for waveforms of the propagation delay parameters.
5 tPSKLH is the magnitude of the worst case difference in tDLH that is measured between units at the same operating temperature, supply voltages, and output load within
the recommended operating conditions. See Figure 24 for waveforms of the propagation delay parameters.
6 Static common-mode transient immunity (CMTI) is defined as the largest dv/dt between GND1 and GND2, with inputs held either high or low, such that the output
voltage remains either above 0.8 × VDD2 for output high or 0.8 V for output low. Operation with transients above recommended levels can cause momentary data upsets.
7 Dynamic common-mode transient immunity (CMTI) is defined as the largest dv/dt between GND1 and GND2 with the switching edge coincident with the transient test
pulse. Operation with transients above the recommended levels can cause momentary data upsets.
REGULATORY INFORMATION
The ADuM4121/ADuM4121-1 are pending approval by the organizations listed in Table 2.
Table 2.
UL (Pending) CSA (Pending) VDE (Pending) CQC (Pending)
UL1577 Component
Recognition Program
Approved under CSA Component Acceptance
Notice 5A
DIN V VDE V 0884-10
(VDE V 0884-10):2006-12
Certified under CQC11-
471543-2012
Single Protection, 5000 V rms
Isolation Voltage
CSA 60950-1-07+A1+A2 and IEC 60950-1, second
edition, +A1+A2:
Reinforced insulation, 849 V
peak, VIOSM = 10 kV peak
GB4943.1-2011
Basic insulation at 800 V rms (1131 V peak)
Basic insulation 849 V peak,
VIOSM = 16 kV peak
Basic insulation at 800 V rms
(1131 V peak)
Reinforced insulation at 400 V rms (565 V peak) Reinforced insulation at
400 V rms (565 V peak)
IEC 60601-1 Edition 3.1:
Basic insulation (1 MOPP), 500 V rms (707 V peak)
Reinforced insulation (2 MOPP), 250 V rms
(1414 V peak)
CSA 61010-1-12 and IEC 61010-1 third edition
Basic insulation at: 600 V rms mains, 800 V
secondary (1089 V peak)
Reinforced insulation at: 300 V rms mains, 400 V
secondary (565 V peak)
File E214100 File 205078 File 2471900-4880-0001 File (pending)
PACKAGE CHARACTERISTICS
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Resistance (Input Side to High-Side Output)1 RI-O 1012 Ω
Capacitance (Input Side to High-Side Output)1 CI-O 2.0 pF
Input Capacitance CI 4.0 pF
Junction to Top Characterization Parameter
Ψ
JT
7.3
°C/W
4-layer PCB
1 The device is considered a two-terminal device: Pin 1 through Pin 4 are shorted together, and Pin 5 through Pin 8 are shorted together.
Data Sheet ADuM4121/ADuM4121-1
Rev. 0 | Page 5 of 16
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 4.
Parameter Symbol Value Unit Conditions
Rated Dielectric Insulation Voltage 5000 V rms 1-minute duration
Minimum External Air Gap (Clearance)
L(I01)
8 min
mm
Measured from input terminals to output terminals, shortest
distance through air
Minimum External Tracking (Creepage) L(I02) 8 min mm Measured from input terminals to output terminals, shortest
distance path along body
Minimum Clearance in the Plane of the Printed
Circuit Board (PCB Clearance)
L (PCB) 8.3 min mm Measured from input terminals to output terminals, shortest
distance through air, line of sight, in the PCB mounting plane
Minimum Internal Gap (Internal Clearance) 25.5 min µm Minimum distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303 Part 3
Isolation Group II Material Group (DIN VDE 0110, 1/89, Table 1)
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
This isolator is suitable for reinforced isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits.
Table 5. VDE Characteristics
Description Test Conditions/Comments Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 600 V rms I to IV
Climatic Classification 40/105/21
Pollution Degree per DIN VDE 0110, Table 1
2
Maximum Working Insulation Voltage VIORM 849 V peak
Input to Output Test Voltage, Method B1 VIORM × 1.875 = Vpd (m), 100% production test, tini = tm = 1 sec,
partial discharge < 5 pC
Vpd (m) 1592 V peak
Input to Output Test Voltage, Method A
After Environmental Tests Subgroup 1 VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC Vpd (m) 1274 V peak
After Input and/or Safety Test Subgroup 2
and Subgroup 3
VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC Vpd (m) 1019 V peak
Highest Allowable Overvoltage
V
IOTM
7000
V peak
Surge Isolation Voltage Basic VPEAK = 16 kV, 1.2 µs rise time, 50 µs, 50% fall time VIOSM 16,000 V peak
Surge Isolation Voltage Reinforced VPEAK = 16 kV, 1.2 µs rise time, 50 µs, 50% fall time VIOSM 10,000 V peak
Safety Limiting Values Maximum value allowed in the event of a failure (see Figure 2)
Maximum Junction Temperature TS 150 °C
Safety Total Dissipated Power PS 1.2 W
Insulation Resistance at TS VIO = 500 V RS >109 Ω
Figure 2. Thermal Derating Curve, Dependence of Safety Limiting Values on
Case Temperature, per DIN V VDE V 0884-10
RECOMMENDED OPERATING CONDITIONS
Table 6.
Parameter
Value
Operating Temperature Range (TJ) −40°C to +125°C
Supply Voltages
VDD1 to GND1 2.5 V to 6.5 V
VDD2 to GND2 4.5 V to 35 V
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0050 100 150 200
SAFE LIMITING POWER (W)
AMBI E NT TE M P E RATURE ( °C)
14967-002
ADuM4121/ADuM4121-1 Data Sheet
Rev. 0| Page 6 of 16
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Table 7.
Parameter Rating
Storage Temperature Range (TST) −55°C to +150°C
Junction Operating Temperature Range (TJ) −40°C to +125°C
Supply Voltages
VDD1 to GND1 −0.3 V to +7 V
VDD2 to GND2 −0.3 V to +40 V
Input Voltages
V
I
+, V
I
−
1
−0.3 V to +7 V
VCLAMP2 −0.3 V to VDD2 + 0.3 V
Output Voltages
VOUT2 −0.3 V to VDD2 + 0.3 V
Common-Mode Transients (|CM|)3 −200 kV/µs to
+200 kV/µs
1 Rating assumes VDD1 is above 2.5 V. VI+ and VI− are rated up to 6.5 V when
VDD1 is unpowered.
2 Referenced to GND2, maximum of 40 V.
3 |CM| refers to common-mode transients across the insulation barrier.
Common-mode transients exceeding the Absolute Maximum Rating can
cause latch-up or permanent damage.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required. θJA is thermal resistance,
junction to ambient (°C/W).
Table 8. Thermal Resistance
Package Type θJA Unit
RI-8-1
1
104.2
°C/W
1 Test Condition 1: thermal impedance simulated values are based on a
4-layer PCB.
ESD CAUTION
Table 9. Maximum Continuous Working Voltage1
Parameter
Rating
Unit
Constraint
AC Voltage
Bipolar Waveform
Basic Insulation 849 V peak 50-year minimum insulation lifetime
Reinforced Insulation 789 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
Unipolar Waveform
Basic Insulation 1698 V peak 50-year minimum insulation lifetime
Reinforced Insulation 849 V peak 50-year minimum insulation lifetime
DC Voltage
Basic Insulation 1118 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
Reinforced Insulation 558 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
1 Maximum continuous working voltage refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more
details.
Table 10. Truth Table
VI− VI+ VDD1 State VDD2 State VOUT Output
Don’t care Low Powered Powered Low
Low High Powered Powered High
High Don’t care Powered Powered Low
Don’t care Don’t care Unpowered Powered Low
Don’t care Don’t care Powered Unpowered Low1
1 The output is low, but not actively driven because the device is not powered.
Data Sheet ADuM4121/ADuM4121-1
Rev. 0 | Page 7 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 11. Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD1 Supply Voltage for Isolator Side 1.
2 VI+ Noninverting Gate Drive Logic Input.
3 VI− Inverting Gate Drive Logic Input.
4 GND1 Ground 1. This pin is the ground reference for Isolator Side 1.
5 GND2 Ground 2. This pin is the ground reference for Isolator Side 2.
6 CLAMP Miller Clamp and Gate Voltage Sense. Connect this pin directly to the gate being driven.
7 VOUT Gate Drive Output. Connect this pin to the gate being driven through an external series resistor.
8 VDD2 Supply Voltage for Isolator Side 2.
1
2
3
4
8
7
6
5
ADuM4121/
ADuM4121-1
TOP VIEW
(Not to Scale)
V
DD1
V
I
+
GND
1
V
I
–
V
DD2
V
OUT
CLAMP
GND
2
14967-003
ADuM4121/ADuM4121-1 Data Sheet
Rev. 0| Page 8 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 4. VI+ to VGATE Waveform for 2 nF Load, 3.9 Ω Series Gate Resistor,
VDD2 = 15 V (VGATE Is the Voltage After a Gate Resistor)
Figure 5. VI− to VGATE Waveform for 2 nF Load, 3.9 Ω Series Gate Resistor,
VDD2 = 15 V
Figure 6. VI+ to VGATE Waveform for 2 nF Load, 0 Ω Series Gate Resistor,
VDD2 = 15 V
Figure 7. VI− to VGATE Waveform for 2 nF Load, 0 Ω Series Gate Resistor,
VDD2 = 15 V
Figure 8. Typical VDD1 Delay to Output Waveform, VI+ = VDD1, VI− = GND1
Figure 9. IDD2 vs. Duty Cycle, VDD1 = 5 V, Switching Frequency (fSW) = 10 kHz,
2 nF Load
CH1 2.0V/DIV
CH2 5.0V/DIV
BW
: 1.0G
BW
: 1.0G
A CH1 840mV 40.0ns/DIV 5.0GS/s
200ps/pt
1
2
V
I
+
V
GATE
14967-101
CH1 2.0V/DIV
CH2 5.0V/DIV
BW
: 1.0G
BW
: 1.0G
A CH1 840mV 40.0ns/DIV 5.0GS/s
200ps/pt
1
2
V
I
–
V
GATE
14967-102
CH1 2.0V/DIV
CH2 5.0V/DIV
BW
: 1.0G
BW
: 1.0G
A CH1 840mV 40.0ns/DIV 5.0GS/s
200ps/pt
1
2
V
GATE
V
I
+
14967-103
CH1 2.0V/DIV
CH2 5.0V/DIV
BW
: 1.0G
BW
: 1.0G
A CH1 840mV 40.0ns/DIV 5.0GS/s
200ps/pt
1
2
V
GATE
V
I
–
14967-104
CH1 2.0V/DIV
CH2 5.0V/DIV
BW
: 1.0G
BW
: 1.0G
A CH1 840mV 2.0µs/DIV 5.0GS/s
200ps/pt
1
2
V
OUT
V
DD1
14967-105
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0 20406080100
I
DD2
(mA)
DUTY CYCLE (%)
V
DD2
= 15V
V
DD2
= 10V
V
DD2
= 5V
14967-106
Data Sheet ADuM4121/ADuM4121-1
Rev. 0 | Page 9 of 16
Figure 10. IDD1 vs. Duty Cycle, fSW = 10 kHz, 2 nF Load
Figure 11. IDD1 vs. Frequency
Figure 12. IDD2 vs. Frequency with 2 nF Load
Figure 13. Propagation Delay vs. VDD1, VDD2 = 15 V, 2 nF Load, 0 Ω Gate
Resistor
Figure 14. Propagation Delay vs. Temperature, 2 nF Load
Figure 15. Propagation Delay vs. VDD2, 2 nF Load
0
1
2
4
6
7
3
5
I
DD1
(mA)
0 20406080100
DUTY CYCLE (%)
V
DD1
= 5.0V
V
DD1
= 3.3V
14967-107
3.0
2.5
2.0
1.5
1.0
0.5
0
0 50 100 150 200 250 300 350 400 450 500
I
DD1
(mA)
FREQUENCY (kHz)
V
DD1
= 5.0V
V
DD1
= 3.3V
14967-109
5.0
0
I
DD2
(mA)
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0 50 100 150 200 250 300 350 400 450 500
FREQUENCY (kHz)
V
DD2
= 15V
V
DD2
= 10V
V
DD2
= 5V
14967-110
60
50
30
40
10
20
0
2.53.03.54.04.55.05.5
PROPAGATION DELAY (ns)
V
DD1
(V)
t
DHL
t
DLH
14967-108
60
50
40
30
20
10
0
–40 –20 0 20 40 60 80 100 120
PROPAGATION DELAY (ns)
TEMPERATURE (°C)
t
DHL
t
DLH
14967-111
60
50
30
40
10
20
0
5 101520253035
PROPAGATION DELAY (ns)
V
DD2
(V)
t
DHL
t
DLH
14967-114
ADuM4121/ADuM4121-1 Data Sheet
Rev. 0| Page 10 of 16
Figure 16. Rise and Fall Time vs. VDD2, 2 nF Load, 3.9 Ω Resistor
Figure 17. Peak Output Current vs. VDD2, 2 Ω Series Resistance
Figure 18. Typical Output Resistance (RDSON) vs. VDD2
Figure 19. Typical Output Resistance (RDSON) vs. Temperature, VDD2 = 15 V
40
0
10
5
15
25
35
20
30
4.5 9.5 13.5 24.519.5 34.529.5
RISE/FALL TIME (ns)
V
DD2
(V)
t
F
t
R
14967-115
9
8
7
5
6
3
4
1
2
0
4.5 9.5 14.5 19.5 24.5 34.529.5
V
DD2
(V)
PEAK O UTPUT CURRENT (A)
SOURCE CURRE NT
SINK CURRE NT
14967-116
0.9
0.8
0.7
0.5
0.6
0.3
0.4
0.1
0.2
0
4.5 9.0 13.5 18.0 22.5 31.527.0
V
DD2
(V)
R
DSON
(Ω)
PMOS
NMOS
14967-113
1.2
0
0.2
0.6
1.0
0.4
0.8
–40 10 60 110
RDSON (Ω)
TEMPERATURE (°C)
PMOS
NMOS
14967-112
Data Sheet ADuM4121/ADuM4121-1
Rev. 0 | Page 11 of 16
THEORY OF OPERATION
Gate drivers are required in situations where fast rise times of
switching device gates are desired. The gate signal for most
enhancement type power devices are referenced to a source or
emitter node. The gate driver must be able to follow this source
or emitter node, necessitating isolation between the controlling
signal and the output of the gate driver in topologies where the
source or emitter nodes swing, such as a half bridge. Gate switching
times are a function of drive strength of the gate driver. Buffer
stages before a CMOS output reduce total delay time
andincrease the final drive strength of the driver.
The ADuM4121/ADuM4121-1 achieve isolation between the
control side and output side of the gate driver by means of a
high frequency carrier that transmits data across the isolation
barrier using iCoupler chip scale transformer coils separated by
layers of polyimide isolation. The encoding scheme used by the
ADuM4121/ADuM4121-1 is a positive logic on/off keying
(OOK), meaning a high signal is transmitted by the presence of
the carrier frequency across the iCoupler chip scale transformer
coils. Positive logic encoding ensures that a low signal is seen on
the output when the input side of the gate driver is unpowered.
A low state is the most common safe state in enhancement
mode power devices, driving in situations where shoot through
conditions can exist. The architecture is designed for high
common-mode transient immunity and high immunity to
electrical noise and magnetic interference. Radiated emissions
are minimized with a spread spectrum OOK carrier and other
techniques such as differential coil layout. Figure 20 illustrates
the encoding used by the ADuM4121/ADuM4121-1.
Figure 20. Operational Block Diagram of OOK Encoding
TRANSMITTER
GND
1
GND
2
V
IN
V
OUT
RECEIVER
REGULATOR REGULATOR
14967-014
ADuM4121/ADuM4121-1 Data Sheet
Rev. 0| Page 12 of 16
APPLICATIONS INFORMATION
PRINTED CIRCUIT BOARD (PCB) LAYOUT
The ADuM4121/ADuM4121-1 digital isolators require no
external interface circuitry for the logic interfaces. Power supply
bypassing is required at the input and output supply pins, as
shown in Figure 21. Use a small ceramic capacitor with a value
between 0.01 µF and 0.1 µF to provide a good high frequency
bypass. On the output power supply pin, VDD2, it is recommended
to also add a 10 µF capacitor to provide the charge required to
drive the gate capacitance at the ADuM4121/ADuM4121-1
outputs. On the output supply pin, the bypass capacitor use of
vias must be avoided or multiple vias must be employed to
reduce the inductance in the bypassing. The total lead length
between both ends of the smaller capacitor and the input or
output power supply pin must not exceed 20 mm.
Figure 21. Recommended PCB Layout
VI+ and VI− Operation
The ADuM4121/ADuM4121-1 have two drive inputs, VI+ and
VI−, to control the IGBT gate drive signals, VOUT. Both the VI+
and VI− pins use CMOS logic level inputs. Control the input
logic of the VI+ and VI− pins by either asserting the VI+ pin high,
or the VI− pin low. With the VI− pin low, the VI+ pin accepts
positive logic. If VI+ is held high, the VI− pin accepts negative logic.
Figure 22. VI+ and VI− Block Diagram
See Figure 23 for more details.
Figure 23. VI+ and VI− Timing Diagram
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time a logic
signal takes to propagate through a component. The propagation
delay to a logic low output can differ from the propagation delay to
a logic high output. The ADuM4121/ADuM4121-1 specify tDLH
(see Figure 24) as the time between the rising input high logic
threshold, VIH, to the output rising 10% threshold. Likewise, the
falling propagation delay, tDHL, is defined as the time between the
input falling logic low threshold, VIL, and the output falling 90%
threshold. The rise and fall times are dependent on the loading
conditions and are not included in the propagation delay, as is
the industry standard for gate drivers.
Figure 24. Propagation Delay Parameters
Channel to channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM4121/ADuM4121-1 component.
Propagation delay skew refers to the maximum amount that
the propagation delay differs between multiple ADuM4121/
ADuM4121-1 components operating under the same conditions.
UNDERVOLTAGE LOCKOUT (UVLO)
The ADuM4121/ADuM4121-1 have UVLO protections for
both the primary and secondary side of the device. If either the
primary or secondary side voltages are below the falling edge
UVLO, the device outputs a low signal. After the ADuM4121/
ADuM4121-1 are powered above the rising edge UVLO threshold,
the device outputs the signal found at the input. Hysteresis is built
into the UVLO to account for small voltage source ripple. The
primary side UVLO thresholds are common among all models.
There are three options for the secondary output UVLO
thresholds, listed in Table 12.
Table 12. List of Model Options
Model Number TSD UVLO (V)
ADuM4121ARIZ Yes 4.5
ADuM4121BRIZ Yes 7.5
ADuM4121CRIZ Yes 11.6
ADuM4121ARIZ-1 No 4.5
ADuM4121BRIZ-1 No 7.5
ADuM4121CRIZ-1 No 11.6
VDD1
GND1
VDD2
GND2
VI+VOUT
CLAMP
VI–
14967-015
V
I
+V
OUT
V
I
–
14967-016
V
I
+
V
I
–
V
GATE
tDHL tDLH
14967-017
OUTPUT
INPUT
t
DLH
t
R
90%
10%
V
IH
V
IL
t
F
t
DHL
14967-018
Data Sheet ADuM4121/ADuM4121-1
Rev. 0 | Page 13 of 16
OUTPUT LOAD CHARACTERISTICS
The ADuM4121/ADuM4121-1 output signals depend on the
characteristics of the output load, which is typically an N channel
MOSFET. Model the driver output response to an N channel
MOSFET load with a switch output resistance (RSW), an
inductance due to the printed circuit board trace (LTRACE), a series
gate resistor (RGATE), and a gate to source capacitance (CGS), as
shown in Figure 25.
RSW is the switch resistance of the internal ADuM4121/ADuM4121-1
driver output, which is about 1.5 Ω. RGATE is the intrinsic gate resis-
tance of the MOSFET or IGBT and any external series resistance.
A MOSFET or IGBT that requires a 2 A gate driver has a typical
intrinsic gate resistance of about 1 Ω and a gate to source capaci-
tance, CGS, of between 2 nF and 10 nF. LTRACE is the inductance of
the printed circuit board trace, typically a value of 5 nH or less for
a well designed layout with a very short and wide connection from
the ADuM4121/ADuM4121-1 output to the gate of the MOSFET
or IGBT.
The following equation defines the quality factor, Q, of the RLC
circuit, which indicates how the ADuM4121/ADuM4121-1 output
responds to a step change. For a well damped output, Q is less than
one. Adding a series gate resistance dampens the output response.
GS
TRACE
GATE
SW C
L
RR
Q×
+
=
)(
1
Output ringing is reduced by adding a series gate resistance to
dampen the response. The waveforms shown in Figure 4 show a
correctly damped example with a 2 nF load and a 3.9 Ω external
series gate resistor. The waveforms shown in Figure 6 show an
underdamped example with a 2 nF load and a 0 Ω external
series gate resistor.
Figure 25. RLC Model of the Gate of an N Channel MOSFET
Miller Clamp
The ADuM4121/ADuM4121-1 have an integrated Miller clamp
to reduce voltage spikes on the MOSFET or IGBT gate caused
by the Miller capacitance during shutoff of the MOSFET or IGBT.
When the input gate signal requests the IGBT to be turned off
(driven low), the Miller clamp MOSFET is off initially. After the
voltage on the gate sense pin crosses the 2 V internal voltage
reference that is referenced to GND2, the internal Miller clamp
latches on for the remainder of the off time of the MOSFET or
IGBT, creating a second low impedance current path for the
gate current to follow. The Miller clamp switch remains on until
the input drive signal changes from low to high. An example
waveform of the timings is shown in Figure 26.
Figure 26. Miller Clamp Example
POWER DISSIPATION
During the driving of a MOSFET or IGBT gate, the driver must
dissipate power. This power is not insignificant, and can lead to
thermal shutdown (TSD) if considerations are not made. The
gate of an IGBT can be approximately simulated as a capacitive
load. Due to Miller capacitance and other nonlinearities, it is
common practice to take the stated input capacitance of a given
MOSFET or IGBT, CISS, and multiply it by a factor of 3 to 5 to
arrive at a conservative estimate of the approximate load being
driven. With this value, the estimated total power dissipation in
the system due to switching action is given by
PDISS = CEST × (VDD2 − GND2)2 × fSW
where:
CEST = CISS × 5.
fSW is the switching frequency of the IG BT.
Alternately, the gate charge can be used as follows:
PDISS = QG × (VDD2 − GND2) × fSW
where QG is the total gate charge of the device being driven.
This power dissipation is shared between the internal on resistances
of the internal gate driver switches, and the external gate resistances,
RGON and RGOFF. The ratio of the internal gate resistances to the
total series resistance allows the calculation of losses seen within
the ADuM4121/ADuM4121-1 devices. The following calculations
for the ADuM4121also apply to the ADuM4121-1.
PDISS_ADuM4121 = PDISS × 0.5(RDSON_P/(RGON + RDSON_P) +
0.5(RDSON_N/(RGOFF + RDSON_N))
Taking this power dissipation found inside the chip, and multiply-
ing it by the θJA gives the rise above ambient temperature that
the ADuM4121 experiences.
TADuM4121 = θJA × PDISS_ADuM4121 + TAMB
For the device to remain within specification, TADUM4121 must not
exceed 125°C. If TADuM4121 exceeds the TSD rising edge, the device
enters TSD, and the output remains low until the TSD falling edge
is crossed. The ADuM4121-1 does not include thermal shutdown.
ADuM4121/
ADuM4121-1
V
I
V
OUT
R
SW RGATE
C
GS
L
TRACE
V
O
14967-019
V
CLAMP
V
DD2
GND
2
MILLER
CLAMP
SWITCH
2V
V
I
+
V
I
–
ONOFF OFF
LATCH OFF
LAT CH ON
14967-020
ADuM4121/ADuM4121-1 Data Sheet
Rev. 0| Page 14 of 16
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of insu-
lation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation. In addition
to the testing performed by the regulatory agencies, Analog
Devices carries out an extensive set of evaluations to determine
the lifetime of the insulation structure within the ADuM4121/
ADuM4121-1.
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage. Accel-
eration factors for several operating conditions are determined.
These factors allow calculation of the time to failure at the actual
working voltage.
The values shown in Table 9 summarize the peak voltage for
50 years of service life for a bipolar ac operating condition, and
the maximum CSA/VDE approved working voltages. In many
cases, the approved working voltage is higher than the 50-year
service life voltage. Operation at these high working voltages
can lead to shortened insulation life in some cases.
The insulation lifetime of the ADuM4121/ADuM4121-1
depends on the voltage waveform type imposed across the
isolation barrier. The iCoupler insulation structure degrades at
different rates depending on whether the waveform is bipolar
ac, unipolar ac, or dc. Figure 27, Figure 28, and Figure 29
illustrate these different isolation voltage waveforms.
A bipolar ac voltage environment is the worst case for the
iCoupler products and is the 50-year operating lifetime that
Analog Devices recommends for maximum working voltage. In
the case of unipolar ac or dc voltage, the stress on the insulation
is significantly lower. This unipolar ac or dc voltage operation
allows operation at higher working voltages while still achieving
a 50-year service life. Any cross insulation voltage waveform that
does not conform to Figure 28 or Figure 29 must be treated as a
bipolar ac waveform, and its peak voltage must be limited to the
50-year lifetime voltage value listed in Table 9.
Note that the voltage presented in Figure 28 is shown as sinu-
soidal for illustration purposes only. It is meant to represent any
voltage waveform varying between 0 V and some limiting value.
The limiting value can be positive or negative, but the voltage
cannot cross 0 V.
Figure 27. Bipolar AC Waveform
Figure 28. Unipolar AC Waveform
Figure 29. DC Waveform
TYPICAL APPLICATIONS
A typical application of the ADuM4121/ADuM4121-1 is shown
in Figure 30. An external gate resistor, RG, controls the rise and
fall times of the gate voltage seen at the device being driven. An
optional turn off path is available for further tuning by creating
a parallel path through D1. An example bootstrap setup is shown
in Figure 31. In both of these examples, the VI− pins are tied
low, creating a positive logic input to the gate drivers. In this
manner, the VI− pins act as a disable pin, bringing the outputs
low if the VI− pins are brought high.
Figure 30. Typical Application Diagram, Single Device
0V
RATED PEAK VOLTAGE
14967-023
0V
RATED PEAK VOLTAGE
14967-024
0V
RATED PEAK VOLTAGE
14967-025
3
1
2
4
8
7
6
5
ADuM4121/
ADuM4121-1
V
I
–
V
DD1
V
I
+
GND
1
V
DD2
V
OUT
CLAMP
GND
2
R
G
0.1µF 10µF
0.1µF GND
2
D1
V
DD2
V
DD1
OPTIONAL
R
GOFF
14967-120
NOTES
1. INDIVIDUAL GROUNDS ARE ISOLATED FROM EACH OTHER.
Data Sheet ADuM4121/ADuM4121-1
Rev. 0 | Page 15 of 16
Figure 31. Typical Application Diagram, Bootstrap Setup
14967-121
3
1
2
4
8
7
6
5
ADuM4121/
ADuM4121-1
VI–
VDD1
VI+
GND1
VDD2
VOUT
CLAMP
GND2
RGA
0.1µF 10µF
0.1µF
D2
DBOOT
OPTIONAL
RGAOFF
3
1
2
4
8
7
6
5
ADuM4121/
ADuM4121-1
VI–
VDD1
VI+
GND1
VDD2
VOUT
CLAMP
GND2
RGB
0.1µF 20µF
0.1µF
D1
VDD2
VDD1
OPTIONAL
RGBOFF
TO LOAD
V
BUS
RBOOT
NOTES
1. INDIVIDUAL GROUNDS ARE ISOLATED FROM EACH OTHER.
ADuM4121/ADuM4121-1 Data Sheet
Rev. 0| Page 16 of 16
OUTLINE DIMENSIONS
Figure 32. 8-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]
Wide Body
(RI-8-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
No. of
Channels
Output Peak
Current (A)
Thermal
Shutdown
Minimum Output
Voltage (V)
Temperature
Range Package Description
Package
Option
ADuM4121ARIZ
1
2
Yes
4.5
−40°C to +125°C
8-Lead SOIC_IC
RI-8-1
ADuM4121ARIZ-RL 1 2 Yes 4.5 −40°C to +125°C 8-Lead SOIC_IC, 13”
Tape and Reel
RI-8-1
ADuM4121BRIZ 1 2 Yes 7.5 −40°C to +125°C 8-Lead SOIC_IC RI-8-1
ADuM4121BRIZ-RL 1 2 Yes 7.5 −40°C to +125°C 8-Lead SOIC_IC, 13”
Tape and Reel
RI-8-1
ADuM4121CRIZ 1 2 Yes 11.6 −40°C to +125°C 8-Lead SOIC_IC RI-8-1
ADuM4121CRIZ-RL 1 2 Yes 11.6 −40°C to +125°C 8-Lead SOIC_IC, 13”
Tape and Reel
RI-8-1
ADuM4121-1ARIZ 1 2 No 4.5 −40°C to +125°C 8-Lead SOIC_IC RI-8-1
ADuM4121-1ARIZ-RL 1 2 No 4.5 −40°C to +125°C 8-Lead SOIC_IC, 13”
Tape and Reel
RI-8-1
ADuM4121-1BRIZ 1 2 No 7.5 −40°C to +125°C 8-Lead SOIC_IC RI-8-1
ADuM4121-1BRIZ-RL 1 2 No 7.5 −40°C to +125°C 8-Lead SOIC_IC, 13”
Tape and Reel
RI-8-1
ADuM4121-1CRIZ 1 2 No 11.6 −40°C to +125°C 8-Lead SOIC_IC RI-8-1
ADuM4121-1CRIZ-RL 1 2 No 11.6 −40°C to +125°C 8-Lead SOIC_IC, 13”
Tape and Reel
RI-8-1
EVAL-ADuM4121EBZ 1 2 Yes 4.5 −40°C to +125°C Evaluation Board RI-8-1
EVAL-ADuM4121-1EBZ 1 2 No 4.5 −40°C to +125°C Evaluation Board RI-8-1
1 Z = RoHS Compliant Part.
09-17-2014-B
85
4
1
SEATING
PLANE
COPLANARITY
0.10
1.27 BSC
1.04
BSC
6.05
5.85
5.65
7.60
7.50
7.40
2.65
2.50
2.35
0.75
0.58
0.40
0.30
0.20
0.10
2.45
2.35
2.25
10.51
10.31
10.11
0.51
0.41
0.31
PIN 1
MARK
8°
0°
0.33
0.27
0.20
0.75
0.50
0.25 45°
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14967-0-10/16(0)