FUJITSU MICROELECTRONICS
DATA SHEET
Copyright©2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2009.11
ASSP for Power Management Applications
Buck DC/DC Converter +
Low noise LDO
MB39C022G/MB39C022J/MB39C022L
MB39C022N
■DESCRIPTION
The MB39C022 is a 2 channels power supply IC. It consists of one channel Buck DC/DC Converter and one
channel LDO regulator. The DC/DC converter has fast transient response with current mode control topology.
Moreover, the integrated LDO provides an auxiliary output supply for noise sensitive circuit.
■FEATURES
• Power supply voltage range : 2.5 V to 5.5 V
• For Buck DC/DC included SW FET (CH1) : output 0.8 V to 4.5 V, 600 mA Max DC
• For LDO (CH2) : output 3.30 V (MB39C022G) 300 mA Max DC
output 2.85 V (MB39C022J) 300 mA Max DC
output 1.80 V (MB39C022L) 300 mA Max DC
output 1.20 V (MB39C022N) 300 mA Max DC
• Error amplifier threshold voltage : 0.3 V ± (2.5%) (CH1)
• Fast line transient response with current mode topology (CH1)
• PFM mode at light load current with VO1/VIN1 ≤ 80% (IO1 ≤ 10 mA) (CH1)
• Power-on-reset with 66 ms delay (CH1)
• Built-in short circuit protect (CH2)
• Built-in over current protect (CH1, CH2)
• Built-in thermal protection function
• Small size plastic SON-10 (3 mm × 3 mm) package
■APPLICATIONS
• Portable Equipment
• PND, GPS
•PMP
• Mobile TV, USB-dongle (CMMB, DVB-T, DMB-T)
• Smart-phone
•MP3
DS04-27271-2E
MB39C022
2DS04-27271-2E
■PIN ASSIGNMENT
■PIN DESCRIPTIONS
Block Pin No. Pin name I/O Descriptions
CH1 (Buck DC/DC) 6 FB I CH1 Error Amplifier input pin
9 LX O CH1 Inductor connection pin
CH2 (LDO) 3 VOUT2 O CH2 LDO output pin
Control 7 EN1 I CH1 Control pin (L : shutdown / H : operation)
1 EN2 I CH2 Control pin (L : shutdown / H : operation)
Power
8VIN1⎯CH1 Power supply pin
2VIN2⎯CH2 Power supply pin
10 GND1 ⎯CH1 Ground pin
5GND2⎯CH2 Ground pin
Power-on Reset 4 POR O CH1 Power on reset output pin (NMOS open drain)
(TOP VIEW)
(LCC-10P-M04)
EN2 VIN2 VOUT2 GND2POR
GND1 LX VIN1 FBEN1
24351
7689
10
MB39C022
DS04-27271-2E 3
■I/O TERMINAL EQUIVALENT CIRCUIT DIAGRAM
GND1
VIN1
LX
GND2
POR
GND2
VIN1
EN∗
GND2
VIN1
FB
GND2
VIN2
VOUT2
∗
∗
∗
∗
∗ ∗
* : ESD Protection device
MB39C022
4DS04-27271-2E
■BLOCK DIAGRAM
Current
Limit
PFM
PWM
Logic
Control
ICOMP
FB
POR
6
4
POR
DRV
OSC
VREF
OCP/SCP
Error
Amp.
Error
Amp.
OTP
UVLO
8
9
LEVEL
CONV.
10
7
1
2
3
5
enb1 (H: CH1 ON)
enb2 (H: CH2 ON)
EN1
EN2
VIN or VO1
VIN1
LX
GND1
VIN2
VOUT2
GND2
<<CH1 Buck DC/DC>>
<<CH2: LDO>>
IO2
(300 mA Max)
VO2
IO1
(600 mA Max)
VO1
(0.8 V to 4.5 V)
VIN
(2.5 V to 5.5 V)
<<10 PIN>>
POR
3.3 V: MB39C022G
2.85 V: MB39C022J
1.8 V: MB39C022L
1.2 V: MB39C022N
MB39C022
DS04-27271-2E 5
■FUNCTION DESCRIPTIONS
(1) PFM/PWM Logic Control Block (CH1)
The built-in P-ch and N-ch MOS FETs are controlled f or synchronization rectification according to the frequency
(2.0 MHz) oscillated from the built-in oscillator (square wave oscillation circuit). Under light load, it operates
intermittently.
This circuit protects the through current caused by synchronous rectification and the reverse current in
Discontinuous Conduction Mode.
Since the PWM control circuit of this IC is in the control method in current mode, the current peak value is
monitored and controlled as required.
(2) Level converter and Iout Comparator circuit (CH1)
The Level converter circuit detects the current (ILX) which flows to the exter nal inductor from the built-in P-ch
MOS FET. By comparing VIDET obtained through I-V conv ersion of peak current IPK of ILX with the Error Amp.
output, the Iout Comparator turns off the built-in P-ch MOS FET via the PWM Logic Control circuit.
(3) Error Amp. circuit (CH1)
The error amplifier (Error Amp.) detects the output voltage from the DC/DC converter and output to the current
comparators (ICOMP). The output v oltage setting resistor e xternally connected to FB allows an arbitrary output
voltage to be set.
(4) LDO Block (CH2)
The integrated low noise low dropout regulator (LDO) is available up to 300 mA current capability and 700 mA
ov er current protection (OCP) 350 mA short circuit protection (SCP). The LDO output V OUT2 requires a 4.7 μF
capacitor for MB39C022G and MB39C022N and a 1.0 μF capacitor for MB39C022J and MB39C022L for stability .
MB39C022G, MB39C022J, MB39C022L and MB39C022N have fixed 3.3 V, 2.85 V, 1.8 V and 1.2 V output
voltages respectively, eliminating the need for an external resistor divider.
(5) POR Block
The POR circuit monitors the VO1 through the FB pin voltage. When the FB pin voltage reaches 97% of VFBTH,
POR pin becomes high level after the hold time of 66 ms. The POR pin is an open-drain output and pulled up
to VIN or VO1 with an e xternal resistor.
Timing Chart : (POR pin pulled up to VIN with resistor)
VIN
EN1
FB
POR
thold thold
VTH × 97%
VUVLO
VUVLO : UVLO threshold voltage (VTLH = 2.050 V)
VTH : FB pin threshold voltage (VTH = 0.3 V)
MB39C022
6DS04-27271-2E
(6) Reference Voltage Block (VREF)
A high accuracy reference voltage is generated with BGR (bandgap reference) circuit.
(7) Under Voltage Lockout Protection Circuit Block (UVLO)
The circuit protects against IC malfunction and system destruction/deterioration in a transitional state or a
momentary drop of when the internal reference voltage starts. It detects a voltage drop at the VIN1 pin and stops
IC operation. When voltages at the VIN1 pin exceed the threshold voltage of the under voltage lockout protection
circuit, the system is restored.
(8) Over Temperature Protection Block (OTP)
The circuit protects an IC from heat-destruction. If the junction temperature reaches 135 °C, the circuit turns off
the CH1 and CH2 operation, When the junction temperature comes down to + 110 °C, the CH1 and CH2 are
returned to the normal operation.
(9) Control Block (CTL)
• Control function table
EN1 EN2 CH1 and POR CH2 VREF, UVLO, OTP
LL OFF OFF OFF
H L ON OFF ON
LH OFF ON ON
H H ON ON ON
MB39C022
DS04-27271-2E 7
■ABSOLUTE MAXIMUM RATINGS
*1: When mounted on four layer epoxy board of 11.7 cm × 8.4 cm
*2: At connect the exposure pad and with thermal via (Thermal via 4 pcs).
*3: At connect the exposure pad and not thermal via.
*4: Power dissipation value between + 25 °C and + 85 °C is obtained by connecting these two points with a straight
line
Notes: • The use of negativ e v oltages below − 0.3 V to the GND pin ma y create par asitic transistors on LSI lines ,
which can cause abnormal operation.
• If LX terminal is short-circuited to VIN1 or VIN2 or GND line, there is a possibility to destroy it. Such usage
is prohibit
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Parameter Symbol Condition Rating Unit
Min Max
Power supply voltage VIN1 VIN1 pin − 0.3 + 6.0 V
VIN2 VIN2 pin − 0.3 VIN1 + 0.3 V
Input voltage
VFB FB pin − 0.3 VIN1 + 0.3 V
VEN1 EN1 pin − 0.3 + 6.0 V
VEN2 EN2 pin − 0.3 + 6.0 V
POR pull-up voltage VPOR POR pin − 0.3 + 6.0 V
LX voltage VLX LX pin − 0.3 VIN1 + 0.3 V
LX peak current ILX LX pin AC ⎯1.6 A
VOUT2 peak current IO2 VOUT2 pin AC ⎯0.8 A
Power dissipation PD
Ta ≤ + 25 °C⎯2632*1, *2
mW
⎯980*1, *3
Ta = + 85 °C⎯1053*1, *2, *4
⎯392*1, *3, *4
Storage temperature TSTG ⎯ − 55 + 125 °C
MB39C022
8DS04-27271-2E
■RECOMMENDED OPERATING CONDITIONS
*1 : The minimum VIN1 has to meet two conditions : VIN1 ≥ (VIN1 Min) and VIN1 ≥ VO1 + 0.5 V
*2 : The minimum VIN2 has to meet two conditions : VIN2 ≥ (VIN2 Min) and VIN2 ≥ VO2 + Vdrop (VO2 and Vdrop
values are specified in “■ ELECTRICAL CHARACTERISTICS”)
*3 : VIN1 ≥ VIN2
*4 : VIN1 startup rise time ≤ 1 ms is recommended
*5 : PFM mode at light load current with VO1/VIN1 ≤ 80% (IO1 ≤ 10 mA)
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
Parameter Symbol Condition Value Unit
Min Typ Max
Power supply voltage VIN1 VIN1 pin*1, *3, *4, *52.5 3.7 5.5 V
VIN2 VIN2 pin*2, *3
Input voltage
VFB FB pin ⎯0.30 ⎯V
VEN1 EN1 pin 0 ⎯5.5 V
VEN2 EN2 pin 0 ⎯5.5 V
Output voltage VO1 CH1 : Buck DC/DC*1, *50.8 ⎯4.5 V
Output current ILX LX pin DC ⎯⎯0.6 A
IVOUT2 VOUT2 pin DC ⎯⎯0.3 A
Operating ambient
temperature Ta ⎯ − 40 + 25 + 85 °C
MB39C022
DS04-27271-2E 9
■ELECTRICAL CHARACTERISTICS
(Ta = + 25 °C, VIN1 = VIN2 = 3.7 V)
(Continued)
Parameter Sym-
bol Pin No. Condition Value Unit
Min Typ Max
CH1
[ Buck
DC/DC ]
Threshold voltage VTH 6 FB pin − 2.5% 0.3 + 2.5% V
Input Bias current IFB 6 FB = 0 V − 100 0 + 100 nA
SW PMOS-Tr On
resistor RPON 8,9 ILX = − 100 mA ⎯0.35 ⎯Ω
SW NMOS-Tr On
resistor RNON 9,10 ILX = 100 mA ⎯0.25 ⎯Ω
Line regulation Vline1 ⎯VIN1 = 2.5 V to 5.5 V*1⎯10 ⎯mV
Load regulation Vload1 ⎯IO1 = 100 mA to 600 mA ⎯10 ⎯mV
Over current
protect ILIM1 9 VOUT1 × 0.9 0.9 1.2 1.5 A
CH2
[ LDO ]
Output voltage VO2 3
IO2 = 0 mA to − 300 mA
MB39C022G − 2.5% 3.30 + 2.5% V
IO2 = 0 mA to − 300 mA
MB39C022J − 2.5% 2.85 + 2.5% V
IO2 = 0 mA to − 300 mA
MB39C022L − 2.5% 1.80 + 2.5% V
IO2 = 0 mA to − 300 mA
MB39C022N − 2.5% 1.20 + 2.5% V
Line regulation Vline2 3 VIN2 = 2.5 V to 5.5 V*2⎯⎯10 mV
Load regulation Vload2 3 IO2 = 0 mA to − 300 mA ⎯⎯25 mV
Drop out voltage Vdrop 3 IO2 = − 300 mA,
VIN2 = VO2 :
MB39C022G, MB39C022J ⎯200 ⎯mV
Power supply
rejection ratio PSRR 3
MB39C022G*3f = 1 kHz ⎯70*4⎯dB
f = 10 kHz ⎯70*4⎯dB
MB39C022J*3f = 1 kHz ⎯65*4⎯dB
f = 10 kHz ⎯65*4⎯dB
MB39C022L*3f = 1 kHz ⎯60*4⎯dB
f = 10 kHz ⎯60*4⎯dB
MB39C022N*3f = 1 kHz ⎯55*4⎯dB
f = 10 kHz ⎯55*4⎯dB
Output noise
voltage Vnoise 3 f = 10 Hz to 100 kHz,
EN1 = 0 V ⎯55*4⎯μVrms
Over current
protect ILIM2 3 VO2 × 0.9 500 700 980 mA
Short circuit
protect ISCP2 3 VO2 = 0 V 150 350 700 mA
MB39C022
10 DS04-27271-2E
(Continued) (Ta = + 25 °C, VIN1 = VIN2 = 3.7 V)
*1 : The minimum VIN1 has to meet two conditions : VIN1 ≥ (VIN1 Min) and VIN1 ≥ VO1 + 0.5 V
*2 : The minimum VIN2 has to meet two conditions : VIN2 ≥ (VIN2 Min) and VIN2 ≥ VO2 + Vdrop (VO2 and Vdrop
values are specified in “■ ELECTRICAL CHARACTERISTICS”)
*3 : VIN2 = VO2 + 1 V, (MB39C022N: VIN2 = 2.5 V), IO2 = 100 mA
*4 : This value is not be specified. This should be used as a reference to support designing the circuits.
P arameter Symbol Pin No. Condition Value Unit
Min Typ Max
Power On
Reset
[ POR ]
Hold time Thold 4 fosc = 2 MHz 52.8 66 79.2 ms
Output voltage VPOR 4 POR = 250 μA⎯⎯0.1 V
Output current IPOR 4 POR = 5.5 V ⎯⎯ 1μA
Under Voltage
Lockout
Protection
Circuit Block
[ UVLO ]
Threshold
voltage VTHL 2, 8 VIN1 1.95 2.10 2.25 V
Hysteresis
width VH 2, 8 ⎯⎯0.20 ⎯V
Over
Temperature
Protection
Block
[ OTP ]
Stop
temperature TOTPH ⎯⎯⎯ + 135 ⎯ °C
Hysteresis
width TOTPHYS ⎯⎯⎯ + 25 ⎯ °C
Oscillator
Block
[ OSC ]
Output
frequency fosc 9 ⎯1.6 2.0 2.4 MHz
Control Block
[CTL ] Input voltage VIH 1, 7 EN1, EN2 ON 1.5 ⎯⎯V
VIL 1, 7 EN1, EN2 OFF ⎯⎯0.4 V
Input current IEN 1, 7 EN1, EN2 = 0 V − 100 0 + 100 nA
General
Shut down
power supply
current
ICC1 8 EN1, EN2 = 0 V ⎯01μA
ICC1 2 EN1, EN2 = 0 V ⎯01μA
Standby power
supply current
(DC/DC)
ICC2 8 EN1 = VIN1, EN2 = 0 V
IO1 = 0 mA, VFB = VIN1
⎯30 60
μA
ICC2 2 ⎯01
Standby power
supply current
(LDO)
ICC3 8 EN1 = 0 V, EN2 = VIN1
IO2 = 0 mA
⎯10 18
μA
ICC3 2 ⎯60 120
Power-on
invalid
current
ICC4 8 EN1, EN2 = VIN1,
VFB = 0.2 V
⎯0.9 1.5 mA
ICC4 2 ⎯60 120 μA
MB39C022
DS04-27271-2E 11
■TEST CIRCUIT FOR MEASURING TYPICAL OPERATING CHARACTERISTICS
* : The output voltage of VO1 can be adjusted by the external resistor divider R5.
Component Item Specification Remarks
C1 Ceramic capacitor 10 μF
C2 Ceramic capacitor 4.7 μF
C3 Ceramic capacitor 22 pF
C4 Ceramic capacitor 4.7 μF
C5 Ceramic capacitor 1 μF for MB39C022J, MB39C022L
4.7 μF for MB39C022G, MB39C022N
L1 Inductor 2.2 μH
R3 Resistor 1 MΩ
R5 Resistor 600 kΩat VO1 = 1.2 V*
R6 Resistor 200 kΩ
VO1 = Vref × (R5 + R6) = 0.3 V × (600 kΩ + 200 kΩ) = 1.2 V
R6 200 kΩ
EN2
VIN2
VOUT2
POR
GND2 FB
EN1
VIN1
LX
GND1
VO1
VIN
POR
EN2
EN1
C4
C5
C2
C1
L1
R6
R3 C3R5
VO2
MB39C022
12 DS04-27271-2E
■APPLICATION NOTES
[1] Selection of components
Selection of an external inductor for DC/DC
This IC is designed to operate well with a 2.2 μH inductor . Choosing larger values would lead to larger overshoot/
undershoot during load transient. Choosing a smaller value would lead to larger ripple voltage.
The inductor should be rated for a saturation current higher than the LX peak current value during normal
operating conditions, and should have a minimal DC resistance. (100 mΩ or less is recommended to improve
efficiency.)
LX peak current value IPK is obtained by the following formula.
L : External inductor value
IOUT : Load current (DC)
VIN : Power supply voltage
VOUT : Output setting voltage
D : ON- duty to be switched ( = VOUT/VIN)
fosc : Switching frequency (2.0 MHz)
ex) At VIN = 3.7 V, VOUT = 1.2 V, IOUT = 0.6 A, L = 2.2 μH, fosc = 2.0 MHz
The maximum peak current value IPK;
I/O capacitor selection
• DC/DC's output capacitor's finite equivalent ser ies resistance (ESR) causes ripple voltages on output equal
to the amount of current variation multiplied by the ESR value. The output capacitor value also has a significant
impact on the operating stability of the device when used as a DC/DC converter. Therefore, FUJITSU
MICROELECTR ONICS gener ally recommends C2 = 4.7 μF as DC/DC output capacitor, or a larger capacitor
value can be used if ripple voltages are not suitable.
• For DC/DC, select a low ESR for the VIN1/VIN2 input capacitor to suppress dissipation from ripple currents.
In addition, to reduce startup ov ershoot f or DC/DC and LDO, it is recommended that larger ceramic capacitor
be used for input capacitors C1 and C4. Recommended values are C1 = 10 μF, C4 = 4.7 μF.
• Types of capacitors
Ceramic capacitors are effective for reducing the ESR and afford smaller DC/DC conver ter circuit. However,
power supply functions as a heat gener ator , theref ore a void using capacitor with the F-temper ature rating
( − 80% to + 20%). FUJITSU MICROELECTRONICS recommends capacitors with the B-temperature rating
( ± 10% to ± 20%).
Normal electrolytic capacitors are not recommended due to their high ESR.
Tantalum capacitor will reduce ESR, however, it is dangerous to use because it tur ns into short mode when
damaged. If you insist on using a tantalum capacitor , FUJITSU MICR OELECTRONICS recommends the type
with an internal fuse.
IPK = IOUT +VIN − VOUT × D × 1 = IOUT + (VIN − VOUT) × VOUT
L fosc 2 2 × L × fosc × VIN
IPK = IOUT + (VIN − VOUT) × VOUT = 0.6 A + (3.7 V − 1.2 V) × 1.2 V = 0.69 A
2 × L × fosc × VIN 2 × 2.2 μH × 2 MHz × 3.7 V
MB39C022
DS04-27271-2E 13
[2] DC/DC Output voltage setting
The output v oltage VO1 of this IC is defined b y the e xternal resistive divider R5 & R6. Note that C3 is a capacitor
used for improving stability. Use a 22 pF cap for C3 should be suitable in all cases.
[3] Power On Reset (POR)
R3 and R4 are the pull-up resistors for POR (Pin 4). A 1 MΩ resistor is required to placed at either R3 or R4.
When R3 has a 1 MΩ resistor and R4 is open; the POR will be connected VIN. When R4 has a 1 MΩ resistor
and R3 is open; the POR pin will be connected to VO1.
By default, only R3 require a 1 MΩ resistor while R4 is open.
VO1 = Vref × R5 + R6 = 0.3 V × 600 kΩ + 200 kΩ = 1.2 V
R6 200 kΩ
R6
R5
VO1
6 FB
MB39C022
C3
-
+
Vref
(0.3 V)
MB39C022
14 DS04-27271-2E
[4] Power dissipation and heat considerations
The DC/DC is so efficient that no consideration is required in most cases. The LDO, on the other hand, would
be the dominant heat generator due to its inherent efficiency loss. Thus , if the IC is used at a high power supply
voltage, heavy load, and low LDO output voltage, or high temperature, it requires further consideration.
The internal loss (Pc) is roughly obtained from the following formula :
PC = PC1 + PC2 = IO12 × (RDC + D × RONP + (1 − D) × RONN) + IO2 × Vdrop
PC1 : DC/DC continuity loss
PC2 : LDO continuity loss
RDC : External inductor series resistance ( < 100 mΩ recommended)
D : Switching ON-duty cycle ( = VOUT / VIN)
RONP : Internal P-ch SW FET ON resistance
RONN : Internal N-ch SW FET ON resistance
IO1 : DC/DC Load current
IO2 : LDO Load current
Vdrop : LDO Dropout voltage
The loss e xpressed by the abov e f ormula is continuity loss . The internal loss includes the s witching loss and the
control circuit loss as well but they are so small compared to the continuity loss they can be ignored.
For PC1, consider the scenario with high temperature and heavy load (VIN = 3.7 V, VO1 = 1.2 V, IO1 = 0.6 A, Ta =
+ 70 °C). Here, RONP := 0.4 Ω and RONN := 0.3 Ω according to the graph “MOS FET ON resistance vs. Operating
ambient temperature”. PC1 = 156 mW.
Fo r P C2, consider the scenar io with low output vo ltage (MB39C022N), high temperature and heavy load
(VIN = 3.7 V, VO2 = 1.2 V, IO2 = 0.3 A, Ta = + 70 °C). Here, PC2 = 0.75 W. Note that PC2 >> PC1.
According to the graph “P ower dissipation vs. Operating ambient temperature”, the maximum permissible power
dissipation at an operating ambient temperature Ta of + 70 °C is 1.4 W. The internal loss is lower than the
maximum permissible power dissipation.
MB39C022
DS04-27271-2E 15
[5] Board layout, design example
Some basic design guidelines should be used when physically placing the MB39C022 on a Printed Circuit Board
(PCB).
• Regarding to GND pattern of PCB lay out of MB39C022, It needs to separate lik e AGND (analog ground) and
PGND (pow er ground). By separating g rounds, it is possib le to minimize the s witching frequency noise on the
LDO output.
• Arrange the input capacitor C1 and C4 as close as possible between VIN1 & PGND pins and VIN2 & AGND
pins. Make a through hole near the pins of this capacitor if the board has planes for power and GND.
• Large AC currents flow between this IC and the input capacitor (C1), output capacitor (C2), and external
inductor (L1). Group these components as close as possible to this IC to reduce the overall loop area occupied
by this group. Also try to mount these components on the same surface and arrange wir ing without through
hole wiring. Use thick, short, and straight routes to wire the net (The layout by planes is recommended.).
• The C1 and C2 capacitor returns are connected closely together at the PGND plane.
• The LDO input capacitor (C4) and LDO output capacitor (C5) are returned to the AGND plane.
• The analog ground plane and power ground plane are connected at one point.
• All other signals (EN1, EN2, FB) should be ref erenced to A GND and hav e the A GND plane underneath them.
• The feedback wiring to the VO1 and the VO1 pin should be wired closest to the output capacitor (C2). The
resistive divider and FB pin is extremely sensitive and should thus be k ept wired away from the LX pin of this
IC as far as possible.
• Try to make a GND plane on the surface to which this IC will be mounted. For efficient heat dissipation when
using the SON-10 package, FUJITSU MICROELECTRONICS recommends providing a thermal via in the
footprint of the thermal pad.
Layout Example of IC components
AGND
AGND
AGND
PGND
PGND
VIN2
VIN2
VIN2
VIN1
VIN1
VIN1
C4
C4
C4
C2
C2
C2
C1
C1
C1
R6
R6
R6
R5
R5
R5
L1
C5C5
C5
C5
VO2
VO2
VO1
PGND
Plane
AGND Plane
MB39C022
16 DS04-27271-2E
■EXAMPLE OF STANDARD OPERATION CHARACTERISTICS
(Shown below is an example of characteristics for connection according to “■ TEST CIRCUIT FOR MEASURING
TYPICAL OPERATING CHARACTERISTICS”.)
(1) DC/DC Conversion Efficiency
(2) DC/DC Load Regulation
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1
Load Current IO1 (A)
Conversion Efficiency η (%)
VIN = 3.7 V
VIN = 4.3 V
VIN = 5.5 V
CH1 Test Condition :
EN1 = VIN; EN2 = 0 V
VO1 = 1.2 V; C1 = 10 μF; C2 = 4.7 μF
1.1
1.12
1.14
1.16
1.18
1.2
1.22
1.24
1.26
1.28
1.3
0 0.2 0.4 0.6
Load Current IO1 (A)
Output Voltage VO1 (V)
VIN = 3.7 V
VIN = 4.3 V
VIN = 5.5 V
CH1 Test Condition :
EN1 = VIN; EN2 = 0 V
VO1 = 1.2 V; C1 = 10 μF; C2 = 4.7 μF
MB39C022
DS04-27271-2E 17
(3) DC/DC Line Regulation
(4) DC/DC Switching Waveform
1.1
1.12
1.14
1.16
1.18
1.2
1.22
1.24
1.26
1.28
1.3
3.2 3.7 4.2 4.7 5.2
Input V oltage VIN (V)
Output V oltage V O1 (V)
IO1 = 0 mA
IO1 = 300 mA
IO1 = 600 mA
CH1 Test Condition :
EN1 = VIN; EN2 = 0 V
VO1 = 1.2 V; C1 = 10 μF; C2 = 4.7 μF
500 ns/div
VLx
5 V/div
ILx
100 mA/div
VO1
20 mV/div
VO2
20 mV/div
CH1 Test Condition :
EN1 = EN2 = VIN = 3.7 V;
VO1 = 1.8 V; IO1 = 250 mA; C1 = 10 μF; C2 = 4.7 μF
VO2 = 3.3 V; IO2 = 150 mA; C4 = C5 = 4.7 μF
MB39C022
18 DS04-27271-2E
(5) LDO Load Regulation
(6) LDO Line Regulation
0
3.2
3.22
3.24
3.26
3.28
3.3
3.32
3.34
3.36
3.38
3.4
0.05 0.1 0.15 0.2 0.25 0.3
VIN = 3.7 V
VIN = 4.3 V
VIN = 5.5 V
MB39C022G CH2 Test Condition :
EN2 = VIN; EN1 = 0 V
VO2 = 3.3 V; C4 = C5 = 4.7 μF
Load Current IO2 (A)
Output Voltage VO2 (V)
3.4
3.38
3.36
3.34
3.32
3.3
3.28
3.26
3.24
3.22
3.2 3.6 4.1 4.6 5.1
IO2 = 0 mA
IO2 = 120 mA
IO2 = 300 mA
MB39C022G CH2 Test Condition :
EN2 = VIN; EN1 = 0 V
VO2 = 3.3 V; C4 = C5 = 4.7 μF
Input Voltage VIN (V)
Output Voltage VO2 (V)
MB39C022
DS04-27271-2E 19
(7) LDO Power Supply Rejection Ratio
(8) DC/DC Load Transient Waveforms
Frequency (Hz)
PSRR (dB)
10
VIN = 3.7 V
VIN = 4.3 V
100 1000 10000 100000 1000000
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
MB39C022G CH2 Test Condition :
EN2 = VIN = 3.7 V; EN1 = 0 V
VO2 = 3.3 V; IO2 = 100 mA; C1 = C4 = 0 μF
IO1 = 10 mA to 400 mA
IO2 = 150 mA
100 μs/div
T
IO1
500 mA/div
VO2
20 mV/div
VO1
100 mV/div
Test Condition :
VIN = EN1 = EN2 = 3.7 V; VO1 = 1.2 V; C1 = 10 μF; C2 = 4.7 μF; VO2 = 3.3 V; C4 = C5 = 4.7 μF
CH1 Load Transient Waveforms
MB39C022
20 DS04-27271-2E
(9) DC/DC Power MOS FET ON Resistance
0.6
P-ch
N-ch
0.5
0.4
0.3
0.2
0.1
0.0
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.6
0.5
0.4
0.3
0.2
0.1
0.0
2.0 3.0 4.0 5.0 6.0
-50 0 50 100
-50 0 50 100
V
IN
= 3.7 V
V
IN
= 5.5 V
V
IN
= 3.7 V
V
IN
= 5.5 V
Input voltage VIN (V) Operating Ambient Temperature Ta ( °C)
N-ch MOS FET ON Resistance vs.
Operating Ambient Temperature
Operating Ambient Temperature Ta ( °C)
MOS FET ON Resistance vs. Input Voltage P-ch MOS FET ON Resistance vs.
Operating Ambient Temperature
P-ch MOS FET ON Resistance RON (Ω)
MOS FET ON Resistance RON (Ω)
N-ch MOS FET ON Resistance RON (Ω)
MB39C022
DS04-27271-2E 21
3000
2500
2000
1500
1000
500
0-40 -20 0 20 40 60 80 100
2630
Permissible Power Dissipation vs. Operating Ambient Temperature
Operating Ambient Temperature Ta ( °C)
Power Dissipation PD (mW)
MB39C022
22 DS04-27271-2E
■APPLICATION CIRCUITS EXAMPLES
EXAMPLE 1 (VIN1 = VIN2)
VIN1 and VIN2 are connected together and POR is pulled up to VIN
EXAMPLE 2 (VIN2 = VO1)
• VIN2 is connected to VO1 and POR is pulled up to VIN
• It is possible to maximize LDO efficiency by connecting DC/DC Output to LDO supply.
• Maximum DC/DC output current ( = IO1) is limited by VIN2 input current ( := IO2)
EN2
VIN2
VOUT2
POR
GND2 FB
EN1
VIN1
LX
GND1
POR
EN2
EN1
C4
C5
C2
C1
L1
R5
R3 C3R6
VO1
IO1 ≤ 600 mA
VO2
IO2 ≤ 300 mA
(MB39C022)
VIN
EN2
VIN2
VOUT2
POR
GND2 FB
EN1
VIN1
LX
GND1
POR
EN2
EN1
C4
C5
C2
C1
L1
R5
R3 C3R6
VO1
IO1 ≤ 600 mA - IO2
VO2
IO2 ≤ 300 mA
(MB39C022)
VIN
MB39C022
DS04-27271-2E 23
EXAMPLE 3 (POR and RC delay channel control)
• EN1 is controlled by RC delay and EN2 is controlled by POR output.
• It is possible to control each channel without signal from MCU
EN2
VIN2
VOUT2
POR
GND2 FB
EN1
VIN1
LX
GND1
POR
C4
C5
C2
C1
L1
R6
R3
C3
VO1
IO1 ≤ 600 mA
VO2
IO2 ≤ 300 mA
(MB39C022)
R5
100 kΩ
1 μF
VIN
VIN
VO1
(1.2 V)
VO2
(1.8 V)
tatb
VUVLO
Vth(POR)
tc
td
Timing chart
Start up control
ta : RC delay time (28 ms at VIN = 3.7 V, R = 100 kΩ, C = 1 μF)
tb : POR hold time (66 ms fixed)
Power down control
tc, td : depend on internal discharge path and output loading
MB39C022
24 DS04-27271-2E
■USAGE PRECAUTIONS
1. Never use setting exceeding maximum rated conditions.
Semiconductor devices can be per manently damaged by application of stress (voltage, current, temperature,
etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
2. Use the devices within recommended conditions
It is recommended that devices be operated within recommended conditions.
Exceeding the recommended operating condition may adversely affect devices reliability.
Nominal electrical characteristics are warranted within the range of recommended operating conditions otherwise
specified on each parameter in the section of electrical characteristics.
3. Design the ground line on printed circuit boards with consideration of common impedance.
4. Take appropriate measures against static electricity.
The LX pin has less built-in ESD protection than other pins.
LX pin : 150 V (MM), 1500 V (HBM), Other pins : 200 V (MM), 2000 V (HBM)
Containers for semiconductor mater ials should have anti-static protection or be made of conductive material.
After mounting, printed circuit boards should be stored and shipped in conductive bags or containers.
Work platforms, tools, and instruments should be properly grounded.
Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ between body and ground.
5. Do not apply negative voltages
The use of negative voltages below − 0.3 V may activate parasitic transistors on the device, which can cause
abnormal operation.
MB39C022
DS04-27271-2E 25
■ORDERING INFORMATION
Part number Package Remarks
MB39C022GPN
10-pin plastic SON
(LCC-10P-M04)
MB39C022JPN
MB39C022LPN
MB39C022NPN
MB39C022
26 DS04-27271-2E
■RoHS COMPLIANCE INFORMATION OF LEAD(Pb) FREE VERSION
The LSI products of FUJITSU MICROELECTRONICS with “E1” are compliant with RoHS Directive, and has
observ ed the standard of lead, cadmium, mercury, chromium, polybrominated biphenyls (PBB), and polybromi-
nated diphenylethers (PBDE).
A product whose part number has trailing characters “E1” is RoHS compliant.
MB39C022
DS04-27271-2E 27
■PACKAGE DIMENSION
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
10-pin plastic SON Lead pitch 0.50 mm
Package width ×
package length 3.00 mm × 3.00 mm
Sealing method Plastic mold
Mounting height 0.75 mm MAX
Weight 0.018 g
10-pin plastic SON
(LCC-10P-M04)
(LCC-10P-M04)
C
2008 FUJITSU MICROELECTRONICS LIMITED C10004S-c-1-2
INDEX AREA
(.118±.004)
3.00±0.10
(.067±.004)
3.00±0.10
(.118±.004) 1.70±0.10
2.40±0.10
(.094±.004)
0.50(.020)
TYP
1PIN CORNER
(C0.30(C.012))
MAX
0.75(.030)
0.15(.006)
(.016±.004)
0.40±0.10
(.010±.001)
0.25±0.03
1 5
10 6
0.05(.002)
(.000 )
0.00 –0.00
+0.05
–.000
+.002
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB39C022
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,
Shinjuku-ku, Tokyo 163-0722, Japan
Tel: +81-3-5322-3329
http://jp.fujitsu.com/fml/en/
For further information please contact:
North and South America
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fmal.fujitsu.com/
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS
or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or
other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear
facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department
