Data Sheet R1EV5801MB Series 1M EEPROM (128-Kword x 8-bit)Ready/ Busy and RES function R10DS0209EJ0200 Rev.2.00 May 12, 2016 Description Renesas Electronics' R1EV5801MB is an electrically erasable and programmable ROM organized as 131072-word 8bit. It has realized high speed, low power consumption and high reliability by employing advanced MONOS memory technology and CMOS process and circuitry technology. It also has a 128-byte page programming function to make the write operations faster. Features Single voltage supply: 2.7 V to 5.5 V Access time: 150 ns (max) at Vcc=4.5 V to 5.5 V 250 ns (max) at Vcc=2.7 V to 5.5 V Power dissipation Active: 20 mW/MHz, (typ) Standby: 110 W (max) On-chip latches: address, data, CE, OE, WE Automatic byte write: 10 ms (max) Automatic page write (128 bytes): 10 ms (max) Data polling and RDY/Busy Data protection circuit on power on/off Conforms to JEDEC byte-wide standard Reliable CMOS with MONOS cell technology 104 or more erase/write cycles 10 or more years data retention Software data protection Write protection by RES pin Temperature range: 40 to +85C There are lead free products. R10DS0209EJ0200 Rev.2.00 May 12, 2016 Page 1 of 20 R1EV5801MB Series Ordering Information Orderable Part Name R1EV5801MBSDRDI#B0 R1EV5801MBTDRDI#B0 Access time Package 150ns/250ns 525mil 32-pin plastic SOP PRSP0032DC-A (FP-32DV) Shipping Container Quality Tube Max. 22 pcs/tube Max. 880 pcs/inner box 150ns/250ns 32-pin plastic TSOP Tray Max. 60 pcs/reel PTSA0032KD-A (TFP-32DAV) Max. 600 pcs/inner box Pin Arrangement R1EV5801MBSDR Series RDY/Busy A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 RES WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 R1EV5801MBTDR Series A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7 CE A10 OE 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A4 A5 A6 A7 A12 A14 A16 RDY/Busy VCC A15 RES WE A13 A8 A9 A11 (Top view) (Top view) Pin Description Pin name Function A0 to A16 Address input I/O0 to I/O7 Data input/output OE Output enable CE Chip enable WE Write enable VCC Power supply VSS Ground RDY/Busy Ready busy RES Reset R10DS0209EJ0200 Rev.2.00 May 12, 2016 Page 2 of 20 R1EV5801MB Series Block Diagram I/O0 to I/O7 V CC High voltage generator V SS RDY/Busy Voltage detector RES I/O buffer and input latch OE CE Control logic and timing WE RES A0 to Y decoder Y gating X decoder Memory array A6 Address buffer and latch A7 to A16 Data latch Operation Table Operation Read Standby Write Deselect Write Inhibit Data Polling Program reset CE OE WE RES RDY/Busy VIL VIH VIL VIL VIL VIL *2 VIH VIH VIL VIL VIH VIL VIH VIH VIH VH*1 VH VH VH VIL High-Z High-Z High-Z to VOL High-Z VOL High-Z I/O Dout High-Z Din High-Z Dout (I/O7) High-Z Notes: 1. Refer to the recommended DC operating conditions. 2. : Don't care Absolute Maximum Ratings Parameter Supply voltage relative to VSS Input voltage relative to VSS Operating temperature range*2 Storage temperature range Symbol Value Unit VCC Vin Topr Tstg 0.6 to +7.0 0.5*1 to +7.0 -40 to +85 -55 to +125 V V C C Notes: 1. Vin min = 3.0 V for pulse width 50 ns 2. Including electrical characteristics and data retention R10DS0209EJ0200 Rev.2.00 May 12, 2016 Page 3 of 20 R1EV5801MB Series Recommended DC Operating Conditions Parameter Supply voltage 3 Input voltage* Operating temperature Symbol Min Typ Max Unit VCC 2.7 3.0 5.5 V VSS 0 0 0 V 1 VIL 0.3* 0.8 V VIH 1.9*2 VCC + 0.3 V VH VCC 0.5 VCC + 1.0 V Topr -40 +85 C Notes: 1. VIL (min): 1.0 V for pulse width 50 ns 2. VIH (min): 2.2 V for VCC = 3.6 to 5.5 V 3. Refer to the recommended AC test condition during read and write operation. DC Characteristics (Ta = -40 to +85C, VCC = 2.7 V to 5.5 V) Parameter Input leakage current Output leakage current Standby VCC current Operating VCC current Output low voltage Output high voltage Symbol Min Typ Max Unit ILI ILO ICC1 ICC2 ICC3 2*1 2 20 1 15 A A A mA mA 6 50 15 VCC 0.8 0.4 VCC = 5.5 V, Vin =5.5 V VCC = 5.5 V, Vout = 5.5/0.4 V CE = VCC CE = VIH Iout = 0 mA, Duty = 100%, Cycle = 1 s, VCC = 5.5 V mA Iout = 0 mA, Duty = 100%, Cycle = 1 s, VCC = 3.3 V mA Iout = 0 mA, Duty = 100%, Cycle = 150 ns, VCC = 5.5 V mA Iout = 0 mA, Duty = 100%, Cycle = 250 ns, VCC = 3.3 V V IOL = 2.1 mA V IOH = 400 A Symbol Min Typ Max Unit Cin Cout 6 12 pF pF VOL VOH Test conditions Notes: 1. ILI on RES: 100 A (max) Capacitance (Ta = +25C, f = 1 MHz) Parameter 1 Input capacitance* Output capacitance*1 Note: Test conditions Vin = 0 V Vout = 0 V 1. This parameter is periodically sampled and not 100 tested. R10DS0209EJ0200 Rev.2.00 May 12, 2016 Page 4 of 20 R1EV5801MB Series AC Characteristics (Ta = -40 to +85C, VCC = 4.5 V to 5.5 V) Test Conditions Input pulse levels: 0.4 V to 2.4 V, 0 V to VCC (RES pin) Input rise and fall time: 20 ns Output load: 1TTL Gate +100 pF Reference levels for measuring timing: 0.8 V, 2.0 V Read Cycle Parameter Address to output delay CE to output delay OE to output delay Address to output hold OE (CE) high to output float*1 RES low to output float*1 RES to output delay Symbol Min Max Unit tACC tCE tOE tOH tDF tDFR tRR 10 0 0 0 0 150 150 75 50 350 450 ns ns ns ns ns ns ns Test conditions CE = OE = VIL, WE = VIH OE = VIL, WE = VIH CE = VIL, WE = VIH CE = OE = VIL, WE = VIH CE = VIL, WE = VIH CE = OE = VIL, WE = VIH CE = OE = VIL, WE = VIH Write Cycle Parameter Address setup time Address hold time CE to write setup time (WE controlled) CE hold time (WE controlled) WE to write setup time (CE controlled) WE hold time (CE controlled) OE to write setup time OE hold time Data setup time Data hold time WE pulse width (WE controlled) CE pulse width (CE controlled) Data latch time Byte load cycle Byte load window Write cycle time Time to device busy Write start time Reset protect time Reset high time*5 Symbol Min*2 Typ Max Unit tAS tAH tCS tCH tWS tWH tOES tOEH tDS tDH tWP tCW tDL tBLC tBL tWC tDB tDW tRP tRES 0 150 0 0 0 0 0 0 100 10 0.250 0.250 300 0.55 100 -- 120 150*4 100 1 30 30 30 10*3 ns ns ns ns ns ns ns ns ns ns s s ns s s ms ns ns s s Test conditions Notes: 1. tDF and tDFR are defined as the time at which the outputs achieve the open circuit conditions and are no longer driven. 2. Use this device in longer cycle than this value. 3. tWC must be longer than this value unless polling techniques or RDY/Busy are used. This device automatically completes the internal write operation within this value. 4. Next read or write operation can be initiated after tDW if polling techniques or RDY/Busy are used. 5. This parameter is sampled and not 100 tested. 6. A7 through A16 are page addresses and these addresses are latched at the first falling edge of WE. 7. A7 through A16 are page addresses and these addresses are latched at the first falling edge of CE. 8. See AC read characteristics. R10DS0209EJ0200 Rev.2.00 May 12, 2016 Page 5 of 20 R1EV5801MB Series AC Characteristics (Ta = -40 to +85C, VCC = 2.7 V to 5.5 V) Test Conditions Input pulse levels: 0.4 V to 2.4 V, 0 V to VCC (RES pin) Input rise and fall time: 20 ns Output load: 1TTL Gate +100 pF Reference levels for measuring timing: 0.8 V, 2.0 V Read Cycle Parameter Address to output delay CE to output delay OE to output delay Address to output hold OE (CE) high to output float*1 RES low to output float*1 RES to output delay Symbol Min Max Unit tACC tCE tOE tOH tDF tDFR tRR 10 0 0 0 0 250 250 120 50 350 600 ns ns ns ns ns ns ns Test conditions CE = OE = VIL, WE = VIH OE = VIL, WE = VIH CE = VIL, WE = VIH CE = OE = VIL, WE = VIH CE = VIL, WE = VIH CE = OE = VIL, WE = VIH CE = OE = VIL, WE = VIH Write Cycle Parameter Address setup time Address hold time CE to write setup time (WE controlled) CE hold time (WE controlled) WE to write setup time (CE controlled) WE hold time (CE controlled) OE to write setup time OE hold time Data setup time Data hold time WE pulse width (WE controlled) CE pulse width (CE controlled) Data latch time Byte load cycle Byte load window Write cycle time Time to device busy Write start time Reset protect time Reset high time*5 Symbol Min*2 Typ Max Unit tAS tAH tCS tCH tWS tWH tOES tOEH tDS tDH tWP tCW tDL tBLC tBL tWC tDB tDW tRP tRES 0 150 0 0 0 0 0 0 100 10 0.250 0.250 750 1.0 100 120 250*4 100 1 30 30 30 10*3 ns ns ns ns ns ns ns ns ns ns s s ns s s ms ns ns s s Test conditions Notes: 1. tDF and tDFR are defined as the time at which the outputs achieve the open circuit conditions and are no longer driven. 2. Use this device in longer cycle than this value. 3. tWC must be longer than this value unless polling techniques or RDY/Busy are used. This device automatically completes the internal write operation within this value. 4. Next read or write operation can be initiated after tDW if polling techniques or RDY/Busy are used. 5. This parameter is sampled and not 100 tested. 6. A7 through A16 are page addresses and these addresses are latched at the first falling edge of WE. 7. A7 through A16 are page addresses and these addresses are latched at the first falling edge of CE. 8. See AC read characteristics. R10DS0209EJ0200 Rev.2.00 May 12, 2016 Page 6 of 20 R1EV5801MB Series Timing Waveforms Read Timing Waveform Address tACC CE tOH tCE OE tDF tOE WE High Data Out Data out valid tRR tDFR RES R10DS0209EJ0200 Rev.2.00 May 12, 2016 Page 7 of 20 R1EV5801MB Series Byte Write Timing Waveform (1) (WE Controlled) tWC Address tCS tAH tCH CE tAS tBL tWP WE tOES tOEH OE tDS tDH Din tDW High-Z RDY/Busy tDB High-Z tRP tRES RES VCC R10DS0209EJ0200 Rev.2.00 May 12, 2016 Page 8 of 20 R1EV5801MB Series Byte Write Timing Waveform (2) (CE Controlled) Address tWS tAH tBL tWC tCW CE tAS tWH WE tOES tOEH OE tDS tDH Din tDW RDY/Busy tDB High-Z High-Z tRP tRES RES VCC R10DS0209EJ0200 Rev.2.00 May 12, 2016 Page 9 of 20 R1EV5801MB Series Page Write Timing Waveform (1) (WE Controlled) *6 Address A0 to A16 tAS tAH tBL tWP WE tDL tCS tBLC tWC tCH CE tOEH tOES tDH OE tDS Din RDY/Busy High-Z tDB tDW High-Z tRP RES tRES VCC R10DS0209EJ0200 Rev.2.00 May 12, 2016 Page 10 of 20 R1EV5801MB Series Page Write Timing Waveform (2) (CE Controlled) *6 Address A0 to A16 tAS CE tAH tBL tCW tDL tWS tBLC tWC tWH WE tOEH tOES OE tDH tDS Din RDY/Busy High-Z tDB tDW High-Z tRP RES tRES VCC R10DS0209EJ0200 Rev.2.00 May 12, 2016 Page 11 of 20 R1EV5801MB Series Data Polling Timing Waveform Address An An CE WE tOEH tCE *8 tOES OE tDW tOE *8 I/O7 Din X R10DS0209EJ0200 Rev.2.00 May 12, 2016 Dout X Dout X tWC Page 12 of 20 R1EV5801MB Series Toggle bit This device provide another function to determine the internal programming cycle. If the EEPROM is set to read mode during the internal programming cycle, I/O6 will charge from "1" to "0" (toggling) for each read. When the internal programming cycle is finished, toggling of I/O6 will stop and the device can be accessible for next read or program. Notes: 1. 2. 3. 4. I/O6 beginning state is "1". I/O6 ending state will vary. See AC read characteristics. Any location can be used, but the address must be fixed. Toggle bit Waveform Next mode *4 Address tCE *3 CE WE *3 tOE OE tOES tOEH *1 I/O6 Din Dout Dout tWC R10DS0209EJ0200 Rev.2.00 May 12, 2016 *2 *2 Dout Dout tDW Page 13 of 20 R1EV5801MB Series Software Data Protection Timing Waveform (1) (in protection mode) VCC CE WE tBLC Address 5555 Data AA 5555 AAAA or 2AAA 55 A0 tWC Write address Write data Software Data Protection Timing Waveform (2) (in non-protection mode) VCC tWC Normal active mode CE WE Address Data R10DS0209EJ0200 Rev.2.00 May 12, 2016 5555 AAAA or 2AAA 5555 5555 AAAA or 2AAA 5555 AA 55 80 AA 55 20 Page 14 of 20 R1EV5801MB Series Functional Description Automatic Page Write Page-mode write feature allows 1 to 128 bytes of data to be written into the EEPROM in a single write cycle. Following the initial byte cycle, an additional 1 to 127 bytes can be written in the same manner. Each additional byte load cycle must be started within 30 s from the preceding falling edge of WE or CE. When CE or WE is kept high for 100 s after data input, the EEPROM enters write mode automatically and the input data are written into the EEPROM. Data Polling Data polling allows the status of the EEPROM to be determined. If EEPROM is set to read mode during a write cycle, an inversion of the last byte of data to be loaded outputs from I/O7 to indicate that the EEPROM is performing a write operation. RDY/Busy Signal RDY/Busy signal also allows status of the EEPROM to be determined. The RDY/Busy signal has high impedance except in write cycle and is lowered to VOL after the first write signal. At the end of write cycle, the RDY/Busy signal changes state to high impedance. RES Signal When RES is low, the EEPROM cannot be read or programmed. Therefore, data can be protected by keeping RES low when VCC is switched. RES should be high during read and programming because it doesn't provide a latch function. VCC Read inhibit Read inhibit RES Program inhibit Program inhibit WE, CE Pin Operation During a write cycle, addresses are latched by the falling edge of WE or CE, and data is latched by the rising edge of WE or CE. Write/Erase Endurance and Data Retention Time The endurance is 104 cycles (1% cumulative failure rate). The data retention time is more than 10 years. R10DS0209EJ0200 Rev.2.00 May 12, 2016 Page 15 of 20 R1EV5801MB Series Data Protection To prevent this phenomenon, this device has a noise cancellation function that cuts noise if its width is 20 ns or less in program mode. 1. Data Protection against Noise on Control Pins (CE, OE, WE) during Operation During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to programming mode by mistake. Be careful not to allow noise of a width of more than 20 ns on the control pins. WE CE VIH 0V VIH OE 0V 20 ns max R10DS0209EJ0200 Rev.2.00 May 12, 2016 Page 16 of 20 R1EV5801MB Series 2. Data Protection at VCC On/Off When VCC is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may act as a trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional programming, the EEPROM must be kept in an unprogrammable state while the CPU is in an unstable state. Note: The EEPROM should be kept in unprogrammable state during VCC on/off by using CPU RESET signal. VCC CPU RESET * Unprogrammable * Unprogrammable 2.1 Protection by RES The unprogrammable state can be realized by that the CPU's reset signal inputs directly to the EEPROM's RES pin. RES should be kept VSS level during VCC on/off. The EEPROM brakes off programming operation when RES becomes low, programming operation doesn't finish correctly in case that RES falls low during programming operation. RES should be kept high for 10 ms after the last data input. VCC RES Program inhibit WE or CE R10DS0209EJ0200 Rev.2.00 May 12, 2016 1 s min 100 s min Program inhibit 10 ms min Page 17 of 20 R1EV5801MB Series 3. Software data protection To prevent unintentional programming, this device has the software data protection (SDP) mode. The SDP is enabled by inputting the following 3 bytes code and write data. SDP is not enabled if only the 3 bytes code is input. To program data in the SDP enable mode, 3 bytes code must be input before write data. Address Data 5555 AA AAAA or 2AAA 55 5555 A0 Write address Write data } Normal data input The SDP mode is disabled by inputting the following 6 bytes code. Note that, if data is input in the SDP disable cycle, data can not be written. Address Data 5555 AAAA or 2AAA 5555 5555 AAAA or 2AAA 5555 AA 55 80 AA 55 20 The software data protection is not enabled at the shipment. Note: There are some differences between Renesas Electronics' and other company's for enable/disable sequence of software data protection. If there are any questions , please contact with Rnesas Electronics' sales offices. R10DS0209EJ0200 Rev.2.00 May 12, 2016 Page 18 of 20 R1EV5801MB Series Orderable part Number Guide Orderable part Number Guide of Parallel EEPROM R1EV58 01MB SD Parallel EEPROM R D I #B0 Packaging, Environmental Memory density 064B : 64Kbit 256B : 256Kbit 01MB : 1Mbit #S0 : Embossed tape (Pb free) #B0 : Tray or Tube (Pb free) Quality grade I : -40 to +85 deg C (Industry) Package type DA : DiLP-28pin SC : SOP-28pin SD : SOP-32pin TC : TSOP-28pin TD : TSOP-32pin Access time B: D: 85/100/120ns 150ns/250ns Function R : Reset function suported N : Reset function not suported R10DS0209EJ0200 Rev.2.00 May 12, 2016 Page 19 of 20 R1EV5801MB Series Package Dimensions R1EV5801MBSD Series (PRSP0032DC-A / Previous code: FP-32DV) JEITA Package Code P-SOP32-11.3x20.45-1.27 RENESAS Code PRSP0032DC-A *1 Previous Code FP-32D/FP-32DV MASS[Typ.] 1.3g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. F D 32 17 bp Index mark Terminal cross section 1 16 *3 e Z bp x L1 M A1 A S L Detail F y S c c1 HE *2 E b1 Reference Symbol Dimension in Millimeters Min Nom D 20.45 E 11.30 A2 A1 0.05 0.15 A bp 0.32 0.40 b1 0.38 c 0.17 0.22 c1 0.20 0 HE 13.84 14.14 e 1.27 x y Z L 0.60 0.80 L1 1.42 Max 20.95 0.27 3.00 0.48 0.27 8 14.44 0.15 0.10 1.00 1.00 R1EV5801MBTD Series (PTSA0032KD-A / Previous Code: TFP-32DAV) JEITA Package Code P-TSOP(1)32-8x12.4-0.50 RENESAS Code PTSA0032KD-A Previous Code TFP-32DA/TFP-32DAV MASS[Typ.] 0.26g NOTE) 1. DIMENSION"*1"AND"*2(Nom)" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. HD A y S 32 *3 1 D x M *1 bp Index mark bp 17 Z 16 c c1 e *2 E b1 S Terminal cross section F A1 L1 L Detail F R10DS0209EJ0200 Rev.2.00 May 12, 2016 Reference Symbol D E A2 A1 A bp b1 c c1 HD e x y Z L L1 Dimension in Millimeters Min 0.08 0.14 Nom 12.40 8.00 0.13 Max 8.20 0.18 1.20 0.30 0.22 0.20 0.12 0.17 0.22 0.125 0 5 13.80 14.00 14.20 0.50 0.08 0.10 0.45 0.40 0.50 0.60 0.80 Page 20 of 20 Revision History R1EV5801MB Series Data Sheet Description Rev. 0.01 0.02 1.00 2.00 Date Oct 17, 2013 Oct 18, 2013 Jun 09, 2014 May 12, 2016 Page 19 -- 4 5 6 Summary Initial issue Orderable part Number Guide: Deletion of A and C for access time. Delete preliminary DC Operating Conditions: Addition of Note 3. AC Characteristics: Addition of Max. 30us for WE pulse width (tWP) AC Characteristics: Addition of Max. 30us for CE pulse width (tCW) AC Characteristics: Addition of Max. 30us for WE pulse width (tWP) AC Characteristics: Addition of Max. 30us for CE pulse width (tCW) All trademarks and registered trademarks are the property of their respective owners. C-1 Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. 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