GT24C64 GT24C64 2-WIRE 64K Bits Automotive Serial EEPROM Copyright (c) 2011 Giantec Semiconductor Inc. (Giantec). All rights reserved. Giantec reserves the right to make changes to this specification and its products at any time without notice. Giantec products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for critical medical or surgical equipment, aerospace or military, or other applications planned to support or sustain life. It is the customer's obligation to optimize the design in their own products for the best performance and optimization on the functionality and etc. Giantec assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and prior placing orders for products. Giantec Semiconductor, Inc. A0 www.giantec-semi.com 1/20 GT24C64 Table of Contents 1. Features ...................................................................................................................................................................... 3 2. General Description .............................................................................................................................................. 3 3. Functional Block Diagram ................................................................................................................................. 4 4. Pin Configuration.................................................................................................................................................... 5 4.1 8-Pin SOIC and TSSOP.......................................................................................................................... 5 4.2 8-Lead UDFN .......................................................................................................................................... 5 4.3 Pin Definition ........................................................................................................................................... 5 4.4 Pin Descriptions ...................................................................................................................................... 5 5. Device Operation .................................................................................................................................................... 6 5.1 2-WIRE Bus ............................................................................................................................................ 6 5.2 The Bus Protocol .................................................................................................................................... 6 5.3 Start Condition ........................................................................................................................................ 6 5.4 Stop Condition ......................................................................................................................................... 6 5.5 Acknowledge ........................................................................................................................................... 6 5.6 Reset ....................................................................................................................................................... 6 5.7 Standby Mode ......................................................................................................................................... 6 5.8 Device Addressing .................................................................................................................................. 6 5.9 Write Operation ....................................................................................................................................... 7 5.10 Read Operation ..................................................................................................................................... 7 5.11 Diagrams ............................................................................................................................................... 8 5.12 Timing Diagrams ..................................................................................................................................11 6. Electrical Characteristics ............................................................................................................................... 12 6.1 Absolute Maximum Ratings .................................................................................................................. 12 6.2 Operating Range ................................................................................................................................... 12 6.3 Reliability ............................................................................................................................................... 12 6.4 Capacitance .......................................................................................................................................... 12 6.5 DC Electrical Characteristic .................................................................................................................. 13 6.6 AC Electrical Characteristic .................................................................................................................. 14 7. Ordering Information .......................................................................................................................................... 15 8. Top Markings .......................................................................................................................................................... 16 8.1 SOIC package ....................................................................................................................................... 16 8.2 TSSOP package ................................................................................................................................... 16 8.3 UDFN package...................................................................................................................................... 16 9. Package Information .......................................................................................................................................... 17 9.1 SOIC ..................................................................................................................................................... 17 9.2 TSSOP .................................................................................................................................................. 18 9.3 UDFN .................................................................................................................................................... 19 10. Revision History ................................................................................................................................................. 20 Giantec Semiconductor, Inc. A0 www.giantec-semi.com 2/20 GT24C64 1. Features 2 Two-Wire Serial Interface, I C - TM Compatible - - Bi-directional data transfer protocol Wide-voltage Operation - Page write mode Partial page writes allowed Up to 32 bytes per page write V CC = 2.5V to 5.5V Self timed write cycle: 5 ms (max.) Speed: 1 MHz (2.5V~5.5V) Noise immunity on inputs, besides Schmitt trigger Standby current (max.): 2 A, 2.5V High-reliability Operating current (max.): 3 mA, 5.5V Hardware Data Protection - - - Endurance: 1 million cycles Data retention: 100 years Automotive grade Sequential & Random Read Features Packages: SOIC, TSSOP and UDFN Memory organization: 64Kb (8,192 x 8) Lead-free, RoHS, Halogen free, Green Page Size: 32 bytes Write Protect Pin 2. General Description The GT24C64 erasable series of data, if appropriate. The GT24C64 also has a programmable read only memory (EEPROM) device that Write Protect function via WP pin to cease from overwriting utilizes the data stored inside the memory array. the is a industrial standard standard electrically 2-wire interface for communications. The GT24C64 contains a memory array of In order to refrain the state machine from entering into a 64K bits (8,192x8), which is organized in 32-byte per page. wrong state during power-up sequence or a power toggle The EEPROM operates in a voltage range from 2.5V to off-on condition, a power on reset circuit is embedded. 5.5V, which fits most application. The product provides During power-up, the device does not respond to any low-power operations and low standby current. The device instructions until the supply voltage (V CC) has reached an is offered in Lead-free, RoHS, halogen free or Green acceptable stable level above the reset threshold voltage. package. The available package types are 8-pin SOIC, Once VCC passes the power on reset threshold, the device TSSOP and UDFN. is reset and enters into the Standby mode. This would also The GT24C64 is fully compatible to the industrial standard avoid any inadvertent Write operations during power-up 2-wire bus protocol. The simple bus consists of Serial Clock stage. During power-down process, the device will enter (SCL) and Serial Data (SDA) signals. Utilizing such bus into standby mode, once V CC drops below the power on protocol, a Master device, such as a microcontroller, can reset threshold voltage. In addition, the device will be in usually control one or more Slave devices, alike this standby mode after receiving the Stop command, provided GT24C64. The bit stream over the SDA line includes a that no internal write operation is in progress. Nevertheless, series of bytes, which identifies a particular Slave device, it is illegal to send a command unless the VCC is within its an instruction, an address within that Slave device, and a operating level. Giantec Semiconductor, Inc. A0 www.giantec-semi.com 3/20 GT24C64 3. Functional Block Diagram Giantec Semiconductor, Inc. A0 www.giantec-semi.com 4/20 GT24C64 4. Pin Configuration 4.1 8-Pin SOIC and TSSOP 4.2 8-Lead UDFN Top View Top View 4.3 Pin Definition Pin No. Pin Name I/O 1 A0 I Device Address Input Definition 2 A1 I Device Address Input 3 A2 I Device Address Input 4 GND - Ground 5 SDA I/O 6 SCL I Serial Clock Input 7 WP I Write Protect Input 8 V CC - Power Supply Serial Address and Data input and Data out put 4.4 Pin Descriptions SCL the inputs are defaulted to zero. This input clock pin is used to synchronize the data transfer WP to and from the device. WP is the Write Protect pin. While the WP pin is connected SDA to the power supply of GT24C64, the entire array becomes The SDA is a bi-directional pin used to transfer addresses Write Protected (i.e. the device becomes Read only). When and data into and out of the device. The SDA pin is an open WP is tied to Ground or left floating, the normal write drain output and can be wired with other open drain or open operations are allowed. collector outputs. However, the SDA pin requires a pull-up VCC resistor connected to the power supply. Supply voltage A0, A1, A2 GND The A0, A1 and A2 are the device address inputs. Ground of supply voltage Typically, the A0, A1, and A2 pins are for hardware addressing and a total of 8 devices can be connected on a single bus system. When A0, A1, and A2 are left floating, Giantec Semiconductor, Inc. A0 www.giantec-semi.com 5/20 GT24C64 5. Device Operation The GT24C64 serial interface supports communications 2 loss), or needs to be terminated mid-stream. The reset is using industrial standard 2-wire bus protocol, such as I C. initiated when the Master device creates a Start condition. 5.1 2-WIRE Bus To do this, it may be necessary for the Master device to The two-wire bus is defined as Serial Data (SDA), and monitor the SDA line while cycling the SCL up to nine times. Serial Clock (SCL). The protocol defines any device that (For each clock signal transition to High, the Master checks sends data onto the SDA bus as a transmitter, and the for a High level on SDA.) receiving devices as receivers. The bus is controlled by 5.7 Standby Mode Master device that generates the SCL, controls the bus While in standby mode, the power consumption is minimal. access, and generates the Start and Stop conditions. The The GT24C64 enters into standby mode during one of the GT24C64 is the Slave device. following conditions: a) After Power-up, while no Op-code is 5.2 The Bus Protocol sent; b) After the completion of an operation and followed Data transfer may be initiated only when the bus is not busy. by the Stop signal, provided that the previous operation is During a data transfer, the SDA line must remain stable not Write related; or c) After the completion of any internal whenever the SCL line is high. Any changes in the SDA line write operations. while the SCL line is high will be interpreted as a Start or 5.8 Device Addressing Stop condition. The Master begins a transmission on by sending a Start The state of the SDA line represents valid data after a Start condition, then sends the address of the particular Slave condition. The SDA line must be stable for the duration of devices to be communicated. The Slave device address is 8 the High period of the clock signal. The data on the SDA line bits format as shown in Figure. 5-5. may be changed during the Low period of the clock signal. The four most significant bits of the Slave address are fixed There is one clock pulse per bit of data. Each data transfer (1010) for GT24C64. is initiated with a Start condition and terminated by a Stop The next three bits, A0, A1 and A2, of the Slave address are condition. specifically related to EEPROM. Up to eight GT24C64 units 5.3 Start Condition can be connected to the 2-wire bus. The Start condition precedes all commands to the device The last bit of the Slave address specifies whether a Read and is defined as a High to Low transition of SDA when SCL or Write operation is to be performed. When this bit is set to is High. The EEPROM monitors the SDA and SCL lines and 1, Read operation is selected. While it is set to 0, Write will not respond until the Start condition is met. operation is selected. 5.4 Stop Condition After the Master transmits the Start condition and Slave The Stop condition is defined as a Low to High transition of address byte appropriately, the associated 2-wire Slave SDA when SCL is High. All operations must end with a Stop device, GT24C64, will respond with ACK on the SDA line. condition. Then GT24C64 will pull down the SDA on the ninth clock 5.5 Acknowledge cycle, signaling that it received the eight bits of data. After a successful data transfer, each receiving device is The GT24C64 then prepares for a Read or Write operation required to generate an ACK. The Acknowledging device by monitoring the bus. pulls down the SDA line. 5.6 Reset The GT24C64 contains a reset function in case the 2-wire bus transmission on is accidentally interrupted (e.g. a power Giantec Semiconductor, Inc. A0 www.giantec-semi.com 6/20 GT24C64 5.9 Write Operation 5.9.1 Byte Write In the Byte Write mode, the Master device sends the Start condition and the Slave address information (with the R/W set to Zero) to the Slave device. After the Slave generates an ACK, the Master sends the byte address that is to be condition followed by the Slave address for a Write operation. If the EEPROM is still busy with the Write operation, no ACK will be returned. If the GT24C64 has completed the Write operation, an ACK will be returned and the host can then proceed with the next Read or Write operation. written into the address pointer of the GT24C64. After 5.10 Read Operation receiving another ACK from the Slave, the Master device Read operations are initiated in the same manner as Write transmits the data byte to be written into the address operations, except that the (R/W) bit of the Slave address is memory location. The GT24C64 acknowledges once more and the Master generates the Stop condition, at which time set to "1". There are three Read operation options: current address read, random address read and sequential read. the device begins its internal programming cycle. While this 5.10.1 Current Address Read internal cycle is in progress, the device will not respond to The GT24C64 contains an internal address counter which any request from the Master device. maintains the 5.9.2 Page Write The GT24C64 is capable of 32-byte Page-Write operation. A Page-Write is initiated in the same manner as a Byte Write, but instead of terminating the internal Write cycle after the first data word is transferred, the Master device can transmit up to 31 more bytes. After the receipt of each data word, the EEPROM responds immediately with an ACK on SDA line, and the five lower order data word address bits are internally incremented by one, while the higher order bits of the data word address remain constant. If a byte address is incremented from the last byte of a page, it returns to the first byte of that page. If the Master device address of the last byte accessed, incremented by one. For example, if the previous operation is either a Read or Write operation addressed to the address location n, the internal address counter would increment to address location n+1. When the EEPROM receives the Slave Addressing Byte with a Read operation (R/W bit set to "1"), it will respond an ACK and transmit the 8-bit data byte stored at address location n+1. The Master should not acknowledge the transfer but should generate a Stop condition so the GT24C64 discontinues transmission. If 'n' is the last byte of the memory, the data from location '0' will be transmitted. (Refer to Figure 5-8. Current Address Read Diagram.) should transmit more than 32 bytes prior to issuing the Stop 5.10.2 Random Address Read condition, the address counter will "roll over," and the Selective Read operations allow the Master device to select previously written data will be overwritten. Once all 32 bytes at random any memory location for a Read operation. The are received and the Stop condition has been sent by the Master device first performs a 'dummy' Write operation by Master, the internal programming cycle begins. At this point, sending the Start condition, Slave address and byte all received data is written to the GT24C64 in a single Write address of the location it wishes to read. After the GT24C64 cycle. All inputs are disabled until completion of the internal acknowledges the byte address, the Master device resends Write cycle. the Start condition and the Slave address, this time with the 5.9.3 Acknowledge (ACK) Polling The disabling of the inputs can be used to take advantage of the typical Write cycle time. Once the Stop condition is issued to indicate the end of the host's Write operation, the R/W bit set to one. The EEPROM then responds with its ACK and sends the data requested. The Master device does not send an ACK but will generate a Stop condition. (Refer to Figure 5-9. Random Address Read Diagram.) GT24C64 initiates the internal Write cycle. ACK polling can 5.10.3 Sequential Read be initiated immediately. This involves issuing the Start Sequential Reads can be initiated as either a Current Giantec Semiconductor, Inc. A0 www.giantec-semi.com 7/20 GT24C64 Address Read or Random Address Read. After the with the data from address n followed by the data from GT24C64 sends the initial byte sequence, the Master address n+1,n+2 ... etc. The address counter increments by device now responds with an ACK indicating it requires one automatically, allow the entire memory contents to be additional data from the GT24C64. The EEPROM continues serially read during sequential Read operation. When the to output data for each ACK received. The Master device memory address boundary of the array is reached, the terminates the sequential Read operation by pulling SDA address counter "rolls over" to address 0, and the device High (no ACK) indicating the last data word to be read, continues to output data. (Refer to Figure 5-10. Sequential followed by a Stop condition. The data output is sequential, Read Diagram). 5.11 Diagrams Figure 5-1. Typical System Bus Configuration Figure 5-2. output Acknowledge Figure 5-3. Start and Stop Conditions Giantec Semiconductor, Inc. A0 www.giantec-semi.com 8/20 GT24C64 Figure 5-4. Data Validity Protocol Figure 5-5. Slave Address Figure 5-6. Byte Write Figure 5-7. Page Write Giantec Semiconductor, Inc. A0 www.giantec-semi.com 9/20 GT24C64 Figure 5-8. Current Address Read Figure 5-9. Random Address Read Figure 5-10. Sequential Read Giantec Semiconductor, Inc. A0 www.giantec-semi.com 10/20 GT24C64 5.12 Timing Diagrams Figure 5-11. Bus Timing Figure 5-12. Write Cycle Timing Giantec Semiconductor, Inc. A0 www.giantec-semi.com 11/20 GT24C64 6. Electrical Characteristics 6.1 Absolute Maximum Ratings Symbol Parameter Value Unit VS Supply Voltage -0.5 to + 6.5 V VP Voltage on Any Pin -0.5 to VCC + 0.5 V TBIAS Temperature Under Bias -55 to +125 C TSTG Storage Temperature -65 to +150 C IOUT Output Current 5 mA Note: Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 6.2 Operating Range Range Ambient Temperature (T A) VCC Automotive -40C to +125C 2.5V to 5.5V 6.3 Reliability Item Ambient Temperature (TA) Min. Max. Unit Ta=+25C 1 million - Cycle Ta=+85C 300k - Cycle Ta=+105C 100k - Cycle Reliability 6.4 Capacitance Symbol Parameter[1, 2] Conditions Max. Unit CIN Input Capacitance VIN = 0V 6 pF CI/O Input / Output Capacitance VI/O = 0V 8 pF Notes: [1] Tested initially and after any design or process changes that may affect these param eters and not 100% tested. [2] Test conditions: TA = 25C, f = 1 MHz, VCC = 5.0V. Giantec Semiconductor, Inc. A0 www.giantec-semi.com 12/20 GT24C64 6.5 DC Electrical Characteristic Automotive: TA = -40C to +125C, VCC = 2.5V ~ 5.5V Symbol Parameter Min. Max. Unit 2.5 5.5 V Input High Voltage 0.7*V CC V CC+1 V VIL Input Low Voltage -1 0.3* VCC V ILI Input Leakage Current 5V -- 2 A ILO Output Leakage Current 5V -- 2 A VOL Output Low Voltage 2.5V IOL = 2.1 mA -- 0.4 V ISB1 Standby Current 2.5V VIN = V CC or GND -- 2 A ISB2 Standby Current 5V VIN = V CC or GND -- 3 A ICC1 Read Current 2.5V Read at 1 MHz -- 1 mA 5.5V Read at 1 MHz -- 2 mA ICC2 Write Current 2.5V Write at 1 MHz -- 2 mA 3 End Endurance DR Data Retention V CC Supply Voltage VIH [1] VCC Test Conditions VIN = V CC max 5.5V Write at 1 MHz -- 5.5V 25C page mode 1M Cycle mA 25C 100 Years Note: The parameters are characterized but not 100% tested. Giantec Semiconductor, Inc. A0 www.giantec-semi.com 13/20 GT24C64 6.6 AC Electrical Characteristic Automotive: TA = -40C to +125C, Supply voltage = 2.5V to 5.5V Symbol Parameter [1] [2] 2.5VV CC<5.5V Min. FSCL SCK Clock Frequency TLOW Clock Low Period 600 THIGH Clock High Period Unit Max. 1000 KHz -- ns 400 -- ns TR Rise Time (SCL and SDA) -- 300 ns TF Fall Time (SCL and SDA) -- 100 ns TSU:STA Start Condition Setup Time 200 -- ns TSU:STO Stop Condition Setup Time 200 -- ns THD:STA Start Condition Hold Time 200 -- ns TSU:DAT Data In Setup Time 40 -- ns THD:DAT Data In Hold Time 0 -- ns TAA Clock to Output Access time (SCL Low to SDA Data Out Valid) 50 400 ns TDH Data Out Hold Time (SCL Low to SDA Data Out Change) 50 -- ns TWR Write Cycle Time -- 5 ms TBUF Bus Free Time Before New Transmission 400 -- ns TSU:WP WP pin Setup Time 400 -- ns THD:WP WP pin Hold Time 400 -- ns -- 50 ns T Notes: Noise Suppression Time [1] The parameters are characterized but not 100% tested. [2] AC measurem ent conditions: RL (connects to VCC): 1.3 k (2.5V, 5.0V) CL = 100 pF Input pulse voltages: 0.3*VCC to 0.7*VCC Input rise and fall times: 50 ns Timing reference voltages: half VCC level Giantec Semiconductor, Inc. A0 www.giantec-semi.com 14/20 GT24C64 7. Ordering Information Automotive Grade: -40C to +125C, Lead-free Voltage Range Part Number* Package (8-pin)* 2.5V to 5.5V GT24C64-3GLA1-TR 150-mil SOIC GT24C64-3ZLA1-TR 3 x 4.4 mm TSSOP GT24C64-3UDLA1-TR 2 x 3 x 0.55 mm UDFN * 1. Contact Giantec Sales Representatives for availability and other package information. 2. The product is packed in tape and reel "-TR" (4K per reel), except UDFN is 5K per reel. 3. Refer to Giantec website for related declaration document on lead free, RoHS, halogen free or Green, whichever is applicable. Giantec Semiconductor, Inc. A0 www.giantec-semi.com 15/20 GT24C64 8. Top Markings 8.1 SOIC package G: Giantec Logo 464-3GLA1: GT24C64-3GLA1-TR YWW: Date Code, Y=year, WW=week 8.2 TSSOP package GT: Giantec Logo 464-3ZLA1: GT24C64-3ZLA1-TR YWW: Date Code, Y=year, WW=week 8.3 UDFN package GT: Giantec Logo 46: GT24C64-3UDLA1-TR YWW: Date Code, Y=year, WW=week Giantec Semiconductor, Inc. A0 www.giantec-semi.com 16/20 GT24C64 9. Package Information 9.1 SOIC 8L 150mil SOIC Package Outline SYMBOLS DIMENSIONS IN MILLIMETERS NOM MAX MIN NOM MAX A 1.35 -- 1.75 0.053 -- 0.069 A1 0.10 -- 0.25 0.004 -- 0.010 b 0.33 -- 0.51 0.013 -- 0.020 D 4.80 -- 5.00 0.189 -- 0.197 E 5.80 -- 6.20 0.228 -- 0.244 E1 3.80 -- 4.00 0.150 -- 0.157 e L 1.27 BSC. 0.38 L1 -- 0.050 BSC. 1.27 0.015 0.25 BSC. ZD -- 0.050 0.010 BSC. 0.545 REF. 0 Giantec Semiconductor, Inc. A0 DIMENSIONS IN INCHES MIN 0.021 REF. 8 0 -- 8 www.giantec-semi.com 17/20 GT24C64 9.2 TSSOP 8L 3x4.4mm TSSOP Package Outline D C e 8 L E E1 1 12(4X) A2 0.10mm b A1 A SYMBOLS A A1 A2 b c D E E1 e L DIMENSIONS IN MILLIMETERS MIN -0.05 0.80 0.19 0.09 2.90 4.30 0.45 0 Giantec Semiconductor, Inc. A0 Note: 1. Controlling Dimension:MM 2. Dimension D and E do not include Mold protrusion 3. Dimension b does not include dambar protrusion/intrusion. 4. Refer to Jedec standard MO-153 AA 5. Drawing is not to scale 6. Package may have exposed tie bar. NOM --1.00 --3.00 4.40 6.4 BSC 0.65 BSC 0.60 -- DIMENSIONS IN INCHES MAX 1.20 0.15 1.05 0.30 0.20 3.10 4.50 MIN -0.002 0.031 0.007 0.004 0.114 0.169 0.75 8 0.018 0 NOM --0.039 --0.118 0.173 0.252 BSC 0.026 BSC 0.024 -- MAX 0.047 0.006 0.041 0.012 0.008 0.122 0.177 0.030 8 www.giantec-semi.com 18/20 GT24C64 9.3 UDFN 8L 2x3mm UDFN Package Outline D2 D e K E2 E PIN#1 IDENTIFICATION CHAMFER L b PIN#1 DOT BY MARKING BOTTOM VIEW TOP VIEW A A1 A2 SIDE VIEW SYMBOLS DIMENSIONS IN MILLIMETERS A A1 b A2 D D2 E E2 e K L MIN 0.50 0.00 0.18 1.25 1.15 0.40 0.20 NOM 0.55 -0.25 0.152 REF 2.00 BSC 1.40 3.00 BSC 1.30 0.50 BSC. -0.30 DIMENSIONS IN INCHES MAX 0.60 0.05 0.30 MIN 0.020 0.000 0.007 1.50 0.049 1.40 0.045 -0.40 0.016 0.008 NOM 0.022 -0.010 0.006 REF 0.079 BSC 0.055 0.118 BSC 0.051 0.020 BSC. -0.012 MAX 0.024 0.002 0.012 0.059 0.055 -0.016 Note: 1. Controlling Dimension:MM 2. Drawing is not to scale Giantec Semiconductor, Inc. A0 www.giantec-semi.com 19/20 GT24C64 10. Revision History Revision Date Descriptions A0 April. 2013 Initial version Giantec Semiconductor, Inc. A0 www.giantec-semi.com 20/20