GT24C64
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GT24C64
2-WIRE 64K Bits
Automotive
Serial EEPROM
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Table of Contents
1. Features ...................................................................................................................................................................... 3
2. General Description .............................................................................................................................................. 3
3. Functional Block Diagram ................................................................................................................................. 4
4. Pin Configuration .................................................................................................................................................... 5
4.1 8-Pin SOIC and TSSOP.......................................................................................................................... 5
4.2 8-Lead UDFN .......................................................................................................................................... 5
4.3 Pin Definition ........................................................................................................................................... 5
4.4 Pin Descriptions ...................................................................................................................................... 5
5. Device Operation .................................................................................................................................................... 6
5.1 2-WIRE Bus ............................................................................................................................................ 6
5.2 The Bus Protocol .................................................................................................................................... 6
5.3 Start Condition ........................................................................................................................................ 6
5.4 Stop Condition ......................................................................................................................................... 6
5.5 Acknowledge ........................................................................................................................................... 6
5.6 Reset ....................................................................................................................................................... 6
5.7 Standby Mode ......................................................................................................................................... 6
5.8 Device Addressing .................................................................................................................................. 6
5.9 Write Operation ....................................................................................................................................... 7
5.10 Read Operation ..................................................................................................................................... 7
5.11 Diagrams ............................................................................................................................................... 8
5.12 Timing Diagrams ..................................................................................................................................11
6. Electrical Characteristics ............................................................................................................................... 12
6.1 Absolute Maximum Ratings .................................................................................................................. 12
6.2 Operating Range ................................................................................................................................... 12
6.3 Reliability ............................................................................................................................................... 12
6.4 Capacitance .......................................................................................................................................... 12
6.5 DC Electrical Characteristic .................................................................................................................. 13
6.6 AC Electrical Characteristic .................................................................................................................. 14
7. Ordering Information .......................................................................................................................................... 15
8. Top Markings .......................................................................................................................................................... 16
8.1 SOIC package ....................................................................................................................................... 16
8.2 TSSOP package ................................................................................................................................... 16
8.3 UDFN package...................................................................................................................................... 16
9. Package Information .......................................................................................................................................... 17
9.1 SOIC ..................................................................................................................................................... 17
9.2 TSSOP .................................................................................................................................................. 18
9.3 UDFN .................................................................................................................................................... 19
10. Revision History ................................................................................................................................................. 20
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1. Features
Two-Wire Serial Interface, I2CTM Compatible
– Bi-directional data transfer protocol
Wide-voltage Operation
– VCC = 2.5V to 5.5V
Speed: 1 MHz (2.5V~5.5V)
Standby current (max.): 2 A, 2.5V
Operating current (max.): 3 mA, 5.5V
Hardware Data Protection
– Write Protect Pin
Sequential & Random Read Features
Memory organization: 64Kb (8,192 x 8)
Page Size: 32 bytes
Page write mode
– Partial page writes allowed
– Up to 32 bytes per page write
Self timed write cycle: 5 ms (max.)
Noise immunity on inputs, besides Schmitt trigger
High-reliability
– Endurance: 1 million cycles
– Data retention: 100 years
Automotive grade
Packages: SOIC, TSSOP and UDFN
Lead-free, RoHS, Halogen free, Green
2. General Description
The GT24C64 is a standard electrically erasable
programmable read only memory (EEPROM) device that
utilizes the industrial standard 2-wire interface for
communications. The GT24C64 contains a memory array of
64K bits (8,192x8), which is organized in 32-byte per page.
The EEPROM operates in a voltage range from 2.5V to
5.5V, which fits most application. The product provides
low-power operations and low standby current. The device
is offered in Lead-free, RoHS, halogen free or Green
package. The available package types are 8-pin SOIC,
TSSOP and UDFN.
The GT24C64 is fully compatible to the industrial standard
2-wire bus protocol. The simple bus consists of Serial Clock
(SCL) and Serial Data (SDA) signals. Utilizing such bus
protocol, a Master device, such as a microcontroller, can
usually control one or more Slave devices, alike this
GT24C64. The bit stream over the SDA line includes a
series of bytes, which identifies a particular Slave device,
an instruction, an address within that Slave device, and a
series of data, if appropriate. The GT24C64 also has a
Write Protect function via WP pin to cease from overwriting
the data stored inside the memory array.
In order to refrain the state machine from entering into a
wrong state during power-up sequence or a power toggle
off-on condition, a power on reset circuit is embedded.
During power-up, the device does not respond to any
instructions until the supply voltage (VCC) has reached an
acceptable stable level above the reset threshold voltage.
Once VCC passes the power on reset threshold, the device
is reset and enters into the Standby mode. This would also
avoid any inadvertent Write operations during power-up
stage. During power-down process, the device will enter
into standby mode, once VCC drops below the power on
reset threshold voltage. In addition, the device will be in
standby mode after receiving the Stop command, provided
that no internal write operation is in progress. Nevertheless,
it is illegal to send a command unless the VCC is within its
operating level.
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3. Functional Block Diagram
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4. Pin Configuration
4.1 8-Pin SOIC and TSSOP
Top View
4.2 8-Lead UDFN
Top View
4.3 Pin Definition
Pin No. Pin Name I/O Definition
1 A0 I Device Address Input
2 A1 I Device Address Input
3 A2 I Device Address Input
4 GND - Ground
5 SDA I/O Serial Address and Data input and Data out put
6 SCL I Serial Clock Input
7 WP I Write Protect Input
8 VCC - Power Supply
4.4 Pin Descriptions
SCL
This input clock pin is used to synchronize the data transfer
to and from the device.
SDA
The SDA is a bi-directional pin used to transfer addresses
and data into and out of the device. The SDA pin is an open
drain output and can be wired with other open drain or open
collector outputs. However, the SDA pin requires a pull-up
resistor connected to the power supply.
A0, A1, A2
The A0, A1 and A2 are the device address inputs.
Typically, the A0, A1, and A2 pins are for hardware
addressing and a total of 8 devices can be connected on a
single bus system. When A0, A1, and A2 are left floating,
the inputs are defaulted to zero.
WP
WP is the Write Protect pin. While the WP pin is connected
to the power supply of GT24C64, the entire array becomes
Write Protected (i.e. the device becomes Read only). When
WP is tied to Ground or left floating, the normal write
operations are allowed.
VCC
Supply voltage
GND
Ground of supply voltage
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5. Device Operation
The GT24C64 serial interface supports communications
using industrial standard 2-wire bus protocol, such as I2C.
5.1 2-WIRE Bus
The two-wire bus is defined as Serial Data (SDA), and
Serial Clock (SCL). The protocol defines any device that
sends data onto the SDA bus as a transmitter, and the
receiving devices as receivers. The bus is controlled by
Master device that generates the SCL, controls the bus
access, and generates the Start and Stop conditions. The
GT24C64 is the Slave device.
5.2 The Bus Protocol
Data transfer may be initiated only when the bus is not busy.
During a data transfer, the SDA line must remain stable
whenever the SCL line is high. Any changes in the SDA line
while the SCL line is high will be interpreted as a Start or
Stop condition.
The state of the SDA line represents valid data after a Start
condition. The SDA line must be stable for the duration of
the High period of the clock signal. The data on the SDA line
may be changed during the Low period of the clock signal.
There is one clock pulse per bit of data. Each data transfer
is initiated with a Start condition and terminated by a Stop
condition.
5.3 Start Condition
The Start condition precedes all commands to the device
and is defined as a High to Low transition of SDA when SCL
is High. The EEPROM monitors the SDA and SCL lines and
will not respond until the Start condition is met.
5.4 Stop Condition
The Stop condition is defined as a Low to High transition of
SDA when SCL is High. All operations must end with a Stop
condition.
5.5 Acknowledge
After a successful data transfer, each receiving device is
required to generate an ACK. The Acknowledging device
pulls down the SDA line.
5.6 Reset
The GT24C64 contains a reset function in case the 2-wire
bus transmission on is accidentally interrupted (e.g. a power
loss), or needs to be terminated mid-stream. The reset is
initiated when the Master device creates a Start condition.
To do this, it may be necessary for the Master device to
monitor the SDA line while cycling the SCL up to nine times.
(For each clock signal transition to High, the Master checks
for a High level on SDA.)
5.7 Standby Mode
While in standby mode, the power consumption is minimal.
The GT24C64 enters into standby mode during one of the
following conditions: a) After Power-up, while no Op-code is
sent; b) After the completion of an operation and followed
by the Stop signal, provided that the previous operation is
not Write related; or c) After the completion of any internal
write operations.
5.8 Device Addressing
The Master begins a transmission on by sending a Start
condition, then sends the address of the particular Slave
devices to be communicated. The Slave device address is 8
bits format as shown in Figure. 5-5.
The four most significant bits of the Slave address are fixed
(1010) for GT24C64.
The next three bits, A0, A1 and A2, of the Slave address are
specifically related to EEPROM. Up to eight GT24C64 units
can be connected to the 2-wire bus.
The last bit of the Slave address specifies whether a Read
or Write operation is to be performed. When this bit is set to
1, Read operation is selected. While it is set to 0, Write
operation is selected.
After the Master transmits the Start condition and Slave
address byte appropriately, the associated 2-wire Slave
device, GT24C64, will respond with ACK on the SDA line.
Then GT24C64 will pull down the SDA on the ninth clock
cycle, signaling that it received the eight bits of data.
The GT24C64 then prepares for a Read or Write operation
by monitoring the bus.
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5.9 Write Operation
5.9.1 Byte Write
In the Byte Write mode, the Master device sends the Start
condition and the Slave address information (with the R/W
set to Zero) to the Slave device. After the Slave generates
an ACK, the Master sends the byte address that is to be
written into the address pointer of the GT24C64. After
receiving another ACK from the Slave, the Master device
transmits the data byte to be written into the address
memory location. The GT24C64 acknowledges once more
and the Master generates the Stop condition, at which time
the device begins its internal programming cycle. While this
internal cycle is in progress, the device will not respond to
any request from the Master device.
5.9.2 Page Write
The GT24C64 is capable of 32-byte Page-Write operation.
A Page-Write is initiated in the same manner as a Byte
Write, but instead of terminating the internal Write cycle
after the first data word is transferred, the Master device
can transmit up to 31 more bytes. After the receipt of each
data word, the EEPROM responds immediately with an
ACK on SDA line, and the five lower order data word
address bits are internally incremented by one, while the
higher order bits of the data word address remain constant.
If a byte address is incremented from the last byte of a page,
it returns to the first byte of that page. If the Master device
should transmit more than 32 bytes prior to issuing the Stop
condition, the address counter will “roll over,” and the
previously written data will be overwritten. Once all 32 bytes
are received and the Stop condition has been sent by the
Master, the internal programming cycle begins. At this point,
all received data is written to the GT24C64 in a single Write
cycle. All inputs are disabled until completion of the internal
Write cycle.
5.9.3 Acknowledge (ACK) Polling
The disabling of the inputs can be used to take advantage
of the typical Write cycle time. Once the Stop condition is
issued to indicate the end of the host's Write operation, the
GT24C64 initiates the internal Write cycle. ACK polling can
be initiated immediately. This involves issuing the Start
condition followed by the Slave address for a Write
operation. If the EEPROM is still busy with the Write
operation, no ACK will be returned. If the GT24C64 has
completed the Write operation, an ACK will be returned and
the host can then proceed with the next Read or Write
operation.
5.10 Read Operation
Read operations are initiated in the same manner as Write
operations, except that the (R/W) bit of the Slave address is
set to “1”. There are three Read operation options: current
address read, random address read and sequential read.
5.10.1 Current Address Read
The GT24C64 contains an internal address counter which
maintains the address of the last byte accessed,
incremented by one. For example, if the previous operation
is either a Read or Write operation addressed to the
address location n, the internal address counter would
increment to address location n+1. When the EEPROM
receives the Slave Addressing Byte with a Read operation
(R/W bit set to “1”), it will respond an ACK and transmit the
8-bit data byte stored at address location n+1. The Master
should not acknowledge the transfer but should generate a
Stop condition so the GT24C64 discontinues transmission.
If 'n' is the last byte of the memory, the data from location '0'
will be transmitted. (Refer to Figure 5-8. Current Address
Read Diagram.)
5.10.2 Random Address Read
Selective Read operations allow the Master device to select
at random any memory location for a Read operation. The
Master device first performs a 'dummy' Write operation by
sending the Start condition, Slave address and byte
address of the location it wishes to read. After the GT24C64
acknowledges the byte address, the Master device resends
the Start condition and the Slave address, this time with the
R/W bit set to one. The EEPROM then responds with its
ACK and sends the data requested. The Master device
does not send an ACK but will generate a Stop condition.
(Refer to Figure 5-9. Random Address Read Diagram.)
5.10.3 Sequential Read
Sequential Reads can be initiated as either a Current
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Address Read or Random Address Read. After the
GT24C64 sends the initial byte sequence, the Master
device now responds with an ACK indicating it requires
additional data from the GT24C64. The EEPROM continues
to output data for each ACK received. The Master device
terminates the sequential Read operation by pulling SDA
High (no ACK) indicating the last data word to be read,
followed by a Stop condition. The data output is sequential,
with the data from address n followed by the data from
address n+1,n+2 ... etc. The address counter increments by
one automatically, allow the entire memory contents to be
serially read during sequential Read operation. When the
memory address boundary of the array is reached, the
address counter “rolls over” to address 0, and the device
continues to output data. (Refer to Figure 5-10. Sequential
Read Diagram).
5.11 Diagrams
Figure 5-1. Typical System Bus Configuration
Figure 5-2. output Acknowledge
Figure 5-3. Start and Stop Conditions
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Figure 5-4. Data Validity Protocol
Figure 5-5. Slave Address
Figure 5-6. Byte Write
Figure 5-7. Page Write
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Figure 5-8. Current Address Read
Figure 5-9. Random Address Read
Figure 5-10. Sequential Read
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5.12 Timing Diagrams
Figure 5-11. Bus Timing
Figure 5-12. Write Cycle Timing
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6. Electrical Characteristics
6.1 Absolute Maximum Ratings
Symbol Parameter Value Unit
VS Supply Voltage -0.5 to + 6.5 V
VP Voltage on Any Pin –0.5 to VCC + 0.5 V
TBIAS Temperature Under Bias –55 to +125 °C
TSTG Storage Temperature –65 to +150 °C
IOUT Output Current 5 mA
Note: Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other condition outside those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
6.2 Operating Range
Range Ambient Temperature (TA) VCC
Automotive –40°C to +125°C 2.5V to 5.5V
6.3 Reliability
Item Ambient Temperature (TA) Min. Max. Unit
Reliability
Ta=+25°C 1 million - Cycle
Ta=+85°C 300k - Cycle
Ta=+105°C 100k - Cycle
6.4 Capacitance
Symbol Parameter[1, 2] Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
CI/O Input / Output Capacitance VI/O = 0V 8 pF
Notes: [1] Tested initially and after any design or process changes that may affect these param eters and not 100% tested.
[2] Test conditions: TA = 25°C, f = 1 MHz, VCC = 5.0V.
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6.5 DC Electrical Characteristic
Automotive: TA = –40°C to +125°C, VCC = 2.5V ~ 5.5V
Symbol Parameter [1] VCC Test Conditions Min. Max. Unit
VCC Supply Voltage 2.5 5.5 V
VIH Input High Voltage 0.7*VCC VCC+1 V
VIL Input Low Voltage -1 0.3* VCC V
ILI Input Leakage Current 5 V VIN = VCC max — 2 μA
ILO Output Leakage Current 5V — 2 μA
VOL Output Low Voltage 2.5V IOL = 2.1 mA — 0.4 V
ISB1 Standby Current 2.5V VIN = VCC or GND — 2 μA
ISB2 Standby Current 5V VIN = VCC or GND — 3 μA
ICC1 Read Current 2.5V Read at 1 MHz — 1 mA
5.5V Read at 1 MHz — 2 mA
ICC2 Write Current 2.5V Write at 1 MHz — 2 mA
5.5V Write at 1 MHz — 3 mA
End Endurance 5.5V 25ºC page mode 1M Cycle
DR Data Retention 25ºC 100 Years
Note: The parameters are characterized but not 100% tested.
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6.6 AC Electrical Characteristic
Automotive: TA = –40°C to +125°C, Supply voltage = 2.5V to 5.5V
Symbol Parameter [1] [2] 2.5VVCC<5.5V Unit
Min. Max.
FSCL SCK Clock Frequency 1000 KHz
TLOW Clock Low Period 600 — ns
THIGH Clock High Period 400 — ns
TR Rise Time (SCL and SDA) — 300 ns
TF Fall Time (SCL and SDA) — 100 ns
TSU:STA Start Condition Setup Time 200 — ns
TSU:STO Stop Condition Setup Time 200 — ns
THD:STA Start Condition Hold Time 200 — ns
TSU:DAT Data In Setup Time 40 — ns
THD:DAT Data In Hold Time 0 — ns
TAA Clock to Output Access time (SCL Low to SDA Data Out Valid)
50 400 ns
TDH Data Out Hold Time (SCL Low to SDA Data Out Change) 50 — ns
TWR Write Cycle Time — 5 ms
TBUF Bus Free Time Before New Transmission 400 — ns
TSU:WP WP pin Setup Time 400 — ns
THD:WP WP pin Hold Time 400 — ns
T Noise Suppression Time — 50 ns
Notes: [1] The parameters are characterized but not 100% tested.
[2] AC measurem ent conditions:
RL (connects to VCC): 1.3 kΩ (2.5V, 5.0V)
CL = 100 pF
Input pulse voltages: 0.3*VCC to 0.7*VCC
Input rise and fall times: ≤ 50 ns
Timing reference voltages: half VCC level
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7. Ordering Information
Automotive Grade: -40°C to +125°C, Lead-free
Voltage Range Part Number* Package (8-pin)*
2.5V to 5.5V GT24C64-3GLA1-TR 150-mil SOIC
GT24C64-3ZLA1-TR 3 x 4.4 mm TSSOP
GT24C64-3UDLA1-TR 2 x 3 x 0.55 mm UDFN
*
1. Contact Giantec Sales Representatives for availability and other package information.
2. The product is packed in tape and reel “-TR” (4K per reel), except UDFN is 5K per reel.
3. Refer to Giantec website for related declaration document on lead free, RoHS, halogen free or Green, whichever is applicable.
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8. Top Markings
8.1 SOIC package
G: Giantec Logo
464-3GLA1: GT24C64-3GLA1-TR
YWW: Date Code, Y=year, WW=week
8.2 TSSOP package
GT: Giantec Logo
464-3ZLA1: GT24C64-3ZLA1-TR
YWW: Date Code, Y=year, WW=week
8.3 UDFN package
GT: Giantec Logo
46: GT24C64-3UDLA1-TR
YWW: Date Code, Y=year, WW=week
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9. Package Information
9.1 SOIC
8L 150mil SOIC Package Outline
MIN NOM MAX MIN NOM MAX
A 1.35 -- 1.75 0.053 -- 0.069
A1 0.10 -- 0.25 0.004 -- 0.010
b 0.33 -- 0.51 0.013 -- 0.020
D 4.80 -- 5.00 0.189 -- 0.197
E 5.80 -- 6.20 0.228 -- 0.244
E1 3.80 -- 4.00 0.150 -- 0.157
e
L 0.38 -- 1.27 0.015 0.050
L1
ZD
Θ 0 -- 8°0 -- 8°
0.545 REF.
0.050 BSC.
0.010 BSC.
0.021 REF.
SYMBOLS DIMENSIONS IN MILLIMETERS DIMENSIONS IN INCHES
1.27 BSC.
0.25 BSC.
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9.2 TSSOP
8L 3x4.4mm TSSOP Package Outline
A2
A1
b
MIN NOM MAX MIN NOM MAX
A -- -- 1.20 -- -- 0.047
A1 0.05 -- 0.15 0.002 -- 0.006
A2 0.80 1.00 1.05 0.031 0.039 0.041
b 0.19 -- 0.30 0.007 -- 0.012
c 0.09 -- 0.20 0.004 -- 0.008
D 2.90 3.00 3.10 0.114 0.118 0.122
E 4.30 4.40 4.50 0.169 0.173 0.177
E1
e
L 0.45 0.60 0.75 0.018 0.024 0.030
Θ 0 -- 8°0 -- 8°
0.252 BSC
0.026 BSC
SYMBOLS DIMENSIONS IN MILLIMETERS DIMENSIONS IN INCHES
0.65 BSC
6.4 BSC
Θ
A
12°(4X)
0.10mm
L
C
E E1
e
D
Note:
1. Controlling Dimension:MM
2. Dimension D and E do not include Mold protrusion
3. Dimension b does not include dambar protrusion/intrusion.
4. Refer to Jedec standard MO-153 AA
5. Drawing is not to scale
6. Package may have exposed tie bar.
1
8
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9.3 UDFN
8L 2x3mm UDFN Package Outline
MIN NOM MAX MIN NOM MAX
A 0.50 0.55 0.60 0.020 0.022 0.024
A1 0.00 -- 0.05 0.000 -- 0.002
b 0.18 0.25 0.30 0.007 0.010 0.012
A2
D
D2 1.25 1.40 1.50 0.049 0.055 0.059
E
E2 1.15 1.30 1.40 0.045 0.051 0.055
e
K 0.40 -- -- 0.016 -- --
L 0.20 0.30 0.40 0.008 0.012 0.016
3.00 BSC 0.118 BSC
0.020 BSC.
SYMBOLS DIMENSIONS IN MILLIMETERS DIMENSIONS IN INCHES
0.50 BSC.
0.152 REF 0.006 REF
2.00 BSC 0.079 BSC
Note:
1. Controlling Dimension:MM
2. Drawing is not to scale
TOP VIEW BOTTOM VIEW
SIDE VIEW
D
E
PIN#1 DOT
BY MARKING
D2
e
E2
K
L
b
A
A1
A2
PIN#1
IDENTIFICATION
CHAMFER
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10. Revision History
Revision Date Descriptions
A0 April. 2013 Initial version
