DS92LV3241,DS92LV3242
DS92LV3241/DS92LV3242 20-85 MHz 32-Bit Channel Link II Serializer /
Deserializer
Literature Number: SNLS314C
DS92LV3241/DS92LV3242
September 17, 2009
20-85 MHz 32-Bit Channel Link II Serializer / Deserializer
General Description
The DS92LV3241 (SER) serializes a 32-bit data bus into 2 or
4 (selectable) embedded clock LVDS serial channels for a
data payload rate up to 2.72 Gbps over cables such as CATx,
or backplanes FR-4 traces. The companion DS92LV3242
(DES) deserializes the 2 or 4 LVDS serial data channels, de-
skews channel-to-channel delay variations and converts the
LVDS data stream back into a 32-bit LVCMOS parallel data
bus.
On-chip data Randomization/Scrambling and DC balance en-
coding and selectable serializer Pre-emphasis ensure a ro-
bust, low-EMI transmission over longer, lossy cables and
backplanes. The Deserializer automatically locks to incoming
data without an external reference clock or special sync pat-
terns, providing an easy “plug-and-lock” operation.
By embedding the clock in the data payload and including
signal conditioning functions, the Channel-Link II SerDes de-
vices reduce trace count, eliminate skew issues, simplify
design effort and lower cable/connector cost for a wide variety
of video, control and imaging applications. A built-in AT-
SPEED BIST feature validates link integrity and may be used
for system diagnostics.
Features
■Wide Operating Range Embedded Clock SER/DES
—Up to 32-bit parallel LVCMOS data
—20 to 85 MHz parallel clock
—Up to 2.72 Gbps application data paylod
■Selectable Serial LVDS Bus Width
—Dual Lane Mode (20 to 50 MHz)
—Quad Lane Mode (40 to 85 MHz)
■Simplified Clocking Architecture
—No separate serial clock line
—No reference clock required
—Receiver locks to random data
■On-chip Signal Conditioning for Robust Serial
Connectivity
—Transmit Pre-Emphasis
—Data randomization
—DC-balance encoding
—Receive channel deskew
—Supports up to 10m CAT-5 at 2.7 Gbps
■Integrated LVDS Terminations
■Built-in AT-SPEED BIST for end-to-end system testing
■AC-coupled interconnect for isolation and fault protection
■> 4KV HBM ESD protection
■Space-saving 64-pin TQFP package
■Full industrial temperature range : -40° to +85°C
Applications
■Industrial imaging (Machine-vision) and control
■Security & Surveillance cameras and infrastructure
■Medical imaging
■Up to 30 bits per pixel, VGA to HD video transport and
display
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2010 National Semiconductor Corporation 301036 www.national.com
DS92LV3241/DS92LV3242 20-85 MHz 32-Bit Channel Link II Serializer / Deserializer
Block Diagram
30103627
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DS92LV3241/DS92LV3242
Mode Diagrams
30103628
FIGURE 1. Dual Mode
30103629
FIGURE 2. Quad Mode
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DS92LV3241/DS92LV3242
DS92LV3241 Pin Diagram
30103630
FIGURE 3. DS92LV3241 Pin Diagram— Top View
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DS92LV3241/DS92LV3242
DS92LV3241 Serializer Pin Descriptions
Pin # Pin Name I/O, Type Description
LVCMOS PARALLEL INTERFACE PINS
10–8,
5–1,
64–57,
52–51,
48–44.
41–33
TxIN[31:29],
TxIN[28:24],
TxIN[23:16],
TxIN[15:14],
TxIN[13:9],
TxIN[8:0]
I, LVCMOS Serializer Parallel Interface Data Input Pins.
11 TxCLKIN I, LVCMOS Serializer Parallel Interface Clock Input Pin. Strobe edge set by R_FB configuration pin.
CONTROL AND CONFIGURATION PINS
12 PDB I, LVCMOS Serializer Power Down Bar (ACTIVE LOW)
PDB = L; Device Disabled, Differential serial outputs are put into TRI-STATE® stand-by mode,
PLL is shutdown
PDB = H; Device Enabled
15 MODE I, LVCMOS Dual or Quad mode select (ACTIVE H)
MODE = L (default); Dual Mode,
MODE = H; Quad Mode
19 PRE I, LVCMOS PRE-emphasis level select pin
PRE = (RPRE > 12kΩ); Imax = [(1.2/R) x 20 x 2], Rmin = 12kΩ.
PRE = H or floating; pre-emphasis is disabled.
14 R_FB I, LVCMOS Rising/Falling Bar Clock Edge Select
R_FB = H; Rising Edge,
R_FB = L; Falling Edge
20 VSEL I, LVCMOS VOD (Differential Output Voltage) Llevel Select
VSEL = L; Low Swing,
VSEL = H; High Swing
13 BISTEN I, LVCMOS BIST Enable
BISTEN = L; BIST OFF, (default), normal operating mode.
BISTEN = H; BIST Enabled (ACTIVE HIGH)
16 RSVD I, LVCMOS Reserved — MUST BE TIED LOW
LVDS SERIAL INTERFACE PINS
22, 24,
28, 30
TxOUT[3:0]+ O, LVDS Serializer LVDS Non-Inverted Outputs(+)
21, 23,
27, 29
TxOUT[3:0]- O, LVDS Serializer LVDS Inverted Outputs(-)
POWER / GROUND PINS
7, 18,
32, 42
VDD VDD Digital Voltage supply, 3.3V
6, 17,
31, 43
VSS GND Digital ground
53, 56 VDDPLL VDD Analog Voltage supply, PLL POWER, 3.3V
54, 55 VSSPLL GND Analog ground, PLL GROUND
26 VDDA VDD Analog Voltage supply
25 VSSA GND Analog ground
49 IOVDD VDD Digital IO Voltage supply
Connect to 1.8V typ for 1.8V LVCMOS interface
Connect to 3.3V typ for 3.3V LVCMOS interface
50 IOVSS GND Digital IO ground
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DS92LV3241/DS92LV3242
DS92LV3242 Pin Diagram
30103631
FIGURE 4. DS92LV3242 Pin Diagram — Top View
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DS92LV3241/DS92LV3242
DS92LV3242 Deserializer Pin Descriptions
Pin # Pin Name I/O, Type Description
LVCMOS PARALLEL INTERFACE PINS
5–7,
10–14,
19–25,
28–32,
33–39,
42–46
RxOUT[31:29],
RxOUT[28:24],
RxOUT[23:17],
RxOUT[16:12],
RxOUT[11:5],
RxOUT[4:0]
O, LVCMOS Deserializer Parallel Interface Data Output Pins.
4 RxCLKOUT O, LVCMOS Deserializer Recovered Clock Output. Parallel data rate clock recovered from the embedded
clock.
3 LOCK O, LVCMOS LOCK indicates the status of the receiver PLL LOCK = L; deserializer CDR/PLL is not locked,
RxOUT[31:0] and RCLK are TRI-STATED®
LOCK = H; deserializer CDR/PLL is locked
CONTROL AND CONFIGURATION PINS
48 R_FB I, LVCMOS Rising/Falling Bar Clock Edge Select
R_FB = H; RxOUT clocked on rising edge
R_FB = L; RxOUT clocked on falling edge
50 REN I, LVCMOS Deserializer Enable, DES Output Enable Control Input (ACTIVE HIGH)
REN = L; disabled, RxOUT[31:0] and RxCLKOUT TRI-STATED, PLL still operational
REN = H; Enabled (ACTIVE HIGH)
49 PDB I, LVCMOS Power Down Bar, Control Input Signal (ACTIVE LOW)
PDB = L; disabled, RxOUT[31:0], RCLK, and LOCK are TRI-STATED in stand-by mode,
PLL is shutdown
PDB = H; Enabled
47 RSVD I, LVCMOS Reserved — MUST BE TIED LOW
LVDS SERIAL INTERFACE PINS
51, 53,
57, 59
RxIN[0:3]+ I, LVDS Deserializer LVDS Non-Inverted Inputs(+)
52, 54,
58, 60
RxIN[0:3]- I, LVDS Deserializer LVDS Inverted Inputs(-)
POWER / GROUND PINS
9, 16,
17, 26,
61
VDD VDD Digital Voltage supply, 3.3V
8, 15,
18, 27,
62
VSS GND Digital Ground
55 VDDA VDD Analog LVDS Voltage supply, POWER, 3.3V
56 VSSA GND Analog LVDS GROUND
1, 40, 64 VDDPLL VDD Analog Voltage supply PLL VCO POWER, 3.3V
2, 41, 63 VSSPLL GND Analog ground, PLL VCO GROUND
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DS92LV3241/DS92LV3242
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VDD)−0.3V to +4V
LVCMOS Input
Voltage −0.3V to (VDD +0.3V)
LVCMOS Output
Voltage −0.3V to (VDD +0.3V)
LVDS Deserializer Input
Voltage −0.3V to +3.9V
LVDS Driver Output
Voltage −0.3V to +3.9V
Junction Temperature +125°C
Storage Temperature −65°C to +150°C
Lead Temperature
(Soldering, 4 seconds) +260°C
Maximum Package Power Dissipation Capacity
Package Derating: 1/θJA °C/W above +25°C
θJA 35.7 °C/W*
θJC 12.6 °C/W
*4 Layer JEDEC
ESD Rating (HBM) >4 kV
Recommended Operating
Conditions
Min Nom Max Units
Supply Voltage (VDD) 3.135 3.3 3.465 V
Supply Voltage(IOVDD)
(SER ONLY)
3.3V I/O Interface 3.135 3.3 3.465 V
1.8V I/O Interface 1.71 1.8 1.89 V
Operating Free Air
Temperature (TA) −40 +25 +85 °C
Input Clock Rate
Dual Mode 20 50 MHz
Quad Mode 40 85 MHz
Tolerable Supply Noise 100 mVP-P
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2, Note 3)
Symbol Parameter Conditions Min Typ Max Units
LVCMOS DC SPECIFICATIONS
VIH High Level Input Voltage Tx: IOVDD = 1.71V to 1.89V 0.65 x
IOVDD
IOVDD +
0.3 V
Tx: IOVDD = 3.135V to 3.465V 2.0 VDD
Rx
VIL Low Level Input Voltage Tx: IOVDD = 1.71V to 1.89V GND 0.35 x
IOVDD V
Tx: IOVDD = 3.135V to 3.465V GND 0.8
Rx
VCL Input Clamp Voltage ICL = −18 mA −0.8 −1.5 V
IIN Input Current Tx: VIN = 0V or 3.465V(1.89V)
IOVDD = 3.465V(1.89V) −10 +10 µA
Rx: VIN = 0V or 3.465V −10 +10
VOH High Level Output Voltage IOH = −2mA (Dual) 2.4 3.0 VDD V
IOH = −2mA (Quad)
VOL Low Level Output Voltage IOH = −2mA (Dual) GND 0.33 0.5 V
IOH = −2mA (Quad)
IOS Output Short Circuit Current VOUT = 0V (Dual) −22 −40 mA
VOUT = 0V (Quad) −33 −70 mA
IOZ TRI-STATE® Output Current PDB = 0V,
VOUT = 0V or VDD
−10 +10 μA
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DS92LV3241/DS92LV3242
Symbol Parameter Conditions Min Typ Max Units
SERIALIZER LVDS DC SPECIFICATIONS
VOD Output Differential Voltage No pre-emphasis, VSEL = L
(VSEL = H)
350
(629)
440
(850)
525
(1000) mVP-P
ΔVOD Output Differential Voltage Unbalance VSEL = L,
No pre-emphasis 1 50 mVP-P
VOS Offset Voltage VSEL = L,
No pre-emphasis 1.00 1.25 1.50 V
ΔVOS Offset Voltage Unbalance VSEL = L,
No pre-emphasis 4 50 mV
IOS Output Short Circuit Current TxOUT[3:0] = 0V,
PDB = VDD,
VSEL = L,
No pre-emphasis
−2 −5
mA
TxOUT[3:0] = 0V,
PDB = VDD,
VSEL = H,
No pre-emphasis
−6 −10
IOZ TRI-STATE® Output Current PDB = 0V,
TxOUT[3:0] = 0V OR VDD
−15 ±1 +15 µA
PDB = VDD,
TxOUT[3:0] = 0V OR VDD
−15 ±1 +15 µA
RTOutput Termination Internal differential output termination
between differential pairs 90 100 130 Ω
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DS92LV3241/DS92LV3242
Symbol Parameter Conditions Min Typ Max Units
SERIALIZER SUPPLY CURRENT (DVDD*, PVDD* AND AVDD* PINS) *DIGITAL, PLL, AND ANALOG VDDS
IDDTQ Serializer (Tx) Total Supply Current
Quad Mode
(includes load current)
f = 85 MHz,
CHECKER BOARD pattern
MODE = H,
VSEL = H,
PRE = OFF
150 200
mA
f = 85 MHz,
CHECKER BOARD pattern
MODE = H,
VSEL = H,
RPRE = 12 kΩ
150 200
f = 85 MHz,
RANDOM pattern
MODE = H,
VSEL = H,
PRE = OFF
140 195
f = 85 MHz,
RANDOM pattern
MODE = H,
VSEL = H,
RPRE = 12 kΩ
140 195
IDDTD Serializer (Tx) Total Supply Current
Dual Mode
(includes load current)
f= 50 MHz,
CHECKER BOARD pattern
MODE = L,
VSEL = H,
PRE = OFF
120 145
mA
f= 50 MHz,
CHECKER BOARD pattern
MODE = H,
VSEL = H,
RPRE = 12 kΩ
120 145
f= 50 MHz,
RANDOM pattern
MODE = L,
VSEL = H,
PRE = OFF
115 135
f= 50 MHz,
RANDOM pattern
MODE = L,
VSEL = H,
RPRE = 12 kΩ
115 135
IDDTZ Serializer Supply Current
Power-down
TPWDNB = 0V
(All other LVCMOS Inputs = 0V) 2 50 µA
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DS92LV3241/DS92LV3242
Symbol Parameter Conditions Min Typ Max Units
DESERIALIZER LVDS DC SPECIFICATIONS
VTH Differential Threshold High Voltage VCM = +1.8V +50 mV
VTL Differential Threshold Low Voltage −50 mV
RTInput Termination Internal differential output termination
between differential pairs 90 100 130 Ω
IIN Input Current VIN = +2.4V, VDD = 3.6V ±100 ±250 µA
VIN = 0V, VDD = 3.6V ±100 ±250 µA
DESERIALIZER SUPPLY CURRENT (DVDD*, PVDD* AND AVDD* PINS) *DIGITAL, PLL, AND ANALOG VDDS
IDDR Deserializer Total Supply Current
(includes load current)
f = 85 MHz,
CL = 8 pF,
CHECKER BOARD pattern,
Quad Mode
240 265
mA
f = 85 MHz,
CL = 8 pF,
RANDOM pattern,
Quad Mode
190 210
f = 50 MHz,
CL = 8 pF,
CHECKER BOARD pattern,
Dual Mode
145 185
mA
f = 50 MHz,
CL = 8 pF,
RANDOM pattern,
Dual Mode
122 140
IDDRZ Deserializer Supply Current Power-
down
PDB = 0V
(All other LVCMOS Inputs = 0V,
RxIN[3:0](P/N) = 0V)
100 µA
Serializer Input Timing Requirements for TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
tCIP TxCLKIN Period MODE = L (Dual Mode) 20 tCIP 50
ns
MODE = H (Quad Mode) 11.76 tCIP 25
tCIH TxCLKIN High Time 20 MHz – 50 MHz 0.45 x
tCIP
0.5 x tCIP
0.55 x
tCIP ns
40 MHz – 85 MHz 0.45 x
tCIP
0.5 x tCIP
0.55 x
tCIP
tTCIL TxCLKIN Low Time 20 MHz – 50 MHz
Figure 7
0.45 x
tCIP
0.5 x tCIP
0.55 x
tCIP ns
40 MHz – 85 MHz 0.45 x
tCIP
0.5 x tCIP
0.55 x
tCIP
tCIT TxCLKIN Transition Time 20 MHz – 50 MHz
Figure 6 0.5 1.2
ns
40 MHz – 85 MHz 0.5 1.2
tJIT TxCLKIN Jitter ±100 psP-P
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DS92LV3241/DS92LV3242
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
tLLHT LVDS Low-to-High Transition Time No pre-emphasis
Figure 5
350 ps
tLHLT LVDS High-to-Low Transition Time 350 ps
tSTC TxIN[31:0] Setup to TxCLKIN IOVDD = 1.71V to 1.89V
Figure 7 0
ns
IOVDD = 3.135V to 3.465V 0
tHTC TxIN[31:0] Hold from TxCLKIN IOVDD = 1.71V to 1.89V 2.5
ns
IOVDD = 3.135V to 3.465V 2.25
tPLD Serializer PLL Lock Time Figure 9 4400 x
tCIP
5000 x
tCIP
ns
tLZD Data Output LOW to TRI-STATE®
Delay
(Note 4) 5 10 ns
tHZD Data Output TRI-STATE® to HIGH
Delay
(Note 4) 5 10 ns
tSD Serializer Propagation Delay -
Latency
f = 50 MHz,
R_FB = H,
PRE = OFF,
MODE = L
Figure 8
4.5 tCIP +
6.77
ns
f = 50 MHz,
R_FB = L,
PRE = OFF,
MODE = L
4.5 tCIP +
5.63
4.5 tCIP +
7.09
4.5 tCIP +
9.29
f = 20 MHz,
R_FB = H,
PRE = OFF,
MODE = L
4.5 tCIP +
6.57
4.5 tCIP +
8.74
4.5 tCIP +
10.74
f = 85MHz,
R_FB = H,
PRE = OFF,
MODE = H
9.0 tCIP +
6.99
f = 85MHz,
R_FB = L,
PRE = OFF,
MODE = H
9.0 tCIP +
5.97
9.0 tCIP +
7.38
9.0 tCIP +
9.64
f = 40 MHz,
R_FB = HL,
PRE = OFF,
MODE = H
9.0 tCIP +
6.30
9.0 tCIP +
8.26
9.0 tCIP +
10.49
tLVSKD LVDS Output Skew LVDS differential output channel-to-
channel skew 30 500 ps
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DS92LV3241/DS92LV3242
Symbol Parameter Conditions Min Typ Max Units
ΛSTXBW Jitter Transfer Function -3 dB
Bandwidth
Dual Mode
f = 50 MHz
Figure 15
2.8
MHz
Quad Mode
f = 85 MHz 2
δSTX Serializer Jitter Transfer Function
Peaking
Dual Mode
f = 50 MHz 0.3
dB
Quad Mode
f = 85 MHz 0.9
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
tROCP Receiver Output Clock Period tROCP = tCIP
(Dual Mode)
Figure 11
20 tROCP 50
ns
tROCP = tCIP
(Quad Mode) 11.76 tROCP 25
tRODC RxCLKOUT Duty Cycle 45 50 55 %
tROTR LVCMOS Low-to-High Transition
Time
CL = 8pF
(lumped load)
(Dual Mode)
Figure 10
3.2 ns
tROTF LVCMOS High-to-Low Transition
Time 3.5 ns
tROTR LVCMOS Low-to-High Transition
Time
CL = 8pF
(lumped load)
(Quad Mode)
2.4 ns
tROTF LVCMOS High-to-Low Transition
Time 1.9 ns
tROSC RxOUT[31:0] Setup to RxCLKOUT f = 50 MHz
(Dual Mode) 5.6 0.5 x
tROCP
ns
tROHC RxOUT[31:0] Hold to RxCLKOUT 7.4 0.5 x
tROCP
ns
tROSC RxOUT[31:0] Setup to RxCLKOUT f = 85 MHz
(Quad Mode) 3.4 0.5 x
tROCP
ns
tROHC RxOUT[31:0] Hold to RxCLKOUT 3.4 0.5 x
tROCP
ns
tHZR Data Output High to TRI-STATE®
Delay
Figure 13 5 10 ns
tLZR Data Output Low to TRI-STATE®
Delay 5 10 ns
tZHR Data Output TRI-STATE® to High
Delay 5 10 ns
tZLR Data Output TRI-STATE® to Low
Delay 5 10 ns
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DS92LV3241/DS92LV3242
Symbol Parameter Conditions Min Typ Max Units
tRD Deserializer Porpagation Delay –
Latency
f = 20 MHz
(Dual Mode)
Figure 12
5.5 x
tROCP +
3.35
ns
f = 50 MHz
(Dual Mode)
5.5 x
tROCP +
6.00
ns
f = 40 MHz
(Quad Mode)
12.0 x
tROCP +
7.4
ns
f = 85 MHz
(Quad Mode)
12.0 x
tROCP +
5.7
ns
tRPLLS Deserializer PLL Lock Time 20 MHz – 50 MHz
(Dual Mode)
Figure 13
(Note 5)
128k x
tROCP
ns
40 MHz – 85 MHz
(Quad Mode)
Figure 13
(Note 5)
256k x
tROCP
ns
TOLJIT Deserializer Input Jitter Tolerance 0.25 UI
tLVSKR LVDS Differential Input Skew
Tolerance
20 MHz – 85 MHz
Figure 17 0.4 x
tROCP
ns
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 2: Typical values represent most likely parametric norms at VDD = 3.3V, TA = +25°C, and at the Recommended Operating Conditions at the time of product
characterization and are not guaranteed.
Note 3: Current into a the device is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD,
ΔVOD, VTH, VTL which are differential voltages.
Note 4: When the Serializer output is at TRI-STATE® the Deserializer will lose PLL lock. Resynchronization MUST occur before data transfer.
Note 5: tRPLLS is the time required by the Deserializer to obtain lock when exiting power-down mode.
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DS92LV3241/DS92LV3242
AC Timing Diagrams and Test Circuits
30103632
FIGURE 5. Serializer LVDS Transition Times
30103645
FIGURE 6. Serializer Input Clock Transition Time
30103649
FIGURE 7. Serializer Setup/Hold and High/Low Times
30103647
FIGURE 8. Serializer Propagation Delay
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DS92LV3241/DS92LV3242
30103633
FIGURE 9. Serializer PLL Lock Time
30103648
FIGURE 10. Deserializer LVCMOS Output Transition Time
30103634
FIGURE 11. Deserializer Setup and Hold times
30103646
FIGURE 12. Deserializer Propagation Delay
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DS92LV3241/DS92LV3242
30103635
FIGURE 13. Deserializer PLL Lock Time and PDB TRI-STATE® Delay
30103636
FIGURE 14. Deserializer TRI_STATE Test Circuit and Timing
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DS92LV3241/DS92LV3242
30103651
FIGURE 15. Serializer Jitter Transfer
30103637
FIGURE 16. Serializer VOD Test Circuit Diagram
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DS92LV3241/DS92LV3242
30103638
FIGURE 17. LVDS Deserializer Input Skew
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DS92LV3241/DS92LV3242
Functional Description
The DS92LV3241 Serializer (SER) and DS92LV3242 Dese-
rializer (DES) chipset is a flexible SER/DES chipset that
translates a 32-bit parallel LVCMOS data bus into a quad (4
pairs) or dual (2 pairs) LVDS serial links with embedded clock.
The DS92LV3241 serializes the 32-bit wide parallel LVCMOS
word into four or two high-speed LVDS serial data streams
with embedded clock, scrambles and DC Balances the data
to support AC coupling and enhance signal quality. The
DS92LV3242 receives the dual/quad LVDS serial data
streams and converts it back into a 32-bit wide parallel data
with a recovered clock. The dual/quad LVDS serial data
stream reduces cable size, the number of connectors, and
eases skew concerns.
Parallel clocks between 20 MHz to 85 MHz are supported by
the dual or quad operating modes. The modes are user se-
lectable through a control pin on Serializer. In dual mode, the
transmit clock frequency supports 20 MHz to 50 MHz and in
quad mode the transmit clock frequency supports 40 MHz to
85 MHz. In the dual mode configuration, the embedded clock
LVDS serial streams have an effective data payload of 640
Mbps (20MHz x 32-bit) to 1.6 Gbps (50MHz x 32- bit). In the
quad mode configuration, the embedded clock LVDS serial
streams have an effective data payload of 1.28 Gbps (40MHz
x 32-bit) to 2.72 Gbps (85MHz x 32-bit). The SER/DES
chipset is designed to transmit data over long distances
through standard twisted pair (TWP) cables. The differential
inputs and outputs are internally terminated with 100 ohm re-
sistors to provide source and load termination, minimize stub
length, to reduce component count and further minimize
board space.
The DES can attain lock to a data stream without the use of
a separate reference clock source; greatly simplifying system
complexity and reducing overall cost. The DES synchronizes
to the SER regardless of data pattern, delivering true auto-
matic “plug-and-lock” performance. It will lock to the incoming
serial stream without the need of special training patterns or
special sync characters. The DES recovers the clock and data
by extracting the embedded clock information, deskews the
serial data channels and then deserializes the data. The DES
also monitors the incoming clock information, determines lock
status, and asserts the LOCK output high when lock occurs.
In addition the DES also supports an optional AT-SPEED
BIST (Built In Self Test) mode, BIST error flag, and LOCK
status reporting pin. The SER and the DES have a power
down control signal to enable efficient operation in various
applications.
DESKEW AND CHANNEL ALIGNMENT
The DES automatically detects dual or quad serial channel
mode and provides a clock alignment and deskew function
without the need for any special training patterns. During the
locking phase, the embedded clock information is recovered
on all channels and the serial links are internally synchro-
nized, de-skewed, and auto aligned. The internal CDR cir-
cuitry will dynamically compensate for up to 0.4 times the
parallel clock period of per channel phase skew (channel-to-
channel) between the recovered clocks of the serial links. This
provides skew phase tolerance from mismatches in intercon-
nect wires such as PCB trace routing, cable pair-to-pair length
differences, and connector imbalances.
DATA TRANSFER
After SER lock is established (SER PLL to TxCLKIN), the in-
puts TxIN0–TxIN31 are latched into the encoder block. Data
is clocked into the SER by the TxCLKIN input. The edge of
TxCLKIN used to strobe the data is selectable via the R_FB
(SER) pin. R_FB (SER) high selects the rising edge for clock-
ing data and low selects the falling edge. The SER outputs
(TxOUT[3:0]+/-) are intended to drive a AC Coupled point-to-
point connections.
The SER latches 32-bit parallel data bus and performs sev-
eral operations to it. The 32-bit parallel data is internally
encoded and sequentially transmitted over the two high-
speed serial LVDS channels. For each serial channel, the
SER transmits 20