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APPENDIX 1: ST72334 Regist er and Memory M a pping File
**********************************************************************
; Miscellaneous 1 register
;**********************************************************************
.MISCR1 DS.B 1 ; miscellaneous register 1
;**********************************************************************
; SPI registers
;**********************************************************************
.SPIDR DS.B 1 ; SPI data register
.SPICR DS.B 1 ; SPI control register
.SPISR DS.B 1 ; SPI status register
reserved1 DS.B 5 ; unused
;**********************************************************************
; Main Clock Registers
;**********************************************************************
.MCCSR DS.B 1; Main Clock Control/Status register
;**********************************************************************
; Watchdog Registers
;**********************************************************************
.WDGCR DS.B 1 ; Watchdog control register
.CRSR DS.B 1; clock, reset, supply control/status register
;**********************************************************************
; EEPROM Register
;**********************************************************************
.EECSR DS.B 1 ; Data-EEPROM Control/Status register
reserved2 DS.B 4 ; unused
;**********************************************************************
; Timer A registers
;**********************************************************************
.TACR2 DS.B 1 ; timer A control register 2
.TACR1 DS.B 1 ; timer A control register 1
.TASR DS.B 1 ; timer status register
.TAIC1HR DS.B 1 ; timer A input capture 1 high register
.TAIC1LR DS.B 1 ; timer A input capture 1 low register
.TAOC1HR DS.B 1 ; timer A output compare 1 high register
.TAOC1LR DS.B 1 ; timer A output compare 1 low register
.TACHR DS.B 1 ; timer A counter high register
.TACLR DS.B 1 ; timer A counter low register
.TAACHR DS.B 1 ; timer A alternate counter high register
.TAACLR DS.B 1 ; timer A alternate counter low register
.TAIC2HR DS.B 1 ; timer A input capture 2 high register
.TAIC2LR DS.B 1 ; timer A input capture 2 low register
.TAOC2HR DS.B 1 ; timer A output compare 2 high register
.TAOC2LR DS.B 1 ; timer A output compare 2 low register
;**********************************************************************
; Miscellaneous 2 register
;**********************************************************************
.MISCR2 DS.B 1 ; miscellaneous register 2
;**********************************************************************
; Timer B registers
;**********************************************************************
.TBCR2 DS.B 1 ; timer B control register 2
.TBCR1 DS.B 1 ; timer B control register 1
.TBSR DS.B 1 ; timer B status register
.TBIC1HR DS.B 1 ; timer B input capture 1 high register