VIPER50A-E - STMICROELECTRONICS - Datasheet.Directory

Rev 1

September 2005 1/31

VIPer50A-E

VIPer50ASP-E

SMPS PRIMARY I.C.

General Features

■ADJUSTABLE SWITCHING FREQUENCY UP

TO 200 kHz

■CURRENT MODE CONTROL

■SOFT START AND SHUTDOWN CONTROL

■AUTOMATIC BURST MODE OPERATION IN

STAND - BY CONDITION ABLE TO MEET

“BLUE ANGEL” NORM (<1w TOTAL POWER

CONSUMPTION)

■INTERNALLY TRIMMED ZENER

REFERENCE

■UNDERVOLTAGE LOCK-OUT WITH

HYSTERESIS

■INTEGRATED START-UP SUPPLY

■OVER-TEMPERATURE PROTECTION

■LOW STAND-BY CURRENT

■ADJUSTABLE CURRENT LIMITAT ION

Blo ck Diag r am

Description

VIPer50A-E/ASP-E, made using VIPower M0

Technology, combines on the same silicon chip a

state-of-the-art PWM circuit together with an

optimized, high voltage, Vertical Power MOSFET

(700V/ 1.5A).

Typical applications cover offline power supplies

with a secondary power capability of 25W in wide

range condition and 50W in single range or with

doubler configuration. It is compatible from both

primary or secondary regulation loop despite

using around 50% less components when

compared with a discrete solution. Burst mode

operation is an additional feature of this device,

offering the ability to operate in stand-by mode

without extra components.

Type VDSS InRDS(on)

VIPer50A-E/ASP-E 700V 1.5A 5.7Ω

PENTAWATT HV

PENTAWATT HV (022Y)

www.st.com

POWERSO-10TM

FC002

VDD

OSC

COMP

DRAIN

SOURCE

13 V

UVLO

LOGIC

SECURITY

LATCH PWM

LATCH

R/S SQS

R2 R3Q

OSCILLATOR

OVERTEMP.

DETECTOR

ERROR

AMPLIFIER

0.5 V +

_1.7 µs

DELAY 250 ns

BLANKING CURRENT

AMPLIFIER

ON/OFF

0.5V

2 V/A

4. 5 V

VIPer50A-E/ASP-E

2/31

Contents

1 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1 Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1 Drain Pin (Integrated Power MOSFET Drain): . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2 Source Pin: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.3 VDD P in (Power Supply): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.4 Compensation Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3. 5 OSC Pin (O s c illat or Frequency ): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Typical Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5 Operation Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.1 Current M ode Topology: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

5.2 Stand-by Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

5.3 High Voltage Start-up C urrent Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.4 Transconductance Erro r Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.5 External Clock Synchronization: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.6 Primary Peak Current Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.7 Over-Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.8 Operation Pictures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

VIPer50A-E/ASP-E

3/31

6 Electrical Over Stress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.1 Electrical Over Stress Ruggedness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.1 Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8 Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

9 Order Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

1 E lectrical Data VIPer50A-E/ASP-E

4/31

1 Electrical Data

1.1 Maximum Rating

Table 1. Absolute Maximum Rating

Symbol Parameter Value Unit

VDS Continuous Drain-Source Voltage (TJ = 25 to 125°C) –0.3 to 700 V

IDMaximum Current Internally limited A

VDD Supply Voltage 0 to 15 V

VOSC Voltage Range Input 0 to VDD V

VCOMP Voltage Range Input 0 to 5 V

ICOMP Maximum Continuous Current ±2 mA

VESD Ele c tro static D is c h ar g e (R = 1. 5 kΩ; C=100pF) 4000 V

ID(AR) Avalanche Drain-So urce Current, Repetit ive or Not Repetitive

(Tc=100°C; Pulse width lim it ed by TJ m ax; δ < 1 % ) 1A

Ptot Power Dissipation at Tc = 25ºC 60 W

TjJunction Operating Temperature Internally limite d °C

Tstg Storage Temperature -65 to 150 °C

VIPer50A-E/ASP-E 1 Elec tric al Da ta

5/31

1.2 Electrical Characteristics

TJ = 25°C; VDD = 13V, unless otherwise specified

Table 2. Power Section

(1) On Inductive Load, Clamped.

Table 3. Supply Section

Table 4. Oscillato r Section

Symbol Parameter Test Conditions Min Typ Max Unit

BVDS Drain-Source Voltage ID = 1mA; VCOMP = 0V 700 V

IDSS Of f-State Drain

Current VCOMP = 0V; Tj = 125°C

VDS = 700V 1mA

RDS(on) Static Drain-Source

On Resistance ID = 2A

ID = 2A; Tj = 100°C 4.6 5.7

10.3

Ω

tfFa ll Time ID = 0.2A; VIN =300V (1)Figure 7 100 ns

tr Ri se Time ID = 1A; VIN = 300V (1)Figure 7 50 ns

Coss Output Capacitance VDS = 25V 120 pF

Symbol Parameter Test Conditions Min Typ Max Unit

IDDch Start-Up Charging Current VDD = 5 V; V DS = 35V

(see Fig ure 6)(see Fig ure 11) -2 mA

IDD0 Operati ng Supply Current VDD = 12V; FSW = 0kHz

(see Fig ure 6) 12 16 mA

IDD1 Operati ng Supply Current VDD = 12V; Fsw = 100k Hz 14 mA

VDD = 12V; Fsw = 200kHz 16 mA

VDDoff Undervoltage Shutdown (see Fig ure 6) 7.5 8 9 V

VDDon Undervoltage Reset (see Fig ure 6) 11 12 V

VDDhyst Hys t e resis Start -u p (see Fig ure 6) 2.4 3 V

Symbol Parameter Test Conditions‘ Min Typ Max Unit

FSW Oscillator Frequency Total

Variation RT=8.2KΩ; CT=2.4nF

VDD= 9 to 1 5 V;

with RT± 1%; CT± 5%

(see Fig ure 10)(see Fi gure 14 )

90 100 110 KHz

VOSCIH Oscillator Peak Voltage 7.1 V

VOSCIL Oscillator Valley Voltage 3.7 V

1 E lectrical Data VIPer50A-E/ASP-E

6/31

Table 5. Error Amplifier Section

Table 6. PWM Com parator Section

Table 7. Shutdown and Ov ertemperature Section

Symbol Parameter Test Conditions‘ Min Typ Max Unit

VDDREG VDD Regulation Point ICOMP = 0mA (see Figure 5) 12.6 13 13.4 V

∆VDDreg Total Vari at io n TJ = 0 to 100°C 2 %

GBW Unity Gain Bandwidth From Input = VDD to

Output = VCOMP

COMP pi n is open

(see Figure 15)

150 KHz

AVOL Open Loop Voltage Gain COMP pin is open

(see Figure 15) 45 52 dB

GmDC Transconductance VCOMP=2.5V(see Figure 5) 1.1 1.5 1.9 mA/V

VCOMPLO Output Low Level ICOMP=-400µA; VDD=14V 0.2 V

VCOMPHI Output High Level ICOMP=400µ A; VDD=12V 4.5 V

ICOMPLO Output Low Cur rent Capability VCOMP=2.5V; VDD=14V -600 µA

ICOMPHI Output High Current

Capability VCOMP=2.5V; VDD=12V 600 µA

Symbol Parameter Test Conditions‘ Min Typ Max Unit

HID ∆VCOMP / ∆IDPEAK VCOMP = 1 to 3 V 1.4 2 2.6 V/A

VCOMPoff VCOMP Offset IDPEAK = 10mA 0.5 V

IDpeak Peak Current Li mitation VDD = 12V; COMP pin open 1.5 2 2.7 A

tdCurrent Se nse Delay to Turn-

Off ID = 0.5A 250 ns

tbBlanking Time 250 360 ns

ton(min) M inimum On Time 350 1200 ns

Symbol Parameter Test Conditions‘ Min Typ Max Unit

VCOMPth Restart Threshold (see Figure 8) 0.5 V

tDISsu Disable Set Up Time (see Fig ure 8) 1.7 5 µs

Ttsd Thermal Shutdown

Temperature (see Figure 8) 140 170 °C

Thyst Thermal Shutdown Hysteresis (see Figure 8) 40 °C

VIPer50A-E/ASP-E 2 Therma l Dat a

7/31

2 Thermal Data

Tabl e 8. Thermal data

Symbol Parameter PENTAWATT HV Unit

RthJC Thermal Resistance Juncti on-case Max 1 .9 °C/W

RthJA Thermal Resistance Ambien t-case Max 60 °C/W

3 P in Description VIPer50A-E/ASP-E

8/31

3 Pin Description

3.1 Drain Pin (Integ rated Power MOSFET Drain):

Integrated Power MOSFET drain pin. It provides internal bias current during start-up via an

integrated high voltage current source which is switc hed off during normal operation. The

device is able to handle an unclamped current during its normal operation, assuring self

protection against voltage s urges, PCB stray inductance, and allowing a snubberless operation

for low output power.

3.2 Source Pin:

Power MOSFET source pin. Primary side circuit common ground connection.

3.3 VDD Pin (Powe r Supply):

This pin provides two functions :

●It corresponds to the low voltage supply of t he control part of the circuit. If V DD goes below

8V, the start -up current source is activated and the output power MOSFET is switched off

until the VDD voltage reaches 11V. During this phase, the internal current consum pt ion is

reduced, the VDD pin is sourcing a current of about 2mA and the COMP pin is shorted to

ground. After th at, the current source is shut down, and the device trie s to start up by

switching agai n.

●This pin is also c onnect ed to the error amplifier, in order to allow prim ary as well as

secondary regulation configuration s. In case of primary regulation, an internal 13V

trimmed referenc e voltage is u sed to maintain VDD at 13V. For secondary regulation, a

voltage between 8.5V and 12.5 V will b e put on VDD pin by transformer design, in order to

stuck the output of the transconductance amplifier to the high state. Th e COMP pin

behave s as a constant current source, and can easily be connected to the output of an

optocoupler. Note that any overvoltage due to regulation loop failure is still detected by the

error amplifier through the VDD voltage, which cannot ov erpass 13V. The outpu t voltage

will be som ewhat higher than the nominal one, but still un der control.

3.4 Compensation Pin

This pin provides two functions :

●It is the output of the error transconductance amplifier, and allows for the connection of a

compens ation network to provide the desired transfer function of the regulation loop. Its

bandwidth can be easily adjusted to the needed value with usual components value. As

stated above, secondary regulation configuration s are also implemented throu gh the

COMP pin.

●When the COMP voltage is go ing below 0.5V, the shut-down of the circuit occurs, with a

zero duty cycle for the power MOSFET. This feature can be used to swit ch off the

converter, and is automatically activated by the regulation loop (no matter what the

configuration is) to provide a burst mode operation in case of negligible output p ower or

open load condition.

VIPer50A-E/ASP-E 3 Pin Description

9/31

3.5 OSC Pin (Oscillator Frequency):

An Rt-Ct network must be connected on that to define the switching frequency. Note that

des pite the connect ion of Rt to VDD, no significant frequency chan ge occurs for VDD varying

from 8V to 15V. It provides also a synchronisation capabilit y, when connected to an exte rnal

freque ncy source.

Figure 1. Connection Diagrams (Top View)

Figure 2. Current and Voltage Convention

PENTAWATT HV PENTAWATT HV (022Y) PowerSO-10TM

13V

OSC

COMP SOURCE

DRAINVDD

VCOMP

VOSC

VDD VDS

ICOMP

IOSC

IDD ID

FC00020

4 Typical Cir cuit VIPer50A-E/ASP-E

10/31

4 Typical Circuit

Figure 3. Offline Power Supply With Auxiliary Supply Feedback

Figure 4. Offline Power Supply With Optocoupler Feedback

AC IN +Vcc

GND

BR1

TR2

C10

TR1

VIPer50

13V

OSC

COMP SOURCE

DRAINVDD

FC00301

C11

FC00091

AC IN

BR1

TR2

C10

TR1

C9C7

L2 +Vcc

GND

VIPer100

ISO1 R6

13V

OSC

COMP SOURCE

DRAINVDD

C11

VIPer50A-E/ASP-E 5 Operation Description

11/31

5 Operation Description

5.1 Current Mode Topology:

The curre nt mode control method, like the one integrated in the V IPer50 A-E/ASP -E , uses two

con trol loops - an inner current control loop and an outer loop for voltage control. When the

Power MOSFET output transistor i s on, the i nductor current (primary side of the transformer) is

moni tored with a SenseFET tech nique and convert ed into a voltage VS proportional to thi s

current. When VS reaches VCOMP (the amplified output voltage error) the power switch is

swi tched off. Thus, the out er voltage control loop defines the level at wh ich the inner loop

regulates peak current through the power switch and the primary winding of th e transformer.

Excellent open loop D.C. and dynamic line regulation is ensured due to the inherent input

voltage feedforward characteristic of the current mode control. This results in improved line

regulation, instantaneous correction to lin e chan ges, and better stability fo r the voltage

regulation loop .

Curr ent mode topology also ensures good limitation in case there is a short circuit. During the

first phase the output current increases slowly following the dynamic of the regulation loop.

Then it reache s the maximum limitation current internally set and finally st ops because the

powe r supply on V DD is no longer correct. For specific applications the maximum peak current

intern ally set can be overridden by externally limiting the voltage excursion on the COM P pin.

An integrated blanki ng filter inhibits the PWM com parator output for a short tim e after the

integrated Power MOS FET is switched on. This function prevents anomalous or premature

termination of the switching pulse in case there are current sp ikes caused by primary side

capacitance or secondary side rectifier reverse recovery time.

5.2 Stand-by Mode

Stand-by operation in nearly open load conditions automatically leads to a burst mode

operat ion allowing voltage regulation on the secondary side. The transition from norm al

operat ion to burst mode operation happens for a power PSTBY given by :

Where:

LP is the primary inductance of the transformer. FSW is the normal switching frequency.

ISTBY is the minimum controllable current, corresponding to the minimum on time that the

dev ice is able to provide in normal operation. This current can b e comput ed as :

tb + td is the sum of the blanking time and of the propagation time of the internal current sense

and comparator, and represents roughly the minimum on time of the device. Note: that PSTBY

may be affected by the efficienc y of the converter at lo w load, and must include the power

drawn on the primary auxiliary voltage.

PSTBY 1

---LPI2STBYFSW=

ISTBY tbtd

+()VIN

-----------------------------=

5 Op eration Descr iption VIPer50A-E/ASP-E

12/31

As soon as the power goes below this limit, the auxili ary secondary voltage starts to increase

abov e the 13V regulation level , forcing the output volta ge of the transconduc tance amplifier to

low state (VCOMP < VCOMPth). This situation leads to the shutdown mode where the power

switch is maintained in the Of f state, resulting in missing cycles and zero duty cycle. As soon as

VDD gets back to the regula tion level and the VCOMPth threshold is reached, the dev ice

operates again. The above cycle repeats indefinitely, providing a burst mode of which the

effective duty cycle is mu ch lower than the minimum one when in normal operation. The

equivale nt switch ing frequency is also lower th an the normal one, leading to a reduce d

consumption on the input main supply lines. This mode of operation allows the VIPer50A-E/

ASP-E to meet th e n e w G e r man "Blu e Angel" Norm w it h less than 1W total power consumption

for the system when working in stand-by mode . The output voltage remains regu lated around

the normal level, with a low frequency ripple corresponding to the burst mode. The amplitude of

this ripple is low, because of the output capacitors and low output current drawn in such

con ditions.The norm al operation resum es automat ically when the power gets back to high er

levels than PSTBY.

5.3 High Voltage Start-up Current Source

An integrated high voltage current source provides a bias current from the DRAIN pin during

the start-up phase. This current is partially absorbed by internal control circuits which are

placed into a standby mode with reduced consumption and also provided to the external

capacitor connected to the V DD pin. As soon as t he voltage on t his pi n reaches the high volt age

threshold VDDon of the UVLO logic, the device becomes active mode and starts switching. The

start-up current generator is switched off, and the convert er should normally provide the

needed c urrent on the VDD pin through the auxiliary winding of the transformer , as shown on

(see Figure 11).

In case there are abnormal conditions where the auxiliary winding is unable to provide the l ow

voltage supply curre nt to the VDD pin (i.e. short circui t on the output of the converter), the

external capacitor discharges to the low thre shold voltage VDDo ff of the UVLO logic, and the

device goes back to the inactive state where the internal circuits are in standby mode and the

start-up current source is activated. The converter en ters a endless start-up cycle, with a start-

up duty cycle defined by the ratio of charging current towards discharging when the device tries

to start. This ratio is fixed by design to 2A to 15A, which gives a 12% start-up duty cycle while

the power dissipation at start-up is approximately 0.6W, for a 2 30Vrms in put voltage.

This low value start-up duty cycle prevents the appl ication of stress to the output rectifiers as

well as the transformer when a short circuit occurs.

The external c apacitor C VDD on the V DD pin must be sized according t o the ti me needed by the

con verter to start up, when the device starts switching. This time tSS depend s on many

parameters, amo ng which transforme r design, output capacitors, soft start feature, and

compensation network implemented on the COMP pin. The following formula can be used for

defining th e minimu m capacitor needed:

where:

IDD is the consumption current on the VDD pin when switching. Refer to specified IDD1 and IDD2

values.

tSS is the start up time of the converter when the device begins to switc h. Worst case is

generally at full load.

CVDD

IDDtSS

VDDhyst

-------------------->

VIPer50A-E/ASP-E 5 Operation Description

13/31

VDDhyst is the voltage hysteresis of the UVLO logic (refer to the minimum specified value).

The soft start featu re can be implement ed on the COMP pin through a simple capacitor which

w ill b e a ls o u s ed a s the compens a tion ne two r k . In this cas e , the re gu lation lo op ba n d wid th is

rather low, because of the large value of this cap acitor. In case a large regulation loop

bandwidth is mandatory, the schemat ics of (see Figure 17) can be used. It mixes a high

performanc e comp ensati on network together with a separate high value soft start capacitor.

Both s oft start time and regulation loop bandw idth can be ad juste d separately.

If the device is intentionally shut down by tying the COMP pin to ground, the device is a lso

performing start-up cycles, and the VDD voltage is oscillating between VDDon and VDDoff.

This voltage can be used for supplying external functions, provided that their consumption does

not exceed 0.5 mA. (see Figure 18) shows a typical application of this function, with a latched

shu tdown. Once the "Shutdown" signal has been activated, the device remains in the Off state

until the input voltage is removed.

5.4 Transconductance Error Amplifier

The VIPer50A-E/ASP-E includes a transconductance error amplifier. Transconduct ance Gm is

the change in output current (ICOMP) versus change in input voltage (VDD). Thus:

The output impedance ZCOMP at the output of this amplifier (COMP pin) can be defined as:

This last equ ation show s that the open loop gain AVOL can be related to Gm and ZCOMP:

AVOL = Gm x ZCOMP

where Gm value for VIPer5 0 A-E/AS P-E is 1.5 mA/V ty pi cally.

Gm is defined by sp ecificatio n, but ZCOMP and therefore AVOL are subject to large tolerances .

An impedance Z can be connected betw een the COMP pin and ground in order to define the

transf er function F of the e rror amplifier more accurately, according to the following equation

(very similar to the one above):

F(S) = Gm x Z(S )

The error amplifier frequency response is reported in Figure 10. for different values of a simple

resistance connected on the COMP pin. The unloaded transconductance error amplifier shows

an internal ZCOMP of about 330KΩ. More complex impedance can be connected on the COMP

pin to achieve dif ferent compensation level. A capacitor will provide an integrator function, thus

eliminating the DC static error, and a resistance in series leads to a flat gain at hi gher

frequency, insuring a correct phase margin. This conf igurat ion is illustrat ed in Figure 20

As shown in Figure 19 an addi tional noise filtering capacitor of 2.2nF is generall y needed to

avo id any high frequency interference.

Is also possible to implement a slope compensation when working in continuous mode with

duty cycle higher than 50%. Figure 21 shows such a configuration. Note: R1 and C2 build the

classical compensation network, and Q1 is injecting the slope compensation with the correct

polarity from the oscillator sawtooth.

∂lCOMP

∂VDD

-------------------=

ZCOMP ∂VCOMP

∂ICOMP

---------------------1

--------∂VCOMP

∂VDD

-------------------------×==

5 Op eration Descr iption VIPer50A-E/ASP-E

14/31

5.5 External Clock Synchronization:

The OS C pin provides a synchronisa tion capability when connected to an external frequenc y

source. Figure 21 shows one possible schematic to be adapted, depending the specific needs.

If the proposed schema tic is used, the pulse duration must be kept at a low va lue (500ns is

sufficient) for minimizing consumption. The optocoupler must be able to provide 20mA through

the optot ransistor.

5.6 Primary Peak Current Limitation

The primary IDPEAK current a nd, conseque ntl y, the output power can be limited using the

simple circuit shown in Figure 22 . The circuit based on Q1, R1 and R2 clamps the volta ge on

the COMP pin in order to limit the primary peak current of the device to a value:

where:

The sugges t ed value for R1+R2 is in the range of 220KΩ.

5.7 Over-Temperature Protection

Ov er-temperature prote ction is based on chip temperature sensing. The minimum junction

temperat ure at which over-temperature cut-ou t occurs is 140ºC, while th e typical value is

170ºC. The device is automatically restarted when the junction te mpe rature decreases to the

restart temperature threshold that is typically 40ºC below the shutdown value (s ee Figure 13)

IDPEAK VCOMP 0.5–

HID

--------------------------------=

VCOMP 0.6 R1R2

-------------------×=

VIPer50A-E/ASP-E 5 Operation Description

15/31

5.8 Operation Pictures

Figure 5. VDD Regul ation Poin t Fi gur e 6 . Undervoltage Lockout

Fi gur e 7. Transition T i m e Fi gur e 8 . S hutdo wn Action

Figure 9. Brea kdown Voltage vs. Tem per ature Figure 10. Typical Freque ncy Variation

ICOMP

ICOMPHI

COMPLO VDDreg

Slope =

Gm in mA/V

FC00150

VDDon

DDch

IDD0

VDDoff

VDS= 35 V

Fsw = 0

IDD

VDDhyst

FC00170

tf tr

10% Ipe ak

10% V D

90% V D

FC00160

VCOMP

VOSC

tDISsu

ENABLE DISABLEENABLE

COMPth

FC0006

Temperature (°C)

FC00180

0 20406080100120

0.95

1.05

1.1

1.15

BVDSS

(

Normalized)

Temperature ( °C )

0 20 40 60 80 100 120

140

-5

-4

-3

-2

-1

1FC00190

(

5 Op erati on D escr iption VIPer50A-E/ASP-E

16/31

Figure 11. Behavio ur of the high voltage curr ent sou rce at star t-up

Figure 12. Start-Up Waveforms

Ref.

UNDERVOLTAGE

LOCK OUT LOGIC

15 mA1 mA

3 mA

2 mA

15 mA

VDD DRAIN

SOURCE

VIPer50

Auxiliary primary

winding

VDD

DDoff

VDDon

Start up duty cycle ~ 12%

CVDD

FC0032

VIPer50A-E/ASP-E 5 Operation Descr i ption

17/31

Figure 13. Over-temperature Protection

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0000000

00000000000000000

SC 101 91

tsd

-T

h yst

ts c

dd on

dd off

com p

5 Op erati on D escr iption VIPer50A-E/ASP-E

18/31

Figure 14. Oscillator

OSC

VDD

~360Ω

CLK

FC00050

40kHz

15nF

22nF

Forbidden are a

Forbidden area

Ct(nF) = Fsw(kHz)

880

1 2 3 5 10 20 30 50

100

200

300

500

1,000

Rt (kΩ)

Frequency (kHz)

Oscillator frequency vs Rt and Ct

Ct = 1.5 nF

Ct = 2.7 nF

Ct = 4.7 nF

Ct = 10 nF

FC00030FC00030

For Rt > 1.2k Ω and Ct ≤ 40KHz

FSW 2.3

RtCt

-----------1 550

Rt150–

--------------------–

⎝⎠

⎛⎞

⋅=

VIPer50A-E/ASP-E 5 Operation Descr i ption

19/31

Figure 15. Error Amplifier frequency Response

Figure 16. Error Amplifier Phase Response

0.001 0.01 0.1 1 10 100 1,00

(20)

Frequency (kHz)

Volta ge Gain (dB )

RCOMP = +∞

RCOMP = 270k

RCOMP = 82k

RCOMP = 27k

RCOMP = 12k

FC00200

0.001 0.01 0.1 1 10 100 1,00

(50)

100

150

200

Fre que n c y ( kH z )

Phase (°)

RCOMP = +∞

RCOMP = 270k

RCOMP = 82k

RCOMP = 27k

RCOMP = 12k

FC00210

5 Op erati on D escr iption VIPer50A-E/ASP-E

20/31

Figure 17. Mixed Soft Start and Compen sati on Figure 18. Latched Shut Down

Figure 19. Ty pical Co mpen sation Netwo rk Figure 20. Slope Compensa tion

Figu re 21. E xt ernal Cl ock S ync h roni za tion F ig ure 22. Current Li m itati on Ci rc u it Exam pl e

13V

OSC

COMP SOURCE

DRAINVDD

VIPer50

C1 +C2

+C3

AUXILIAR

WINDING

FC00331

13V

OSC

COMP SOURCE

DRAINVDD

VIPer50

Shutdown Q1

R2R3

R4 D1

FC00340

13V

OSC

COMP SOURCE

DRAINVDD

VIPer50

FC00351

13V

OSC

COMP SOURCE

DRAINVDD

VIPer50

R1R2

C1 R3

FC00361

13V

OSC

COMP SOURCE

DRAINVDD

VIPer50

10 kΩ

FC00370

13V

OSC

COMP SOURCE

DRAINVDD

VIPer50

FC00380

VIPer50A-E/ASP-E 6 Electri cal Over Stress

21/31

6 Electrical Over Stress

6.1 Electrical Over Stress Ruggedness

The VIPer may be submitted to electrical over-stress, caused by violent input voltage surges or

lightning. Following the Layout Considerations is sufficient to prevent catastrophic damages

most of the time. However in some cases, the voltage surges coupled through the transformer

auxiliary winding can exceed the VDD pin absolute maximum rating voltage value. Such events

may trigger the VDD in ternal protection circuitry which could be damaged by the strong

disch arge curren t of the VDD bulk cap acitor. The simple RC filter shown in Figure 23 can b e

imp lement ed to improve the application immuni ty to such surges.

Figure 23. Input Volta ge Surg es Pr otection

ulk capacitor

(Optional)

22nF

Auxilliary windin

13V

OSC

COMPSOURCE

DRAIN

VDD

VIPerXX0

39R

7 Layout VIPer50A-E/ASP-E

22/31

7 Layout

7.1 Layout Considerations

Some simple rules insure a correct running of switching power supplies. They may be

classifi ed into two categories:

– Minimizing power loops: The switched power current must be carefully analysed and

the corresponding paths must be as small an inner l oop area as possible. T his avoids

radiated EMC noises, conducted EMC noises by magnetic coupling, and provides a

better efficiency by eliminating parasitic inductances, especially on secondary side.

– Using diffe rent tracks for low level and powe r signals: Interference due to mixing of

signal and power may result in instabilities and/or anomalo us behavior of the device

in case of violent power surge (Input overvoltages, output short circuit s...).

In case of VIPer, the se rules apply as shown on (see Figure 24).

– Loops C1-T1-U1, C5-D2-T1, and C7-D1-T1 m ust be minimized.

– C6 must be as close as possible to T1.

– Signal components C2, ISO1, C3, and C4 are using a dedicated track connected

directly to the power source of the device.

Figure 24. Recommended Layout

VIPerXX0

13V

OSC

COMP SOURCE

DRAINVDD

ISO1

From input

iodes bridge

To s ec ondary

filtering an d loa

FC00500

VIPer50A-E/ASP-E 8 Package Mechanical Data

23/31

8 Package M echani ca l Data

In order to meet environmen tal requirements, ST offe rs these devices in ECOPACK®

packages. These packages have a Lead-free second level interconn ect . The category of

second Level Interconnect is marked on the package and on the inner box label, in compliance

w ith JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also

marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifi cations are

available at: www.st.com.

8 P ackage Mechanical Data VIPer50A-E/ASP-E

24/31

Pentawatt HV Mechanical Data

Dim mm. inch

Min. Typ. Maw. Min. Typ. Max.

A 4.30 4.80 0.169 0.189

C 1.17 1.37 0.046 0.054

D 2.40 2.80 0.094 0.11

E 0.35 0.55 0.014 0.022

F 0.60 0.80 0.024 0.031

G1 4.91 5.21 0.193 0.205

G2 7.49 7.80 0.295 0.307

H1 9.30 9.70 0.366 0.382

H2 10.40 0.409

H3 10.05 10.40 0.396 0.409

L 15.60 17.30 6.14 0.681

L1 14.60 15.22 0.575 0.599

L2 21.20 21.85 0.835 0.860

L3 22.20 22.82 0.874 0.898

L5 2.60 3 0.102 0.118

L6 15.10 15.80 0.594 0.622

L7 6 6.60 0.236 0.260

M 2.50 3.10 0.098 0.122

M1 4.50 5.60 0.177 0.220

R0.50 0.02

V4 90°

Diam 3.65 3.85 0.144 0.152

P023H3

VIPer50A-E/ASP-E 8 Package Mechanical Data

25/31

Pentawatt HV 022Y ( Vertical High Pitch ) Mechanical Data

Dim mm. inch

Min. Typ. Maw. Min. Typ. Max.

A 4.30 4.80 0.169 0.189

C 1.17 1.37 0.046 0.054

D 2.40 2.80 0.094 0.110

E 0.35 0.55 0.014 0.022

F 0.60 0.80 0.024 0.031

G1 4.91 5.21 0.193 0.205

G2 7.49 7.80 0.295 0.307

H1 9.30 9.70 0.366 0.382

H2 10.40 0.409

H3 10.05 10.40 0.396 0.409

L 16.42 17.42 0.646 0.686

L1 14.60 15.22 0.575 0.599

L3 20.52 21.52 0.808 0.847

L5 2.60 3.00 0.102 0.118

L6 15.10 15.80 0.594 0.622

L7 6.00 6.60 0.236 0.260

M 2.50 3.10 0.098 0.122

M1 5.00 5.70 0.197 0.224

R 0.50 0.02 0.020

V4 90°90°

Diam 3.65 3.85 0.144 0.154

DIA

LL1

Resin between

leads

8 P ackage Mechanical Data VIPer50A-E/ASP-E

26/31

Figure 25. Pentawatt HV T ube Shipment ( no suffix )

A ll di m e nsions ar e i n mm.

Base Q.ty 50

Bulk Q.ty 1000

Tube lengt h ( ± 0.5 )532

A18

B33.1

C ( ± 0.1)1

VIPer50A-E/ASP-E 8 Package Mechanical Data

27/31

DIM. mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 3.35 3.65 0.132 0.144

A1 0.00 0.10 0.000 0.004

B 0.40 0.60 0.016 0.024

C 0.35 0.55 0.013 0.022

D 9.40 9.60 0.370 0.378

D1 7.40 7.60 0.291 0.300

e 1.27 0.050

E 9.30 9.50 0.366 0.374

E1 7.20 7.40 0.283 0.291

E2 7.20 7.60 0.283 0.300

E3 6.10 6.35 0.240 0.250

E4 5.90 6.10 0.232 0.240

F 1.25 1.35 0.049 0.053

h 0.50 0.002

H 13.80 14.40 0.543 0.567

L 1.20 1.80 0.047 0.071

q 1.70 0.067

α0o8o

DETAIL "A"

PLANE

SEATING

= =

0.10 A

E1E3

= =

DETAIL "A"

SEATING

PLANE

= =

610

0.25

= =

0068039-C

PowerSO-10 MEC HANICAL DATA

8 P ackage Mechanical Data VIPer50A-E/ASP-E

28/31

PowerSO-10™ SUGGESTED PAD LAYOUT

TAPE AND REEL SHI PMENT (suffix “13TR”)

REEL DIMENSIONS

All dimensions are in mm.

Base Q.ty 600

Bulk Q.ty 600

A (max) 330

B (min) 1.5

C (± 0.2) 13

F20.2

G (+ 2 / -0) 24.4

N (min) 60

T (max) 30.4

TAPE DIMENSI ONS

According to Electronic Industries Association

(EIA) Standard 481 rev. A, Feb. 1986

All dimensions are in mm.

Tape width W 24

Tape Hole Spacing P0 (± 0.1) 4

Component Spacing P 24

Hole Diameter D (± 0.1/-0) 1.5

Hole Diameter D1 (min) 1.5

Hole Position F (± 0.05) 11.5

Compartment Depth K (max) 6.5

Hole Spacing P1 (± 0.1) 2

Top

cover

tape

End

Start

No com pone ntsNo components Components

500mm min

Empt y components pockets

saled with cover tape.

User direction of feed

6.30

10.8 - 11

14.6 - 14.9

51.27

0.67 - 0 . 7

0.54 - 0.

All dimensions are in mm.

Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.1)

Casablanca 50 1000 532 10.4 16.4 0.8

Muar 50 1000 532 4.9 17.2 0.8

TUBE SHIPMENT (no suffix)

MUARCASABLANCA

VIPer50A-E/ASP-E 9 Order Codes

29/31

9 Order Codes

PENTAWATT HV PENTAWATT HV (022Y) PowerSO-10

VIPer50A-E VIPer50A-22-E VIPer50ASP-E

10 Revisi on history VIPer50A-E/ASP-E

30/31

10 Revision history

Date Revision Changes

26-Sep-2005 1 In it i al r elease.

VIPer50A-E/ASP-E 10 Revisi on history

31/31

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o change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are n

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