Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1
Rev. C
11/03/2017
Copyright © 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specication and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specication before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to signicantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
FEATURES
• Internalself-timedwritecycle
• IndividualByteWriteControlandGlobalWrite
• Clockcontrolled,registeredaddress,dataand
control
• BurstsequencecontrolusingMODEinput
• Threechipenableoptionforsimpledepthex-
pansionandaddresspipelining
• Commondatainputsanddataoutputs
• AutoPower-downduringdeselect
• Singlecycledeselect
• SnoozeMODEforreduced-powerstandby
• JTAGBoundaryScanforBGApackage
• PowerSupply
LPS:Vdd 3.3V (+ 5%), Vddq 3.3V/2.5V (+ 5%)
VPS:Vdd 2.5V (+ 5%), Vddq 2.5V (+ 5%)
VVPS:Vdd 1.8V (+ 5%), Vddq 1.8V (+ 5%)
• JEDEC100-PinQFP,119-ballBGA,and165-
ballBGApackages
• Lead-freeavailable
DESCRIPTION
The36Mbproductfamilyfeatures high-speed,low-power
synchronousstatic
RAMs
designedtoprovideburstable,
high-performance
memory for communication and net-
working applications.The IS61LPS/VPS102436B and
IS64LPS102436Bareorganizedas1,048,476wordsby
36bits.TheIS61LPS102432Bisorganizedas1,048,476
wordsby32bits.TheIS61LPS/VPS204818Bisorganized
as2,096,952wordsby18bits.FabricatedwithISSI's
advanced CMOS technology, the device integrates a
2-bitburstcounter,high-speedSRAMcore,andhigh-
drivecapabilityoutputsintoasinglemonolithiccircuit.All
synchronousinputspassthroughregisterscontrolledby
apositive-edge-triggeredsingleclockinput.
Writecyclesareinternallyself-timedandareinitiatedby
therisingedgeoftheclockinput.Writecyclescanbe
onetofourbyteswideascontrolledbythewritecontrol
inputs.
Separatebyteenablesallowindividualbytestobewritten.
Thebytewriteoperationisperformedbyusingthebyte
writeenable(BWE)inputcombined withoneormore
individualbytewritesignals(BWx). Inaddition,Global
Write(GW)isavailableforwritingallbytesatonetime,
regardlessofthebytewritecontrols.
BurstscanbeinitiatedwitheitherADSP(AddressStatus
Processor)orADSC(AddressStatusCacheController)
inputpins.Subsequentburstaddressescanbegener-
atedinternallyandcontrolledbytheADV(burstaddress
advance)inputpin.
Themodepinisusedtoselecttheburstsequenceor-
der,LinearburstisachievedwhenthispinistiedLOW.
InterleaveburstisachievedwhenthispinistiedHIGH
orleftoating.
1M x 36, 1M x 32, 2M x 18
36 Mb SYNCHRONOUS PIPELINED,
SINGLE CYCLE DESELECT STATIC RAM
NOVEMBER 2017
Symbol Parameter 250 200 166 Units
tkq Clock Access Time 2.8 3.1 3.8 ns
tkc Cycle Time 4 5 6 ns
Frequency 250 200 166 MHz
FAST ACCESS TIME
2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
BLOCK DIAGRAM
CLK
/CKE
/CE
CE2
/CE2
/CE
/CLR
/ADV
/ADSC
/ADSP
/GW
/BWE
/BW(a-x)
x18:x=b,
x32,x36:x=d
/CE
CLK
ADDRESS
REGISTER
D Q
A0-x
x18: x=20
x36: x=19
18/19
20/21
CLK
DQ(a-d)
BYTE WRITE
REGISTERS
D Q
CLK
ENABLE
REGISTERS
D Q
CLK
ENABLE DELAY
REGISTERS
D Q
/OE
CLK
INPUT
REGISTER
Q0
Q1
BINARY
COUNTER
MODE
A0`
A1`
A0
A1
1Mx36;
2Mx18
Memory Array
CLK
OUTPUT
REGISTER DQ(a-x)
x18:x=b,
x32,x36:x=d
Power
Down
ZZ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 3
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
BOTTOMVIEW
BOTTOMVIEW
165-PIN BGA
165-Ball,13x15mmBGA
119-PIN BGA
119-Ball,14x22mmBGA
4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
119 BGA PACKAGE PIN CONFIGURATION-1M x 36 (TOP VIEW)
PIN DESCRIPTIONS
1 2 3 4 5 6 7
AVDDQ A A ADSP A A VDDQ
BNC A A ADSC A A NC
CNC A A VDD A A NC
DDQc DQPc Vss NC Vss DQPb DQb
EDQc DQc Vss CE Vss DQb DQb
FVDDQ DQc Vss OE Vss DQb VDDQ
GDQc DQc BWc ADV BWb DQb DQb
HDQc DQc Vss GW Vss DQb DQb
JVDDQ VDD NC VDD NC VDD VDDQ
KDQd DQd Vss CLK Vss DQa DQa
LDQd DQd BWd NC BWa DQa DQa
MVDDQ DQd Vss BWE Vss DQa VDDQ
NDQd DQd Vss A1*Vss DQa DQa
PDQd DQPd Vss A0*Vss DQPa DQa
RNC A MODE VDD NC A NC
TNC NC A A A A ZZ
UVDDQ TMS TDI TCK TDO NC VDDQ
Symbol Pin Name
A SynchronousAddressInputs
A0,A1 SynchronousBurstAddressInputs
ADV SynchronousBurstAddress
Advance
ADSP SynchronousAddressStatusProcessor
ADSC SynchronousAddressStatusController
GW SynchronousGlobalWriteEnable
CLK SynchronousClock
CE,CE2 SynchronousChipSelect
BWa-BWd SynchronousByteWriteControls
BWE SynchronousByteWriteEnable
Symbol Pin Name
OEAsynchronousOutputEnable
ZZ AsynchronousPowerSleepMode
MODE BurstSequenceSelection
TCK,TDO JTAGPins
TMS,TDI
NC NoConnect
DQa-DQd Synchronous Data Inputs/Outputs
DQPa-DQPd Synchronous Parity Data
Inputs/Outputs
Vdd PowerSupply
Vddq I/OPowerSupply
Vss Ground
Note: *A0andA1arethetwoleastsignicantbits(LSB)oftheaddresseldandsettheinternalburstcounterifburstisdesired.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 5
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
119 BGA PACKAGE PIN CONFIGURATION
2Mx18 (TOP VIEW)
PIN DESCRIPTIONS
Note: *A0andA1arethetwoleastsignicantbits(LSB)oftheaddresseldandsettheinternalburstcounterifburstisdesired.
1 2 3 4 5 6 7
AVDDQ A A ADSP A A VDDQ
BNC A A ADSC A A NC
CNC A A VDD A A NC
DDQb NC Vss NC Vss DQPa NC 
ENC DQb Vss CE Vss NC DQa
FVDDQ NC Vss OE Vss DQa VDDQ
GNC DQb BWb ADV Vss NC DQa
HDQb NC Vss GW Vss DQa NC
JVDDQ VDD NC VDD NC VDD VDDQ
KNC DQb Vss CLK Vss NC DQa
LDQb NC Vss NC BWa DQa NC
MVDDQ DQb Vss BWE Vss NC VDDQ
NDQb NC Vss A1*Vss DQa NC
PNC DQPb Vss A0*Vss NC DQa
RNC A MODE VDD NC A NC
TNC A A A A A ZZ
UVDDQ TMS TDI TCK TDO NC VDDQ
Symbol Pin Name
A SynchronousAddressInputs
A0,A1 SynchronousBurstAddressInputs
ADV SynchronousBurstAddress
Advance
ADSP SynchronousAddressStatusProcessor
ADSC SynchronousAddressStatusController
GW SynchronousGlobalWriteEnable
CLK SynchronousClock
CE,CE2 SynchronousChipSelect
BWa-BWb SynchronousByteWriteControls
BWE SynchronousByteWriteEnable
Symbol Pin Name
OEAsynchronous OutputEnable
ZZ Asynchronous PowerSleepMode
MODE BurstSequenceSelection
TCK,TDO JTAGPins
TMS,TDI
NC NoConnect
DQa-DQb Synchronous Data Inputs/Outputs
DQPa-DQPb Synchronous Parity Data
Inputs/Outputs
Vdd PowerSupply
Vddq I/OPowerSupply
Vss Ground
6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
PIN DESCRIPTIONS
165 BGA PACKAGE PIN CONFIGURATION
1M x 36 (TOP VIEW)
Note: *A0andA1arethetwoleastsignicantbits(LSB)oftheaddresseldandsettheinternalburstcounterifburstisdesired.
1 2 3 4 5 6 7 8 9 10 11
ANC A CE BWc BWb CE2 BWE ADSC ADV A NC
BNC A CE2 BWd BWa CLK GW OE ADSP A NC
CDQPc NC Vddq Vss Vss Vss Vss Vss Vddq NC DQPb
DDQc DQc Vddq Vdd Vss Vss Vss Vdd Vddq DQb DQb
EDQc DQc Vddq Vdd Vss Vss Vss Vdd Vddq DQb DQb
FDQc DQc Vddq Vdd Vss Vss Vss Vdd Vddq DQb DQb
GDQc DQc Vddq Vdd Vss Vss Vss Vdd Vddq DQb DQb
HNC NC NC Vdd Vss Vss Vss Vdd NC NC ZZ
JDQd DQd Vddq Vdd Vss Vss Vss Vdd Vddq dqadqa
KDQd DQd Vddq Vdd Vss Vss Vss Vdd Vddq dqadqa
LDQd DQd Vddq Vdd Vss Vss Vss Vdd Vddq dqadqa
MDQd DQd Vddq Vdd Vss Vss Vss Vdd Vddq dqadqa
NDQPd NC Vddq Vss NC A NC Vss Vddq N C  DQPa
PNC NC A A TDI A1*TDO A A A A
RMODE A A A TMS A0*TCK A A A A
Symbol Pin Name
A SynchronousAddressInputs
A0,A1 SynchronousBurstAddressInputs
ADV SynchronousBurstAddress
Advance
ADSP SynchronousAddressStatusProcessor
ADSC SynchronousAddressStatusController
GW SynchronousGlobalWriteEnable
CLK SynchronousClock
CE, CE2, CE2 SynchronousChipSelect
BWa-BWd SynchronousByteWriteControls
Symbol Pin Name
BWE SynchronousByteWriteEnable
OEAsynchronousOutputEnable
ZZ AsynchronousPowerSleepMode
MODE BurstSequenceSelection
TCK,TDO JTAGPins
TMS,TDI
NC NoConnect
DQa-DQd Synchronous Data Inputs/Outputs
DQPa-DQPd Synchronous Parity Data
Inputs/Outputs
Vdd PowerSupply
Vddq I/OPowerSupply
Vss Ground
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 7
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
Note: *A0andA1arethetwoleastsignicantbits(LSB)oftheaddresseldandsettheinternalburstcounterifburstisdesired.
165 BGA PACKAGE PIN CONFIGURATION
2M x 18 (TOP VIEW)
PIN DESCRIPTIONS
1 2 3 4 5 6 7 8 9 10 11
ANC A CE BWb NC CE2 BWE ADSC ADV A A
BNC A CE2 NC BWa CLK GW OE ADSP A NC
CNC NC Vddq Vss Vss Vss Vss Vss Vddq NC DQPa
DNC DQb Vddq Vdd Vss Vss Vss Vdd Vddq NC DQa
ENC DQb Vddq Vdd Vss Vss Vss Vdd Vddq NC DQa
FNC DQb Vddq Vdd Vss Vss Vss Vdd Vddq NC DQa
GNC DQb Vddq Vdd Vss Vss Vss Vdd Vddq NC DQa
HNC NC NC Vdd Vss Vss Vss Vdd NC NC ZZ
JDQb NC Vddq Vdd Vss Vss Vss Vdd Vddq dqaNC
KDQb NC Vddq Vdd Vss Vss Vss Vdd Vddq dqaNC
LDQb NC Vddq Vdd Vss Vss Vss Vdd Vddq dqaNC
MDQb NC Vddq Vdd Vss Vss Vss Vdd Vddq dqaNC
NDQPb NC Vddq Vss NC A NC Vss Vddq NC NC
PNC NC A A TDI A1*TDO A A A A
RMODE A A A TMS A0*TCK A A A A
Symbol Pin Name
A SynchronousAddressInputs
A0,A1 SynchronousBurstAddressInputs
ADV SynchronousBurstAddress
Advance
ADSP SynchronousAddressStatusProcessor
ADSC SynchronousAddressStatusController
GW SynchronousGlobalWriteEnable
CLK SynchronousClock
CE, CE2, CE2 SynchronousChipSelect
BWa-BWb SynchronousByteWriteControls
Symbol Pin Name
BWE SynchronousByteWriteEnable
OEAsynchronousOutputEnable
ZZ AsynchronousPowerSleepMode
MODE BurstSequenceSelection
TCK,TDO JTAGPins
TMS,TDI
NC NoConnect
DQa-DQb Synchronous Data Inputs/Outputs
DQPa-DQPb Synchronous Parity Data
Inputs/Outputs
Vdd 3.3V/2.5VPowerSupply
Vddq I/OPowerSupply
Vss Ground
8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
DQPb
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
DQPa
A
A
CE
CE2
BWd
BWc
BWb
BWa
CE2
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
DQPc
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A
A
A
A
A1
A0
NC
A
VSS
VDD
A
A
A
A
A
A
A
A
A
46 47 48 49 50
PIN DESCRIPTIONS
A0,A1 SynchronousAddressInputs.These
pinsmusttiedtothetwoLSBsofthe
addressbus.
A SynchronousAddressInputs
ADSC
SynchronousControllerAddressStatus
ADSP
SynchronousProcessorAddressStatus
ADV
SynchronousBurstAddressAdvance
BWa-BWd SynchronousByteWriteEnable
BWE SynchronousByteWriteEnable
CE, CE2, CE2 SynchronousChipEnable
CLK SynchronousClock
DQa-DQd Synchronous Data Inputs/Outputs
DQPa-DQPd Synchronous Parity Data
Inputs/Outputs
GW SynchronousGlobalWriteEnable
MODE BurstSequenceModeSelection
OE AsynchronousOutputEnable
Vdd PowerSupply
Vddq I/OPowerSupply
Vss Ground
ZZ AsynchronousSnoozeEnable
PIN CONFIGURATION
(3 Chip-Enable option)
100-PIN QFP (1M x 36)
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 9
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
NC
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
NC
A
A
CE
CE2
BWd
BWc
BWb
BWa
CE2
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
NC
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A
A
A
A
A1
A0
NC
A
VSS
VDD
A
A
A
A
A
A
A
A
A
46 47 48 49 50
PIN DESCRIPTIONS
A0,A1 SynchronousAddressInputs.These
pinsmusttiedtothetwoLSBsofthe
addressbus.
A SynchronousAddressInputs
ADSC
SynchronousControllerAddressStatus
ADSP
SynchronousProcessorAddressStatus
ADV
SynchronousBurstAddressAdvance
BWa-BWd SynchronousByteWriteEnable
BWE SynchronousByteWriteEnable
CE, CE2, CE2 SynchronousChipEnable
CLK SynchronousClock
DQa-DQd Synchronous Data Inputs/Outputs
GW SynchronousGlobalWriteEnable
MODE BurstSequenceModeSelection
OE AsynchronousOutputEnable
Vdd PowerSupply
Vddq I/OPowerSupply
Vss Ground
ZZ AsynchronousSnoozeEnable
PIN CONFIGURATION
(3 Chip-Enable option)
100-PIN QFP (1M x 32)
10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
PIN CONFIGURATION
(3 Chip-Enable Option)
PIN DESCRIPTIONS
A0,A1 SynchronousAddressInputs.These
pinsmusttiedtothetwoLSBsofthe
addressbus.
A SynchronousAddressInputs
ADSC
SynchronousControllerAddressStatus
ADSP
SynchronousProcessorAddressStatus
ADV
SynchronousBurstAddressAdvance
BWa-BWb SynchronousByteWriteEnable
BWE SynchronousByteWriteEnable
CE,CE2,CE2 SynchronousChipEnable
CLK SynchronousClock
DQa-DQb Synchronous Data Inputs/Outputs
DQPa-DQPb Synchronous Parity Data
Inputs/Outputs
GW SynchronousGlobalWriteEnable
MODE BurstSequenceModeSelection
OE AsynchronousOutputEnable
Vdd PowerSupply
Vddq I/OPowerSupply
Vss Ground
ZZ AsynchronousSnoozeEnable
100-PIN QFP (2M x 18)
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
A
A
CE
CE2
NC
NC
BWb
BWa
CE2
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
NC
NC
NC
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
DQb
DQb
NC
VDD
NC
VSS
DQb
DQb
VDDQ
VSS
DQb
DQb
DQPb
NC
VSS
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A
A
A
A
A1
A0
NC
A
VSS
VDD
A
A
A
A
A
A
A
A
A
46 47 48 49 50
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 11
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
PARTIAL TRUTH TABLE
Function GW BWE BWa BWb BWc BWd
Read H H X X X X
Read H L H H H H
WriteByte1 H L L H H H
WriteAllBytes H L L L L L
WriteAllBytes L X X X X X
TRUTH TABLE(1-8)
OPERATION ADDRESS
CE
CE2
CE2 ZZ
ADSP
ADSC
ADV
WRITE
OE
CLK DQ
DeselectCycle,Power-Down None H X X L X L X X X L-H High-Z
DeselectCycle,Power-Down None L X L L L X X X X L-H High-Z
DeselectCycle,Power-Down None L H X L L X X X X L-H High-Z
DeselectCycle,Power-Down None L X L L H L X X X L-H High-Z
DeselectCycle,Power-Down None L H X L H L X X X L-H High-Z
SnoozeMode,Power-Down None X X X H X X X X X X High-Z
ReadCycle,BeginBurst External L L H L L X X X L L-H Q
ReadCycle,BeginBurst External L L H L L X X X H L-H High-Z
WriteCycle,BeginBurst External L L H L H L X L X L-H D
ReadCycle,BeginBurst External L L H L H L X H L L-H Q
ReadCycle,BeginBurst External L L H L H L X H H L-H High-Z
ReadCycle,ContinueBurst Next X X X L H H L H L L-H Q
ReadCycle,ContinueBurst Next X X X L H H L H H L-H High-Z
ReadCycle,ContinueBurst Next H X X L X H L H L L-H Q
ReadCycle,ContinueBurst Next H X X L X H L H H L-H High-Z
WriteCycle,ContinueBurst Next X X X L H H L L X L-H D
WriteCycle,ContinueBurst Next H X X L X H L L X L-H D
ReadCycle,SuspendBurst Current X X X L H H H H L L-H Q
ReadCycle,SuspendBurst Current X X X L H H H H H L-H High-Z
ReadCycle,SuspendBurst Current H X X L X H H H L L-H Q
ReadCycle,SuspendBurst Current H X X L X H H H H L-H High-Z
WriteCycle,SuspendBurst Current X X X L H H H L X L-H D
WriteCycle,SuspendBurst Current H X X L X H H L X L-H D
NOTE:
1. Xmeans“Don’tCare.”HmeanslogicHIGH.LmeanslogicLOW.
2. ForWRITE,Lmeansoneormorebytewriteenablesignals(BWa-d)andBWEareLOWorGWisLOW.WRITE=Hforall
BWx,BWE,GWHIGH.
3. BWaenablesWRITEstoDQa’sandDQPa.BWbenablesWRITEstoDQb’sandDQPb.BWcenablesWRITEstoDQc’s and
DQPc.BWdenablesWRITEstoDQd’sandDQPd.DQPaandDQPbareavailableonthex18version. DQPa-DQPdareavail-
ableonthex36version.
4. AllinputsexceptOEandZZmustmeetsetupandholdtimesaroundtherisingedge(LOWtoHIGH)ofCLK.
5. Waitstatesareinsertedbysuspendingburst.
6. ForaWRITEoperationfollowingaREADoperation,OEmustbeHIGHbeforetheinputdatasetuptimeandheldHIGHduring
theinputdataholdtime.
7. ThisdevicecontainscircuitrythatwillensuretheoutputswillbeinHigh-Zduringpower-up.
8. ADSPLOWalwaysinitiatesaninternalREADattheL-HedgeofCLK.AWRITEisperformedbysettingoneormorebytewrite
enablesignalsandBWELOWorGWLOWforthesubsequentL-HedgeofCLK.SeeWRITEtimingdiagramforclarication.
12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address
A1 A0 A1 A0 A1 A0 A1 A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
LINEAR BURST ADDRESS TABLE (MODE = VSS)
0,0
1,0
0,1A1', A0' = 1,1
POWER UP SEQUENCE
Vddq→Vdd1→I/OPins2
Notes:
1. Vdd can be applied at the same time as Vddq
2. Applying I/O inputs is recommended after Vddq is ready. The inputs of the I/O pins can be applied at the
same time as Vddq provided Vih (level of I/O pins) is lower than Vddq.
POWER-UP INITIALIZATION TIMING
VDD
Device Initialization
power > 1ms Device ready for
normal operation
VDD
VDDQ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 13
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
OPERATING RANGE (IS61/64LPSXXXXX)
Range Ambient Temperature VDD VDDq
Commercial 0°Cto+70°C 3.3V+5%3.3V/2.5V+5%
Industrial –40°Cto+85°C 3.3V+5%3.3V/2.5V+5%
Automotive –40°Cto+125°C 3.3V+5%3.3V/2.5V+5%
OPERATING RANGE (IS61/64VPSXXXXX)
Range Ambient Temperature VDD VDDq
Commercial 0°Cto+70°C 2.5V+5%2.5V+5%
Industrial –40°Cto+85°C 2.5V+5%2.5V+5%
Automotive –40°Cto+125°C 2.5V+5%2.5V+5%
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter LPS Value VPS/VVPS Value Unit
TsTg StorageTemperature –55to+150 –55to+150 °C
Pd PowerDissipation 1.6 1.6 W
IOuT OutputCurrent(perI/O) 100 100 mA
VIN, VOuT VoltageRelativetoVssforI/OPins –0.5toVddq + 0.5 –0.5toVddq + 0.3 V
VIN VoltageRelativetoVssfor –0.5toVdd + 0.5 –0.5toVdd + 0.3 V
forAddressandControlInputs
Vdd VoltageonVddSupplyRelativetoVss –0.5toVdd + 0.5 –0.3toVdd + 0.3 V
Notes:
1.StressgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGSmaycausepermanentdamagetothedevice.
Thisisastressratingonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethoseindicatedin
theoperationalsectionsofthisspecicationisnotimplied.Exposuretoabsolutemaximumratingconditionsforextended
periodsmayaffectreliability.
2.Thisdevicecontainscircuitytoprotecttheinputsagainstdamageduetohighstaticvoltagesorelectricelds;however,
precautionsmaybetakentoavoidapplicationofanyvoltagehigherthanmaximumratedvoltagestothishigh-impedance
circuit.
3.ThisdevicecontainscircuitrythatwillensuretheoutputdevicesareinHigh-Zatpowerup.
OPERATING RANGE (IS61/64VVPSXXXXX)
Range Ambient Temperature VDD VDDq
Commercial 0°Cto+70°C 1.8V+5%1.8V+5%
Industrial –40°Cto+85°C 1.8V+5%1.8V+5%
Automotive –40°Cto+125°C 1.8V+5%1.8V+5%
14 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-250 -200 -166
MAX MAX MAX
Symbol Parameter Test Conditions
Temp. range x18 x36 x18 x36 x18 x36 Uni
t
icc AC Operating Device Selected, Com. 400 400 350 350 320 320 mA
Supply Current OE = Vih, ZZ ≤ Vil, ind. 450 450 400 400 350 350
All Inputs ≤ 0.2V or ≥ Vdd – 0.2V, Auto - - 500 500 450 450
Cycle Time ≥ tkc min.
isb Standby Current Device Deselected, Com. 200 200 200 200 200 200 mA
TTL Input Vdd = Max., Ind. 220 220 220 220 220 220
All Inputs ≤ Vil or ≥ Vih, Auto - - 350 350 350 350
ZZ ≤ Vil, f = Max.
Isbi Standby Current Device Deselected, Com. 180 180 180 180 180 180 mA
cMOs Input Vdd = Max., Ind. 200 200 200 200 200 200
Vin
≤
Vss + 0.2V or ≥Vdd – 0.2V Auto - - 320 320 320 320
f = 0
DC ELECTRICAL CHARACTERISTICS (OverOperatingRange)1,2,3
3.3V 2.5V 1.8V
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit
VOh OutputHIGHVoltage IOh = –4.0mA(3.3V) 2.4 — 2.0 — Vddq - 0.4 — V
 IOh = –1.0mA(2.5V,1.8V)
VOl OutputLOWVoltage IOl = 8.0mA(3.3V) — 0.4 — 0.4 — 0.4 V
 IOl = 1.0mA(2.5V,1.8V)
VIh InputHIGHVoltage 2.0 Vdd +0.3 1.7 Vdd + 0.3 0.6Vdd Vdd + 0.3 V
VIl InputLOWVoltage -0.3 0.8 -0.3 0.7 -0.3 0.3VddV
IlI InputLeakageCurrent Vss≤VIN ≤ Vdd(1,4)-5 5 -5 5 -5 5 µA
InputCurrentofMODE Vss≤VIN ≤ Vdd(5)-30 5 -30 5 -30 5
InputCurrentofZZ Vss≤VIN ≤ Vdd(6)-5 30 -5 30 -5 30
IlO OutputLeakageCurrent Vss≤VOuT ≤ Vddq, -5 5 -5 5 -5 5 µA
 OE = VIh
Notes:
1. All voltages referenced to ground.
2. Overshoot:
3.3V and 2.5V: Vih (AC) ≤ Vdd + 1.5V (Pulse width less than tkc /2)
1.8V: Vih (AC) ≤ Vdd + 0.5V (Pulse width less than tkc /2)
3. Undershoot:
3.3V and 2.5V: Vil (AC) ≥ -1.5V (Pulse width less than tkc /2)
1.8V: Vil (AC) ≥ -0.5V (Pulse width less than tkc /2)
4. Except MODE and ZZ
5. MODE is connected to pull-up resister internally.
6. ZZ is connected to pull-down resister internally.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 15
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
CAPACITANCE(1,2)
Symbol Parameter Conditions Max. Unit
CIN InputCapacitance VIN = 0V 6 pF
COuT Input/OutputCapacitance VOuT = 0V 8 pF
Notes:
1.Testedinitiallyandafteranydesignorprocesschangesthatmayaffecttheseparameters.
2. Testconditions:T
a = 25°C, f=1MHz,Vdd=3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter Unit
InputPulseLevel 0Vto3.0V
InputRiseandFallTimes 1.5ns
InputandOutputTiming 1.5V
andReferenceLevel
OutputLoad SeeFigures1and2
AC TEST LOADS
Figure 2
317 Ω
5 pF
Including
jig and
scope
351 Ω
OUTPUT
3.3V
Figure 1
Output
Z
O
= 50Ω
1.5V
50Ω
16 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
2.5V I/O AC TEST CONDITIONS
Parameter Unit
InputPulseLevel 0Vto2.5V
InputRiseandFallTimes 1.5ns
InputandOutputTiming 1.25V
andReferenceLevel
OutputLoad SeeFigures3and4
Figure 4
1,667 Ω
5 pF
Including
jig and
scope
1,538 Ω
OUTPUT
2.5V
Figure 3
Output
Z
O
= 50Ω
1.25V
50Ω
2.5 I/O OUTPUT LOAD EQUIVALENT
1.8V I/O AC TEST CONDITIONS
Parameter Unit
InputPulseLevel 0Vto1.8V
InputRiseandFallTimes 1.5ns
InputandOutputTiming 0.9V
andReferenceLevel
OutputLoad SeeFigures5and6
Figure 6
1K Ω
5 pF
Including
jig and
scope
1K Ω
OUTPUT
1.8V
Figure 5
Output
Z
O
= 50Ω
0.9V
50Ω
1.8 I/O OUTPUT LOAD EQUIVALENT
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 17
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (OverOperatingRange)
-250 -200 -166
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
fMax ClockFrequency — 250 — 200 — 166 MHz
tkC CycleTime 4.0 — 5 — 6 — ns
tkh ClockHighTime 1.7 — 2 — 2.4 — ns
tkl ClockLowTime 1.7 — 2 — 2.3 — ns
tkq ClockAccessTime — 2.8 — 3.1 — 3.8 ns
tkqx(2) ClockHightoOutputInvalid 0.8 — 1.5 — 1.5 — ns
tkqlZ(2,3) ClockHightoOutputLow-Z 0.8 — 1 — 1.5 — ns
tkqhZ(2,3) ClockHightoOutputHigh-Z — 2.8 — 3.1 — 3.8 ns
tOEq OutputEnabletoOutputValid — 2.8 — 3.1 — 3.8 ns
tOElZ(2,3) OutputEnabletoOutputLow-Z 0 — 0 — 0 — ns
tOEhZ(2,3) OutputDisabletoOutputHigh-Z — 2.8 — 3.1 — 3.8 ns
tas AddressSetupTime 1.4 — 1.4 — 1.5 — ns
tss AddressStatusSetupTime 1.4 — 1.4 — 1.5 — ns
tWs Read/WriteSetupTime 1.4 — 1.4 — 1.5 — ns
tCEs ChipEnableSetupTime 1.4 — 1.4 — 1.5 — ns
taVs AddressAdvanceSetupTime 1.4 — 1.4 — 1.5 — ns
tds DataSetupTime 1.4 — 1.4 — 1.5 — ns
tah AddressHoldTime 0.4 — 0.4 — 0.5 — ns
tsh AddressStatusHoldTime 0.4 — 0.4 — 0.5 — ns
tWh WriteHoldTime 0.4 — 0.4 — 0.5 — ns
tCEh ChipEnableHoldTime 0.4 — 0.4 — 0.5 — ns
taVh AddressAdvanceHoldTime 0.4 — 0.4 — 0.5 — ns
tdh DataHoldTime 0.4 — 0.4 — 0.5 — ns
tPOWEr
(4)
Vdd(typical)toFirstAccess 1 — 1 — 1 — ms
Note:
1.CongurationsignalMODEisstaticandmustnotchangeduringnormaloperation.
2.Guaranteedbutnot100%tested.Thisparameterisperiodicallysampled.
3. TestedwithloadinFigure2.
4. tpOwer is the time that the power needs to be supplied above Vdd (min) initially before READ or WRITE operation can be
initiated.
18 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
READ CYCLE TIMING
Single Read
High-Z
High-Z
DATAOUT
DATAIN
OE
CE2
CE2
CE
BWx
BWE
GW
Address
ADV
ADSC
ADSP
CLK
RD1 RD2
1a 2c 2d
Unselected
Burst Read
t
KQX
t
KC
t
KL
t
KH
t
SS
t
SH
t
SS
t
SH
t
AS
t
AH
t
WS
t
WH
t
WS
t
WH
RD3
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
CE2 and CE2 only sampled with ADSP or ADSC
CE Masks ADSP
Unselected with CE2
t
OEQ
t
OELZ
t
KQLZ
t
KQ
t
OEHZ
t
KQHZ
ADSC initiate read
ADSP is blocked by CE inactive
t
AVH
t
AVS
Suspend Burst
Pipelined Read
2a 2b
t
SS
t
SH
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 19
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
WRITE CYCLE TIMING
Single Write
DATAOUT
DATAIN
OE
CE2
CE2
CE
BWx
BWE
GW
Address
ADV
ADSC
ADSP
CLK
WR1WR2
Unselected
Burst Write
t
KC
t
KL
t
KH
t
SS
t
SH
t
AS
t
AH
t
WS
t
WH
t
WS
t
WH
WR3
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
CE2 and CE2 only sampled with ADSP or ADSC
CE Masks ADSP
Unselected with CE2
ADSC initiate Write
ADSP is blocked by CE inactive
t
AVH
t
AVS
ADV must be inactive for ADSP Write
WR1WR2
t
WS
t
WH
WR3
t
WS
t
WH
High-Z
High-Z 1a 3a
t
DS
t
DH
BW4-BW1 only are applied to first cycle of WR2
Write
2c 2d2a 2b
20 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
SNOOZE MODE TIMING
Don't Care
Deselect or Read Only Deselect or Read Only
tRZZI
CLK
ZZ
Isupply
All Inputs
(except ZZ)
Outputs
(Q)
ISB2
ZZ setup cycle ZZ recovery cycle
Normal
operation
cycle
tPDS tPUS
tZZI
High-Z
SNOOZE MODE ELECTRICAL CHARACTERISTICS
Symbol Parameter Conditions Temperature Min. Max. Unit
Range
Isb2 CurrentduringSNOOZEMODE ZZ ≥ Vdd - 0.2V Com. — 120 mA
Ind. — 130
Auto. — 250
tPds ZZactivetoinputignored — 2 cycle
tPus ZZinactivetoinputsampled 2 — cycle
tZZI ZZactivetoSNOOZEcurrent — 2 cycle
trZZI ZZinactivetoexitSNOOZEcurrent 0 — ns
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 21
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG)
TheserialboundaryscanTestAccessPort(TAP)isonly
available in the BGA package. (The QFP package not
available.)This port operates in accordance with
IEEE
Standard1149.1-1900,butdoesnotincludeallfunctions
requiredforfull1149.1compliance.Thesefunctionsfrom
the
IEEE specication
are excluded because they place
addeddelayinthecriticalspeedpathoftheSRAM.The
TAPcontrolleroperatesinamannerthatdoesnotconict
withtheperformanceofotherdevicesusing1149.1fully
compliantTAPs.
DISABLING THE JTAG FEATURE
TheSRAMcanoperatewithoutusingtheJTAGfeature.
To disable the TAP controller, TCK must be tied LOW
(Vss)topreventclockingofthedevice.TDIandTMSare
internallypulledupandmaybedisconnected.Theymay
alternatelybeconnectedtoVddthroughapull-upresistor.
TDOshouldbeleftdisconnected.Onpower-up,thedevice
willstartinaresetstatewhichwillnotinterferewiththe
deviceoperation.
TEST ACCESS PORT (TAP) - TEST CLOCK
ThetestclockisonlyusedwiththeTAPcontroller.Allinputs
arecapturedontherisingedgeofTCKandoutputsare
drivenfromthefallingedgeofTCK.
TEST MODE SELECT (TMS)
TheTMS input is used to send commands to theTAP
controllerandissampledontherisingedgeofTCK.This
pinmaybeleftdisconnectediftheTAPisnotused.Thepin
isinternallypulledup,resultinginalogicHIGHlevel.
TEST DATA-IN (TDI)
TheTDI pin is used to serially input information to the
registersandcanbeconnectedtotheinputofanyregis-
ter.TheregisterbetweenTDIandTDOischosenbythe
instruction loaded into theTAP instruction register. For
informationon instructionregister loading,seetheTAP
ControllerStateDiagram.TDIisinternallypulledupand
canbedisconnectediftheTAPisunusedinanapplica-
tion.TDIisconnectedtotheMostSignicantBit(MSB)
onanyregister.
TAP CONTROLLER BLOCK DIAGRAM
22 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
TEST DATA OUT (TDO)
TheTDOoutputpinisusedtoseriallyclockdata-outfrom
theregisters.Theoutputisactivedependingonthecurrent
stateofthe
TA P
statemachine(see
TA P
ControllerState
Diagram).TheoutputchangesonthefallingedgeofTCK
andTDOisconnectedtotheLeastSignicantBit(LSB)
ofanyregister.
PERFORMING A TAP RESET
AResetisperformedbyforcingTMSHIGH(Vdd)forve
risingedgesofTCK.RESETmaybeperformedwhilethe
SRAMisoperatinganddoesnotaffectitsoperation.At
power-up,theTAPisinternallyresettoensurethatTDO
comesupinahigh-Zstate.
TAP REGISTERS
RegistersareconnectedbetweentheTDIandTDOpins
andallowdatatobescannedintoandoutoftheSRAM
testcircuitry. Onlyoneregistercanbeselectedatatime
throughtheinstructionregisters.Dataisseriallyloaded
intotheTDIpinontherisingedgeofTCKandoutputon
theTDOpinonthefallingedgeofTCK.
Instruction Register
Three-bitinstructionscanbeseriallyloadedintothein-
structionregister.Thisregisterisloadedwhenitisplaced
betweenthe
TDI
and
TDO
pins.(See
TA P
ControllerBlock
Diagram) Atpower-up,theinstructionregisterisloaded
with the IDCODE instruction. It is also loaded with the
IDCODEinstructionifthecontrollerisplacedinareset
stateaspreviouslydescribed.
WhentheTAPcontrollerisintheCapture-IRstate,thetwo
leastsignicantbitsareloadedwithabinary“01”pattern
toallowforfaultisolationoftheboardlevelserialtestpath.
Bypass Register
Tosavetimewhenseriallyshiftingdatathroughregisters,
itissometimesadvantageoustoskipcertainstates.The
bypassregisterisasingle-bitregisterthatcanbeplaced
betweenTDIandTDOpins.Thisallowsdatatobeshifted
through the
SRAM
with minimal delay.The bypass reg-
isteris setLOW(Vss)when theBYPASSinstructionis
executed.
Boundary Scan Register
Theboundaryscanregisterisconnectedtoallinputand
outputpinsonthe
SRAM
.Severalnoconnect
(NC)
pinsare
alsoincludedinthescanregistertoreservepinsforhigher
densitydevices.Thex36congurationhasa75-bit-long
registerandthex18congurationalsohasa75-bit-long
register.The boundary scan register is loaded with the
contentsoftheRAMInputandOutputringwhentheTAP
controllerisintheCapture-DRstateandthenplacedbe-
tweenthe
TDI
and
TDO
pinswhenthecontrollerismoved
tothe
Shift-DR
state.TheEXTEST,SAMPLE/PRELOAD
andSAMPLE-Zinstructionscanbeusedtocapturethe
contentsoftheInputandOutputring.
TheBoundaryScanOrdertablesshowtheorderinwhich
thebitsareconnected.Eachbitcorrespondstooneofthe
bumpsontheSRAMpackage.TheMSBoftheregisteris
connectedtoTDI,andtheLSBisconnectedtoTDO.
Identification (ID) Register
The ID register is loaded with a vendor-specic, 32-bit
codeduringtheCapture-DRstatewhentheIDCODEcom-
mandisloadedtotheinstructionregister.TheIDCODE
ishardwiredintotheSRAMandcanbeshiftedoutwhen
theTAPcontrollerisintheShift-DRstate.TheIDregister
hasvendorcodeandotherinformationdescribedinthe
IdenticationRegisterDenitionstable.
Scan Register Sizes
Register Bit Size Bit Size
Name (x18) (x36)
Instruction 3 3
Bypass 1 1
ID 32 32
BoundaryScan 75 75
IDENTIFICATION REGISTER DEFINITIONS
Instruction Field Description 1M x 36 2M x 18
RevisionNumber (31:28) Reservedforversionnumber. xxxx xxxx
DeviceDepth (27:23) DenesdepthofSRAM.1Mor2M 01001 01010
DeviceWidth (22:18) DeneswidthoftheSRAM.x36orx18 00100 00011
ISSIDeviceID (17:12) Reservedforfutureuse. xxxxx xxxxx
ISSIJEDECID (11:1) AllowsuniqueidenticationofSRAMvendor. 00001010101 00001010101
IDRegisterPresence (0) IndicatethepresenceofanIDregister. 1 1
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 23
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
TAP INSTRUCTION SET
Eightinstructionsarepossiblewiththethree-bitinstruction
registerandallcombinationsare listedintheInstruction
Code table.Three instructions are listed as
RESERVED
andshouldnotbeusedandtheotherveinstructionsare
describedbelow.TheTAPcontrollerusedinthisSRAM
isnotfullycompliantwiththe1149.1conventionbecause
somemandatoryinstructionsarenotfullyimplemented.
TheTAPcontrollercannotbeusedtoloadaddress,dataor
controlsignalsandcannotpreloadthe
Input
or
Output
buf-
fers.The
SRAM
doesnotimplementthe
1149.1
commands
EXTEST
or
INTEST
orthe
PRELOAD
portionof
SAMPLE/
PRELOAD
;insteaditperformsacaptureofthe
Inputsand
Output
ringwhentheseinstructionsareexecuted.Instruc-
tionsareloadedintotheTAPcontrollerduringtheShift-IR
statewhentheinstructionregisterisplacedbetweenTDI
andTDO.Duringthisstate,instructionsareshiftedfrom
theinstructionregisterthroughtheTDIandTDOpins.To
executeaninstructiononceitisshiftedin,theTAPcontrol-
lermustbemovedintotheUpdate-IRstate.
EXTEST
EXTESTisamandatory1149.1instructionwhichistobe
executedwhenevertheinstructionregisterisloadedwith
all0s.BecauseEXTESTisnotimplementedintheTAP
controller,thisdeviceisnot1149.1standardcompliant.
TheTAPcontrollerrecognizesanall-0instruction.Whenan
EXTESTinstructionisloadedintotheinstructionregister,
theSRAMrespondsasifaSAMPLE/PRELOADinstruction
hasbeenloaded.Thereisadifferencebetweentheinstruc-
tions,unlikethe
SAMPLE/PRELOAD
instruction,EXTEST
placestheSRAMoutputsinaHigh-Zstate.
IDCODE
The IDCODE instruction causes a vendor-specic, 32-
bitcodetobeloadedintotheinstructionregister.Italso
placestheinstructionregisterbetweentheTDIandTDO
pinsandallowstheIDCODEtobeshiftedoutofthedevice
when theTAP controller enters the Shift-DR state.The
IDCODEinstructionisloadedintotheinstructionregister
uponpower-uporwhenevertheTAPcontrollerisgivena
testlogicresetstate.
SAMPLE-Z
The SAMPLE-Z instruction causes the boundary scan
registertobeconnectedbetweentheTDIandTDOpins
whentheTAPcontrollerisinaShift-DRstate.Italsoplaces
allSRAMoutputsintoaHigh-Zstate.
SAMPLE/PRELOAD
SAMPLE/PRELOADisa1149.1mandatoryinstruction.The
PRELOADportionofthisinstructionisnotimplemented,so
theTAPcontrollerisnotfully1149.1compliant.Whenthe
SAMPLE/PRELOADinstructionisloadedtotheinstruc-
tionregisterandtheTAPcontrollerisintheCapture-DR
state,asnapshotofdataontheinputsandoutputpinsis
capturedintheboundaryscanregister.
ItisimportanttorealizethattheTAPcontrollerclockoper-
atesatafrequencyupto10MHz,whiletheSRAMclock
runsmorethananorderofmagnitudefaster.Becauseof
theclockfrequencydifferences,itispossiblethatduring
theCapture-DRstate,aninputoroutputwillunder-goa
transition.TheTAPmayattemptasignalcapturewhilein
transition(metastablestate).Thedevicewillnotbeharmed,
butthereisnoguaranteeofthevaluethatwillbecaptured
orrepeatableresults.
Toguaranteethattheboundaryscanregisterwillcapture
thecorrectsignalvalue,theSRAMsignalmustbestabilized
longenoughtomeettheTAPcontroller’scaptureset-up
plusholdtimes(tCsandtCh).ToinsurethattheSRAMclock
inputiscapturedcorrectly,designsneedawaytostop(or
slow)theclockduringaSAMPLE/PRELOADinstruction.
Ifthis isnot anissue,it ispossibleto captureall other
signalsandsimplyignorethevalueoftheCLKcaptured
intheboundaryscanregister.
Oncethedataiscaptured,itispossibletoshiftoutthedata
byputtingtheTAPintotheShift-DRstate.Thisplacesthe
boundaryscanregisterbetweentheTDIandTDOpins.
Notethatsincethe
PRELOAD
partofthecommandisnot
implemented,puttingthe
TA P
intothe
Update
tothe
Update-
DR
statewhileperforminga
SAMPLE/PRELOAD
instruction
willhavethesameeffectasthePause-DRcommand.
BYPASS
When the BYPASS instruction is loaded in the instruc-
tionregister and theTAP is placed in a Shift-DR state,
thebypassregisterisplacedbetweentheTDIandTDO
pins.TheadvantageoftheBYPASSinstructionisthatit
shortenstheboundaryscanpathwhenmultipledevices
areconnectedtogetheronaboard.
RESERVED
Theseinstructionsarenotimplementedbutarereserved
forfutureuse.Donotusetheseinstructions.
24 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
INSTRUCTION CODES
Code Instruction Description
000 EXTEST CapturestheInput/Outputringcontents.Placestheboundaryscanregisterbe-
tweentheTDIandTDO.ForcesallSRAMoutputstoHigh-Zstate.This
instructionisnot1149.1compliant.
001 IDCODE LoadstheIDregisterwiththevendorIDcodeandplacestheregisterbetweenTDI
andTDO.ThisoperationdoesnotaffectSRAMoperation.
010 SAMPLE-Z CapturestheInput/Outputcontents.Placestheboundaryscanregisterbetween
TDIandTDO.ForcesallSRAMoutputdriverstoaHigh-Zstate.
011 RESERVED DoNotUse:Thisinstructionisreservedforfutureuse.
100
SAMPLE/PRELOAD
CapturestheInput/Outputringcontents.Placestheboundaryscanregister
between
TDIandTDO.DoesnotaffecttheSRAMoperation.Thisinstructiondoesnot
implement1149.1preloadfunctionandisthereforenot1149.1compliant.
101 RESERVED DoNotUse:Thisinstructionisreservedforfutureuse.
110 RESERVED DoNotUse:Thisinstructionisreservedforfutureuse.
111 BYPASS PlacesthebypassregisterbetweenTDIandTDO.Thisoperationdoesnot
affectSRAMoperation.
Select DR
Capture DR
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
Select IR
Capture IR
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
Test Logic Reset
Run Test/Idle 11 1
11
11
1
1
11
11
1
0
0
0
0
1
00
0
0
0
0
0
0
0
0
0
10
TAP CONTROLLER STATE DIAGRAM
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 25
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
TAP Electrical Characteristics (Vddq = 1.8V Operating Range)
Symbol Parameter Test Conditions Min. Max. Units
VOh1 Output HIGH Voltage IOh = -1 mA Vdd -0.4 — V
VOl1 Output LOW Voltage IOl = 1 mA — 0.5 V
Vih Input HIGH Voltage 1.3 Vdd +0.3 V
Vil Input LOW Voltage -0.3 0.7 V
Ix Input Load Current Vss ≤ V I ≤ Vddq -30 30 mA
TAP Electrical Characteristics (Vddq = 3.3V Operating Range)
Symbol Parameter Test Conditions Min. Max. Units
VOh1 Output HIGH Voltage IOh = -4 mA 2.4 — V
VOh2 Output HIGH Voltage IOh = -100 µA 2.9 — V
VOl1 Output LOW Voltage IOl = 8 mA — 0.4 V
VOl2 Output LOW Voltage IOl = 100 µA — 0.2 V
Vih Input HIGH Voltage 2.0 Vdd+0.3 V
Vil Input LOW Voltage –0.3 0.8 V
Ix Input Load Current Vss ≤ Vin ≤ Vddq –30 30 mA
TAP Electrical Characteristics (Vddq = 2.5V Operating Range)
Symbol Parameter Test Conditions Min. Max. Units
VOh1 Output HIGH Voltage IOh = -1 mA 2.0 — V
VOh2 Output HIGH Voltage IOh = -100 µA 2.1 — V
VOl1 Output LOW Voltage IOl = 1 mA — 0.4 V
VOl2 Output LOW Voltage IOl = 100 µA — 0.2 V
Vih Input HIGH Voltage 1.7 Vdd+0.3 V
Vil Input LOW Voltage -0.3 0.7 V
Ix Input Load Current Vss ≤ Vin ≤ Vddq –30 30 mA
26 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
DON'T CARE
UNDEFINED
TCK
TMS
TDI
TDO
tTHTL
tTLTH
tTHTH
tMVTH tTHMX
tDVTH tTHDX
1 2 3 4 5 6
tTLOX
tTLOV
TAP TIMING
20 pF
TDO
GND
50Ω
Vtrig
Z0 = 50Ω
TAP Output Load Equivalent
TAP AC TEST CONDITIONS (1.8V/2.5V/3.3V)
Inputpulselevels 0to1.8V/0to2.5V/0to3.0V
Inputriseandfalltimes 1.5ns
Inputtimingreferencelevels 0.9V/1.25V/1.5V
Outputreferencelevels 0.9V/1.25V/1.5V
Testloadterminationsupplyvoltage 0.9V/1.25V/1.5V
Vtrig 0.9V/1.25V/1.5V
Parameter Symbol Min Max Units
TCK cycle time tTHTH 100 – ns
TCK high pulse width tTHTL 40 – ns
TCK low pulse width tTLTH 40 – ns
TMS Setup tMVTH 10 – ns
TMS Hold tTHMX 10 – ns
TDI Setup tDVTH 10 – ns
TDI Hold tTHDX 10 – ns
TCK Low to Valid Data tTLOV – 20 ns
TAP AC ELECTRICAL CHARACTERISTICS (OVER OPERATING RANGE)
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 27
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
BOUNDARY SCAN ORDER
Continued on next page
165 BGA 119 BGA
X36 X18 X36 X18
Bit # Bump ID Signal Bump ID Signal Bit # Bump ID Signal Bump ID Signal
1 N6 A9 N6 A9 1 C7 NC C7 NC
2 N7 NC N7 NC 2 R5 NC R5 NC
3 N10 NC N10 NC 3 R7 NC R7 NC
4P11 A8 P11 A8 4 U6 NC U6 NC
5P8 A18 P8 A18 5 B5 A18 B5 A18
6 R8 A17 R8 A17 6 C6 A17 C6 A17
7 R9 A16 R9 A16 7 T3 A16 T3 A16
8P9 A15 P9 A15 8 T4 A15 T4 A15
9P10 A14 P10 A14 9 T5 A14 T5 A14
10 R10 A13 R10 A13 10 T6 A13 T6 A13
11 R11 A12 R11 A12 11 R6 A12 R6 A12
12 H11 ZZ H11 ZZ 12 T7 ZZ T7 ZZ
13 N11 DQa0 N11 NC 13 P6 DQa0 P6 NC
14 M11 DQa1 M11 NC 14 N7 DQa1 N7 NC
15 L11 DQa2 L11 NC 15 M6 DQa2 M6 NC
16 K11 DQa6 K11 NC 16 L7 DQa6 L7 NC
17 J11 DQa7 J11 NC 17 K6 DQa7 K6 NC
18 M10 DQa3 M10 DQa8 18 P7 DQa3 P7 DQa8
19 L10 DQa4 L10 DQa7 19 N6 DQa4 N6 DQa7
20 K10 DQa5 K10 DQa6 20 L6 DQa5 L6 DQa6
21 J10 DQa8 J10 DQa5 21 K7 DQa8 K7 DQa5
22 H9 NC H9 NC 22 - NC - NC
23 H10 NC H10 NC 23 - NC - NC
24 G11 DQb8 G11 DQa4 24 H6 DQb8 H6 DQa4
25 F11 DQb7 F11 DQa3 25 G7 DQb7 G7 DQa3
26 E11 DQb5 E11 DQa2 26 F6 DQb5 F6 DQa2
27 D11 DQb4 D11 DQa1 27 E7 DQb4 E7 DQa1
28 G10 DQb6 G10 NC 28 H7 DQb6 H7 NC
29 F10 DQb3 F10 NC 29 G6 DQb3 G6 NC
30 E10 DQb2 E10 NC 30 E6 DQb2 E6 NC
31 D10 DQb1 D10 NC 31 D7 DQb1 D7 NC
32 C11 DQb0 C11 DQa0 32 D6 DQb0 D6 DQa0
33 A11 NC A11 A20 33 T1 NC T1 NC
34 B11 NC B11 NC 34 R1 NC R1 NC
35 A10 A11 A10 A11 35 A6 A11 A6 A11
36 B10 A10 B10 A10 36 A5 A10 A5 A10
37 A9 /ADV A9 /ADV 37 G4 /ADV G4 /ADV
38 B9 /ADSP B9 /ADSP 38 A4 /ADSP A4 /ADSP
39 C10 NC C10 NC 39 B7 NC B7 NC
40 A8 /ADSC A8 /ADSC 40 B4 /ADSC B4 /ADSC
41 B8 /OE B8 /OE 41 F4 /OE F4 /OE
42 A7 /BWE A7 /BWE 42 M4 /BWE M4 /BWE
43 B7 /GW B7 /GW 43 H4 /GW H4 /GW
44 B6 CLK B6 CLK 44 K4 CLK K4 CLK
28 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
165 BGA 119 BGA
X36 X18 X36 X18
Bit # Bump ID Signal Bump ID Signal Bit # Bump ID Signal Bump ID Signal
45 A6 /CE2 A6 /CE2 45 B6 A9 B6 A9
46 B5 /Bwa B5 /Bwa 46 L5 /Bwa L5 /Bwa
47 A5 /Bwb A5 NC 47 G5 /Bwb G5 NC
48 A4 /Bwc A4 /Bwb 48 G3 /Bwc G3 /Bwb
49 B4 /Bwd B4 NC 49 L3 /Bwd L3 NC
50 B3 CE2 B3 CE2 50 B2 A8 B2 A8
51 A3 /CE1 A3 /CE1 51 E4 /CE1 E4 /CE1
52 A2 A7 A2 A7 52 A3 A7 A3 A7
53 B2 A6 B2 A6 53 A2 A6 A2 A6
54 C2 NC C2 NC 54 B1 NC B1 NC
55 B1 NC B1 NC 55 C1 NC C1 NC
56 A1 NC A1 NC 56 D4 NC D4 NC
57 C1 DQc0 C1 NC 57 D2 DQc0 D2 NC
58 D1 DQc1 D1 NC 58 E1 DQc1 E1 NC
59 E1 DQc2 E1 NC 59 F2 DQc2 F2 NC
60 F1 DQc6 F1 NC 60 G1 DQc6 G1 NC
61 G1 DQc7 G1 NC 61 H2 DQc7 H2 NC
62 D2 DQc3 D2 DQb8 62 D1 DQc3 D1 DQb8
63 E2 DQc4 E2 DQb7 63 E2 DQc4 E2 DQb7
64 F2 DQc5 F2 DQb6 64 G2 DQc5 G2 DQb6
65 G2 DQc8 G2 DQb5 65 H1 DQc8 H1 DQb5
66 H1 NC H1 NC 66 - NC - NC
67 H2 NC H2 NC 67 - NC - NC
68 H3 NC H3 NC 68 - NC - NC
69 J1 DQd8 J1 DQb4 69 K2 DQd8 K2 DQb4
70 K1 DQd7 K1 DQb3 70 L1 DQd7 L1 DQb3
71 L1 DQd5 L1 DQb2 71 M2 DQd5 M2 DQb2
72 M1 DQd4 M1 DQb1 72 N1 DQd4 N1 DQb1
73 J2 DQd6 J2 NC 73 K1 DQd6 K1 NC
74 K2 DQd3 K2 NC 74 L2 DQd3 L2 NC
75 L2 DQd2 L2 NC 75 N2 DQd2 N2 NC
76 M2 DQd1 M2 NC 76 P1 DQd1 P1 NC
77 N1 DQd0 N1 DQb0 77 P2 DQd0 P2 DQb0
78 N2 NC N2 NC 78 L4 NC L4 NC
79 P1 NC P1 NC 79 J5 NC J5 NC
80 R1 MODE R1 MODE 80 R3 MODE R3 MODE
81 R2 A5 R2 A5 81 C2 A4 C2 A4
82 P3 A4 P3 A4 82 B3 A3 B3 A3
83 R3 A3 R3 A3 83 C3 A2 C3 A2
84 P2 NC P2 NC 84 R2 A5 R2 A5
85 R4 A19 R4 A19 85 C5 A19 C5 A19
86 P4 A2 P4 A2 86 T2 NC T2 A20
87 N5 NC N5 NC 87 J3 NC J3 NC
88 P6 A1 P6 A1 88 N4 A1 N4 A1
89 R6 A0 R6 A0 89 P4 A0 P4 A0
90 * Int * Int 90 * Int * Int
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 29
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
ORDERING INFORMATION
Commercial Range: 0°C to 70°C (VDD = 3.3V / VDDQ = 2.5V/3.3V)
Speed x36 x18 Package
250MHz IS61LPS102436B-250TQ IS61LPS204818B-250TQ 100 QFP
IS61LPS102436B-250B3 IS61LPS204818B-250B3 165 BGA
IS61LPS102436B-250B2 IS61LPS204818B-250B2 119 BGA
IS61LPS102436B-250TQL IS61LPS204818B-250TQL 100 QFP, Lead-free
IS61LPS102436B-250B3L IS61LPS204818B-250B3L 165 BGA, Lead-free
IS61LPS102436B-250B2L IS61LPS204818B-250B2L 119 BGA, Lead-free
200MHz IS61LPS102436B-200TQ IS61LPS204818B-200TQ 100 QFP
IS61LPS102436B-200B3 IS61LPS204818B-200B3 165 BGA
IS61LPS102436B-200B2 IS61LPS204818B-200B2 119 BGA
IS61LPS102436B-200TQL IS61LPS204818B-200TQL 100 QFP, Lead-free
IS61LPS102436B-200B3L IS61LPS204818B-200B3L 165 BGA, Lead-free
IS61LPS102436B-200B2L IS61LPS204818B-200B2L 119 BGA, Lead-free
166MHz IS61LPS102436B-166TQ IS61LPS204818B-166TQ 100 QFP
IS61LPS102436B-166B3 IS61LPS204818B-166B3 165 BGA
IS61LPS102436B-166B2 IS61LPS204818B-166B2 119 BGA
IS61LPS102436B-166TQL IS61LPS204818B-166TQL 100 QFP, Lead-free
IS61LPS102436B-166B3L IS61LPS204818B-166B3L 165 BGA, Lead-free
IS61LPS102436B-166B2L IS61LPS204818B-166B2L 119 BGA, Lead-free
Commercial Range: 0°C to 70°C (VDD = 2.5V / VDDQ = 2.5V)
Speed x36 x18 Package
250MHz IS61VPS102436B-250TQ IS61VPS204818B-250TQ 100 QFP
IS61VPS102436B-250B3 IS61VPS204818B-250B3 165 BGA
IS61VPS102436B-250B2 IS61VPS204818B-250B2 119 BGA
IS61VPS102436B-250TQL IS61VPS204818B-250TQL 100 QFP, Lead-free
IS61VPS102436B-250B3L IS61VPS204818B-250B3L 165 BGA, Lead-free
IS61VPS102436B-250B2L IS61VPS204818B-250B2L 119 BGA, Lead-free
200MHz IS61VPS102436B-200TQ IS61VPS204818B-200TQ 100 QFP
IS61VPS102436B-200B3 IS61VPS204818B-200B3 165 BGA
IS61VPS102436B-200B2 IS61VPS204818B-200B2 119 BGA
IS61VPS102436B-200TQL IS61VPS204818B-200TQL 100 QFP, Lead-free
IS61VPS102436B-200B3L IS61VPS204818B-200B3L 165 BGA, Lead-free
IS61VPS102436B-200B2L IS61VPS204818B-200B2L 119 BGA, Lead-free
166MHz IS61VPS102436B-166TQ IS61VPS204818B-166TQ 100 QFP
IS61VPS102436B-166B3 IS61VPS204818B-166B3 165 BGA
IS61VPS102436B-166B2 IS61VPS204818B-166B2 119 BGA
IS61VPS102436B-166TQL IS61VPS204818B-166TQL 100 QFP, Lead-free
IS61VPS102436B-166B3L IS61VPS204818B-166B3L 165 BGA, Lead-free
IS61VPS102436B-166B2L IS61VPS204818B-166B2L 119 BGA, Lead-free
30 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
Commercial Range: 0°C to 70°C (VDD = 1.8V / VDDQ = 1.8V)
Speed x36 x18 Package
200MHz Please contat ISSI (SRAM@issi.com)
166MHz IS61VVPS102436B-166TQ IS61VVPS204818B-166TQ 100 QFP
IS61VVPS102436B-166B3 IS61VVPS204818B-166B3 165 BGA
IS61VVPS102436B-166B2 IS61VVPS204818B-166B2 119 BGA
IS61VVPS102436B-166TQL IS61VVPS204818B-166TQL 100 QFP, Lead-free
IS61VVPS102436B-166B3L IS61VVPS204818B-166B3L 165 BGA, Lead-free
IS61VVPS102436B-166B2L IS61VVPS204818B-166B2L 119 BGA, Lead-free
Industrial Range: -40°C to +85°C (VDD = 3.3V / VDDQ = 2.5V/3.3V)
Speed x36 x18 Package
250MHz IS61LPS102436B-250TQI IS61LPS204818B-250TQI 100 QFP
IS61LPS102436B-250B3I IS61LPS204818B-250B3I 165 BGA
IS61LPS102436B-250B2I IS61LPS204818B-250B2I 119 BGA
IS61LPS102436B-250TQLI IS61LPS204818B-250TQLI 100 QFP, Lead-free
IS61LPS102436B-250B3LI IS61LPS204818B-250B3LI 165 BGA, Lead-free
IS61LPS102436B-250B2LI IS61LPS204818B-250B2LI 119 BGA, Lead-free
200MHz IS61LPS102436B-200TQI IS61LPS204818B-200TQI 100 QFP
IS61LPS102436B-200B3I IS61LPS204818B-200B3I 165 BGA
IS61LPS102436B-200B2I IS61LPS204818B-200B2I 119 BGA
IS61LPS102436B-200TQLI IS61LPS204818B-200TQLI 100 QFP, Lead-free
IS61LPS102436B-200B3LI IS61LPS204818B-200B3LI 165 BGA, Lead-free
IS61LPS102436B-200B2LI IS61LPS204818B-200B2LI 119 BGA, Lead-free
166MHz IS61LPS102436B-166TQI IS61LPS204818B-166TQI 100 QFP
IS61LPS102436B-166B3I IS61LPS204818B-166B3I 165 BGA
IS61LPS102436B-166B2I IS61LPS204818B-166B2I 119 BGA
IS61LPS102436B-166TQLI IS61LPS204818B-166TQLI 100 QFP, Lead-free
IS61LPS102436B-166B3LI IS61LPS204818B-166B3LI 165 BGA, Lead-free
IS61LPS102436B-166B2LI IS61LPS204818B-166B2LI 119 BGA, Lead-free
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 31
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
Industrial Range: -40°C to +85°C (VDD = 2.5V / VDDQ = 2.5V)
Speed x36 x18 Package
250MHz IS61VPS102436B-250TQI IS61VPS204818B-250TQI 100 QFP
IS61VPS102436B-250B3I IS61VPS204818B-250B3I 165 BGA
IS61VPS102436B-250B2I IS61VPS204818B-250B2I 119 BGA
IS61VPS102436B-250TQLI IS61VPS204818B-250TQLI 100 QFP, Lead-free
IS61VPS102436B-250B3LI IS61VPS204818B-250B3LI 165 BGA, Lead-free
IS61VPS102436B-250B2LI IS61VPS204818B-250B2LI 119 BGA, Lead-free
200MHz IS61VPS102436B-200TQI IS61VPS204818B-200TQI 100 QFP
IS61VPS102436B-200B3I IS61VPS204818B-200B3I 165 BGA
IS61VPS102436B-200B2I IS61VPS204818B-200B2I 119 BGA
IS61VPS102436B-200TQLI IS61VPS204818B-200TQLI 100 QFP, Lead-free
IS61VPS102436B-200B3LI IS61VPS204818B-200B3LI 165 BGA, Lead-free
IS61VPS102436B-200B2LI IS61VPS204818B-200B2LI 119 BGA, Lead-free
166MHz IS61VPS102436B-166TQI IS61VPS204818B-166TQI 100 QFP
IS61VPS102436B-166B3I IS61VPS204818B-166B3I 165 BGA
IS61VPS102436B-166B2I IS61VPS204818B-166B2I 119 BGA
IS61VPS102436B-166TQLI IS61VPS204818B-166TQLI 100 QFP, Lead-free
IS61VPS102436B-166B3LI IS61VPS204818B-166B3LI 165 BGA, Lead-free
IS61VPS102436B-166B2LI IS61VPS204818B-166B2LI 119 BGA, Lead-free
Industrial Range: -40°C to +85°C (VDD = 1.8V / VDDQ = 1.8V)
Speed x36 x18 Package
200MHz IS61VVPS102436B-200TQLI IS61VVPS204818B-200TQLI 100 QFP, Lead-free
IS61VVPS102436B-200B3LI IS61VVPS204818B-200B3LI 165 BGA, Lead-free
166MHz IS61VVPS102436B-166TQI IS61VVPS204818B-166TQI 100 QFP
IS61VVPS102436B-166B3I IS61VVPS204818B-166B3I 165 BGA
IS61VVPS102436B-166B2I IS61VVPS204818B-166B2I 119 BGA
IS61VVPS102436B-166TQLI IS61VVPS204818B-166TQLI 100 QFP, Lead-free
IS61VVPS102436B-166B3LI IS61VVPS204818B-166B3LI 165 BGA, Lead-free
IS61VVPS102436B-166B2LI IS61VVPS204818B-166B2LI 119 BGA, Lead-free
32 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
Automotive(A3) Range: -40°C to +125°C (VDD = 3.3V / VDDQ = 2.5V/3.3V)
Speed x36 x18 Package
200MHz Please contact ISSI (SRAM@issi.com)
166MHz IS64LPS102436B-166TQA3 IS64LPS204818B-166TQA3 100 QFP
IS64LPS102436B-166B3A3 IS64LPS204818B-166B3A3 165 BGA
IS64LPS102436B-166B2A3 IS64LPS204818B-166B2A3 119 BGA
IS64LPS102436B-166TQLA3 IS64LPS204818B-166TQLA3 100 QFP, Lead-free
IS64LPS102436B-166B3LA3 IS64LPS204818B-166B3LA3 165 BGA, Lead-free
IS64LPS102436B-166B2LA3 IS64LPS204818B-166B2LA3 119 BGA, Lead-free
Automotive(A3) Range: -40°C to +125°C (VDD = 2.5V / VDDQ = 2.5V)
Speed x36 x18 Package
200MHz Please contact ISSI (SRAM@issi.com)
166MHz IS64VPS102436B-166TQA3 IS64VPS204818B-166TQA3 100 QFP
IS64VPS102436B-166B3A3 IS64VPS204818B-166B3A3 165 BGA
IS64VPS102436B-166B2A3 IS64VPS204818B-166B2A3 119 BGA
IS64VPS102436B-166TQLA3 IS64VPS204818B-166TQLA3 100 QFP, Lead-free
IS64VPS102436B-166B3LA3 IS64VPS204818B-166B3LA3 165 BGA, Lead-free
IS64VPS102436B-166B2LA3 IS64VPS204818B-166B2LA3 119 BGA, Lead-free
Automotive(A3) Range: -40°C to +125°C (VDD = 1.8V / VDDQ = 1.8V)
Speed x36 x18 Package
Please contact ISSI MKT (SRAM@issi.com)
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 33
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
34 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 35
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
1. CONTROLLING DIMENSION : MM .
NOTE :
Package Outline 08/28/2008