SCAN92LV090 www.ti.com SNLS058I - SEPTEMBER 2000 - REVISED APRIL 2013 SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN Check for Samples: SCAN92LV090 FEATURES DESCRIPTION * * * * The SCAN92LV090A is one in a series of Bus LVDS transceivers designed specifically for the high speed, low power proprietary backplane or cable interfaces. The device operates from a single 3.3V power supply and includes nine differential line drivers and nine receivers. To minimize bus loading, the driver outputs and receiver inputs are internally connected. The separate I/O of the logic side allows for loop back support. The device also features a flow through pin out which allows easy PCB routing for short stubs between its pins and the connector. 1 2 * * * * * * * * * * IEEE 1149.1 (JTAG) Compliant Bus LVDS Signaling Low Power CMOS Design High Signaling Rate Capability (Above 100 Mbps) 0.1V to 2.3V Common Mode Range for VID = 200mV 100 mV Receiver Sensitivity Supports Open and Terminated Failsafe on Port Pins 3.3V Operation Glitch Free Power Up/Down (Driver & Receiver Disabled) Light Bus Loading (5 pF Typical) per Bus LVDS Load Designed for Double Termination Applications Balanced Output Impedance Product Offered in 64 Pin LQFP Package and NFBGA Package High Impedance Bus Pins on Power Off (VCC = 0V) The driver translates 3V TTL levels (single-ended) to differential Bus LVDS (BLVDS) output levels. This allows for high speed operation, while consuming minimal power with reduced EMI. In addition, the differential signaling provides common mode noise rejection of 1V. The receiver threshold is less than 100 mV over a 1V common mode range and translates the differential Bus LVDS to standard (TTL/CMOS) levels. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and test access port consisting of Test Data Input (TDI), Test Data Out (TDO), Test Mode Select (TMS), Test Clock (TCK), and the optional Test Reset (TRST). SIMPLIFIED FUNCTIONAL DIAGRAM D0+/RI+ BLVDS I/O D0-/RI- D DIN DE R ROUT RE Channel 1 of 9 Common to all data channels TDI TDO TCK TMS TRST IEEE 1149.1 (JTAG) Test Access Port Figure 1. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2000-2013, Texas Instruments Incorporated SCAN92LV090 SNLS058I - SEPTEMBER 2000 - REVISED APRIL 2013 www.ti.com CONNECTION DIAGRAM Figure 2. Top View Package Number PM0064 Figure 3. Top View Package Number NZC0064A 2 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: SCAN92LV090 SCAN92LV090 www.ti.com SNLS058I - SEPTEMBER 2000 - REVISED APRIL 2013 PINOUT DESCRIPTION Pin Name LQFP Pin # NFBGA Pin # Input/Output Descriptions DO+/RI+ 27, 31, 35, 37, 41, 45, 47, 51, 55 A7, B8, C6, D5, D8, E6, F7, G5, G6 I/O True Bus LVDS Driver Outputs and Receiver Inputs. DO-/RI- 26, 30, 34, 36, 40, 44, 46, 50, 54 B5, B6, C7, D6, E5, E8, F6, G8, H7 I/O Complimentary Bus LVDS Driver Outputs and Receiver Inputs. DIN 2, 6, 12, 18, 20, 22, 58, A2, A4, C3, C4, D2, E3, 60, 62 G3, G4, H3 I TTL Driver Input. RO 3, 7, 13, 19, 21, 23, 59, A3, B3, C1, C2, D4, E4, 61, 63 F4, G1, H2 O TTL Receiver Output. RE 17 H1 I Receiver Enable TTL Input (Active Low). DE 16 G2 I Driver Enable TTL Input (Active High). GND 4, 5, 9, 14, 25, 56 B1, B4, D3, E1, F2, H5 Power Ground for digital circuitry (must connect to GND on PC board). These pins connected internally. VCC 10, 15, 24, 57, 64 A1, A5, F1, F3, H4 Power VCC for digital circuitry (must connect to VCC on PC board). These pins connected internally. AGND 28, 33, 43, 49, 53 A8, C5, D7, F5, G7 Power Ground for analog circuitry (must connect to GND on PC board). These pins connected internally. AVCC 29, 32, 42, 48, 52 A6, B7, C8, H6, H8 Power Analog VCC (must connect to VCC on PC board). These pins connected internally. TRST 39 F8 I Test Reset Input to support IEEE 1149.1 (Active Low) TMS 38 E7 I Test Mode Select Input to support IEEE 1149.1 TCK 1 B2 I Test Clock Input to support IEEE 1149.1 TDI 8 D1 I Test Data Input to support IEEE 1149.1 TDO 11 E2 O Test Data Output to support IEEE 1149.1 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) (3) Supply Voltage (VCC) 4.0V Enable Input Voltage (DE, RE) -0.3V to (VCC +0.3V) Driver Input Voltage (DIN) -0.3V to (VCC +0.3V) Receiver Output Voltage (ROUT) -0.3V to (VCC +0.3V) -0.3V to +3.9V Bus Pin Voltage (DO/RI) ESD (HBM 1.5 k, 100 pF) >4.5 kV Driver Short Circuit Duration momentary Receiver Short Circuit Duration Maximum Package Power Dissipation at 25C momentary LQFP Derate LQFP Package 1.74 W 13.9 mW/C ja 71.7C/W jc 10.9C/W Junction Temperature +150C -65C to +150C Storage Temperature Range Lead Temperature (Soldering, 4 sec.) (1) (2) (3) 260C Absolute Maximum Ratings are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified except VOD, VOD and VID. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: SCAN92LV090 3 SCAN92LV090 SNLS058I - SEPTEMBER 2000 - REVISED APRIL 2013 www.ti.com RECOMMENDED OPERATING CONDITIONS Min Max Units Supply Voltage (VCC) 3.0 3.6 V Receiver Input Voltage 0.0 2.4 V Operating Free Air Temperature -40 +85 C Maximum Input Edge Rate (1) (20% to 80%) (1) t/V Data 1.0 ns/V Control 3.0 ns/V Generator waveforms for all tests unless otherwise specified: f = 25 MHz, ZO = 50, tr, tf = <1.0 ns (0%-100%). To ensure fastest propagation delay and minimum skew, data input edge rates should be equal to or faster than 1ns/V; control signals equal to or faster than 3ns/V. In general, the faster the input edge rate, the better the AC performance. DC ELECTRICAL CHARACTERISTICS Over recommended operating supply voltage and temperature ranges unless otherwise specified Symbol Parameter Conditions VOD Output Differential Voltage RL = 27, See Figure 4 VOD VOD Magnitude Change VOS Offset Voltage VOS Offset Magnitude Change VOH Driver Output High Voltage (3) Pin DO+/RI+, DO-/RI- VOL Driver Output Low Voltage IOSD Output Short Circuit Current VOH Voltage Output High RL = 27 (4) Units 460 mV 27 mV (5) 0.95 1.5 V 5 10 mV 1.4 1.65 V 1.1 V |65| mA VCC-0.2 V Inputs Open VCC-0.2 V Inputs Terminated, RL = 27 VCC-0.2 V VID = +300 mV IOH = -400 A 1.3 |36| ROUT Voltage Output Low IOL = 2.0 mA, VID = -300 mV Receiver Output Dynamic Current (4) VID = 300mV, VOUT = VCC-1.0V VTH Input Threshold High DE = 0V, VCM = 1.5V VTL Input Threshold Low VCMR Receiver Common Mode Range IIN Input Current VIH Minimum Input High Voltage VIL Maximum Input Low Voltage IIH Input High Current VIN = VCC or 2.4V IIL Input Low Current VIN = GND or 0.4V VCL Input Diode Clamp Voltage ICLAMP = -18 mA IIH Input High Current VIN = VCC TDI, TMS, TCK, TRST IILR Input Low Current VIN = GND, VCC = 3.6v TDI, TMS, TRST 0.05 -110 VID = -300mV, VOUT = 1.0V DIN, DE, RE, TCK, TRST, TMS, TDI DIN, DE, RE V mA 110 mA +100 mV -100 mV |VID|/2 DE = 0V, RE = 2.4V, VIN = +2.4V or 0V 0.075 |75| |75| DO+/RI+, DO-/RI- VCC = 0V, VIN = +2.4V or 0V 4 Max 300 VOD = 0V, DE = VCC, Driver outputs shorted together IOD (2) (3) (4) (5) Typ 240 RL = 27 VOL (1) Min 1.1 (3) (1) (2) -25 1 -20 1 2.4 - |VID|/2 V +25 A +20 A 2.0 VCC V GND 0.8 V 10 +20 A -20 10 +20 A -1.5 -0.8 -20 +20 A -25 -115 A -20 V All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified except VOD, VOD and VID. All typicals are given for VCC = +3.3V and TA = +25C, unless otherwise stated. The SCAN92LV090 functions within datasheet specification when a resistive load is applied to the driver outputs. Only one output at a time should be shorted, do not exceed maximum package power dissipation capacity. VOH failsafe terminated test performed with 27 connected between RI+ and RI- inputs. No external voltage is applied. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: SCAN92LV090 SCAN92LV090 www.ti.com SNLS058I - SEPTEMBER 2000 - REVISED APRIL 2013 DC ELECTRICAL CHARACTERISTICS (continued) Over recommended operating supply voltage and temperature ranges unless otherwise specified (1)(2) Symbol Parameter Conditions Pin Min Typ Max Units +20 A 50 80 mA IIL Input Low Current VIN = GND TCK ICCD Power Supply Current Drivers Enabled, Receivers Disabled No Load, DE = RE = VCC, DIN = VCC or GND VCC ICCR Power Supply Current Drivers Disabled, Receivers Enabled DE = RE = 0V, VID = 300mV 50 80 mA ICCZ Power Supply Current, Drivers and Receivers tri-state DE = 0V; RE = VCC, DIN = VCC or GND 50 80 mA ICC Power Supply Current, Drivers and Receivers Enabled DE = VCC; RE = 0V, DIN = VCC or GND, RL = 27 160 210 mA Power Supply Current (SCAN Test Mode), Drivers and Receivers Enabled DE = VCC; RE = 0V, DIN = VCC or GND, RL = 27, TAP in any state other than Test-Logic-Reset 180 230 mA Power Off Leakage Current VCC = 0V or OPEN, DIN, DE, RE = 0V or OPEN, VAPPLIED = 3.6V (Port Pins) +20 A ICCS IOFF DO+/RI+, DO-/RI- -20 -20 COUTPUT Capacitance @ Bus Pins DO+/RI+, DO-/RI- 5 pF COUTPUT Capacitance @ ROUT ROUT 7 pF AC ELECTRICAL CHARACTERISTICS Over recommended operating supply voltage and temperature ranges unless otherwise specified Symbol Parameter Conditions (1) Min Typ Max Units 1.0 1.8 2.6 ns 1.0 1.8 2.6 ns DIFFERENTIAL DRIVER TIMING REQUIREMENTS Differential Prop. Delay High to Low (2) tPLHD Differential Prop. Delay Low to High (2) tSKD1 Differential Skew |tPHLD-tPLHD| tPHLD (3) RL = 27, See Figure 5 and Figure 6 CL = 10 pF 120 (4) tSKD2 Chip to Chip Skew tSKD3 Channel to Channel Skew tTLH Transition Time Low to High tTHL Transition Time High to Low tPHZ Disable Time High to Z tPLZ Disable Time Low to Z tPZH Enable Time Z to High tPZL Enable Time Z to Low (5) RL = 27, See Figure 7 and Figure 8 CL = 10 pF ps 1.6 ns 0.25 0.55 ns 0.5 1.2 ns 0.5 1.2 ns 3 8 ns 3 8 ns 3 8 ns 3 8 ns 2.4 3.9 ns 2.4 3.9 ns DIFFERENTIAL RECEIVER TIMING REQUIREMENTS tPHLD (2) Differential Prop. Delay High to Low tPLHD Differential Prop Delay Low to High tSDK1 Differential Skew |tPHLD-tPLHD| tSDK2 Chip to Chip Skew (2) (3) See Figure 9 and Figure 10 CL = 35 pF 2.0 2.0 210 (4) (5) ps 1.9 ns tSDK3 Channel to Channel skew 0.35 0.7 ns tTLH Transition Time Low to High 1.5 2.5 ns tTHL Transition Time High to Low 1.5 2.5 ns (1) (2) (3) (4) (5) Generator waveforms for all tests unless otherwise specified: f = 25 MHz, ZO = 50, tr, tf = <1.0 ns (0%-100%). To ensure fastest propagation delay and minimum skew, data input edge rates should be equal to or faster than 1ns/V; control signals equal to or faster than 3ns/V. In general, the faster the input edge rate, the better the AC performance. Propagation delays are specified by design and characterization. tSKD1 |tPHLD-tPLHD| is the worse case skew between any channel and any device over recommended operation conditions. Chip to Chip skew is the difference in differential propagation delay between any channels of any devices, either edge. Channel to Channel skew is the difference in driver output or receiver output propagation delay between any channels within a device, common edge. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: SCAN92LV090 5 SCAN92LV090 SNLS058I - SEPTEMBER 2000 - REVISED APRIL 2013 www.ti.com AC ELECTRICAL CHARACTERISTICS (continued) Over recommended operating supply voltage and temperature ranges unless otherwise specified (1) Symbol Parameter tPHZ Disable Time High to Z tPLZ Disable Time Low to Z tPZH Enable Time Z to High tPZL Enable Time Z to Low Conditions Min RL = 500, See Figure 11 and Figure 12 CL = 35 pF Typ Max Units 4.5 10 ns 3.5 8 ns 3.5 8 ns 3.5 8 ns SCAN CIRCUITRY TIMING REQUIREMENTS fMAX Maximum TCK Clock Frequency tS TDI to TCK, H or L 1.5 ns tH TDI to TCK, H or L 1.5 ns tS TMS to TCK, H or L 2.5 ns tH TMS to TCK, H or L 1.5 ns tW TCK Pulse Width, H or L 10.0 ns tW TRST Pulse Width, L 2.5 ns tREC Recovery Time, TRST to TCK 2.0 ns 6 RL = 500, CL = 35 pF Submit Documentation Feedback 25.0 75.0 MHz Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: SCAN92LV090 SCAN92LV090 www.ti.com SNLS058I - SEPTEMBER 2000 - REVISED APRIL 2013 APPLICATIONS INFORMATION General application guidelines and hints may be found in the following application notes: AN-808 (SNLA028), AN-1108 (SNLA008), AN-977 (SNLA166), AN-971 (SNLA165), and AN-903 (SNLA034). There are a few common practices which should be implied when designing PCB for Bus LVDS signaling. Recommended practices are: * Use at least 4 PCB board layer (Bus LVDS signals, ground, power and TTL signals). * Keep drivers and receivers as close to the (Bus LVDS port side) connector as possible. * Bypass each Bus LVDS device and also use distributed bulk capacitance between power planes. Surface mount capacitors placed close to power and ground pins work best. Two or three high frequency, multi-layer ceramic (MLC) surface mount (0.1 F, 0.01 F, 0.001 F) in parallel should be used between each VCC and ground. The capacitors should be as close as possible to the VCC pin. - Multiple vias should be used to connect VCC and Ground planes to the pads of the by-pass capacitors. - In addition, randomly distributed by-pass capacitors should be used. * Use the termination resistor which best matches the differential impedance of your transmission line. * Leave unused Bus LVDS receiver inputs open (floating). Limit traces on unused inputs to <0.5 inches. * Isolate TTL signals from Bus LVDS signals MEDIA (CONNECTOR or BACKPLANE) SELECTION: * Use controlled impedance media. The backplane and connectors should have a matched differential impedance. Table 1. Functional Table MODE SELECTED DE RE DRIVER MODE H H RECEIVER MODE L L tri-state MODE L H LOOP BACK MODE H L Table 2. Transmitter Mode INPUTS DE OUTPUTS DIN DO+ DO- H H L L H H H L H 0.8V< DIN <2.0V X X L X Z Z Table 3. Receiver Mode (1) INPUTS (1) OUTPUT RE (RI+) - (RI-) L L (< -100 mV) L L H (> +100 mV) H L -100 mV < VID < +100 mV X H X Z X = High or Low logic state L = Low state Z = High impedance state H = High state Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: SCAN92LV090 7 SCAN92LV090 SNLS058I - SEPTEMBER 2000 - REVISED APRIL 2013 www.ti.com TEST CIRCUITS AND TIMING WAVEFORMS Figure 4. Differential Driver DC Test Circuit Figure 5. Differential Driver Propagation Delay and Transition Time Test Circuit Figure 6. Differential Driver Propagation Delay and Transition Time Waveforms 8 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: SCAN92LV090 SCAN92LV090 www.ti.com SNLS058I - SEPTEMBER 2000 - REVISED APRIL 2013 Figure 7. Driver Tri-State Delay Test Circuit Figure 8. Driver Tri-State Delay Waveforms Figure 9. Receiver Propagation Delay and Transition Time Test Circuit Figure 10. Receiver Propagation Delay and Transition Time Waveforms Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: SCAN92LV090 9 SCAN92LV090 SNLS058I - SEPTEMBER 2000 - REVISED APRIL 2013 www.ti.com Figure 11. Receiver Tri-State Delay Test Circuit Figure 12. Receiver Tri-State Delay Waveforms TYPICAL BUS APPLICATION CONFIGURATIONS Figure 13. Bi-Directional Half-Duplex Point-to-Point Applications Figure 14. Multi-Point Bus Applications 10 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: SCAN92LV090 SCAN92LV090 www.ti.com SNLS058I - SEPTEMBER 2000 - REVISED APRIL 2013 DESCRIPTION OF BOUNDARY-SCAN CIRCUITRY The SCAN92LV090 features two unique Scan test modes, each which requires a unique BSDL model depending on the level of test access and fault coverage goals. In the first mode (Mode0), only the TTL Inputs and Outputs of each transceiver are accessible via a 1149.1 compliant protocol. In the second mode (Mode1), both the TTL Inputs and Outputs and the differential LVDS I/Os are included in the Scan chain. All test modes are handled by the ATPG software, and BSDL selection should be invisible to the user. The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low. Figure 15. Bypass Register Scan Chain Definition Logic 0 The INSTRUCTION register is an eight-bit register which captures the value 00111101. Figure 16. Instruction Register Scan Chain Definition Table 4. MSB LSB (Mode0) Instruction Code Instruction 00000000 EXTEST 10000010 SAMPLE/PRELOAD 10000111 CLAMP 00000110 HIGHZ All Others BYPASS Table 5. MSB LSB (Mode1) Instruction Code Instruction 10011001 EXTEST 10010010 SAMPLE/PRELOAD 10001111 CLAMP 00000110 HIGHZ All Others BYPASS Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: SCAN92LV090 11 SCAN92LV090 SNLS058I - SEPTEMBER 2000 - REVISED APRIL 2013 www.ti.com To Other Channel ^Z[* DIN D0+/RI+ BLVDS I/O D0-/RI- BSR DE ROUT BSR RE BSR Channel 1 of 9 Common to all data channels d} ^Z[* &OE}u ^Z[* BYPASS REGISTER TDI INSTRUCTION REGISTER TMS TCK TEST ACCESS PORT (TAP) TDO INSTRUCTION TRI-STATE TRST Figure 17. Mode 0 Boundary Scan Register Configuration (Refer to the BSDL for exact register order) 12 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: SCAN92LV090 SCAN92LV090 www.ti.com SNLS058I - SEPTEMBER 2000 - REVISED APRIL 2013 To Other Channel ^Z[* DIN BSR DE BSR ROUT BSR RE BSR D0+/RI+ BLVDS I/O D0-/RI- BSR BSR Channel 1 of 9 Common to all data channels d} ^Z[* &OE}u ^Z[* BYPASS REGISTER TDI INSTRUCTION REGISTER TMS TCK TEST ACCESS PORT (TAP) TDO INSTRUCTION TRI-STATE TRST Figure 18. Mode 1 Boundary Scan Register Configuration (Refer to the BSDL for exact register order) Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: SCAN92LV090 13 SCAN92LV090 SNLS058I - SEPTEMBER 2000 - REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision H (April 2013) to Revision I * 14 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 13 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: SCAN92LV090 PACKAGE OPTION ADDENDUM www.ti.com 8-Oct-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) SCAN92LV090SLC NRND NFBGA NZC 64 360 TBD Call TI Call TI -40 to 85 SCAN92LV090 SLC SCAN92LV090SLC/NOPB ACTIVE NFBGA NZC 64 360 Green (RoHS & no Sb/Br) SNAGCU Level-4-260C-72 HR -40 to 85 SCAN92LV090 SLC SCAN92LV090VEH/NOPB ACTIVE LQFP PM 64 160 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 SCAN92LV090 VEH (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 8-Oct-2015 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA NZC0064A SLC64A (Rev C) www.ti.com MECHANICAL DATA MTQF008A - JANUARY 1995 - REVISED DECEMBER 1996 PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 33 48 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 0- 7 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040152 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MS-026 May also be thermally enhanced plastic with leads connected to the die pads. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as "components") are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. 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