IEEE 1149.1 (JTAG)
Test Access Port
TDI
TDO
TCK
TMS
TRST
Common to all
data channels
Channel 1 of 9
DIN
ROUT
DE
RE
D0+/RI+
BLVDS I/O
D0-/RI-
D
R
SCAN92LV090
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SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN
Check for Samples: SCAN92LV090
1FEATURES DESCRIPTION
The SCAN92LV090A is one in a series of Bus LVDS
2• IEEE 1149.1 (JTAG) Compliant transceivers designed specifically for the high speed,
• Bus LVDS Signaling low power proprietary backplane or cable interfaces.
• Low Power CMOS Design The device operates from a single 3.3V power supply
and includes nine differential line drivers and nine
• High Signaling Rate Capability (Above 100 receivers. To minimize bus loading, the driver outputs
Mbps) and receiver inputs are internally connected. The
• 0.1V to 2.3V Common Mode Range for VID =separate I/O of the logic side allows for loop back
200mV support. The device also features a flow through pin
• ±100 mV Receiver Sensitivity out which allows easy PCB routing for short stubs
between its pins and the connector.
• Supports Open and Terminated Failsafe on
Port Pins The driver translates 3V TTL levels (single-ended) to
differential Bus LVDS (BLVDS) output levels. This
• 3.3V Operation allows for high speed operation, while consuming
• Glitch Free Power Up/Down (Driver & Receiver minimal power with reduced EMI. In addition, the
Disabled) differential signaling provides common mode noise
• Light Bus Loading (5 pF Typical) per Bus rejection of ±1V.
LVDS Load The receiver threshold is less than ±100 mV over a
• Designed for Double Termination Applications ±1V common mode range and translates the
differential Bus LVDS to standard (TTL/CMOS)
• Balanced Output Impedance levels.
• Product Offered in 64 Pin LQFP Package and
NFBGA Package This device is compliant with IEEE 1149.1 Standard
Test Access Port and Boundary Scan Architecture
• High Impedance Bus Pins on Power Off (VCC =with the incorporation of the defined boundary-scan
0V) test logic and test access port consisting of Test Data
Input (TDI), Test Data Out (TDO), Test Mode Select
(TMS), Test Clock (TCK), and the optional Test Reset
(TRST).
SIMPLIFIED FUNCTIONAL DIAGRAM
Figure 1.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2000–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SCAN92LV090
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PINOUT DESCRIPTION
Pin Name LQFP Pin # NFBGA Pin # Input/Output Descriptions
DO+/RI+ 27, 31, 35, 37, 41, 45, A7, B8, C6, D5, D8, E6, I/O True Bus LVDS Driver Outputs and Receiver Inputs.
47, 51, 55 F7, G5, G6
DO−/RI−26, 30, 34, 36, 40, 44, B5, B6, C7, D6, E5, E8, I/O Complimentary Bus LVDS Driver Outputs and Receiver
46, 50, 54 F6, G8, H7 Inputs.
DIN 2, 6, 12, 18, 20, 22, 58, A2, A4, C3, C4, D2, E3, I TTL Driver Input.
60, 62 G3, G4, H3
RO 3, 7, 13, 19, 21, 23, 59, A3, B3, C1, C2, D4, E4, O TTL Receiver Output.
61, 63 F4, G1, H2
RE 17 H1 I Receiver Enable TTL Input (Active Low).
DE 16 G2 I Driver Enable TTL Input (Active High).
GND 4, 5, 9, 14, 25, 56 B1, B4, D3, E1, F2, H5 Power Ground for digital circuitry (must connect to GND on PC
board). These pins connected internally.
VCC 10, 15, 24, 57, 64 A1, A5, F1, F3, H4 Power VCC for digital circuitry (must connect to VCC on PC
board). These pins connected internally.
AGND 28, 33, 43, 49, 53 A8, C5, D7, F5, G7 Power Ground for analog circuitry (must connect to GND on PC
board). These pins connected internally.
AVCC 29, 32, 42, 48, 52 A6, B7, C8, H6, H8 Power Analog VCC (must connect to VCC on PC board). These
pins connected internally.
TRST 39 F8 I Test Reset Input to support IEEE 1149.1 (Active Low)
TMS 38 E7 I Test Mode Select Input to support IEEE 1149.1
TCK 1 B2 I Test Clock Input to support IEEE 1149.1
TDI 8 D1 I Test Data Input to support IEEE 1149.1
TDO 11 E2 O Test Data Output to support IEEE 1149.1
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS (1)(2)(3)
Supply Voltage (VCC) 4.0V
Enable Input Voltage (DE, RE) −0.3V to (VCC +0.3V)
Driver Input Voltage (DIN)−0.3V to (VCC +0.3V)
Receiver Output Voltage (ROUT)−0.3V to (VCC +0.3V)
Bus Pin Voltage (DO/RI±) −0.3V to +3.9V
ESD (HBM 1.5 kΩ, 100 pF) >4.5 kV
Driver Short Circuit Duration momentary
Receiver Short Circuit Duration momentary
Maximum Package Power Dissipation at 25°C LQFP 1.74 W
Derate LQFP Package 13.9 mW/°C
θja 71.7°C/W
θjc 10.9°C/W
Junction Temperature +150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 4 sec.) 260°C
(1) Absolute Maximum Ratings are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that
the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.
(2) All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless
otherwise specified except VOD,ΔVOD and VID.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
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RECOMMENDED OPERATING CONDITIONS Min Max Units
Supply Voltage (VCC) 3.0 3.6 V
Receiver Input Voltage 0.0 2.4 V
Operating Free Air Temperature −40 +85 °C
Maximum Input Edge Rate (20% to 80%) (1) Δt/ΔV
Data 1.0 ns/V
Control 3.0 ns/V
(1) Generator waveforms for all tests unless otherwise specified: f = 25 MHz, ZO= 50Ω, tr, tf= <1.0 ns (0%–100%). To ensure fastest
propagation delay and minimum skew, data input edge rates should be equal to or faster than 1ns/V; control signals equal to or faster
than 3ns/V. In general, the faster the input edge rate, the better the AC performance.
DC ELECTRICAL CHARACTERISTICS
Over recommended operating supply voltage and temperature ranges unless otherwise specified (1)(2)
Symbol Parameter Conditions Pin Min Typ Max Units
VOD Output Differential Voltage RL= 27Ω, See Figure 4 DO+/RI+, 240 300 460 mV
DO−/RI−
ΔVOD VOD Magnitude Change 27 mV
VOS Offset Voltage 1.1 1.3 1.5 V
ΔVOS Offset Magnitude Change 5 10 mV
VOH Driver Output High Voltage(3) RL= 27Ω1.4 1.65 V
VOL Driver Output Low Voltage(3) RL= 27Ω0.95 1.1 V
IOSD Output Short Circuit Current (4) VOD = 0V, DE = VCC, Driver outputs |36| |65| mA
shorted together
VOH Voltage Output High (5) VID = +300 mV IOH =−400 µA ROUT VCC−0.2 V
Inputs Open VCC−0.2 V
Inputs Terminated, VCC−0.2 V
RL= 27Ω
VOL Voltage Output Low IOL = 2.0 mA, VID =−300 mV 0.05 0.075 V
IOD Receiver Output Dynamic VID = 300mV, VOUT = VCC−1.0V −110 |75| mA
Current (4) VID =−300mV, VOUT = 1.0V |75| 110 mA
VTH Input Threshold High DE = 0V, VCM = 1.5V DO+/RI+, +100 mV
DO−/RI−
VTL Input Threshold Low −100 mV
VCMR Receiver Common Mode Range |VID|/2 2.4 −V
|VID|/2
IIN Input Current DE = 0V, RE = 2.4V, −25 ±1 +25 µA
VIN = +2.4V or 0V
VCC = 0V, VIN = +2.4V or 0V −20 ±1 +20 µA
VIH Minimum Input High Voltage DIN, DE, 2.0 VCC V
RE, TCK,
VIL Maximum Input Low Voltage TRST, GND 0.8 V
TMS, TDI
IIH Input High Current VIN = VCC or 2.4V DIN, DE, RE −20 ±10 +20 µA
IIL Input Low Current VIN = GND or 0.4V −20 ±10 +20 µA
VCL Input Diode Clamp Voltage ICLAMP =−18 mA −1.5 −0.8 V
IIH Input High Current VIN = VCC TDI, TMS, -20 +20 µA
TCK, TRST
IILR Input Low Current VIN = GND, VCC = 3.6v TDI, TMS, -25 -115 µA
TRST
(1) All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless
otherwise specified except VOD,ΔVOD and VID.
(2) All typicals are given for VCC = +3.3V and TA= +25°C, unless otherwise stated.
(3) The SCAN92LV090 functions within datasheet specification when a resistive load is applied to the driver outputs.
(4) Only one output at a time should be shorted, do not exceed maximum package power dissipation capacity.
(5) VOH failsafe terminated test performed with 27Ωconnected between RI+ and RI−inputs. No external voltage is applied.
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DC ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating supply voltage and temperature ranges unless otherwise specified (1)(2)
Symbol Parameter Conditions Pin Min Typ Max Units
IIL Input Low Current VIN = GND TCK -20 +20 µA
ICCD Power Supply Current Drivers No Load, DE = RE = VCC, VCC 50 80 mA
Enabled, Receivers Disabled DIN = VCC or GND
ICCR Power Supply Current Drivers DE = RE = 0V, VID = ±300mV 50 80 mA
Disabled, Receivers Enabled
ICCZ Power Supply Current, Drivers DE = 0V; RE = VCC,50 80 mA
and Receivers tri-state DIN = VCC or GND
ICC Power Supply Current, Drivers DE = VCC; RE = 0V,
and Receivers Enabled DIN = VCC or GND, 160 210 mA
RL= 27Ω
ICCS Power Supply Current (SCAN DE = VCC; RE = 0V,
Test Mode), Drivers and DIN = VCC or GND, 180 230 mA
Receivers Enabled RL= 27Ω, TAP in any state other
than Test-Logic-Reset
IOFF Power Off Leakage Current VCC = 0V or OPEN, DO+/RI+,
DIN, DE, RE = 0V or OPEN, DO−/RI− −20 +20 µA
VAPPLIED = 3.6V (Port Pins)
COUTPUT Capacitance @ Bus Pins DO+/RI+, 5 pF
DO−/RI−
COUTPUT Capacitance @ ROUT ROUT 7 pF
AC ELECTRICAL CHARACTERISTICS
Over recommended operating supply voltage and temperature ranges unless otherwise specified (1)
Symbol Parameter Conditions Min Typ Max Units
DIFFERENTIAL DRIVER TIMING REQUIREMENTS
tPHLD Differential Prop. Delay High to Low (2) RL= 27Ω, 1.0 1.8 2.6 ns
See Figure 5 and
tPLHD Differential Prop. Delay Low to High (2) 1.0 1.8 2.6 ns
Figure 6
tSKD1 Differential Skew |tPHLD–tPLHD|(3) 120 ps
CL= 10 pF
tSKD2 Chip to Chip Skew (4) 1.6 ns
tSKD3 Channel to Channel Skew (5) 0.25 0.55 ns
tTLH Transition Time Low to High 0.5 1.2 ns
tTHL Transition Time High to Low 0.5 1.2 ns
tPHZ Disable Time High to Z RL= 27Ω, 3 8 ns
See Figure 7 and
tPLZ Disable Time Low to Z 3 8 ns
Figure 8
tPZH Enable Time Z to High 3 8 ns
CL= 10 pF
tPZL Enable Time Z to Low 3 8 ns
DIFFERENTIAL RECEIVER TIMING REQUIREMENTS
tPHLD Differential Prop. Delay High to Low (2) See Figure 9 and 2.0 2.4 3.9 ns
Figure 10
tPLHD Differential Prop Delay Low to High (2) 2.0 2.4 3.9 ns
CL= 35 pF
tSDK1 Differential Skew |tPHLD–tPLHD|(3) 210 ps
tSDK2 Chip to Chip Skew (4) 1.9 ns
tSDK3 Channel to Channel skew (5) 0.35 0.7 ns
tTLH Transition Time Low to High 1.5 2.5 ns
tTHL Transition Time High to Low 1.5 2.5 ns
(1) Generator waveforms for all tests unless otherwise specified: f = 25 MHz, ZO= 50Ω, tr, tf= <1.0 ns (0%–100%). To ensure fastest
propagation delay and minimum skew, data input edge rates should be equal to or faster than 1ns/V; control signals equal to or faster
than 3ns/V. In general, the faster the input edge rate, the better the AC performance.
(2) Propagation delays are specified by design and characterization.
(3) tSKD1 |tPHLD–tPLHD| is the worse case skew between any channel and any device over recommended operation conditions.
(4) Chip to Chip skew is the difference in differential propagation delay between any channels of any devices, either edge.
(5) Channel to Channel skew is the difference in driver output or receiver output propagation delay between any channels within a device,
common edge.
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AC ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating supply voltage and temperature ranges unless otherwise specified (1)
Symbol Parameter Conditions Min Typ Max Units
tPHZ Disable Time High to Z RL= 500Ω, 4.5 10 ns
See Figure 11 and
tPLZ Disable Time Low to Z 3.5 8 ns
Figure 12
tPZH Enable Time Z to High 3.5 8 ns
CL= 35 pF
tPZL Enable Time Z to Low 3.5 8 ns
SCAN CIRCUITRY TIMING REQUIREMENTS
fMAX Maximum TCK Clock Frequency RL= 500Ω, CL= 35 pF 25.0 75.0 MHz
tSTDI to TCK, H or L 1.5 ns
tHTDI to TCK, H or L 1.5 ns
tSTMS to TCK, H or L 2.5 ns
tHTMS to TCK, H or L 1.5 ns
tWTCK Pulse Width, H or L 10.0 ns
tWTRST Pulse Width, L 2.5 ns
tREC Recovery Time, TRST to TCK 2.0 ns
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APPLICATIONS INFORMATION
General application guidelines and hints may be found in the following application notes: AN-808 (SNLA028),
AN-1108 (SNLA008), AN-977 (SNLA166), AN-971 (SNLA165), and AN-903 (SNLA034).
There are a few common practices which should be implied when designing PCB for Bus LVDS signaling.
Recommended practices are:
• Use at least 4 PCB board layer (Bus LVDS signals, ground, power and TTL signals).
• Keep drivers and receivers as close to the (Bus LVDS port side) connector as possible.
• Bypass each Bus LVDS device and also use distributed bulk capacitance between power planes. Surface
mount capacitors placed close to power and ground pins work best. Two or three high frequency, multi-layer
ceramic (MLC) surface mount (0.1 µF, 0.01 µF, 0.001 µF) in parallel should be used between each VCC and
ground. The capacitors should be as close as possible to the VCC pin.
– Multiple vias should be used to connect VCC and Ground planes to the pads of the by-pass capacitors.
– In addition, randomly distributed by-pass capacitors should be used.
• Use the termination resistor which best matches the differential impedance of your transmission line.
• Leave unused Bus LVDS receiver inputs open (floating). Limit traces on unused inputs to <0.5 inches.
• Isolate TTL signals from Bus LVDS signals
MEDIA (CONNECTOR or BACKPLANE) SELECTION:
• Use controlled impedance media. The backplane and connectors should have a matched differential
impedance.
Table 1. Functional Table
MODE SELECTED DE RE
DRIVER MODE H H
RECEIVER MODE L L
tri-state MODE L H
LOOP BACK MODE H L
Table 2. Transmitter Mode
INPUTS OUTPUTS
DE DIN DO+ DO−
H L L H
H H H L
H 0.8V< DIN <2.0V X X
L X Z Z
Table 3. Receiver Mode(1)
INPUTS OUTPUT
RE (RI+) – (RI−)
L L (< −100 mV) L
L H (> +100 mV) H
L−100 mV < VID < +100 mV X
H X Z
(1) X = High or Low logic state
L = Low state
Z = High impedance state
H = High state
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TEST CIRCUITS AND TIMING WAVEFORMS
Figure 4. Differential Driver DC Test Circuit
Figure 5. Differential Driver Propagation Delay and Transition Time Test Circuit
Figure 6. Differential Driver Propagation Delay and Transition Time Waveforms
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Figure 7. Driver Tri-State Delay Test Circuit
Figure 8. Driver Tri-State Delay Waveforms
Figure 9. Receiver Propagation Delay and Transition Time Test Circuit
Figure 10. Receiver Propagation Delay and Transition Time Waveforms
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Figure 11. Receiver Tri-State Delay Test Circuit
Figure 12. Receiver Tri-State Delay Waveforms
TYPICAL BUS APPLICATION CONFIGURATIONS
Figure 13. Bi-Directional Half-Duplex Point-to-Point Applications
Figure 14. Multi-Point Bus Applications
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DESCRIPTION OF BOUNDARY-SCAN CIRCUITRY
The SCAN92LV090 features two unique Scan test modes, each which requires a unique BSDL model depending
on the level of test access and fault coverage goals. In the first mode (Mode0), only the TTL Inputs and Outputs
of each transceiver are accessible via a 1149.1 compliant protocol. In the second mode (Mode1), both the TTL
Inputs and Outputs and the differential LVDS I/Os are included in the Scan chain.
All test modes are handled by the ATPG software, and BSDL selection should be invisible to the user.
The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low.
Figure 15. Bypass Register Scan Chain Definition
Logic 0
The INSTRUCTION register is an eight-bit register which captures the value 00111101.
Figure 16. Instruction Register Scan Chain Definition
Table 4. MSB →LSB (Mode0)
Instruction Code Instruction
00000000 EXTEST
10000010 SAMPLE/PRELOAD
10000111 CLAMP
00000110 HIGHZ
All Others BYPASS
Table 5. MSB →LSB (Mode1)
Instruction Code Instruction
10011001 EXTEST
10010010 SAMPLE/PRELOAD
10001111 CLAMP
00000110 HIGHZ
All Others BYPASS
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BYPASS
REGISTER
INSTRUCTION
REGISTER
TEST
ACCESS
PORT (TAP)
Common to all
data channels
Channel 1 of 9
DIN
ROUT
DE
RE
D0+/RI+
BLVDS I/O
D0-/RI-
BSR
BSR
BSR
d}^Z[•&Œ}u^Z[•
INSTRUCTION
TRI-STATE
TMS
TCK
TRST
TDI
TDO
To Other
Channel
^Z[•
SCAN92LV090
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Figure 17. Mode 0 Boundary Scan Register Configuration
(Refer to the BSDL for exact register order)
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BYPASS
REGISTER
INSTRUCTION
REGISTER
TEST
ACCESS
PORT (TAP)
Common to all
data channels
Channel 1 of 9
DIN
ROUT
DE
RE
D0+/RI+
BLVDS I/O
D0-/RI-
BSR
BSR
BSR
BSR
d}^Z[•&Œ}u^Z[•
INSTRUCTION
TRI-STATE
TMS
TCK
TRST
TDI
TDO
BSR
BSR
To Other
Channel
^Z[•
SCAN92LV090
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Figure 18. Mode 1 Boundary Scan Register Configuration
(Refer to the BSDL for exact register order)
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REVISION HISTORY
Changes from Revision H (April 2013) to Revision I Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 13
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PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SCAN92LV090SLC NRND NFBGA NZC 64 360 TBD Call TI Call TI -40 to 85 SCAN92LV090
SLC
SCAN92LV090SLC/NOPB ACTIVE NFBGA NZC 64 360 Green (RoHS
& no Sb/Br) SNAGCU Level-4-260C-72 HR -40 to 85 SCAN92LV090
SLC
SCAN92LV090VEH/NOPB ACTIVE LQFP PM 64 160 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 SCAN92LV090
VEH
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
MECHANICAL DATA
NZC0064A
www.ti.com
SLC64A (Rev C)
MECHANICAL DATA
MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PM (S-PQFP-G64) PLASTIC QUAD FLATPACK
4040152/C 11/96
32
17 0,13 NOM
0,25
0,45
0,75
Seating Plane
0,05 MIN
Gage Plane
0,27
33
16
48
1
0,17
49
64
SQ
SQ
10,20
11,80
12,20
9,80
7,50 TYP
1,60 MAX
1,45
1,35
0,08
0,50 M
0,08
0°–7°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. May also be thermally enhanced plastic with leads connected to the die pads.
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
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supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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