1 Introduction
1.1 Related Documentation From Texas Instruments
User's GuideSLVU191A – November 2006 – Revised April 2007
TPS6505xEVM-195
This user’s guide describes the characteristics, operation, and use of theTPS65050EVM-195, TPS65051EVM-195, TPS65052EVM-195, TPS65054EVM-195and TPS65056EVM-195 evaluation module (EVM). This EVM demonstrates the TexasInstruments TPS6505x power management IC (PMIC). This document includes setupinstructions, a schematic diagram, a bill of materials (BOM), and PCB layout drawingsfor the evaluation module.
Contents1 Introduction .......................................................................................... 12 Setup ................................................................................................. 23 Board Layout ........................................................................................ 74 Schematic and Bill of Materials ................................................................. 12
List of Figures
1 Assembly Layer ..................................................................................... 72 Top Layer Routing .................................................................................. 83 Inner Layer 2 Routing .............................................................................. 94 Inner Layer 3 Top Layer Routing ............................................................... 105 Bottom Layer Routing ............................................................................ 116 TPS6505xEVM-195 Schematic ................................................................. 12
List of Tables
1 EVM Preset Output Voltage ....................................................................... 52 Maximum Load Current ............................................................................ 53 Factory EVM Jumper Settings .................................................................... 64 TPS6505xEVM-195 Bill of Materials............................................................ 13
The Texas Instruments TPS6505xEVM-195 evaluation module (EVM) helps designers evaluate theoperation and performance of the TPS65050, TPS65051, TPS65052, TPS65054 and TPS65056 PMICsfor applications that are powered with one Li ion or Li polymer cell and require multiple power rails. TheTPS6505x contains two highly efficient step-down switching converters, four low dropout linear regulators(LDO), and additional status I/O pins.
TPS6505x data sheet (SLVS710 )
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2 Setup
2.1 Input/Output Connector Descriptions
2.1.1 J1 —VIN
2.1.2 J2—GND
2.1.3 J3—VDCDC1
2.1.4 J4—GND
2.1.5 J5 —VDCDC2
2.1.6 J6—GND
2.1.7 J7—VLDO1
2.1.8 J8—GND
2.1.9 J9—VLDO2
Setup
This section describes the jumpers and connectors on the EVM as well as how to properly connect, setup, and use the TPS6505xEVM-195.
This is the positive input voltage connection to the converter. The EVM operates from any supply voltagebetween 2.5 V and 6 V. The leads to the input supply should be twisted and kept as short as possible tominimize EMI transmission and input voltage droop.
This is the input return connection for the input power supply.
This is the positive output for VDCDC1 step-down converter. This output is externally adjustable for theTPS65050, TPS65051, and TPS65054. The output for the TPS65052 and TPS65056 is fixed. The EVMpreset output voltages are found in Table 1 . VDCDC1 is capable of sourcing up to 600 mA for theTPS65050 and TPS65054 and up to 1 A for the TPS65051, TPS65052 and TPS65056.
This is the return connection for the VDCDC1 output rail.
This is the positive output for VDCDC2 step-down converter. This output is externally adjustable for theTPS65050 and TPS65051. The output for the TPS65052, TPS65054 and TPS65056 is programmed bythe DEFDCDC2 input to two factory-programmed voltages. The EVM preset output voltages are found inTable 1 . VDCDC2 is capable of sourcing up to 600 mA for all versions.
This is the return connection for the VDCDC2 output rail.
This is the positive output for the VLDO1 LDO linear regulator. This output is input programmable for theTPS65050 and TPS65052 and externally adjustable for the TPS65051, TPS65054 and TPS65056. TheVLDO1 output is capable of supplying up to 400 mA. The EVM preset output voltages are found inTable 1 .
This is the return connection for the VLDO1 output rail.
This is the positive output for the VLDO2 LDO linear regulator. This output is input programmable for theTPS65050 and TPS65052 and externally adjustable for the TPS65051, TPS65054 and TPS65056. TheVLDO2 output is capable of supplying up to 400 mA. The EVM preset output voltages are found inTable 1 .
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2.1.10 J10—GND
2.1.11 J11—VLDO3
2.1.12 J12 —GND
2.1.13 J13 —VLDO4
2.1.14 J14—GND
2.1.15 J15 —PB_OUT or RESET
2.1.16 JP1 —EN VDCDC1
2.1.17 JP2 —MODE
2.1.18 JP3 —DEFLDO1
2.1.19 JP4—DEFLDO2
Setup
This is the return connection for the VLDO2 output rail.
This is the positive output for the VLDO3 LDO linear regulator. This output is input programmable for theTPS65050 and TPS65052 and externally adjustable for the TPS65051, TPS65054 and TPS65056. TheVLDO3 output is capable of supplying up to 200 mA. The EVM preset output voltages are found inTable 1 .
This is the return connection for the VLDO3 output rail.
This is the positive output for the VLDO4 LDO linear regulator. This output is input programmable for theTPS65050 and TPS65052 and externally adjustable for the TPS65051, TPS65054 and TPS65056. TheVLDO4 output is capable of supplying up to 200 mA. The EVM preset output voltages are found inTable 1 .
This is the return connection for the VLDO4 output rail.
Pin 1 of this output allows the user to measure the PB_OUT (TPS65050) or RESET (TPS65051/TPS65052/ TPS65054/ TPS65056) output. The PB_OUT output is toggled using the SW1 pushbuttonswitch. The RESET output goes high 100 ms after the THRESHOLD input exceeds 1 V. RESET goes lowwhen the HYSTERESIS input falls below 1 V. On the EVM, the RESET circuitry monitors the inputvoltage. The rising threshold is set to a 3.4-V input and the falling threshold is set to 3.3 V.
JP1 is used to enable the VDCDC1 output. Place a shorting bar in the ON position to turn on the VDCDC1step-down converter. Place a shorting bar in the OFF position to turn off the VDCDC1 converter.
JP2 is used to select between the forced PWM and Power Save mode operation for the switchingconverters. Place a shorting bar in the PSM position to select the Power Save mode. In this mode, PFM isused for light loads, and PWM is used for heavier loads. Place a shorting bar in the PWM position to forcePWM operation at all loads.
JP3–JP6 are used to program the LDO regulation voltages for the TPS65050 and TPS65052. Place ashorting bar in the HI position to connect DEFLDO1 to the input voltage. Place a shorting bar in the LOposition to connect DEFLDO1 to GND. This jumper is not installed on the TPS65051, TPS65054 andTPS65056 EVMs.
JP3 - JP6 are used to program the LDO regulation voltages for the TPS65050 and TPS65052. Place ashorting bar in the HI position to connect DEFLDO2 to the input voltage. Place a shorting bar in the LOposition to connect DEFLDO2 to GND. This jumper is not installed on the TPS65051, TPS65054 andTPS65056 EVMs.
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2.1.20 JP5—DEFLDO3
2.1.21 JP6—DEFLDO4
2.1.22 JP7—EN VDCDC2
2.1.23 JP8 —DEFDCDC2
2.1.24 JP9 —EN LDO1
2.1.25 JP10 —EN LDO2
2.1.26 JP11—EN LDO3
2.1.27 JP12—EN LDO4
Setup
JP3–JP6 are used to program the LDO regulation voltages for the TPS65050 and TPS65052. Place ashorting bar in the HI position to connect DEFLDO3 to the input voltage. Place a shorting bar in the LOposition to connect DEFLDO3 to GND. This jumper is not installed on the TPS65051, TPS65054 andTPS65056 EVMs.
JP3–JP6 are used to program the LDO regulation voltages for the TPS65050 and TPS65052. Place ashorting bar in the HI position to connect DEFLDO4 to the input voltage. Place a shorting bar in the LOposition to connect DEFLDO4 to GND. This jumper is not installed on the TPS65051, TPS65054 andTPS65056 EVMs.
JP7 is used to enable the VDCDC2 output. Place a shorting bar in the ON position to turn on the VDCDC2step-down converter. Place a shorting bar in the OFF position to turn off the VDCDC2 converter.
JP8 is used to select the VDCDC2 output voltage for the TPS65052 and TPS65054. Place a shorting barin the HI position to regulate the VDCDC2 output to 1.3 V (TPS65052/TPS65056) or 1.05 V (TPS65054).Place a shorting bar in the LO position to regulate the VDCDC2 output to 1 V (TPS65052/TPS65056) or1.3 V (TPS65054).
JP9 is used to enable the VLDO1 output. Remove the shorting bar to turn off the VLDO1 LDO converter.Place a shorting bar in the ON position to turn on the VLDO1 LDO converter. For the TPS65050, place theshunt in the PB position to connect EN_LDO1 to the PB_OUT output. This allows the user to control theenable using the installed pushbutton switch (SW1). The PB position should not be used for theTPS65051/ TPS65052/ TPS65054/ TPS65056 EVMs.
JP10 is used to enable the VLDO2 output. Remove the shorting bar to turn off the VLDO2 LDO converter.Place a shorting bar in the ON position to turn on the VLDO2 LDO converter. For the TPS65050, place theshunt in the PB position to connect EN_LDO2 to the PB_OUT output. This allows the user to control theenable using the installed pushbutton switch (SW1). The PB position should not be used for theTPS65051/ TPS65052/ TPS65054/ TPS65056 EVMs.
JP11 is used to enable the VLDO3 output. Remove the shorting bar to turn off the VLDO3 LDO converter.Place a shorting bar in the ON position to turn on the VLDO3 LDO converter. For the TPS65050, place theshunt in the PB position to connect EN_LDO3 to the PB_OUT output. This allows the user to control theenable using the installed pushbutton switch (SW1). The PB position should not be used for theTPS65051/ TPS65052/ TPS65054/ TPS65056 EVMs.
JP12 is used to enable the VLDO4 output. Remove the shorting bar to turn off the VLDO4 LDO converter.Place a shorting bar in the ON position to turn on the VLDO4 LDO converter. For the TPS65050, place theshunt in the PB position to connect EN_LDO4 to the PB_OUT output. This allows the user to control theenable using the installed pushbutton switch (SW1). The PB position should not be used for theTPS65051/ TPS65052/ TPS65054/ TPS65056 EVMs.
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2.2 Setup
2.2.1 EVM Family Configuration
2.2.2 Operation
Setup
The EVM is configured to provide the following nominal operating conditions:Input voltage: 2.5 V to 6 VOutput voltage: See Table 1Maximum load current: See Table 2
Table 1. EVM Preset Output Voltage
Output TPS65050EVM TPS65051EVM TPS65052EVM TPS65054EVM TPS65056EVM
VDCDC1 3.3 V 3.3 V 3.3 V 3.3 V 3.3 VVDCDC2 1.6 V 1.6 V 1 V 1.3 V 1 VVLDO1 3.3 V 3.3 V 3.3 V 3.3 V 3.3 VVLDO2 3.3 V 3.3 V 3.3 V 3.3 V 3.3 VVLDO3 1.85 V 1.2 V 1.85 V 1.85 V 1.85 VVLDO4 1.85 V 1.2 V 1.85 V 1.85 V 1.3 V
Table 2. Maximum Load Current
Output TPS65050EVM TPS65051EVM TPS65052EVM TPS65054EVM TPS65056EVM
VDCDC1 600 mA 1 A 1 A 600 mA 1 AVDCDC2 600 mA 600 mA 600 mA 600 mA 600 mAVLDO1 400 mA 400 mA 400 mA 400 mA 400 mAVLDO2 400 mA 400 mA 400 mA 400 mA 400 mAVLDO3 200 mA 200 mA 200 mA 200 mA 200 mAVLDO4 200 mA 200 mA 200 mA 200 mA 200 mA
1. Configure all EVM jumpers to factory settings shown in Table 3 .2. Connect the input voltage return to J2.3. Connect the positive input voltage to J1.4. Connect all loads to the outputs.5. Turn on input voltage.
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Setup
Table 3. Factory EVM Jumper SettingsJumper Shunt Location
TPS65050EVM TPS65051EVM TPS65052EVM TPS65054EVM TPS65056EVM
JP1 Between ON and Between ON and Between ON and Between ON and Between ON andENDCDC1 ENDCDC1 ENDCDC1 ENDCDC1 ENDCDC1
JP2 Between PWM and Between PWM and Between PWM and Between PWM and Between PWM andMODE MODE MODE MODE MODE
JP3 Between LOW and Not Installed Between LOW and Not Installed Not InstalledDEFLDO1 DEFLDO1
JP4 Between LOW and Not Installed Between LOW and Not Installed Not InstalledDEFLDO2 DEFLDO2
JP5 Between LOW and Not Installed Between LOW and Not Installed Not InstalledDEFLDO3 DEFLDO3
JP6 Between LOW and Not Installed Between LOW and Not Installed Not InstalledDEFLDO4 DEFLDO4
JP7 Between OFF and Between OFF and Between OFF and Between OFF and Between OFF andENDCDC2 ENDCDC2 ENDCDC2 ENDCDC2 ENDCDC2
JP8 Not Installed Not Installed Between LOW and Between LOW and Between LOW andDEFDCDC2 DEFDCDC2 DEFDCDC2
JP9 Between ON and Between ON and Between ON and Between ON and Between ON andENLDO1 ENLDO1 ENLDO1 ENLDO1 ENLDO1
JP10 Between ON and Between ON and Between ON and Between ON and Between ON andENLDO2 ENLDO2 ENLDO2 ENLDO1 ENLDO1
JP11 Between ON and Between ON and Between ON and Between ON and Between ON andENLDO3 ENLDO3 ENLDO3 ENLDO1 ENLDO1
JP12 Between ON and Between ON and Between ON and Between ON and Between ON andENLDO4 ENLDO4 ENLDO4 ENLDO1 ENLDO1
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3 Board Layout
3.1 Layout
Board Layout
This section provides the TPS6505xEVM-195 board layout and illustrations.
Figure 1 through Figure 5 show the board layout for the TPS6505xEVM-195 PCB.
Figure 1. Assembly Layer
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4.2 Bill of Materials
Schematic and Bill of Materials
Table 4. TPS6505xEVM-195 Bill of MaterialsCOUNT RefDes Value Description Size Part Number MFR
-001 -002 -003 -004 -005
1 1 1 1 1 C1 1.0 µF Capacitor, Ceramic, 25V, X5R, 10% 0603 GRM188R61E105KA12D Murata
0 0 0 1 1 C10 4.7 µF Capacitor, Ceramic, 6.3V, X5R, 10% 0603 GRM188R60J475KE19D Murata
1 1 1 0 0 10 µF Capacitor, Ceramic, 6.3V, X5R, 20% 0603 GRM188R60J106ME47D Murata
0 0 0 1 1 C13 4.7 µF Capacitor, Ceramic, 6.3V, X5R, 10% 0603 GRM188R60J475KE19D Murata
1 1 1 0 0 10 µF Capacitor, Ceramic, 6.3V, X5R, 20% 0603 GRM188R60J106ME47D Murata
1 1 1 0 0 C14 10 µF Capacitor, Ceramic, 6.3V, X5R, 20% 0603 GRM188R60J106ME47D Murata
0 0 0 1 1 2.2 µF Capacitor, Ceramic, 6.3V, X5R, 10% 0603 GRM188R60J225KE01D Murata
0 0 0 1 1 C15 2.2 µF Capacitor, Ceramic, 6.3V, X5R, 10% 0603 GRM188R60J225KE01D Murata
1 1 1 0 0 10 µF Capacitor, Ceramic, 6.3V, X5R, 20% 0603 GRM188R60J106ME47D Murata
1 1 1 1 1 C16 0.01 µF Capacitor, Ceramic, 50V, X7R, 10% 0603 C1608X7R1H103K TDK
3 3 3 3 3 C2–C3 2.2 µF Capacitor, Ceramic, 10V, X5R, 10% 0805 GRM216R61A225KE24D Murata
4 4 4 4 4 C5, C6, 10 µF Capacitor, Ceramic, 10V, X5R, 10% 0805 GRM21BR61A106KE19L MurataC8, C12
0 0 0 0 0 C7, C11 Open Capacitor, Ceramic, vvV 0805
1 1 0 1 1 C9 47pF Capacitor, Ceramic, 50V, COG, 5% 0603 C1608C0G1H470J TDK
15 15 15 15 15 J1–J15 Header, 2 pin, 100mil spacing, (36-pin 0.100 ×2 PTC36SAAN Sullinsstrip)
7 7 7 7 7 JP1, JP2, Header, 3 pin, 100mil spacing, (36-pin 0.100 ×3 PTC36SAAN SullinsJP7, strip)JP9–JP12
4 0 4 4 4 JP3–JP6 Header, 3 pin, 100mil spacing, (36-pin 0.100 ×3 PTC36SAAN Sullinsstrip)
0 0 1 0 0 JP8 Header, 3 pin, 100mil spacing, (36-pin 0.100 ×3 PTC36SAAN Sullinsstrip)
1 1 1 1 1 L1 3.3 µH Inductor, SMT, 1.3A, 130m Ω0.118 ×0.118 LPS3015-332MLC Coilcraft
1 1 1 1 1 L2 2.2 µH Inductor, SMT, 1.4A, 220m Ω0.118 ×0.118 LPS3010-222MLC Coilcraft
1 1 1 0 0 R1 1 Resistor, Chip, 1/16W, 1% 0603 Std Std
0 0 0 1 1 100 Resistor, Chip, 1/16W, 1% 0603 Std Std
3 3 3 3 3 R12–R14 0 Resistor, Chip, 1/16W, 5% 0603 Std Std
0 2 0 2 2 R2, R5 232k Resistor, Chip, 1/16W, 1% 0603 Std Std
0 1 0 0 0 R7 20k Resistor, Chip, 1/16W, 1% 0603 Std Std
0 0 0 1 1 30k Resistor, Chip, 1/16W, 1% 0603 Std Std
0 1 0 0 0 R9 20k Resistor, Chip, 1/16W, 1% 0603 Std Std
0 0 0 1 1 30k Resistor, Chip, 1/16W, 1% 0603 Std Std
1 1 0 0 0 R10 169k Resistor, Chip, 1/16W, 1% 0603 Std Std
0 1 1 0 0 R16 3.01k Resistor, Chip, 1/16W, 1% 0603 Std Std
0 0 0 1 1 3.32k Resistor, Chip, 1/16W, 1% 0603 Std Std
0 1 1 1 1 R17 237k Resistor, Chip, 1/16W, 1% 0603 Std Std
1 1 0 0 0 R18 453k Resistor, Chip, 1/16W, 1% 0603 Std Std
0 0 1 0 1 0 Resistor, Chip, 1/16W, 1% 0603 Std Std
0 0 0 1 0 200k Resistor, Chip, 1/16W, 1% 0603 Std Std
1 1 0 1 0 R19 100k Resistor, Chip, 1/16W, 1% 0603 Std Std
1 1 1 1 1 R20 10k Resistor, Chip, 1/16W, 1% 0603 Std Std
1 0 0 0 0 R21 0 Resistor, Chip, 1/16W, 1% 0603 Std Std
11 11 11 11 11 R3, R4, 100k Resistor, Chip, 1/16W, 1% 0603 Std StdR6, R8,R11, R15,R22–R25
1 0 0 0 0 SW1 Switch, SPST, PB momentary, sealed 0.245 ×0.251 KT11P2JM C & Kwashable
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Schematic and Bill of Materials
Table 4. TPS6505xEVM-195 Bill of Materials (continued)COUNT RefDes Value Description Size Part Number MFR
-001 -002 -003 -004 -005
1 0 0 0 0 U1 IC, Dual step-down converter with 4 QFN-32 TPS65050RSM TIfixed LDOs
0 1 0 0 0 IC, Dual step-down converter with 4 QFN-32 TPS65051RSM TIadjustable LDOs
0 0 1 0 0 IC, Dual fixed step-down converter with QFN-32 TPS65052RSM TI4 fixed LDOs
0 0 0 1 0 IC, Dual step-down converter with 4 QFN-32 TPS65054RSM TIfixed LDOs
0 0 0 0 1 IC, Dual step-down converter with 4 QFN-32 TPS65056RSM TIfixed LDOs
1 1 1 1 1 — PCB, 3.5 In ×2.9 In ×0.062 In HPA195 Any
11 7 12 11 11 — Shunt, 100 mil, Black 0.100 929950-00 3M
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EVALUATION BOARD/KIT IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATIONPURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling theproduct(s) must have electronics training and observe good engineering practice standards. As such, the goods being provided arenot intended to be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations,including product safety and environmental measures typically found in end products that incorporate such semiconductorcomponents or circuit boards. This evaluation board/kit does not fall within the scope of the European Union directives regardingelectromagnetic compatibility, restricted substances (RoHS), recycling (WEEE), FCC, CE or UL, and therefore may not meet thetechnical requirements of these directives or other related directives.Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BYSELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDINGANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from allclaims arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility totake any and all appropriate precautions with regard to electrostatic discharge.EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHERFOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive.
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This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATIONPURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. It generates, uses, andcan radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of thisequipment in other environments may cause interference with radio communications, in which case the user at his own expensewill be required to take whatever measures may be required to correct this interference.
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of 2.5 V to 6 V and the output voltage range of 1 V to VIN.Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there arequestions concerning the input range, please contact a TI field representative prior to connecting the input power.Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to theEVM. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the loadspecification, please contact a TI field representative.During normal operation, some circuit components may have case temperatures greater than 100 °C. The EVM is designed tooperate properly with certain components above 100 °C as long as the input and output ranges are maintained. These componentsinclude but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types ofdevices can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes nearthese devices during operation, please be aware that these devices may be very warm to the touch.
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