SN54ALS113A, SN74ALS113A
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH PRESET
SDAS200 – D2661, APRIL 1982 – REVISED MAY 1986
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1986, Texas Instruments Incorporated
5BASIC
1
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TYPE TYPICAL MAXIMUM
CLOCK FREQUENCY
TYPICAL POWER
DISSIPATION
PER FLIP-FLOP
’ALS113A 40 MHz (CL=15 pF) 6 mW
description
These devices contain two independent J-K
negative-edge-triggered flip-flops. A low level at
the Preset input sets the outputs regardless of the
levels of the other inputs. When Preset PRE is
inactive (high), data at the J and K inputs meeting
the setup time requirements are transferred to the
outputs on the negative-going edge of the clock
pulse. Clock triggering occurs at a voltage level
and is not directly related to the fall time of the
clock pulse. Following the hold time interval, data
at the J and K inputs may be changed without
affecting the levels at the outputs. These versatile
flip-flops can perform as toggle flip-flops by tying
J and K high.
The SN54ALS113A is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74ALS1 13A is characterized for
operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS OUTPUTS
PRE CLK J K Q Q
L X X X H L
H↓LLQ
0Q
0
H↓HL H L
H↓LH L H
H↓H H TOGGLE
H H X X Q0Q0
1Q
1Q
2Q
2Q
8
9
6
5
1K
C1
1J
S
12
2K
10
2PRE
13
2CLK
11
2J
2
1K
1
1CLK
3
1J
1PRE 4
logic symbol†
NC–No internal connection
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for D, J, and N packages.
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
2K
NC
2J
NC
2PRE
1J
NC
1PRE
NC
1Q
SN54ALS113A . . . FK PACKAGE
(TOP VIEW)
1K
1CLK
NC
2Q
2Q 2CLK
1Q
GND
NC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1 CLK
1K
1J
1PRE
1Q
1Q
GND
VCC
2CLK
2K
2J
2PRE
2Q
2Q
SN54ALS113A ...J PACKAGE
SN74ALS113A ...D OR N PACKAGE
(TOP VIEW)
VCC
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
UNIT
tsu Setup time before CLK↓ns
SN54ALS113A, SN74ALS113A
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH PRESET
SDAS200 – D2661, APRIL 1982 – REVISED MAY 1986
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2
logic diagram (positive logic)
CLK
J
Q
K
PRE
Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range: SN54ALS113A –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ALS113A 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions
SN54ALS113A SN74ALS113A
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
IOH High-level output current –0.4 –0.4 mA
IOL Low-level output current 4 8 mA
fclock Clock frequency 0 25 0 30 mHz
PRE low 20 10
twPulse duration CLK high 20 16.5 ns
CLK low 20 16.5
Data 25 22
PRE inactive 20 20
thHold time, data after CLK↓0 0 ns
TAOperating free-air temperature –55 125 0 70 °C
UNIT
VOL V
TEST CONDITIONSPARAMETER
II
IIH
IIL
VCC = 5.5 V, VI = 7 V
VI = 2.7 V
VI = 0.4 V
mA
µA
mA
VCC = 5.5 V,
VCC = 5.5 V,
PARAMETER UNIT
PRE
CLK
Q or Q ns
nsQ or Q
SN54ALS113A, SN74ALS113A
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH PRESET
SDAS200 – D2661, APRIL 1982 – REVISED MAY 1986
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3
electrical characteristic over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS113A SN74ALS113A
MIN TYP†MAX MIN TYP†MAX
VIK VCC = 4.5 V, II = –18 mA –1.5 –1.5 V
VOH VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC–2 VCC–2 V
VCC = 4.5 V, IOL = 4 mA 0.25 0.4 0.25 0.4
VCC = 4.5 V, IOL = 8 mA 0.35 0.5
J, K, or CLK 0.1 0.1
PRE 0.2 0.2
J, K, or CLK 20 20
PRE 40 40
J, K, or CLK –0.2 –0.2
PRE –0.4 –0.4
IO‡VCC = 5.5 V, VO = 2.25 V –30 –112 –30 –112 mA
ICC VCC = 5.5 V, See Note 1 2.5 4.5 2.5 4.5 mA
†All typical values are at VCC = 5 V, TA = 25°C.
‡The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
NOTE 1: ICC is measured with J, K, CLK, and PRE grounded, then with J, K, CLK, and CLR grounded.
switching characteristics (see Note 2)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
FROM TO RL = 500 Ω,
(INPUT) (OUTPUT) TA = MIN to MAX
SN54ALS113A SN74ALS113A
MIN MAX MIN MAX
fmax 25 30 MHz
tPLH 323 3 14
tPHL 4 26 4 18
tPLH 322 3 15
tPHL 5 23 5 19
NOTE 2: Load circuit and voltage waveforms are shown in Section 1.
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