CrossLink Automotive Family Data Sheet FPGA-DS-02013 Version 1.2 March 2018 CrossLink Automotive Family Data Sheet Contents Acronyms in This Document ................................................................................................................................................. 5 1. General Description ...................................................................................................................................................... 6 1.1. Features ............................................................................................................................................................... 6 2. Product Feature Summary ............................................................................................................................................ 7 3. Architecture Overview .................................................................................................................................................. 8 3.1. MIPI D-PHY Blocks ............................................................................................................................................... 9 3.2. Programmable I/O Banks .................................................................................................................................. 13 3.3. sysI/O Buffers .................................................................................................................................................... 15 3.3.1. Programmable PULLMODE Settings .............................................................................................................15 3.3.2. Output Drive Strength ...................................................................................................................................15 3.3.3. On-Chip Termination ....................................................................................................................................15 3.4. Programmable FPGA Fabric .............................................................................................................................. 16 3.4.1. PFU Blocks .....................................................................................................................................................16 3.4.2. Slice ...............................................................................................................................................................17 3.5. Clocking Structure ............................................................................................................................................. 20 3.5.1. sysCLK PLL .....................................................................................................................................................20 3.5.2. Primary Clocks ...............................................................................................................................................21 3.5.3. Edge Clocks ...................................................................................................................................................21 3.5.4. Dynamic Clock Enables .................................................................................................................................22 3.5.5. Internal Oscillator (OSCI) ...............................................................................................................................22 3.6. Embedded Block RAM Overview ....................................................................................................................... 23 3.7. Power Management Unit .................................................................................................................................. 23 3.7.1. PMU State Machine ......................................................................................................................................24 3.8. User I2C IP .......................................................................................................................................................... 25 3.9. Programming and Configuration ....................................................................................................................... 26 4. DC and Switching Characteristics................................................................................................................................ 27 4.1. Absolute Maximum Ratings .............................................................................................................................. 27 4.2. Recommended Operating Conditions ............................................................................................................... 27 4.3. Power Supply Ramp Rates ................................................................................................................................. 28 4.4. Power-On-Reset Voltage Levels ........................................................................................................................ 28 4.5. ESD Performance ............................................................................................................................................... 28 4.6. DC Electrical Characteristics .............................................................................................................................. 29 4.7. CrossLink Automotive Supply Current............................................................................................................... 30 4.8. Power Management Unit (PMU) Timing ........................................................................................................... 31 4.9. sysI/O Recommended Operating Conditions .................................................................................................... 31 4.10. sysI/O Single-Ended DC Electrical Characteristics ............................................................................................. 31 4.11. sysI/O Differential Electrical Characteristics ..................................................................................................... 32 4.11.1. LVDS/subLVDS/SLVS200 ...........................................................................................................................32 4.11.2. Hardened MIPI D-PHY I/Os .......................................................................................................................33 4.12. CrossLink Automotive Maximum General Purpose I/O Buffer Speed ............................................................... 34 4.13. CrossLink Automotive External Switching Characteristics ................................................................................ 35 4.14. sysCLOCK PLL Timing ......................................................................................................................................... 40 4.15. Hardened MIPI D-PHY Performance.................................................................................................................. 41 4.16. Internal Oscillators (HFOSC, LFOSC) .................................................................................................................. 41 4.17. User I2C1............................................................................................................................................................. 41 4.18. CrossLink Automotive sysCONFIG Port Timing Specifications .......................................................................... 42 4.19. SRAM Configuration Time from NVCM ............................................................................................................. 42 4.20. Switching Test Conditions ................................................................................................................................. 43 5. Pinout Information ..................................................................................................................................................... 44 5.1. ctfBGA80/cktBGA80 Pinout ............................................................................................................................... 44 5.2. Dual Function Pin Descriptions ......................................................................................................................... 46 5.3. Dedicated Function Pin Descriptions ................................................................................................................ 47 (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 2 FPGA-DS-02013-1.2 CrossLink Automotive Family Data Sheet 5.4. Pin Information Summary ................................................................................................................................. 47 CrossLink Automotive Part Number Description ........................................................................................................ 48 6.1. Ordering Part Numbers ..................................................................................................................................... 48 References .......................................................................................................................................................................... 49 Technical Support ............................................................................................................................................................... 49 Revision History .................................................................................................................................................................. 50 6. Figures Figure 3.1. CrossLink Automotive Device Block Diagram ..................................................................................................... 8 Figure 3.2. CrossLink Automotive sysI/O Banking ................................................................................................................ 9 Figure 3.3. MIPI DSI Transmit Interface with Hard D-PHY Module ..................................................................................... 10 Figure 3.4. MIPI CSI-2 Transmit Interface with Hard D-PHY Module .................................................................................. 11 Figure 3.5. MIPI DSI Receive Interface with Hard D-PHY Module ...................................................................................... 12 Figure 3.6. MIPI CSI-2 Receive Interface with Hard D-PHY Module.................................................................................... 13 Figure 3.7. CrossLink Automotive Device Simplified Block Diagram (Top Level) ................................................................ 16 Figure 3.8. CrossLink Automotive PFU Diagram ................................................................................................................. 17 Figure 3.9. Slice Diagram .................................................................................................................................................... 18 Figure 3.10. Connectivity Supporting LUT5, LUT6, LUT7 and LUT8 .................................................................................... 19 Figure 3.11. CrossLink Automotive PLL Block Diagram ....................................................................................................... 20 Figure 3.12. CrossLink Automotive Clocking Structure ....................................................................................................... 21 Figure 3.13. CrossLink Automotive Edge Clock Sources per Bank ...................................................................................... 22 Figure 3.14. CrossLink Automotive OSCI Component Symbol ............................................................................................ 22 Figure 3.15. CrossLink Automotive MIPI D-PHY Block ........................................................................................................ 24 Figure 3.16. CrossLink Automotive PMU State Machine .................................................................................................... 24 Figure 4.1. Receiver RX.CLK.Centered Waveforms ............................................................................................................. 38 Figure 4.2. Receiver RX.CLK.Aligned Input Waveforms ...................................................................................................... 38 Figure 4.3. Transmit TX.CLK.Centered Output Waveforms ................................................................................................ 38 Figure 5.5. DDRX71, DDRX141 Video Timing Waveforms .................................................................................................. 39 Figure 4.6. Output Test Load, LVTTL and LVCMOS Standards ............................................................................................ 43 (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.2 3 CrossLink Automotive Family Data Sheet Tables Table 2.1. CrossLink Automotive Feature Summary .............................................................................................................7 Table 3.1. CrossLink Automotive Output Support per Bank Basis ......................................................................................14 Table 3.2. CrossLink Automotive Input Support per Bank Basis .........................................................................................15 Table 3.3. Drive Strength Values .........................................................................................................................................15 Table 3.4. Slice Signal Descriptions .....................................................................................................................................19 Table 3.5. CrossLink Automotive PLL Port Definition .........................................................................................................20 Table 3.6. OSCI Component Port Definition .......................................................................................................................22 Table 3.7. OSCI Component Attribute Definition ...............................................................................................................22 Table 3.8. sysMEM Block Configurations ............................................................................................................................23 Table 3.9. CrossLink Automotive sysCONFIG Pins ..............................................................................................................26 Table 4.1. Absolute Maximum Ratings1, 2, 3 .........................................................................................................................27 Table 4.2. Recommended Operating Conditions1, 2 ............................................................................................................27 Table 4.3. Power Supply Ramp Rates1 ................................................................................................................................28 Table 4.4. Power-On-Reset Voltage Levels1, 3, 4 ...................................................................................................................28 Table 4.5. DC Electrical Characteristics ...............................................................................................................................29 Table 4.6. CrossLink Automotive Supply Current ...............................................................................................................30 Table 4.7. PMU Timing* ......................................................................................................................................................31 Table 4.8. sysI/O Recommended Operating Conditions1....................................................................................................31 Table 5.9. sysI/O Single-Ended DC Electrical Characteristics ..............................................................................................31 Table 4.10. LVDS/subLVDS1/SLVS2001, 2..............................................................................................................................32 Table 4.11. MIPI D-PHY .......................................................................................................................................................33 Table 4.12. CrossLink Automotive Maximum I/O Buffer Speed .........................................................................................34 Table 4.13. CrossLink Automotive External Switching Characteristics4, 5 ...........................................................................35 Table 4.14. sysCLOCK PLL Timing ........................................................................................................................................40 Table 4.15. 1500 Mb/s MIPI_DPHY_X8_RX/TX Timing Table (1500 Mb/s > MIPI D-PHY Data Rate > 1200 Mb/s) ............41 Table 4.16. 1200 Mb/s MIPI_DPHY_X4_RX/TX Timing Table (1200 Mb/s > MIPI D-PHY Data Rate > 1000 Mb/s) ............41 Table 5.17. 1000 Mb/s MIPI_DPHY_X4_RX/TX Timing Table (1000 Mb/s > MIPI D-PHY Data Rate > 10 Mb/s) ................41 Table 5.18. Internal Oscillators ...........................................................................................................................................41 Table 5.19. User I2C1 ...........................................................................................................................................................41 Table 5.20. CrossLink Automotive sysCONFIG Port Timing Specifications .........................................................................42 Table 5.21. SRAM Configuration Time from NVCM ............................................................................................................42 Table 4.22. Test Fixture Required Components, Non-Terminated Interfaces ....................................................................43 (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 4 FPGA-DS-02013-1.2 CrossLink Automotive Family Data Sheet Acronyms in This Document A list of acronyms used in this document. Acronym AR Definition Augmented Reality ASIC BGA Application-Specific Integrated Circuit Ball Grid Array CMOS CSI DBI Complementary Metal Oxide Semiconductor Camera Serial Interface Display Bus Interface DPI DSI EBR Display Pixel Interface Display Serial Interface Embedded Block RAM ECLK FPD Edge Clock Flat Panel Display FPGA GPIO HFOSC Field-Programmable Gate Array General-Purpose Input/Output High Frequency Oscillator HMI I2C Human Machine Interface Inter-Integrated Circuit ISM LFOSC LUT Industrial, Scientific, Medical Low Frequency Oscillator Look Up Table LVCMOS LVDS LVTTL Low-Voltage Complementary Metal Oxide Semiconductor Low-Voltage Differential Signaling Low-Voltage Transistor-Transistor Logic MIPI NVCM Mobile Industry Processor Interface Non-Volatile Configuration Memory OTP PCLK PFU One Time Programmable Primary Clock Programmable Functional Unit PLL PMU Phase Locked Loops Power Management Unit RAM Rx SLVS200 Random Access Memory receive Scalable Low-Voltage Signaling SPI TransFR Serial Peripheral Interface Transparent Field Reconfiguration Tx UHD VR Transmit Ultra-High Definition Virtual Reality WLCSP Wafer Level Chip Scale Packaging (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.2 5 CrossLink Automotive Family Data Sheet 1. General Description CrossLinkTM Automotive from Lattice Semiconductor is a programmable video bridging device that supports a variety of protocols and interfaces for mobile image sensors and displays. The device is based on Lattice mobile FPGA 40nm technology. It combines the extreme flexibility of an FPGA with the low power, low cost and small footprint of an ASIC. CrossLink Automotive supports video interfaces including MIPI(R) DPI, MIPI DBI, CMOS camera and display interfaces, OpenLDI, FPD-Link, FLATLINK, MIPI D-PHY, MIPI CSI-2, MIPI DSI, SLVS200, SubLVDS, HiSPi and more. Lattice Semiconductor provides many pre-engineered IP (Intellectual Property) modules for CrossLink Automotive. By using these configurable soft core IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity. The Lattice Diamond(R) design software allows large complex designs to be efficiently implemented using CrossLink Automotive. Synthesis library support for CrossLink Automotive devices is available for popular logic synthesis tools. The Diamond tools use the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the CrossLink Automotive device. The tools extract the timing from the routing and back-annotate it into the design for timing verification. Interfaces on CrossLink Automotive provide a variety of bridging solutions for smart phone, tablets, wearables, VR, AR, Drone, Smart Home, HMI as well as adjacent ISM markets. The device is capable of supporting high-resolution, high-bandwidth content for mobile cameras and displays at 4k UHD and beyond. 1.1. Features Ultra-low power Sleep Mode Support Normal Operation - From 5 mW to 150 mW Small footprint page 80-ball ctfBGA (42 mm2) 80-ball ckfBGA (49 mm2) Programmable architecture 5936 LUTs 180 kb block RAM 47 kb distributed RAM Two hardened 4-lane MIPI D-PHY interfaces Transmit and receive 6 Gb/s per D-PHY interface Programmable source synchronous I/O MIPI D-PHY Rx, LVDS Rx, LVDS Tx, SubLVDS Rx, SLVS200 Rx, HiSPi Rx Up to 1200 Mb/s per I/O Four high-speed clock inputs Programmable CMOS I/O LVTTL and LVCMOS 3.3 V, 2.5 V, 1.8 V and 1.2 V (outputs) LVCMOS differential outputs Flexible device configuration One Time Programmable (OTP) non-volatile configuration memory Master SPI boot from external flash Dual image booting supported I2C programming SPI programming TransFRTM I/O for simple field updates Enhanced system level support Reveal logic analyzer TraceID for system tracking On-chip hardened I2C block Applications examples Dual MIPI CSI-2 to Single MIPI CSI-2 Aggregation Qual MIPI CSI-2 to Single MIPI CSI-2 Aggregation Single MIPI DSI to Single MIPI DSI Repeater Single MIPI CSI-2 to Single MIPI CSI-2 Repeater Single MIPI DSI to Dual MIPI DSI Splitter Single MIPI CSI-2 to Dual MIPI CSI-2 Splitter MIPI DSI to OpenLDI/FPD-Link/LVDS Translator OpenLDI/FPD-Link/LVDS to MIPI DSI Translator MIPI DSI/CSI-2 to CMOS Translator CMOS to MIPI DSI-2 Translator SubLVDS to MIPI CSI-2 Translator (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 6 FPGA-DS-02013-1.2 CrossLink Automotive Family Data Sheet 2. Product Feature Summary Table 2.1 lists CrossLink Automotive device information and packages. Table 2.1. CrossLink Automotive Feature Summary Device CrossLink Automotive LUTs 5936 sysMEM Blocks (9 kb) 20 Embedded Memory (kb) 180 Distributed RAM Bits (kb) 47 General Purpose PLL 1 NVCM Yes Embedded I2C 2 Oscillator (10 KHz) 1 Oscillator (48 MHz) 1 Hardened MIPI D-PHY 2* Packages (Footprint, Pitch) I/O 80 ctfBGA (6.5 x 6.5 mm2, 0.65 mm) 37 80 ckfBGA (7.0 x 7.0 mm2, 0.65 mm) 37 *Note: Additional D-PHY Rx interfaces are available using programmable I/O. (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.2 7 CrossLink Automotive Family Data Sheet 3. Architecture Overview CrossLink Automotive is designed as a flexible, chip-to-chip bridging solution which supports a wide variety of applications. The device provides three key building blocks for these bridging applications: Up to two embedded Hard D-PHY blocks Two banks of flexible programmable I/O supporting a variety of standards including D-PHY Rx, subLVDS, SLVS200, LVDS, and CMOS A programmable logic core providing the LUTs, memory, and system resources to implement a wide range of bridging operations In addition to these blocks, CrossLink Automotive also provides key system resources including a Power Management Unit, flexible configuration interface, additional CMOS GPIO, and user I 2C blocks. The block diagram for the device is shown in Figure 3.1. Programmable IO MIPI D-PHY Rx: D-PHY/SubLVDS/LVDS/ SLVS200/CMOS Tx: LVDS/CMOS Up to 1.2 Gb/s per Lane 14 IO/7 Pairs Programmable IO Rx: D-PHY/SubLVDS/LVDS/ SLVS200/CMOS Programmable FPGA Fabric 5,936 LUTs 180 kbits block RAM 47 kbits distributed RAM Enough FPGA resources to handle video: Muxing Merging Demuxing Arbitration Splitting Data Conversion Custom Protocol Design 6 Gb/s Rx and Tx 4 Data Lanes 1 Clock Lane MIPI D-PHY 6 Gb/s Rx and Tx Tx: LVDS/CMOS 4 Data Lanes 1 Clock Lane Up to 1.2 Gb/s per Lane 16 IO/8 Pairs Power Management Unit GPIOs I2C/SPI* Figure 3.1. CrossLink Automotive Device Block Diagram *Note: I2C and SPI configuration modes are supported. User mode hardened I2C is also supported. (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 8 FPGA-DS-02013-1.2 CrossLink Automotive Family Data Sheet 3.1. MIPI D-PHY Blocks The top side of the device (Figure 3.2) includes two hard MIPI D-PHY quads. The D-PHY can be configured to support both camera interface (CSI-2) and display interface (DSI) applications. Below is a summary of the features supported by the hard D-PHY quads. Transmit and Receive compliant to MIPI Alliance Specification D-PHY Revision 1.1 High-Speed (HS) and Low-Power (LP) mode support (including built-in contention detect) Supports continuous clock mode or low power clock mode Up to 6 Gb/s per quad (1500 Mb/s data rate per lane) Dedicated PLL for Transmit Frequency Synthesis Dedicated Serializer and De-Serializer blocks for fabric interfacing Lattice Semiconductor provides a set of pre-engineered IP modules which include the full implementation and control of the hard D-PHY blocks to enable designers to focus on unique aspects of their design. Figure 3.3 to Figure 3.6 show the signals connected to the fabric and the automatic settings when the hardened D-PHY is configured for the DSI/CSI-2 transmit and receive modes. Refer to CrossLink High-Speed I/O Interface (FPGA-TN02012) for more information on the Hard D-PHY quads. TOP MIPI D-PHY 0 MIPI D-PHY 1 Bank 2 Bank 1 Bank 0 VCCIO0 GND VCCIO1 GND VCCIO2 GND BOTTOM Figure 3.2. CrossLink Automotive sysI/O Banking (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.2 9 CrossLink Automotive Family Data Sheet MIPIDPHYA CLKP CLKN DP[3:1] DN[3:1] Bidirectional clk and data DP0 DN0 RX - Data LP ports D0_TXHSEN TX - Data HS ports TXHSBYTECLK Dy_HSTXDATA[15:0] D0_TXLPEN D0_RXLPP D0_RXLPN TX - Data LP ports D0_TXLPP D0_TXLPN Dx_TXLPP Dx_TXLPN CLK_TXHSEN CLK_TXHSGATE CLK_TXLPP TX - CLK HS ports TX - CLK LP ports CLK_TXLPN USRSTDBY PDPLL REFCLK Control Ports PLL Ports LOCK * x = 1, 2, 3 y = 0, 1, 2, 3 Figure 3.3. MIPI DSI Transmit Interface with Hard D-PHY Module (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 10 FPGA-DS-02013-1.2 CrossLink Automotive Family Data Sheet MIPIDPHYA CLKP CLKN DP[3:1] DN[3:1] Bidirectional clk and data DP0 DN0 D0_TXHSEN TX - Data HS ports TXHSBYTECLK Dy_HSTXDATA[15:0] D0_TXLPEN TX - Data LP ports TX - CLK HS ports CLK_TXHSEN CLK_TXHSGATE TX - CLK LP ports CLK_TXLPP CLK_TXLPN CLK_TXLPEN Control Ports USRSTDBY PDPLL PLL Ports REFCLK LOCK * x = 1, 2, 3 y = 0, 1, 2, 3 Figure 3.4. MIPI CSI-2 Transmit Interface with Hard D-PHY Module (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.2 11 CrossLink Automotive Family Data Sheet MIPIDPHYA CLKP CLKN DPx DNx Bidirectional clk and data DP0 DN0 RX - Data HS ports Dy_HSRXDATA[15:0] RXHSBYTECLK DO_RXHSEN RX - Data LP ports DO_RXLPEN D0_RXLPP D0_RXLPN D0_CD RX - CLK HS ports CLKRXHSEN CLKHSBYTE RX - CLK LP ports CLKRXLPEN CLK_RXLPP CLK_RXLPN CLK_CD TX - Data LP ports D0_TXLPP D0_TXLPN Control Ports USRSTDBY * x = 1, 2, 3 y = 0, 1, 2, 3 Figure 3.5. MIPI DSI Receive Interface with Hard D-PHY Module (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 12 FPGA-DS-02013-1.2 CrossLink Automotive Family Data Sheet MIPIDPHYA Bidirectional clk and data CLKP CLKN DPx DNx DP0 DN0 RX - Data HS ports Dy_HSRXDATA[15:0] RXHSBYTECLK RX - Data LP ports D0_RXLPP D0_RXLPN D0_CD RX - CLK HS ports CLKHSBYTE RX - CLK LP ports CLK_RXLPP CLK_RXLPN CLK_CD Control Ports USRSTDBY * x = 1, 2, 3 y = 0, 1, 2, 3 Figure 3.6. MIPI CSI-2 Receive Interface with Hard D-PHY Module 3.2. Programmable I/O Banks CrossLink Automotive devices provide programmable I/O which can be used to interface to a variety of external standards on Banks 1 and 2. CrossLink Automotive devices also provide dedicated CMOS GPIOs on Bank 0. Bank 0 GPIOs only support Single Data Rate (SDR) interfaces, while Bank 1 and Bank 2 support both SDR and Double Data Rate (DDR) interfaces. The GPIOs on Bank 0 do not include differential signaling capabilities. The location of the three Banks and their associated supplies are shown in Figure 3.2. Bank 0 features: Support the following single ended standards (ratioed to V CCIO) LVCMOS33 LVCMOS25 LVCMOS18 LVTTL33 Tri-state control for output (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.2 13 CrossLink Automotive Family Data Sheet Input/output register blocks Open-drain option and programmable input hysteresis Internal pull-up resistors with configurable values of 3.3 k, 6.8 k and 10 k Bank 1 and Bank 2 features: Built-in support for the following differential standards LVDS - Tx and Rx SLVS200 - Rx SubLVDS - Rx MIPI - Rx (both LP and HS receive on a single differential pair) Support for the following single ended standards (ratioed to V CCIO) LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS12 (Outputs Only) LVTTL33 Independent voltage levels per bank based on VCCIO supply Input/output gearboxes per LVDS pair supporting several ratios for video interface applications DDRX1, DDRX2, DDRX4, DDRX8 and DDRX71, DDRX141 Programmable delay cells to support edge-aligned and center-aligned interfaces Programmable differential termination (~ 100 ) with dynamic enable control Tri-state control for output Input/output register blocks Single-ended standards support open-drain and programmable input hysteresis Optional weak pull-up resistors Table 3.1. CrossLink Automotive Output Support per Bank Basis OUTPUT LVCMOS12 LVCMOS18 LVCMOS25 LVCMOS33 LVTTL33 LVDS25 BANK 0 -- BANK 1 BANK 2 -- (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 14 FPGA-DS-02013-1.2 CrossLink Automotive Family Data Sheet Table 3.2. CrossLink Automotive Input Support per Bank Basis INPUT BANK 0 BANK 1 BANK 2 -- LVCMOS33 LVTTL33 LVDS25 MIPI D-PHY SLVS200 -- -- -- subLVDS -- LVCMOS12 LVCMOS18 LVCMOS25 3.3. sysI/O Buffers The CrossLink Automotive sysI/O buffers are distributed across three banks located at the bottom of the CrossLink Automotive device as shown in Figure 3.2. The sysI/O buffers support a wide variety of standards to interface to a range of systems including LVDS, subLVDS, LVCMOS, LVTTL, SLVS200 and MIPI. CrossLink Automotive supports singleended buffers on all three banks. Differential I/O is supported on Bank 1 and Bank 2. 3.3.1. Programmable PULLMODE Settings The CrossLink Automotive sysI/O buffers offer multiple programmable value pull-up resistors on the three banks. The pull-up values are programmable on a "per-pin" basis. The default state of the I/O pins prior to configuration is tristated with a weak pull-up to VCCIOx. The I/O pins convert to the software user-defined settings after the configuration bitstream has been successfully downloaded to the device. Each sysIO buffer can be programmed with a 100 k (weak pull-up), 3.3 k, 6.8 k, 10 k or no pull-up. These pull-up options allow an I2C interface to be place on the majority of the pins on the device. These options are not exclusively for I 2C protocol and may be used for other functions. 3.3.2. Output Drive Strength Each CrossLink Automotive output can have its own individual drive strength setting, but is predefined based on the VCCIOx setting. Table 3.3 lists the drive settings for the corresponding I/O type. Table 3.3. Drive Strength Values VCCIOx (V) I/O Type Drive Strength (mA) 3.3 LVTTL33 8 3.3 LVCMOS33 8 2.5 LVCMOS25 6 1.8 LVCMOS18 4 1.2 LVCMOS12 2 3.3.3. On-Chip Termination Bank 1 and bank 2 of CrossLink Automotive support LVDS, SLVS200 subLVDS and MIPI D-PHY inputs. These two banks support on-chip 100 input differential termination between LVDS, SLVS200 and subLVDS pairs. For MIPI D-PHY inputs, the on-chip 100 termination is dynamically enabled based on the HSSEL (High Speed Select) signal. See CrossLink High-Speed I/O Interface (FPGA-TN-02012) and CrossLink sysI/O Usage Guide (FPGA-TN-02016) for details. (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.2 15 CrossLink Automotive Family Data Sheet 3.4. Programmable FPGA Fabric MIPI D-PHY 0 PFU PFU I2C1 NVCM I2C0 CrossLink Automotive is built around a programmable logic fabric consisting of 5936 four input lookup tables (LUT4) arranged alongside dedicated registers in Programmable Functional Units (PFU). These PFU blocks are the building blocks for logic, arithmetic, RAM and ROM functions. The PFU blocks are connected via a programmable routing network. The Lattice Diamond design software configures the PFU blocks and the programmable routing for each unique design. Interspersed between rows of PFU are rows of sysMEMTM Embedded Block RAM (EBR), with programmable I/O banks, embedded I2C and embedded MIPI D-PHY arranged on the top and bottom of the device as shown in Figure 3.7. MIPI D-PHY 1 PFU PFU PFU 4 EBR Blocks (9 kb each) 4 EBR Blocks (9 Kb each) 4 EBR Blocks (9 kb each) PFU PFU PFU PFU PFU Bank 2 Clocking PLL OSC Bank 1 DDRDLL1 4 EBR Blocks (9 kb each) DDRDLL2 4 EBR Blocks (9 kb each) PMU CONFIG Bank 0 Figure 3.7. CrossLink Automotive Device Simplified Block Diagram (Top Level) 3.4.1. PFU Blocks The core of the CrossLink Automotive device consists of PFU blocks. Each PFU block consists of four interconnected slices numbered 0 - 3 as shown in Figure 3.8. Each slice contains two LUTs. All the interconnections to and from PFU blocks are from routing. The PFU block can be used in Distributed RAM or ROM function, or used to perform Logic, Arithmetic or ROM functions. (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 16 FPGA-DS-02013-1.2 CrossLink Automotive Family Data Sheet From Routing LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY Slice 0 LUT4 & CARRY Slice 1 D FF LUT4 & CARRY D FF LUT4 & CARRY D D FF FF LUT4 & CARRY Slice 3 Slice 2 D FF LUT4 & CARRY D D FF FF D FF To Routing Figure 3.8. CrossLink Automotive PFU Diagram 3.4.2. Slice Each slice contains two LUT4s feeding two registers. Each PFU contains logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock select, chip-select and wider RAM/ROM functions. Figure 3.9. shows an overview of the internal logic of the slice. The registers in the slice can be configured for positive/negative and edge triggered or level sensitive clocks. Each slice has 14 input signals: 13 signals from routing and 1 signal from the carry-chain routed from the adjacent slice or PFU. There are five outputs: four to routing and one to carry-chain (to the adjacent PFU). There are two inter slice/PFU output signals that are used to support wider LUT functions, such as LUT6, LUT7, and LUT8. Table 3.4 and Figure 3.9. list the signals associated with all the slices. Figure 3.10 shows the connectivity of the inter-slice/PFU signals that support LUT5, LUT6, LUT7, and LUT8. (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.2 17 CrossLink Automotive Family Data Sheet FCO FXA FXB M1 M0 A1 B1 C1 D1 LUT4 & CARRY* F1 F1 FF Q1 A0 B0 C0 D0 LUT4 & CARRY* F0 F0 FF Q0 CE CLK LSR FCI From Different Slice/PFU Notes: For Slices 0 and 1, memory control signals are generated from Slice 2 as follows: WCK is CLK WRE is from LSR DI[3:2] for Slice 1 and DI[1:0] for Slice 0 data from Slice 2 WAD [A:D] is a 4-bit address from slice 2 LUT input Figure 3.9. Slice Diagram (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 18 FPGA-DS-02013-1.2 CrossLink Automotive Family Data Sheet Q1 A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA F0 LUT5 Q0 F1 LUT6 Q1 LUT5 F0 Q0 Q1 F0 LUT5 Q0 A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA F1 LUT7 Q1 LUT5 F0 Q0 F1 LUT6 Q1 LUT5 F0 Q0 A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA 3 SLICE F0 LUT5 Q0 LUT7 Output From Previous PFU F1 LUT6 2 A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA Q1 Q1 SLICE 3 SLICE 2 LUT6 LUT8 F0 LUT5 Q0 F1 LUT7 1 LUT7 F1 F1 Q1 SLICE F1 A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA F0 LUT5 Q0 F1 LUT6 0 Q0 F0 LUT5 Q0 SLICE F0 LUT5 Q1 1 SLICE Q1 F1 SLICE LUT6 2 F1 PFU Col(n+1) LUT8 0 Q0 A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA SLICE 3 SLICE F0 LUT5 1 A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA Q1 SLICE A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA LUT8 0 LUT7 Output To Next PFU PFU Col(n) F1 SLICE A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA Q1 SLICE PFU Col(n-1) LUT5 F0 Q0 Figure 3.10. Connectivity Supporting LUT5, LUT6, LUT7 and LUT8 Table 3.4. Slice Signal Descriptions Function Type Signal Names Description Input Data signal A0, B0, C0, D0 Inputs to LUT4 Input Data signal A1, B1, C1, D1 Inputs to LUT4 Input Multi-purpose M0 Multipurpose Input Input Multi-purpose M1 Multipurpose Input Input Control signal CE Clock Enable Input Control signal LSR Local Set/Reset Input Control signal CLK System Clock Input Inter-PFU signal FCI Fast Carry-in1 Input Inter-slice signal FXA Intermediate signal to generate LUT6, LUT7 and LUT82 Input Inter-slice signal FXB Intermediate signal to generate LUT6, LUT7 and LUT82 Output Data signals F0, F1 LUT4 output register bypass signals Output Data signals Q0, Q1 Register outputs Output Inter-PFU signal FCO Fast carry chain output1 Notes: See Figure 3.9. for connection details. Requires two adjacent PFUs. (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.2 19 CrossLink Automotive Family Data Sheet 3.5. Clocking Structure The CrossLink Automotive device family provides resources to support a wide range of clocking requirements for programmable video bridging. These resources are described below. For details, refer to CrossLink sysCLOCK PLL/DLL Design and Usage Guide (FPGA-TN-02015). 3.5.1. sysCLK PLL The CrossLink Automotive sysCLK PLL provides the ability to synthesis clock frequencies (See Table 4.14 for input frequency range). The PLL provides features such as dynamic selectable clock input, clock injection delay removal, independent dynamic output enable control, and programmable output phase adjustment. The architecture of the PLL is shown in Figure 3.11 and followed by a description of the PLL blocks. Figure 3.11. CrossLink Automotive PLL Block Diagram Table 3.5 provides a description of the signals in the PLL block. Table 3.5. CrossLink Automotive PLL Port Definition Signal I/O Description CLKI CLKFB USRSTDBY I I I Input clock to PLL Feedback clock User port to put the PLL to sleep mode PHASESEL[1:0] PHASEDIR PHASESTEP I I I Select the output affected by Dynamic Phase adjustment Dynamic phase adjustment direction Dynamic phase adjustment step PHASELOADREG RST I I Load dynamic phase adjustment values into PLL Resets the whole PLL ENCLKOP ENCLKOS ENCLKOS2 I I I Enable PLL output CLKOP Enable PLL output CLKOS Enable PLL output CLKOS2 ENCLKOS3 PLLWAKESYNC I I Enable PLL output CLKOS3 Enable PLL switching from internal to user feedback path when PLL wake up CLKOP CLKOS CLKOS2 O O O PLL main output clock PLL output clock PLL output clock CLKOS3 LOCK O O PLL output clock PLL LOCK to CLKI, asynchronous signal. Active high indicates PLL lock (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 20 FPGA-DS-02013-1.2 CrossLink Automotive Family Data Sheet 3.5.2. Primary Clocks The primary clock routing network is made up of low skew clock routing resources with connectivity to every synchronous element of the device. Primary clock sources are selected in the center mux and distributed on the primary clock routing to clock the synchronous elements in the FPGA fabric. CrossLink Automotive family of devices provide up to eight unique global primary clocks. Primary clock sources are: LVDS PIO pins GPIO pins PLL outputs Clock dividers Fabric internally generated clock signal Divided down clock from DPHY OSCI The routing clock structure is shown in Figure 3.12. MIPI_DPHY0 CLK_HS_BYTE_0 MIPI_DPHY1 HS_BYTE_CLK0 (RX and TX) HS_BYTE_CLK1 (RX and TX) CLK_HS_BYTE_0 2 2 Center Mux (8 PCLKs out) Fabric Entry Fabric Entry 2 2 OSC_HF OSC_LF PLL OSC CLKDIV CLKDIV CLKDIV CLKDIV Edge Clock s Edge Clock s Bank 2 GRPIO LVDS PIO LVDS PIO Bank 0 Bank 1 LVDS PIO LVDS PIO LVDS PIO LVDS PIO GRPIO GPIO GPIO Figure 3.12. CrossLink Automotive Clocking Structure 3.5.3. Edge Clocks The CrossLink Automotive device has Edge Clock (ECLK) at the bottom 2 banks (Bank 1 and Bank 2) of the device (Figure 3.2). The CrossLink Automotive device has 2 edge clocks per Programmable I/O bank. These clocks, which have low injection time and skew, are used to clock I/O registers. Edge clock resources are designed for high speed I/O interfaces with high fan-out capability. The sources of edge clocks are: Dedicated Clock (PCLK) pins muxed with the DLLDEL output PLL outputs (CLKOP and CLKOS) Internal nodes ELCK input MUX collects all clock sources as shown in Figure 3.13 below. There are two ECLK Input MUXs, one on each bank. It drives the ECLK SYNC modules and the ECLK Clock Divider through a 2 to 1 MUX. (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.2 21 CrossLink Automotive Family Data Sheet From ECLKSYNC of other bank on same side Bank 1 or Bank 2 LVDS PCLK Pin Bank 1 or Bank 2 DLLDEL Output ECLK Tree PLL CLKOP ECLKSYNCB PLL CLKOS From Routing To ECLK of other bank on same side Figure 3.13. CrossLink Automotive Edge Clock Sources per Bank 3.5.4. Dynamic Clock Enables Each PLL output has a user input signal to dynamically enable/disable its output to provide a glitch free clock. Then the clock enable signal is set to logic `0', the corresponding output clock is held to logic `0'. This allows the user to save power by stopping the corresponding output clock when not in use. 3.5.5. Internal Oscillator (OSCI) The OSCI element performs multiple functions on the CrossLink Automotive device. It is used for configuration and available during user mode. OSCI element has the following features in user mode: Always-on low frequency clock output (LFCLKOUT) with nominal frequency of 10 kHz High-frequency clock output (HFCLKOUT) with nominal frequency of 48 MHz that can be enabled or disabled using HFOUTEN input Programmable output dividers (HFCLKDIV) for 48 MHz, 24 MHz, 12 MHz or 6 MHz HFCLKOUT output Both output clocks have a direct connection to primary clock routing Figure 3.14, Table 3.6 and Table 3.7 below show the OSCI definitions Figure 3.14. CrossLink Automotive OSCI Component Symbol Table 3.6. OSCI Component Port Definition Port Name HFOUTEN HFCLKOUT I/O I O LFCLKOUT O Description High frequency clock output enable High frequency clock output Low Frequency clock output Table 3.7. OSCI Component Attribute Definition Defparam Name HFCLKDIV Description Configure HF oscillator output divider Value Default 1, 2, 4, 8 1 (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 22 FPGA-DS-02013-1.2 CrossLink Automotive Family Data Sheet 3.6. Embedded Block RAM Overview CrossLink Automotive devices contain sysMEM Embedded Block RAM (EBR). The EBR consists of a 9 kB RAM with memory core, dedicated input registers and output registers with separate clock and clock enable. Support for different memory configurations: Single Port True Dual Port Pseudo Dual Port ROM FIFO (logic wrapper added automatically by design tools) Flexible customization features: Initialization of RAM/ROM Memory cascading (handled automatically by design tools) Optional parity bit support Byte-enable Multiple block size options RAM modes support optional Write Through or Read-Before-Write modes For details, refer to CrossLink Memory Usage Guide (FPGA-TN-02017). Table 3.8. sysMEM Block Configurations Memory Mode Single Port Memory Size Configurations 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 True Dual Port 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 Pseudo Dual Port 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 ROM 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 3.7. Power Management Unit The embedded Power Management Unit (PMU) allows low-power Sleep State of the device. Figure 3.15 shows the block diagram of the PMU IP. When instantiated in the design, PMU is always on, and uses the low-speed clock from oscillator of the device to perform its operations. The typical use case for the PMU is through a user implemented state machine that controls the sleep and wake up of the device. The state machine implemented in the FPGA fabric identifies when the device needs to go into sleep mode, issues the command through PMU's FPGA fabric interface, assigns the parameters for sleep (time to wake up and so on) and issues Sleep command. (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.2 23 CrossLink Automotive Family Data Sheet The device can be woken up externally using the PMU Wake-Up (USRWKUP) pin, or from the PMU Watch Dog Timer expiry or from I2C0 (address decoding detection or FIFO full in one of hardened I2C). Power Management Unit (PMU) PMU Clock (From Oscillator) (PMUCLK) External User Wake-up (USRWKUPN) PMU Wake-up from I2C0 (PMUWKUP) Watch Dog Timer PMU Control Register 8-bit Addressable Fabric Interface PMU Sleep Signal, SLEEP Power Control Unit Watch Dog Timer User Mode Signals From FPGA Fabric Figure 3.15. CrossLink Automotive MIPI D-PHY Block 3.7.1. PMU State Machine PMU can place the device in two mutually exclusive states - Normal State and Sleep State. Figure 3.16 shows the PMU State Machine triggers for transition from one state to the other. Normal state - All elements of the device are active to the extent required by the design. In this state, the device is at fully active and performing as required by the application. Note that the power consumption of the device is highest in this state. Sleep state - The device is power gated such that the device is not operational. The configuration of the device and the EBR contents are retained; thus in Sleep mode, the device does not lose configuration SRAM and EBR contents. When it transitions to Normal state, device operates with these contents preserved. The PMU is active along with the associated GPIOs. The power consumption of the device is lowest in this state. This helps reduce the overall power consumption for the device. User Logic Initiated Sleep Mode Normal Mode User I2C/ External Wake-up/ WDT Expiry Wake-up Figure 3.16. CrossLink Automotive PMU State Machine For more details, refer to Power Management and Calculation for CrossLink Devices (FPGA-TN-02018). (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 24 FPGA-DS-02013-1.2 CrossLink Automotive Family Data Sheet 3.8. User I2C IP CrossLink Automotive devices have two I2C IP cores that can be configured either as an I2C master or as an I2C slave. The I2C0 core has pre-assigned pins, and supports PMU wakeup over I2C. The pins for the I2C1 interface are not pre-assigned - user can use any General Purpose I/O pins. The I2C cores support the following functionality: Master and Slave operation 7-bit and 10-bit addressing Multi-master arbitration support Clock stretching Up to 1 MHz data transfer speed General call support Optionally delaying input or output data, or both Optional FIFO mode Transmit FIFO size is 10 bits x 16 bytes, receive FIFO size is 10 bits x 32 bytes For further information on the User I2C, refer to CrossLink I2C Hardened IP Usage Guide (FPGA-TN-02019). (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.2 25 CrossLink Automotive Family Data Sheet 3.9. Programming and Configuration CrossLink Automotive is a SRAM-based programmable logic device that includes an internal Non-Volatile Configuration Memory (NVCM), as well as flexible SPI and I2C configuration modes. CrossLink Automotive provides four modes for loading the configuration data into the SRAM memory. Self-Download (NVCM) mode - CrossLink Automotive retrieves bitstream from internal NVCM Master SPI mode - CrossLink Automotive retrieves bitstream from an external SPI Flash Slave SPI mode - System microprocessor writes bitstream to CrossLink Automotive through SPI port Slave I2C mode - System microprocessor writes bitstream to CrossLink Automotive through I2C port CrossLink Automotive provides a set of sysCONFIG I/O pins to program and configure the FPGA. The sysCONFIG pins are grouped together to create ports (I2C, SSPI or MSPI) that are used to interact with the FPGA for programming, configuration, and access of resources inside the FPGA. The sysCONFIG pins (Table 3.9) in a configuration group may be active and used for programming the FPGA or they can be reconfigured to act as general purpose I/Os. Table 3.9. CrossLink Automotive sysCONFIG Pins Pin Name Associated sysCONFIG Port CRESETB Self Download Mode/SSPI/MSPI/I2C CDONE Self Download Mode/SSPI/MSPI/I2C SPI_SCK/MCK/SDA SSPI/MSPI/I2C SPI_SS/CSN/SCL SSPI/MSPI/I2C MOSI SSPI/MSPI MISO SSPI/MSPI As external power ramps up, a Power On Reset (POR) circuit inside the FPGA becomes active. When POR conditions are met, the POR circuit releases an internal reset strobe, allowing the device to begin its initialization process. After CrossLink Automotive drives CDONE low, CrossLink Automotive enters the memory initialization phase where it clears all of the SRAM memory inside the FPGA. CrossLink Automotive remains in initialization state until the CRESETB pin is deasserted or after SSPI/SI2C activation code is received. After CRESETB goes from low to high, the Configuration Logic puts the device into master auto booting mode where it boots either from the internal NVRAM or an external SPI boot PROM. Holding the CRESETB low postpones the master auto booting event and allows the slave configuration ports (Slave SPI or Slave I2C) to detect a `Slave Active' condition where the SPI or I 2C Master sends an Activation Key code to CrossLink Automotive. An external SPI Master or I2C Master needs to write the Activation Key to the FPGA while CRESETB is held LOW and within 9.5 ms from Vcc min during power up to enter into one of the slave configuration modes. Sources should not drive output to CrossLink Automotive until configuration has been completed to ensure CrossLink Automotive is in a known state. In addition to the flexible configuration modes, the CrossLink Automotive configuration engine supports the following special features: TransFR (Transparent Field Reconfiguration) allowing users to update logic in field without interrupting system operation by freezing I/O states during configuration Dual-Boot Support for primary and golden bitstreams provides automatic recovery from configuration failures Security and One-Time Programmable (OTP) modes protect bitstream integrity and prevent readback 64-bit unique TraceID per device For more information, refer to CrossLink Programming and Configuration Usage Guide (FPGA-TN-02014). (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 26 FPGA-DS-02013-1.2 CrossLink Automotive Family Data Sheet 4. DC and Switching Characteristics 4.1. Absolute Maximum Ratings Table 4.1. Absolute Maximum Ratings1, 2, 3 Symbol VCC Parameter Min Max Unit Core Supply Voltage -0.5 1.32 V VCCGPLL PLL Supply Voltage -0.5 1.32 V Auxiliary Supply Voltage for Bank 1, 2 and NVCM - @ 2.5 V -0.5 2.75 V Auxiliary Supply Voltage for Bank 1, 2 and NVCM - @ 3.3 V -0.5 3.63 V VCCIO I/O Driver Supply Voltage for Banks 0, 1, 2 -0.5 3.63 V -- VCCA_DPHYx VCCPLL_DPHY Input or I/O Transient Voltage Applied -0.5 3.63 V MIPI D-PHY Supply Voltages -0.5 1.32 V -- Voltage Applied on MIPI D-PHY Pins -0.5 1.32 V TA Storage Temperature (Ambient) -65 150 C TJ Junction Temperature (TJ) -- +125 C VCCAUX Notes: Stress above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Compliance with the Lattice Thermal Management document is required. All voltages referenced to GND. 4.2. Recommended Operating Conditions Table 4.2. Recommended Operating Conditions1, 2 Symbol VCC Parameter Min Max Unit Core Supply Voltage 1.14 1.26 V VCCGPLL PLL Supply Voltage 1.14 1.26 V Auxiliary Supply Voltage for Bank 1, 2 and NVCM - @ 2.5 V 2.375 2.625 V VCCAUX3 Auxiliary Supply Voltage for Bank 1, 2 and NVCM - @ 3.3 V 3.135 3.465 V VCCIO0 I/O Driver Supply Voltage for Bank 0 1.71 3.465 V VCCIO1/2 I/O Driver Supply Voltage for Bank 1, 2 1.14 3.465 V -40 125 C TJAUTO Junction Temperature, Automotive Operation D-PHY External Power Supply VCCA_DPHYx Analog Supply Voltage for D-PHY 1.14 1.26 V VCCPLL_DPHYx PLL Supply voltage for D-PHY 1.14 1.26 V Notes: For correct operation, all supplies must be held in their valid operation range. Like power supplies, must be tied together if they are at the same supply voltage. Follow the noise filtering recommendations in CrossLink Hardware Checklist (FPGA-TN-02013). VCCAUX can operate at either 2.5 V +/- 5% or 3.3 V +/- 5%. (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.2 27 CrossLink Automotive Family Data Sheet 4.3. Power Supply Ramp Rates Table 4.3. Power Supply Ramp Rates* Symbol Parameter Min Max Unit tRAMP Power supply ramp rates for all power supplies 0.6 10 V/ms *Note: Assume monotonic ramp rates. 4.4. Power-On-Reset Voltage Levels Table 4.4. Power-On-Reset Voltage Levels1, 3, 4 Parameter Symbol VPORUP VPORDN Power-On-Reset ramp up trip point (Monitoring VCC, VCCIO0, and VCCAUX) Power-On-Reset ramp down trip point (Monitoring VCC, VCCIO0, and VCCAUX) Min Max Unit VCC 0.62 0.93 V VCCIO02 0.87 1.50 V VCCAUX 0.90 1.53 V -- 0.79 V 2 VCCIO0 -- 1.50 V VCCAUX -- 1.53 V VCC Notes: These POR ramp up trip points are only provided for guidance. Device operation is only characterized for power supply voltages specified under recommended operating conditions. Only VCCIO0 (Config Bank) has a Power-On-Reset ramp up trip point. All other VCCIOs do not have Power-On-Reset ramp up detection. VCCIO supplies should be powered-up before or together with the VCC and VCCAUX supplies. Configuration starts after VCC, VCCIO0 and VCCAUX reach VPORUP. For details, see tCONFIGURATION time in Table 4.21. 4.5. ESD Performance Refer to LIFMD Product Family Qualification Summary for complete qualification data, including ESD performance. (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 28 FPGA-DS-02013-1.2 CrossLink Automotive Family Data Sheet 4.6. DC Electrical Characteristics Over recommended operating conditions. Table 4.5. DC Electrical Characteristics Symbol 1, 4, 5 IIL, IIH IPU4 Parameter Input or I/O Leakage Internal Pull-Up Current Condition Min Typ Max Unit 0 VIN VCCIO -10 -- +10 A VCCIO = 1.8 V between 0 VIN 0.65 * VCCIO -3 -- -31 A VCCIO = 2.5 V between 0 VIN 0.65 * VCCIO -8 -- -72 A VCCIO = 3.3 V between 0 VIN 0.65 * VCCIO -11 -- -128 A C12 I/O Capacitance2 VCCIO = 3.3 V, 2.5 V, 1.8 V, 1.2 V, VCC = 1.2 V, VIO = 0 to VIH (MAX) -- 6 -- pF C22 Dedicated Input Capacitance2 VCCIO = 3.3 V, 2.5 V, 1.8 V, 1.2 V, VCC = 1.2 V, VIO = 0 to VIH (MAX) -- 6 -- pF C32 MIPI D-PHY High Speed IO Capacitance VCCIO = 2.5V,VCC = 1.2V, VCC*_DPHY = 1.2V , VIO = 0 to VIH (MAX) -- 5 -- pF VHYST3 Hysteresis for SingleEnded Inputs VCCIO = 3.3 V, 2.5 V, 1.8 V VCC = 1.2 V, VIO = 0 to VIH (MAX) -- 200 -- mV Notes: Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tristated. It is not measured with the output driver active. Bus maintenance circuits are disabled. TA = 25 oC, f = 1.0 MHz. Hysteresis is not available for VCCIO = 1.2 V. Weak pull-up setting. Programmable pull-up resistors on Bank 0 will see higher current. Refer to CrossLink sysI/O Usage Guide (FPGA-TN-02016) for details on programmable pull-up resistors. Input pins are clamped to VCCIO and GND by a diode. When input is higher than VCCIO, or lower than GND, the Input Leakage current will be higher than the IIL and IIH. (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.2 29 CrossLink Automotive Family Data Sheet 4.7. CrossLink Automotive Supply Current Over recommended operating conditions. Table 4.6. CrossLink Automotive Supply Current Symbol Parameter Typ Unit mA Normal Operation1 ICC Vcc Power Supply Current 7 ICCPLL PLL Power Supply Current 50 A ICCAUX Auxiliary Power Supply Current for Bank 1, 2 and NVCM Programming Supply Current 3 mA ICCIOx Bank x Power Supply Current (per Bank) 60 A ICCA_DPHYx VCCA_DPHYx Power Supply Current 8.5 mA ICCPLL_DPHYx VCCPLL_DPHYx Power Supply Current 1.5 mA Standby Current2 ICC_STDBY Vcc Power Supply Standby Current 4 mA ICCPLL_STDBY PLL Power Supply Standby Current 10 A ICCAUX_STDBY Auxiliary Power Supply Current for Bank 1, 2 and NVCM Programming Supply Standby Current 0.2 mA ICCIOx_STDBY Bank Power Supply Standby Current (per Bank) 6 A ICCA_DPHYx_STDBY VCCA_DPHYx Power Supply Standby Current 6 A ICCPLL_DPHYx_STDBY VCCPLL_DPHYx Power Supply Standby Current 4 A Sleep/Power Down Mode Current3 ICC_SLEEP Vcc Power Supply Sleep Current 0.2 mA ICCPLL_SLEEP PLL Power Supply Current 10 A ICCAUX_SLEEP Auxiliary Power Supply Current for Bank 1, 2 and NVCM Programming Supply Current 20 A ICCIOx_SLEEP Bank Power Supply Current (per Bank) 6 A ICCA_DPHY_SLEEP VCCA_DPHYx Power Supply Sleep Current 6 A ICCPLL_DPHY_SLEEP VCCPLL_DPHYx Power Supply Sleep Current 4 A Notes: Normal Operation 2:1 MIPI CSI-2 Image Sensor Aggregator Bridge design under the following conditions: a. TJ = 25 C, all power supplies at nominal voltages. b. Typical processed device in ctfBGA80 package. c. To determine power for all other applications and operating conditions, use Power Calculator in Lattice Diamond design software Standby Operation A typically processed device in ctfBGA80 package with blank pattern programmed, under the following conditions: a. All outputs are tri-stated, all inputs are held at either VCCIO, or GND. b. All clock inputs are at 0 MHz. c. TJ = 25 C, all power supplies at nominal voltages. d. No pull-ups on I/O. Sleep/Power Down Mode 2:1 MIPI CSI-2 Image Sensor Aggregator Bridge design under the following conditions: a. Design is put into Sleep/Power Down Mode with user logic powers down D-PHY, and enters into Sleep Mode in PMU. b. TJ = 25 C, all power supplies at nominal voltages. c. Typical processed device in ctfBGA80 package. To determine the CrossLink Automotive start-up peak current, use the Power Calculator tool in the Lattice Diamond design software. (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 30 FPGA-DS-02013-1.2 CrossLink Automotive Family Data Sheet 4.8. Power Management Unit (PMU) Timing Table 4.7. PMU Timing* Symbol Parameter tPMUWAKE Time for PMU to wake from Sleep mode Device Max Unit All Devices 0.5 ms *Note: For details on PMU usage, refer to Power Management and Calculation for CrossLink Devices (FPGA-TN-02018). 4.9. sysI/O Recommended Operating Conditions Table 4.8. sysI/O Recommended Operating Conditions1 VCCIO Standard Min Typ Max LVCMOS33/LVTTL33 3.135 3.30 3.465 LVCMOS25 2.375 2.50 2.625 LVCMOS18 1.710 1.80 1.890 LVCMOS12 (Output only)2 1.140 1.20 1.260 1.710 1.80 1.890 2.375 2.50 2.625 3.135 3.30 3.465 1.140 1.20 1.260 1.710 1.80 1.890 2.375 2.50 2.625 3.135 3.30 3.465 1.710 1.80 1.890 2.375 2.50 2.625 3.135 3.30 3.465 LVDS (Output only) 2.375 2.50 2.625 MIPI (Input only) 1.140 1.20 1.260 subLVDS (Input only) SLVS200 (Input only)3 LVDS (Input only) Note: For input voltage compatibility, refer to CrossLink sysI/O Usage Guide (FPGA-TN-02016). For VCCIO1 and VCCIO2 only. For SLVS200/MIPI interface I/O placement, see the Programmable I/O Banks section. 4.10. sysI/O Single-Ended DC Electrical Characteristics Table 4.9. sysI/O Single-Ended DC Electrical Characteristics Input/Output Standard VIL VIH Min (V) Max (V) Min (V) Max (V) LVCMOS33/ LVTTL33 -0.3 0.8 2.0 VCCIO+0.2 LVCMOS25 -0.3 0.7 1.7 VCCIO+0.2 LVCMOS18 -0.3 0.35 VCCIO 0.67 VCCIO VCCIO+0.2 LVCMOS12* (Output only) -- -- -- -- VOL Max (V) VOH Min 0.40 VCCIO - 0.4 8 -8 0.20 VCCIO - 0.2 0.1 -0.1 0.40 VCCIO - 0.4 6 -6 0.20 VCCIO - 0.2 0.1 -0.1 0.40 VCCIO - 0.4 4 -4 0.20 VCCIO - 0.2 0.1 -0.1 0.40 VCCIO - 0.4 2 -2 0.20 VCCIO - 0.2 0.1 -0.1 (V) IOL (mA) IOH (mA) *Note: For VCCIO1 and VCCIO2 only. (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.2 31 CrossLink Automotive Family Data Sheet 4.11. sysI/O Differential Electrical Characteristics 4.11.1. LVDS/subLVDS/SLVS200 Over recommended operating conditions. Table 4.10. LVDS/subLVDS1/SLVS2001, 2 Parameter Description Test Conditions Min Typ Max Unit VINP, VINN Input Voltage -- 0.00 -- 2.40 V VCM Input Common Mode Voltage Half the sum of the two inputs 0.05 -- 2.35 V VTHD(LVDS) Differential Input Threshold VINP - VINN 100 -- -- mV VTHD(subLVDS) Differential Input Threshold VINP - VINN 90 -- -- mV VTHD(SLVS200) Differential Input Threshold VINP - VINN 70 -- -- mV IIN Input Current Normal Mode -10 -- 10 A Standby Mode -10 -- 10 A VOH Output High Voltage for VOP or VOM RT = 100 -- 1.43 1.60 V VOL Output Low Voltage for VOP or VOM RT = 100 0.90 1.08 -- V VOD Output Voltage Differential |VOP - VOM|, RT = 100 250 350 450 mV -- -- 50 mV 1.125 1.250 1.375 V VOS Change in VOD between High and Low Output Voltage Offset (Common Mode Voltage) VOS Change in VOS between H and L -- -- -- 50 mV Output Short Circuit Current VOD = 0 V driver outputs shorted to each other -- -- 12 mA VOD ISAB -- (VOP + VOM)/2, RT = 100 Notes: 1. Inputs only for subLVDS and SLVS200. 2. For SLVS200/MIPI interface I/O placement, see the Programmable I/O Banks section. (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 32 FPGA-DS-02013-1.2 CrossLink Automotive Family Data Sheet 4.11.2. Hardened MIPI D-PHY I/Os Table 4.11. MIPI D-PHY Symbol Description Min Typ Max Unit 70 -- 330 mV Receiver High Speed VCMRX Common-Mode Voltage HS Receive Mode VIDTH Differential Input High Threshold -- -- 70 mV VIDTL Differential Input Low Threshold -70 -- -- mV VIHHS Single-ended input High Voltage -- -- 460 mV VILHS Single-ended Input Low Voltage -40 -- -- mV VTERM-EN Single-ended Threshold for HS Termination Enable -- -- 450 mV ZID Differential Input Impedance 80 100 125 VIH Logic 1 Input Voltage 880 -- -- mV VIL Logic 0 Input Voltage, not in ULP State -- -- 550 mV VIL-ULPS Logic 0 Input Voltage, in ULP State -- -- 300 mV VHYST Input Hysteresis 23.0 -- -- mV Low Power Transmitter High Speed VCMTX HS Transmit Static Common Mode Voltage 150 200 250 mV VOD HS Transmit Differential Voltage 140 200 270 mV VOHHS HS Single-ended Output High Voltage -- -- 360 mV ZOS Single-ended Output Impedance 40 50 62.5 ZOS Single-ended Output Impedance Mismatch -- -- 10 % VOH Output High Voltage 1.1 1.2 1.3 V VOL Output Low Voltage -50 -- 50 mV ZOLP Output Impedance in LP Mode 110 -- -- Low Power (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.2 33 CrossLink Automotive Family Data Sheet 4.12. CrossLink Automotive Maximum General Purpose I/O Buffer Speed Over recommended operating conditions. Table 4.12. CrossLink Automotive Maximum I/O Buffer Speed Buffer Description Max Unit LVDS, VCCIO = 2.5 V, VID = 200 mV 600 MHz subLVDS, VCCIO = 2.5 V, VID = 150 mV 600 MHz MIPI D-PHY 600 MHz 5 600 MHz MHz LVCMOS33/LVTTL33 MIPI D-PHY SLVS200, VCCIO=2.5 V LVCMOS/LVTTL, VCCIO = 3.3 V 300 MHz LVCMOS25D Differential LVCMOS, VCCIO = 2.5 V 300 MHz LVCMOS25 LVCMOS, VCCIO = 2.5 V 300 MHz LVCMOS18 LVCMOS, VCCIO = 1.8 V 155 MHz LVDS25 LVDS, VCCIO = 2.5 V 555 MHz LVCMOS33/LVTTL33 LVCMOS/LVTTL, VCCIO = 3.3 V 300 MHz LVTTL33D Differential LVTTL, VCCIO = 3.3 V 300 MHz LVCMOS33D Differential LVCMOS, 3.3 V 300 MHz LVCMOS25 LVCMOS, 2.5 V 215 MHz LVCMOS25D Differential LVCMOS, 2.5 V 215 MHz LVCMOS18 LVCMOS, 1.8 V 155 MHz LVCMOS12 LVCMOS, VCCIO1/2 = 1.2 V 70 MHz Maximum Input Frequency LVDS25 subLVDS MIPI D-PHY (HS Mode) 6 MIPI D-PHY (LP Mode) SLVS200 Maximum Output Frequency Notes: These maximum speeds are characterized but not tested on every device. Maximum I/O speed for differential output standards emulated with resistors depends on the layout. LVCMOS timing is measured with the load specified in Table 4.22. Actual system operation may vary depending on user logic implementation. Maximum data rate equals two times the clock rate when utilizing DDR. 6. This is the maximum MIPI D-PHY input rate on the programmable I/O banks 1 and 2. The hardened MIPI D-PHY input and output rates are described in Hardened MIPI D-PHY Performance section. For SLVS200/MIPI interface I/O placement, see the Programmable I/O Banks section. 7. To ensure the MIPI Rx interface is implemented optimally in the FPGA fabric with the Programmable I/Os, follow the guidelines of assigning I/Os to the bank for the MIPI Rx inputs: When an SLVS200/MIPI Rx interface is placed in Bank 1 or 2, do not place LVCMOS outputs on both Banks 1 and 2. (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 34 FPGA-DS-02013-1.2 CrossLink Automotive Family Data Sheet 4.13. CrossLink Automotive External Switching Characteristics Table 4.13. CrossLink Automotive External Switching Characteristics4, 5 Parameter Description Clocks Primary Clock fMAX_PRI tW_PRI Frequency for Primary Clock Tree Clock Pulse Width for Primary Clock tSKEW_PRI Edge Clock fMAX_EDGE tW_EDGE tSKEW_EDGE Conditions -6 Unit Min Max -- -- -- 0.8 150 -- MHz ns Primary Clock Skew Within a Clock -- -- 450 ps Frequency for Edge Clock Tree Clock Pulse Width for Edge Clock Edge Clock Skew Within a Bank -- -- -- -- 0.783 -- 600 -- 140 MHz ns ps Generic SDR Interface1 General Purpose I/O Pin Parameters Using Clock Tree Without PLL tCO Clock to Output - PIO Input Register -- -- 5.53 ns tSU Clock to Data Setup - PIO Input Register Clock to Data Hold - PIO Input -- -0.93 -- ns -- 1.83 -- ns tSU_DELAY Register Clock to Data Setup - PIO Input Register with Input Delay for zero tHD With data input delay for hold time = 0 1.28 -- ns tHD_DELAY Clock to Data Hold - PIO Input Register with Input Delay for zero tHD With data input delay for hold time = 0 -0.34 -- ns tHD General Purpose I/O Pin Parameters Using Clock Tree With PLL tCO Clock to Output - PIO Input Register -- -- 4.12 ns tSU Clock to Data Setup - PIO Input Register Clock to Data Hold - PIO Input -- 0.20 -- ns -- 0.42 -- ns tSU_DELAY Register Clock to Data Setup - PIO Input Register with Input Delay for zero tHD With data input delay for hold time = 0 1.67 -- ns tHD_DELAY Clock to Data Hold - PIO Input Register with Input Delay for zero tHD With data input delay for hold time = 0 -1.03 -- ns tHD Generic DDR Interfaces2 Generic DDRX8 or DDRX4 or DDRX2 I/O with Clock and Data Centered at General Purpose Pins (GDDRX8_RX/TX.ECLK.Centered or GDDRX4_RX/TX.ECLK.Centered or GDDRX2_RX/TX.ECLK.Centered) tSU_GDDRX2_4_8_CENTERED Input Data Set-Up Before CLK Rising and Falling edges -- 0.167 -- ns tHD_GDDRX2_4_8_CENTERED Input Data Hold After CLK Rising and Falling edges -- 0.167 -- ns tDVB_GDDRX2_4_8_CENTERED Output Data Valid Before CLK Output Rising and Falling edges tDVA_GDDRX2_4_8_CENTERED Output Data Valid After CLK Output Rising and Falling edges fMAX_GDDRX2_4_8_CENTERED Frequency for ECLK3 Data Rate = 1.2 Gb/s6 Other Data Rates6 Data Rate = 1.2 Gb/s6 Other Data Rates6 GDDRX2 GDDRX4 and GDDRX8 0.297 -0.120 0.297 -0.120 -- -- -- -- -- -- 300 600 ns ns+1/2UI ns ns+1/2UI MHz MHz (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.2 35 CrossLink Automotive Family Data Sheet Table 4.13. CrossLink Automotive External Switching Characteristics (Continued) Parameter Description -6 Conditions Min Max Generic DDRX1 I/O with Clock and Data Centered at General Purpose Pins (GDDRX1_RX/TX.SCLK.Centered) Input Data Set-Up Before CLK tSU_GDDRX1_CENTERED -- 0.917 -- Rising and Falling edges tHD_GDDRX1_CENTERED Input Data Hold After CLK Rising and Falling edges tDVB_GDDRX1_CENTERED Output Data Valid Before CLK Output Rising and Falling edges tDVA_GDDRX1_CENTERED fMAX_GDDRX1_CENTERED Output Data Valid After CLK Output Rising and Falling edges Frequency for PCLK3 Unit ns -- 0.917 -- ns Data Rate = 300 Mb/s 1.217 -- ns+1/2UI Other Data Rates -0.450 -- ns+1/2UI Data Rate = 300 Mb/s 1.217 -- ns+1/2UI Other Data Rates -0.450 -- ns+1/2UI -- -- 150 MHz Generic DDRX8 or DDRX4 or DDRX2 I/O with Clock and Data Aligned at General Purpose Pins (GDDRX8_RX/TX.ECLK.Aligned or GDDRX4_RX/TX.ECLK.Aligned or GDDRX2_RX/TX.ECLK.Aligned) Data Rate = -- 0.188 ns Input Data Valid After CLK Rising 1.2 Gb/s6 tSU_GDDRX2_4_8_ALIGNED and Falling edges Other Data Rates6 -- -0.229 ns+1/2UI Data Rate = 0.646 -- ns Input Data Hold After CLK Rising 1.2 Gb/s6 THD_GDDRX2_4_8_ALIGNED and Falling edges Other Data Rates6 0.229 -- ns+1/2UI Output Data Invalid After CLK tDIA_GDDRX2_4_8_ALIGNED -- -- 0.120 ns Rising and Falling edges Output tDIB_GDDRX2_4_8_ALIGNED Output Data Invalid Before CLK Output Rising and Falling edges fMAX_GDDRX2_4_8_ALIGNED Frequency for ECLK3 TSU_GDDRX1_ALIGNED Input Data Valid After CLK Rising and Falling edges -- -- 0.120 ns GDDRX2 -- 300 MHz GDDRX4 and GDDRX8 -- 600 Generic DDRX1 I/O with Clock and Data Aligned at General Purpose Pins (GDDRX1_RX/TX.SCLK.Aligned) MHz THD_GDDRX1_ALIGNED tDIA_GDDRX1_ALIGNED tDIB_GDDRX1_ALIGNED fMAX_GDDRX1_ALIGNED Input Data Hold After CLK Rising and Falling edges Output Data Invalid After CLK Rising and Falling edges Output Output Data Invalid Before CLK Output Rising and Falling edges Frequency for ECLK3 Data Rate = 300 Mb/s Other Data Rates -- 0.750 ns -- -0.917 ns+1/2UI Data Rate = 300 Mb/s 2.583 -- ns Other Data Rates 0.916 -- ns+1/2UI -- -- 0.450 ns -- -- 0.450 ns -- -- 150 MHz 0.200 -- UI 0.150 -- UI 0.150 -- UI General Purpose I/O MIPI D-PHY Rx with 1:8 or 1:16 Gearing tSU_GDDRX_MP Input Data Set-Up Before CLK 900 Mb/s < Data Rate 1.2 Gb/s and VID = 140 mV 600 Mb/s < Data Rate 900 Mb/s and VID = 140 mV Data Rate 600 Mb/s and VID = 70 mV (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 36 FPGA-DS-02013-1.2 CrossLink Automotive Family Data Sheet Table 4.13. CrossLink Automotive External Switching Characteristics (Continued) Parameter tHO_GDDRX_MP fMAX_GDDRX_MP Description Input Data Hold After CLK Frequency for ECLK3 Conditions 900 Mb/s < Data Rate 1.2 Gb/s and VID = 140 mV 600 Mb/s < Data Rate 900 Mb/s and VID = 140 mV Data Rate 600 Mb/s and VID = 70 mV -- Generic DDRX71 or DDRX141 Inputs (GDDRX71_RX.ECLK or GDDRX141_RX.ECLK) -- Input Valid Bit "i" switching from CLK Rising Edge tRPBi_DVA -- ("i" = 0 to 6, 0 aligns with CLK) -6 Unit Min Max 0.200 -- UI 0.150 -- UI 0.150 -- UI -- 600 MHz -- 0.3 -- -0.222 UI ns+ (i+ 1/2)*UI Input Hold Bit "i" switching from CLK Rising Edge ("i" = 0 to 6, 0 aligns with CLK) -- 0.7 -- tRPBi_DVE -- 0.222 -- fMAX_RX71_141 DDR71/DDR141 ECLK Frequency3 -- -- 450 MHz -- 0.143 ns+i*UI -0.143 -- ns+i*UI -- -- 0.15 UI -- -- 525 MHz Generic DDRX71 Outputs with Clock and Data Aligned at Pin (GDDRX71_TX.ECLK) Data Output Valid Bit "i" switching from CLK Rising Edge ("i" = 0 to 6, 0 aligns with tTPBi_DOV -- CLK) Data Output Invalid Bit "i" switching from tTPBi_DOI CLK Rising Edge ("i" = 0 to 6, 0 aligns with -- CLK) tTPBi_skew_UI fMAX_TX71 Tx skew in UI DDR71 ECLK Frequency 3 UI ns+ (i+ 1/2)*UI Generic DDRX141 Outputs with Clock and Data Aligned at Pin (GDDRX141_TX.ECLK) tTPBi_DOV Data Output Valid Bit "i" switching from CLK Rising Edge ("i" = 0 to 6, 0 aligns with CLK) All Devices -- 0.125 ns+i*UI tTPBi_DOI Data Output Invalid Bit "i" switching from CLK Rising Edge ("i" = 0 to 6, 0 aligns with CLK) All Devices -0.125 -- ns+i*UI tTPBi_skew_UI TX skew in UI All Devices -- 0.15 UI fMAX_TX141 DDR141 ECLK Frequency3 -- -- 600 MHz Notes: General I/O timing numbers based on LVCMOS 2.5, 0 pF load. Generic DDRX8, DDRX71 and DDRX141 timing numbers based on LVDS I/O. Maximum clock frequencies are tested under best case conditions. System performance may vary upon the user environment These numbers are generated using best case PLL located. All numbers are generated with the Lattice Diamond design software. Maximum data rate for GDDRX2 mode is 600 Mbps. (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.2 37 CrossLink Automotive Family Data Sheet Rx CLK (in) Rx DATA (in) tSU/tDVBDQ tSU/tDVBDQ tHD/tDVADQ tHD/tDVADQ Figure 4.1. Receiver RX.CLK.Centered Waveforms 1/2 UI 1/2 UI 1 UI Rx CLK (in) Rx DATA (in) tSU tSU tHD tHD Figure 4.2. Receiver RX.CLK.Aligned Input Waveforms 1/2 UI 1/2 UI 1/2 UI 1/2 UI Tx CLK (out) Tx DATA (out) tDVB tDVB tDVA tDVA Figure 4.3. Transmit TX.CLK.Centered Output Waveforms (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 38 FPGA-DS-02013-1.2 CrossLink Automotive Family Data Sheet 1 UI Tx CLK (out) Tx DATA (out) tDIB tDIB tDIA tDIA Figure 4.4. Transmit TX.CLK.Aligned Waveforms Figure 4.5. DDRX71, DDRX141 Video Timing Waveforms (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.2 39 CrossLink Automotive Family Data Sheet 4.14. sysCLOCK PLL Timing Over recommended operating conditions. Table 4.14. sysCLOCK PLL Timing Parameter Descriptions Conditions Min Max Unit fIN fPD Input Clock Frequency (CLKI, CLKFB) Phase Detector Input Clock Frequency -- -- 10 10 400 400 MHz MHz fOUT Output Clock Frequency (CLKOP, CLKOS) -- 4.6875 600 MHz fVCO PLL VCO Frequency -- 600 1200 MHz -- AC Characteristics tDT Output Clock Duty Cycle 45.0 55.5 % -- fOUT 100 MHz -5 -- 5 100 % ps p-p fOUT < 100 MHz fOUT 100 MHz -- -- 0.025 200 UIPP ps p-p fOUT < 100 MHz fPD > 100 MHz -- -- 0.05 200 UIPP ps p-p fPD < 100 MHz -- 0.05 UIPP Static Phase Offset PLL Lock-in Time Divider ratio = integer -- -- -- 400 15 ps p-p ms PLL Unlock Time -- -- 50 ns tIPJIT Input Clock Period Jitter fPD 20 MHz fPD < 20 MHz -- -- 500 0.02 ps p-p UIPP tHI tLO Input Clock High Time Input Clock Low Time 90% to 90% 10% to 10% 0.5 0.5 -- -- ns ns tPH Output Phase Accuracy Output Clock Period Jitter3 tOPJIT1 Output Clock Cycle-to-Cycle Jitter3 Output Clock Phase Jitter tSPO 2 tLOCK tUNLOCK Notes: Jitter sample is taken over 10,000 samples for Periodic jitter, and 2,000 samples for Cycle-to-Cycle jitter of the primary PLL output with clean reference clock with no additional I/O toggling. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment. Period jitter and cycle-to-cycle jitter numbers are guaranteed for fPD 10 MHz. For fPD < 10 MHz, the jitter numbers may not be met in certain conditions. (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 40 FPGA-DS-02013-1.2 CrossLink Automotive Family Data Sheet 4.15. Hardened MIPI D-PHY Performance Table 4.15. 1500 Mb/s MIPI_DPHY_X8_RX/TX Timing Table (1500 Mb/s > MIPI D-PHY Data Rate > 1200 Mb/s) Parameter Description Min Max Unit tSU_MIPIX8 Input Data Setup before CLK 0.200 -- UI tHO_MIPIX8 Input Data Hold after CLK 0.200 -- UI tDVB_MIPIX8 Output Data Valid before CLK Output 0.300 -- UI tDVA_MIPIX8 Output Data Valid after CLK Output 0.300 -- UI Table 4.16. 1200 Mb/s MIPI_DPHY_X4_RX/TX Timing Table (1200 Mb/s > MIPI D-PHY Data Rate > 1000 Mb/s) Parameter Description Min Max Unit tSU_MIPIX4 Input Data Setup before CLK 0.200 -- UI tHO_MIPIX4 Input Data Hold after CLK 0.200 -- UI tDVB_MIPIX4 Output Data Valid before CLK Output 0.300 -- UI tDVA_MIPIX4 Output Data Valid after CLK Output 0.300 -- UI Table 4.17. 1000 Mb/s MIPI_DPHY_X4_RX/TX Timing Table (1000 Mb/s > MIPI D-PHY Data Rate > 10 Mb/s) Parameter Description Min Max Unit tSU_MIPIX4 Input Data Setup before CLK 0.150 -- UI tHO_MIPIX4 Input Data Hold after CLK 0.150 -- UI tDVB_MIPIX4 Output Data Valid before CLK Output 0.350 -- UI tDVA_MIPIX4 Output Data Valid after CLK Output 0.350 -- UI 4.16. Internal Oscillators (HFOSC, LFOSC) Table 4.18. Internal Oscillators Parameter Parameter Description Min Typ Max Unit fCLKHF HFOSC CLKK Clock Frequency 43.2 48 52.8 MHz fCLKLF LFOSC CLKK Clock Frequency 9 10 11 kHz DCHCLKHF HFOSC Duty Cycle (Clock High Period) 45 50 55 % DCHCLKLF LFOSC Duty Cycle (Clock High Period) 45 50 55 % 4.17. User I2C1 Table 4.19. User I2C1 Symbol Parameter fscl SCL Clock Frequency Optional delay through delay block TDELAY STD Mode FAST Mode Plus2 FAST Mode Units Min Typ Max Min Typ Max Min Typ Max -- -- 100 -- -- 400 -- -- 10002 kHz -- 62 -- -- 62 -- -- 62 -- ns Notes: Refer to the I2C Specification for timing requirements. Fast Mode Plus maximum speed may be achieved by using external pull up resistor on I2C bus. Internal pull up may not be sufficient to support the maximum speed. (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.2 41 CrossLink Automotive Family Data Sheet 4.18. CrossLink Automotive sysCONFIG Port Timing Specifications Over recommended operating conditions. Table 4.20. CrossLink Automotive sysCONFIG Port Timing Specifications Symbol Parameter Min Max Minimum CRESETB LOW pulse width required to restart configuration (from falling edge to rising edge) 145 -- Unit All Configuration Mode tPRGM ns Slave SPI1 fCCLK SPI_SCK Input Clock Frequency -- 110 MHz tSTSU MOSI Setup Time 0.5 -- ns tSTH MOSI Hold Time 2.0 -- ns tSTCO SPI_SCK Falling Edge to Valid MISO Output -- 13.3 ns tSCS Chip Select HIGH Time 25 -- ns tSCSS Chip Select Setup Time 0.5 -- ns tSCSH Chip Select Hold Time 0.5 -- ns MCK Output Clock Frequency -- 52.8 MHz Maximum SCL Clock Frequency (Fast-Mode Plus) -- 1 MHz Master SPI fCCLK I2C2 fMAX Notes: 1. Refer to CrossLink Programming and Configuration Usage Guide (FPGA-TN-02014), for timing requirements to enable CrossLink Automotive SSPI Mode. 2. Refer to the I2C specification for timing requirements when configuring with I2C port. 4.19. SRAM Configuration Time from NVCM Over recommended operating conditions. Table 4.21. SRAM Configuration Time from NVCM Symbol Parameter Typ Unit TCONFIGURATION POR/CRESET_B to Device I/O Active* 83 ms *Note: Before and during configuration, the I/Os are held in tristate with weak internal pullups enabled. I/Os are released to user functionality when the device has finished configuration. (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 42 FPGA-DS-02013-1.2 CrossLink Automotive Family Data Sheet 4.20. Switching Test Conditions Figure 4.6 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are listed in Table 4.22. VT R1 Test Point DUT R2 CL* *CL Includes Test Fixture and Probe Capacitance Figure 4.6. Output Test Load, LVTTL and LVCMOS Standards Table 4.22. Test Fixture Required Components, Non-Terminated Interfaces Test Condition LVTTL and other LVCMOS settings (L H, H L) R1 R2 CL 0 pF Timing Ref. VT LVCMOS 3.3 = 1.5 V -- LVCMOS 2.5 = VCCIO/2 -- LVCMOS 1.8 = VCCIO/2 -- LVCMOS 1.2 = VCCIO/2 -- LVCMOS 2.5 I/O (Z H) 1 M 0 pF VCCIO/2 -- LVCMOS 2.5 I/O (Z L) 1 M 0 pF VCCIO/2 VCCIO LVCMOS 2.5 I/O (H Z) 100 0 pF VOH - 0.10 -- LVCMOS 2.5 I/O (L Z) 100 0 pF VOL + 0.10 VCCIO Note: Output test conditions for all other interfaces are determined by the respective standards. (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.2 43 CrossLink Automotive Family Data Sheet 5. Pinout Information The pinout tables below correspond to CrossLink LIF-MD6000 Pinout Version 1.4. GND pins are referenced as VSS in Lattice Diamond Software. 5.1. ctfBGA80/cktBGA80 Pinout Pin Number Pin Function Bank Dual Function Differential A1 A2 A3 DPHY1_DN2 DPHY1_DN0 DPHY1_CKN DPHY1 DPHY1 DPHY1 -- -- -- Comp_OF_DPHY1_DP2 Comp_OF_DPHY1_DP0 Comp_OF_DPHY1_CKP A4 A5 A6 DPHY1_DN1 DPHY1_DN3 DPHY0_DN2 DPHY1 DPHY1 DPHY0 -- -- -- Comp_OF_DPHY1_DP1 Comp_OF_DPHY1_DP3 Comp_OF_DPHY0_DP2 A7 A8 DPHY0_DN0 DPHY0_CKN DPHY0 DPHY0 -- -- Comp_OF_DPHY0_DP0 Comp_OF_DPHY0_CKP A9 A10 B1 DPHY0_DN1 DPHY0_DN3 DPHY1_DP2 DPHY0 DPHY0 DPHY1 -- -- -- Comp_OF_DPHY0_DP1 Comp_OF_DPHY0_DP3 True_OF_DPHY1_DN2 B2 B3 DPHY1_DP0 DPHY1_CKP DPHY1 DPHY1 -- -- True_OF_DPHY1_DN0 True_OF_DPHY1_CKN B4 B5 B6 DPHY1_DP1 DPHY1_DP3 DPHY0_DP2 DPHY1 DPHY1 DPHY0 -- -- -- True_OF_DPHY1_DN1 True_OF_DPHY1_DN3 True_OF_DPHY0_DN2 B7 B8 B9 DPHY0_DP0 DPHY0_CKP DPHY0_DP1 DPHY0 DPHY0 DPHY0 -- -- -- True_OF_DPHY0_DN0 True_OF_DPHY0_CKN True_OF_DPHY0_DN1 B10 C1 DPHY0_DP3 GND DPHY0 GND -- -- True_OF_DPHY0_DN3 -- C2 C9 C10 GNDA_DPHY1 GNDA_DPHY0 GND DPHY1 DPHY0 GND -- -- -- -- -- -- D1 D2 PB48 VCCPLL_DPHY1 0 DPHY1 PCLKT0_1/USER_SCL -- -- -- D4 D5 D6 VCCA_DPHY1 VCCAUX GNDPLL_DPHYx DPHY1 VCCAUX GND -- -- -- -- -- -- D7 D9 D10 VCCPLL_DPHY0 PB16A PB16B DPHY0 2 2 -- PCLKT2_0 PCLKC2_0 -- True_OF_PB16B Comp_OF_PB16A E1 E2 PB34A PB34B 1 1 GR_PCLK1_0 -- True_OF_PB34B Comp_OF_PB34A E4 E5 E6 VCC GND VCC VCC GND VCC -- -- -- -- -- -- E7 E9 VCCA_DPHY0 PB12A DPHY0 2 -- GPLLT2_0 -- True_OF_PB12B E10 F1 F2 PB12B PB38A PB38B 2 1 1 GPLLC2_0 -- -- Comp_OF_PB12A True_OF_PB38B Comp_OF_PB38A (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 44 FPGA-DS-02013-1.2 CrossLink Automotive Family Data Sheet Pin Number Pin Function Bank Dual Function Differential F4 F5 F6 VCCIO0 VCCIO1 VCCIO2 0 1 2 -- -- -- -- -- -- F7 F9 F10 VCCIO2 PB6A PB6B 2 2 2 -- GR_PCLK2_0 -- -- True_OF_PB6B Comp_OF_PB6A G1 G2 PB50 GND 0 GND MOSI -- -- -- G4 G5 G6 VCCIO1 GND VCCGPLL 1 GND VCCGPLL -- -- -- -- -- -- G7 G9 GNDGPLL PB2A GND 2 -- -- -- True_OF_PB2B G10 H1 H2 PB2B PB52 CRESET_B 2 0 0 -- SPI_SS/CSN/SCL -- Comp_OF_PB2A -- -- H9 H10 PB2D PB2C 2 2 MIPI_CLKC2_0 MIPI_CLKT2_0 Comp_OF_PB2C True_OF_PB2D J1 J2 J3 PB53 PB49 PB43D 0 0 1 SPI_SCK/MCK/SDA PMU_WKUPN/CDONE -- -- -- Comp_OF_PB43C J4 J5 J6 PB38D PB34D PB29D 1 1 1 -- MIPI_CLKC1_0 PCLKC1_1 Comp_OF_PB38C Comp_OF_PB34C Comp_OF_PB29C J7 J8 PB29A PB16D 1 2 PCLKT1_0 PCLKC2_1 True_OF_PB29B Comp_OF_PB16C J9 J10 K1 PB6D PB6C PB51 2 2 0 -- -- MISO Comp_OF_PB6C True_OF_PB6D -- K2 K3 PB47 PB43C 0 1 PCLKT0_0/USER_SDA -- -- True_OF_PB43D K4 K5 K6 PB38C PB34C PB29C 1 1 1 -- MIPI_CLKT1_0 PCLKT1_1 True_OF_PB38D True_OF_PB34D True_OF_PB29D K7 K8 K9 PB29B PB16C PB12D 1 2 2 PCLKC1_0 PCLKT2_1 -- Comp_OF_PB29A True_OF_PB16D Comp_OF_PB12C K10 PB12C 2 -- True_OF_PB12D (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.2 45 CrossLink Automotive Family Data Sheet 5.2. Dual Function Pin Descriptions The following table describes the dual functions available to certain pins on the CrossLink Automotive device. These pins may alternatively be used as general purpose I/O when the described dual function is not enabled. Signal Name I/O Description General Purpose USER_SCL I/O User Slave I2C0 clock input and Master I2C0 clock output. Enables PMU wake-up via I2C0. USER_SDA I/O User Slave I2C0 data input and Master I2C0 data output. Enables PMU wakeup via I2C0. PMU_WKUPN -- This pin wakes the PMU from sleep mode when toggled low. Clock Functions GPLL2_0[T, C]_IN I GR_PCLK[Bank]0 I PCLK[T/C][Bank]_[num] I/O MIPI_CLK[T/C][Bank]_0 I/O General Purpose PLL (GPLL) input pads: T = true and C = complement. These pins can be used to input a reference clock directly to the General Purpose PLL. These pins do not provide direct access to the primary clock network. These pins provide a short General Routing path to the primary clock network. Refer to CrossLink sysCLOCK PLL/DLL Design and Usage Guide (FPGA-TN-02015) for details. General Purpose Primary CLK pads: [T/C] = True/Complement, [Bank] = (0, 1 and 2). These pins provide direct access to the primary and edge clock networks. MIPI D-PHY Reference CLK pads: [T/C] = True/Complement, [Bank] = (0, 1 and 2). These pins can be used to input a reference clock directly to the D-PHY PLLs. These pins do not provide direct access to the primary clock network. Configuration CDONE I/O SPI_SCK I MCK O SPI_SS I CSN O MOSI I/O MISO I/O SCL SDA I/O I/O Open Drain pin. Indicates that the configuration sequence is complete, and the startup sequence is in progress. Holding CDONE delays configuration. Input Configuration Clock for configuring CrossLink Automotive in Slave SPI mode (SSPI). Output Configuration Clock for configuring CrossLink Automotive in Master SPI mode (MSPI). Input Chip Select for configuring CrossLink Automotive in Slave SPI mode (SSPI). Output Chip Select for configuring CrossLink Automotive in Master SPI mode (MSPI). Data Output when configuring CrossLink Automotive in Master SPI mode (MSPI), data input when configuring CrossLink Automotive in Slave SPI mode (SSPI). Data Input when configuring CrossLink Automotive in Master SPI mode (MSPI), data output when configuring CrossLink Automotive in Slave SPI mode (SSPI). Slave I2C clock I/O when configuring CrossLink Automotive in I2C mode. Slave I2C data I/O when configuring CrossLink Automotive in I2C mode. (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 46 FPGA-DS-02013-1.2 CrossLink Automotive Family Data Sheet 5.3. Dedicated Function Pin Descriptions Signal Name Configuration I/O CRESET_B MIPI D-PHY DPHY[num]_CK[P/N] I I/O DPHY[num]_D[P/N][lane] I/O Description Configuration Reset, active LOW. MIPI D-PHY Clock [num] = D-PHY 0 or 1, P = Positive, N = Negative. MIPI D-PHY Data [num] = D-PHY 0 or 1, P = Positive, N = Negative, Lane = data lane in the D-PHY block 0, 1, 2 or 3. 5.4. Pin Information Summary Pin Type CrossLink Automotive ctfBGA80 ckfBGA80 Total General Purpose I/O 37 37 VCC/VCCIOx/VCCAUX/VCCGPLL 9 9 GND 6 6 D-PHY Clock/Data 20 20 D-PHY VCC 4 4 D-PHY GND 3 3 CRESETB 1 1 Total Balls 80 80 General Purpose I/O per Bank Bank 0 7 7 Bank 1 14 14 Bank 2 16 16 Total General Purpose Single Ended I/O 37 37 Bank 0 0 0 Bank 1 7 7 Bank 2 8 8 Total General Purpose Differential I/O pairs 15 15 Differential I/O pairs per Bank (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.2 47 CrossLink Automotive Family Data Sheet 6. CrossLink Automotive Part Number Description LIA-MD XXXX-X XXXXX X Device Family CrossLink Automotive FPGA Grade E = Automotive Logic Capacity 6000 = 6000 LUTs Package JMG80 = 80-ball ctfBGA KMG80 = 80-ball ckfBGA Speed 6 = Fastest 6.1. Ordering Part Numbers Automotive Part Number Speed Package Pins Temp. Grade LUTs (K) LIA-MD6000-6JMG80E -6 Lead free ctfBGA 80 Automotive 5.9 LIA-MD6000-6KMG80E -6 Lead free ckfBGA 80 Automotive 5.9 (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 48 FPGA-DS-02013-1.2 CrossLink Automotive Family Data Sheet References For more information, refer to the following technical notes: CrossLink High-Speed I/O Interface (FPGA-TN-02012) CrossLink Hardware Checklist (FPGA-TN-02013) CrossLink Programming and Configuration Usage Guide (FPGA-TN-02014) CrossLink sysCLOCK PLL/DLL Design and Usage Guide (FPGA-TN-02015) CrossLink sysI/O Usage Guide (FPGA-TN-02016) CrossLink Memory Usage Guide (FPGA-TN-02017) Power Management and Calculation for CrossLink Devices (FPGA-TN-02018) CrossLink I2C Hardened IP Usage Guide (FPGA-TN-02019) Advanced CrossLink I2C Hardened IP Reference Guide (FPGA-TN-02020) For package information, refer to the following technical notes: PCB Layout Recommendations for BGA Packages (TN1074) Solder Reflow Guide for Surface Mount Devices (FPGA-TN-12041, previously TN1076) Wafer-Level Chip-Scale Package Guide (TN1242) Thermal Management Package Diagrams For further information on interface standards refer to the following websites: JEDEC Standards (LVTTL, LVCMOS): www.jedec.org MIPI Standards (D-PHY): www.mipi.org Technical Support For assistance, submit a technical support case at www.latticesemi.com/techsupport. (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.2 49 CrossLink Automotive Family Data Sheet Revision History Date Version March 2018 1.2 Change Summary December 2017 1.1 Added entries to the Acronyms in This Document section. In Features section: Changed footprint to 80-ball ctfBGA (42 mm2) Updated Applications examples Removed Application Examples section and its associated references throughout the document Updated packages in Table 2.1. Updated the Architecture Overview section (general update) Revised introductory paragraph. Reordered the list of features supported by the hard D-PHY quads Added Figure 3.3 to Figure 3.6 to the MIPI D-PHY Blocks section Updated the Programmable I/O Banks section Added Bank 0 list of features Added Table 3.1, Table 3.2, Table 3.3 and Table 3.4 Updated Programmable FPGA Fabric section Removed FPGA Fabric Overview header Added PFU Blocks section Added Slice section Moved Clocking Overview as a new Clocking Structure (heading 2) section and added contents Moved Embedded Block RAM Overview as a new (heading 2) section and added contents Removed System Resources section Moved Power Management Unit section under Embedded Block RAM Overview Removed Device Configuration section Moved User I2C IP as a new (heading 2) section Added Programming and Configuration section Revised footnotes in Table 4.6 Corrected alignment of arrows in Figure 4.4 Revised Min and Max values in Table 4.15, Table 4.16, and Table 4.17 Revised footnote in Table 4.20 Added web link in Pinout Information section Placed captions to pinout table Changed document status from preliminary to final Added items to Acronyms in This Document Updated the Features section Added 80-ball ckfBGA (49 mm2) under Small footprint Removed LVDS under Programmable CMOS I/O Updated note in Table 2.1, Table 2.2, Table 2.3, Table 2.4, Table 2.5, Table 2.6, Table 2.7, Table 2.8, and Table 2.9 Moved Product Feature Summary from section to 2 to section 3. Added 80 ckfBGA (7.0 x 7.0 mm2, 1 mm) in Table 3.1. CrossLink Automotive Feature Summary Updated System Resources section Removed LVCMOS12 (Outputs Only) from CMOS GPIO (Bank 0) section Added information in Device Configuration section Updated Table 5.1. Absolute Maximum Ratings1, 2, 3 Changed symbol from VCCPLL to VCCGPLL (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 50 FPGA-DS-02013-1.2 CrossLink Automotive Family Data Sheet Date Version Change Summary September 2016 1.0 Removed VCC_DPHY, VCCA_DPHY, and VCCMU_DPHY symbol; added VCCA_DPHYx Updated Table 5.2. Recommended Operating Conditions1, 2 Revised symbols to VCCGPLL, VCCAUX, and VCCIO0 Added parameter to VCCAUX Added row of VCCIO1/2 symbol Removed row of VCC_DPHYx and VCCMU_DPHY1 symbol Revised note Updated Power-On-Reset Voltage Levels section. Added VPORDN to Table 5.4. Power-OnReset Voltage Levels1, 3, 4 and revised footnotes Updated LIFMD Product Family Qualification Summary link in ESD Performance section Removed VCCIO = 1.2 V between 0 VIN 0.65 * VCCIO condition from Table 5.5. DC Electrical Characteristics Updated Table 5.6. CrossLink Automotive Supply Current (general update) Removed Preliminary MIPI D-PHY Supply Current section. Added notes to Table 5.8. sysI/O Recommended Operating Conditions1 Added note to Table 5.9. sysI/O Single-Ended DC Electrical Characteristics Added notes to Table 5.10. LVDS/subLVDS1/SLVS2001, 2 Updated Table 5.12. CrossLink Automotive Maximum I/O Buffer Speed (general update) Updated Table 5.13. CrossLink Automotive External Switching Characteristics4, 5 (general update) Updated Figure 5.4. Transmit TX.CLK.Aligned Waveforms Updated Table 5.20. CrossLink Automotive sysCONFIG Port Timing Specifications (general update) Changed TREFRESH to TCONFIGURATION in Table 5.21. SRAM Configuration Time from NVCM Updated Pinout Information section Updated section introduction Updated section to ctfBGA80/cktBGA80 Pinout Updated Pin Information Summary section (general update) Added KMG80 package to CrossLink Automotive Part Number Description section Modified heading and added LIA-MD6000-6KMG80E part number to Ordering Part Numbers section Updated reference to the Solder Reflow Guide for Surface Mount Devices document in References section First preliminary release. (c) 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.2 51 7th Floor, 111 SW 5th Avenue Portland, OR 97204, USA T 503.268.8000 www.latticesemi.com