LIA-MD6000-6KMG80E - LATTICE SEMICONDUCTOR

CrossLink Automotive Family

Data Sheet

FPGA-DS-02013 Version 1.2

March 2018

CrossLink Automotive Family

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

2 FPGA-DS-02013-1.2

Contents

Acronyms in This Document ................................................................................................................................................. 5

1. General Description ...................................................................................................................................................... 6

1.1. Features ............................................................................................................................................................... 6

2. Product Feature Summary ............................................................................................................................................ 7

3. Architecture Overview .................................................................................................................................................. 8

3.1. MIPI D-PHY Blocks ............................................................................................................................................... 9

3.2. Programmable I/O Banks .................................................................................................................................. 13

3.3. sysI/O Buffers .................................................................................................................................................... 15

3.3.1. Programmable PULLMODE Settings ............................................................................................................. 15

3.3.2. Output Drive Strength ................................................................................................................................... 15

3.3.3. On-Chip Termination .................................................................................................................................... 15

3.4. Programmable FPGA Fabric .............................................................................................................................. 16

3.4.1. PFU Blocks ..................................................................................................................................................... 16

3.4.2. Slice ............................................................................................................................................................... 17

3.5. Clocking Structure ............................................................................................................................................. 20

3.5.1. sysCLK PLL ..................................................................................................................................................... 20

3.5.2. Primary Clocks ............................................................................................................................................... 21

3.5.3. Edge Clocks ................................................................................................................................................... 21

3.5.4. Dynamic Clock Enables ................................................................................................................................. 22

3.5.5. Internal Oscillator (OSCI) ............................................................................................................................... 22

3.6. Embedded Block RAM Overview ....................................................................................................................... 23

3.7. Power Management Unit .................................................................................................................................. 23

3.7.1. PMU State Machine ...................................................................................................................................... 24

3.8. User I2C IP .......................................................................................................................................................... 25

3.9. Programming and Configuration ....................................................................................................................... 26

4. DC and Switching Characteristics ................................................................................................................................ 27

4.1. Absolute Maximum Ratings .............................................................................................................................. 27

4.2. Recommended Operating Conditions ............................................................................................................... 27

4.3. Power Supply Ramp Rates ................................................................................................................................. 28

4.4. Power-On-Reset Voltage Levels ........................................................................................................................ 28

4.5. ESD Performance ............................................................................................................................................... 28

4.6. DC Electrical Characteristics .............................................................................................................................. 29

4.7. CrossLink Automotive Supply Current............................................................................................................... 30

4.8. Power Management Unit (PMU) Timing ........................................................................................................... 31

4.9. sysI/O Recommended Operating Conditions .................................................................................................... 31

4.10. sysI/O Single-Ended DC Electrical Characteristics ............................................................................................. 31

4.11. sysI/O Differential Electrical Characteristics ..................................................................................................... 32

4.11.1. LVDS/subLVDS/SLVS200 ........................................................................................................................... 32

4.11.2. Hardened MIPI D-PHY I/Os ....................................................................................................................... 33

4.12. CrossLink Automotive Maximum General Purpose I/O Buffer Speed ............................................................... 34

4.13. CrossLink Automotive External Switching Characteristics ................................................................................ 35

4.14. sysCLOCK PLL Timing ......................................................................................................................................... 40

4.15. Hardened MIPI D-PHY Performance.................................................................................................................. 41

4.16. Internal Oscillators (HFOSC, LFOSC) .................................................................................................................. 41

4.17. User I2C1............................................................................................................................................................. 41

4.18. CrossLink Automotive sysCONFIG Port Timing Specifications .......................................................................... 42

4.19. SRAM Configuration Time from NVCM ............................................................................................................. 42

4.20. Switching Test Conditions ................................................................................................................................. 43

5. Pinout Information ..................................................................................................................................................... 44

5.1. ctfBGA80/cktBGA80 Pinout ............................................................................................................................... 44

5.2. Dual Function Pin Descriptions ......................................................................................................................... 46

5.3. Dedicated Function Pin Descriptions ................................................................................................................ 47

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FPGA-DS-02013-1.2 3

5.4. Pin Information Summary ................................................................................................................................. 47

6. CrossLink Automotive Part Number Description ........................................................................................................ 48

6.1. Ordering Part Numbers ..................................................................................................................................... 48

References .......................................................................................................................................................................... 49

Technical Support ............................................................................................................................................................... 49

Revision History .................................................................................................................................................................. 50

Figures

Figure 3.1. CrossLink Automotive Device Block Diagram ..................................................................................................... 8

Figure 3.2. CrossLink Automotive sysI/O Banking ................................................................................................................ 9

Figure 3.3. MIPI DSI Transmit Interface with Hard D-PHY Module ..................................................................................... 10

Figure 3.4. MIPI CSI-2 Transmit Interface with Hard D-PHY Module .................................................................................. 11

Figure 3.5. MIPI DSI Receive Interface with Hard D-PHY Module ...................................................................................... 12

Figure 3.6. MIPI CSI-2 Receive Interface with Hard D-PHY Module .................................................................................... 13

Figure 3.7. CrossLink Automotive Device Simplified Block Diagram (Top Level) ................................................................ 16

Figure 3.8. CrossLink Automotive PFU Diagram ................................................................................................................. 17

Figure 3.9. Slice Diagram .................................................................................................................................................... 18

Figure 3.10. Connectivity Supporting LUT5, LUT6, LUT7 and LUT8 .................................................................................... 19

Figure 3.11. CrossLink Automotive PLL Block Diagram ....................................................................................................... 20

Figure 3.12. CrossLink Automotive Clocking Structure ....................................................................................................... 21

Figure 3.13. CrossLink Automotive Edge Clock Sources per Bank ...................................................................................... 22

Figure 3.14. CrossLink Automotive OSCI Component Symbol ............................................................................................ 22

Figure 3.15. CrossLink Automotive MIPI D-PHY Block ........................................................................................................ 24

Figure 3.16. CrossLink Automotive PMU State Machine .................................................................................................... 24

Figure 4.1. Receiver RX.CLK.Centered Waveforms ............................................................................................................. 38

Figure 4.2. Receiver RX.CLK.Aligned Input Waveforms ...................................................................................................... 38

Figure 4.3. Transmit TX.CLK.Centered Output Waveforms ................................................................................................ 38

Figure 5.5. DDRX71, DDRX141 Video Timing Waveforms .................................................................................................. 39

Figure 4.6. Output Test Load, LVTTL and LVCMOS Standards ............................................................................................ 43

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4 FPGA-DS-02013-1.2

Tables

Table 2.1. CrossLink Automotive Feature Summary ............................................................................................................. 7

Table 3.1. CrossLink Automotive Output Support per Bank Basis ...................................................................................... 14

Table 3.2. CrossLink Automotive Input Support per Bank Basis ......................................................................................... 15

Table 3.3. Drive Strength Values ......................................................................................................................................... 15

Table 3.4. Slice Signal Descriptions ..................................................................................................................................... 19

Table 3.5. CrossLink Automotive PLL Port Definition ......................................................................................................... 20

Table 3.6. OSCI Component Port Definition ....................................................................................................................... 22

Table 3.7. OSCI Component Attribute Definition ............................................................................................................... 22

Table 3.8. sysMEM Block Configurations ............................................................................................................................ 23

Table 3.9. CrossLink Automotive sysCONFIG Pins .............................................................................................................. 26

Table 4.1. Absolute Maximum Ratings1, 2, 3 ......................................................................................................................... 27

Table 4.2. Recommended Operating Conditions1, 2 ............................................................................................................ 27

Table 4.3. Power Supply Ramp Rates1 ................................................................................................................................ 28

Table 4.4. Power-On-Reset Voltage Levels1, 3, 4 ................................................................................................................... 28

Table 4.5. DC Electrical Characteristics ............................................................................................................................... 29

Table 4.6. CrossLink Automotive Supply Current ............................................................................................................... 30

Table 4.7. PMU Timing* ...................................................................................................................................................... 31

Table 4.8. sysI/O Recommended Operating Conditions1 .................................................................................................... 31

Table 5.9. sysI/O Single-Ended DC Electrical Characteristics .............................................................................................. 31

Table 4.10. LVDS/subLVDS1/SLVS2001, 2 .............................................................................................................................. 32

Table 4.11. MIPI D-PHY ....................................................................................................................................................... 33

Table 4.12. CrossLink Automotive Maximum I/O Buffer Speed ......................................................................................... 34

Table 4.13. CrossLink Automotive External Switching Characteristics4, 5 ........................................................................... 35

Table 4.14. sysCLOCK PLL Timing ........................................................................................................................................ 40

Table 4.15. 1500 Mb/s MIPI_DPHY_X8_RX/TX Timing Table (1500 Mb/s > MIPI D-PHY Data Rate > 1200 Mb/s) ............ 41

Table 4.16. 1200 Mb/s MIPI_DPHY_X4_RX/TX Timing Table (1200 Mb/s > MIPI D-PHY Data Rate > 1000 Mb/s) ............ 41

Table 5.17. 1000 Mb/s MIPI_DPHY_X4_RX/TX Timing Table (1000 Mb/s > MIPI D-PHY Data Rate > 10 Mb/s) ................ 41

Table 5.18. Internal Oscillators ........................................................................................................................................... 41

Table 5.19. User I2C1 ........................................................................................................................................................... 41

Table 5.20. CrossLink Automotive sysCONFIG Port Timing Specifications ......................................................................... 42

Table 5.21. SRAM Configuration Time from NVCM ............................................................................................................ 42

Table 4.22. Test Fixture Required Components, Non-Terminated Interfaces .................................................................... 43

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FPGA-DS-02013-1.2 5

Acronyms in This Document

A list of acronyms used in this document.

Acronym

Definition

Augmented Reality

ASIC

Application-Specific Integrated Circuit

BGA

Ball Grid Array

CMOS

Complementary Metal Oxide Semiconductor

CSI

Camera Serial Interface

DBI

Display Bus Interface

DPI

Display Pixel Interface

DSI

Display Serial Interface

EBR

Embedded Block RAM

ECLK

Edge Clock

FPD

Flat Panel Display

FPGA

Field-Programmable Gate Array

GPIO

General-Purpose Input/Output

HFOSC

High Frequency Oscillator

HMI

Human Machine Interface

I2C

Inter-Integrated Circuit

ISM

Industrial, Scientific, Medical

LFOSC

Low Frequency Oscillator

LUT

Look Up Table

LVCMOS

Low-Voltage Complementary Metal Oxide Semiconductor

LVDS

Low-Voltage Differential Signaling

LVTTL

Low-Voltage Transistor-Transistor Logic

MIPI

Mobile Industry Processor Interface

NVCM

Non-Volatile Configuration Memory

OTP

One Time Programmable

PCLK

Primary Clock

PFU

Programmable Functional Unit

PLL

Phase Locked Loops

PMU

Power Management Unit

RAM

Random Access Memory

receive

SLVS200

Scalable Low-Voltage Signaling

SPI

Serial Peripheral Interface

TransFR

Transparent Field Reconfiguration

Transmit

UHD

Ultra-High Definition

Virtual Reality

WLCSP

Wafer Level Chip Scale Packaging

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6 FPGA-DS-02013-1.2

1. General Description

CrossLink™ Automotive from Lattice Semiconductor is

a programmable video bridging device that supports a

variety of protocols and interfaces for mobile image

sensors and displays. The device is based on Lattice

mobile FPGA 40nm technology. It combines the

extreme flexibility of an FPGA with the low power, low

cost and small footprint of an ASIC.

CrossLink Automotive supports video interfaces

including MIPI® DPI, MIPI DBI, CMOS camera and

display interfaces, OpenLDI, FPD-Link, FLATLINK, MIPI

D-PHY, MIPI CSI-2, MIPI DSI, SLVS200, SubLVDS, HiSPi

and more.

Lattice Semiconductor provides many pre-engineered

IP (Intellectual Property) modules for CrossLink

Automotive. By using these configurable soft core IPs

as standardized blocks, designers are free to

concentrate on the unique aspects of their design,

increasing their productivity.

The Lattice Diamond® design software allows large

complex designs to be efficiently implemented using

CrossLink Automotive. Synthesis library support for

CrossLink Automotive devices is available for popular

logic synthesis tools. The Diamond tools use the

synthesis tool output along with the constraints from

its floor planning tools to place and route the design in

the CrossLink Automotive device. The tools extract the

timing from the routing and back-annotate it into the

design for timing verification.

Interfaces on CrossLink Automotive provide a variety

of bridging solutions for smart phone, tablets,

wearables, VR, AR, Drone, Smart Home, HMI as well as

adjacent ISM markets. The device is capable of

supporting high-resolution, high-bandwidth content

for mobile cameras and displays at 4k UHD and

beyond.

1.1. Features

 Ultra-low power

 Sleep Mode Support

 Normal Operation – From 5 mW to 150 mW

 Small footprint page

 80-ball ctfBGA (42 mm2)

 80-ball ckfBGA (49 mm2)

 Programmable architecture

 5936 LUTs

 180 kb block RAM

 47 kb distributed RAM

 Two hardened 4-lane MIPI D-PHY interfaces

 Transmit and receive

 6 Gb/s per D-PHY interface

 Programmable source synchronous I/O

 MIPI D-PHY Rx, LVDS Rx, LVDS Tx, SubLVDS Rx,

SLVS200 Rx, HiSPi Rx

 Up to 1200 Mb/s per I/O

 Four high-speed clock inputs

 Programmable CMOS I/O

 LVTTL and LVCMOS

 3.3 V, 2.5 V, 1.8 V and 1.2 V (outputs)

 LVCMOS differential outputs

 Flexible device configuration

 One Time Programmable (OTP) non-volatile

configuration memory

 Master SPI boot from external flash

 Dual image booting supported

 I2C programming

 SPI programming

 TransFR™ I/O for simple field updates

 Enhanced system level support

 Reveal logic analyzer

 TraceID for system tracking

 On-chip hardened I2C block

 Applications examples

 Dual MIPI CSI-2 to Single MIPI CSI-2

Aggregation

 Qual MIPI CSI-2 to Single MIPI CSI-2

Aggregation

 Single MIPI DSI to Single MIPI DSI Repeater

 Single MIPI CSI-2 to Single MIPI CSI-2 Repeater

 Single MIPI DSI to Dual MIPI DSI Splitter

 Single MIPI CSI-2 to Dual MIPI CSI-2 Splitter

 MIPI DSI to OpenLDI/FPD-Link/LVDS Translator

 OpenLDI/FPD-Link/LVDS to MIPI DSI Translator

 MIPI DSI/CSI-2 to CMOS Translator

 CMOS to MIPI DSI-2 Translator

 SubLVDS to MIPI CSI-2 Translator

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FPGA-DS-02013-1.2 7

2. Product Feature Summary

Table 2.1 lists CrossLink Automotive device information and packages.

Table 2.1. CrossLink Automotive Feature Summary

Device

CrossLink Automotive

LUTs

5936

sysMEM Blocks (9 kb)

Embedded Memory (kb)

180

Distributed RAM Bits (kb)

General Purpose PLL

NVCM

Yes

Embedded I2C

Oscillator (10 KHz)

Oscillator (48 MHz)

Hardened MIPI D-PHY

Packages (Footprint, Pitch)

I/O

80 ctfBGA (6.5 x 6.5 mm2, 0.65 mm)

80 ckfBGA (7.0 x 7.0 mm2, 0.65 mm)

*Note: Additional D-PHY Rx interfaces are available using programmable I/O.

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8 FPGA-DS-02013-1.2

3. Architecture Overview

CrossLink Automotive is designed as a flexible, chip-to-chip bridging solution which supports a wide variety of

applications. The device provides three key building blocks for these bridging applications:

 Up to two embedded Hard D-PHY blocks

 Two banks of flexible programmable I/O supporting a variety of standards including D-PHY Rx, subLVDS, SLVS200,

LVDS, and CMOS

 A programmable logic core providing the LUTs, memory, and system resources to implement a wide range of

bridging operations

In addition to these blocks, CrossLink Automotive also provides key system resources including a Power Management

Unit, flexible configuration interface, additional CMOS GPIO, and user I2C blocks.

The block diagram for the device is shown in Figure 3.1.

Programmable IO

Rx: D-PHY/SubLVDS/LVDS/

SLVS200/CMOS

Tx: LVDS/CMOS

Up to 1.2 Gb/s per Lane

14 IO/7 Pairs

Programmable IO

Rx: D-PHY/SubLVDS/LVDS/

SLVS200/CMOS

Tx: LVDS/CMOS

Up to 1.2 Gb/s per Lane

16 IO/8 Pairs

MIPI D-PHY

6 Gb/s

Rx and Tx

4 Data Lanes

1 Clock Lane

MIPI D-PHY

6 Gb/s

Rx and Tx

4 Data Lanes

1 Clock Lane

Programmable FPGA Fabric

5,936 LUTs

180 kbits block RAM

47 kbits distributed RAM

Enough FPGA resources to handle video:

Muxing

Merging

Demuxing

Arbitration

Splitting

Data Conversion

Custom Protocol Design

Power Management Unit I2C/SPI*GPIOs

Figure 3.1. CrossLink Automotive Device Block Diagram

*Note: I2C and SPI configuration modes are supported. User mode hardened I2C is also supported.

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FPGA-DS-02013-1.2 9

3.1. MIPI D-PHY Blocks

The top side of the device (Figure 3.2) includes two hard MIPI D-PHY quads. The D-PHY can be configured to support

both camera interface (CSI-2) and display interface (DSI) applications. Below is a summary of the features supported by

the hard D-PHY quads.

 Transmit and Receive compliant to MIPI Alliance Specification D-PHY Revision 1.1

 High-Speed (HS) and Low-Power (LP) mode support (including built-in contention detect)

 Supports continuous clock mode or low power clock mode

 Up to 6 Gb/s per quad (1500 Mb/s data rate per lane)

 Dedicated PLL for Transmit Frequency Synthesis

 Dedicated Serializer and De-Serializer blocks for fabric interfacing

Lattice Semiconductor provides a set of pre-engineered IP modules which include the full implementation and control

of the hard D-PHY blocks to enable designers to focus on unique aspects of their design.

Figure 3.3 to Figure 3.6 show the signals connected to the fabric and the automatic settings when the hardened D-PHY

is configured for the DSI/CSI-2 transmit and receive modes. Refer to CrossLink High-Speed I/O Interface (FPGA-TN-

02012) for more information on the Hard D-PHY quads.

VCCIO1

VCCIO0

GND

MIPI D-PHY 0 MIPI D-PHY 1

Bank 0

Bank 1Bank 2

VCCIO2

TOP

BOTTOM

Figure 3.2. CrossLink Automotive sysI/O Banking

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10 FPGA-DS-02013-1.2

Bidirectional clk and data

TX – CLK HS ports

RX - Data LP ports

TX – Data HS ports

TX – Data LP ports

TX – CLK LP ports

Control Ports

PLL Ports

MIPIDPHYA

CLKP

CLKN

DP0

DN0

DP[3:1]

DN[3:1]

Dy_HSTXDATA[15:0]

D0_TXLPP

D0_TXLPN

D0_TXLPEN

CLK_TXHSGATE

D0_RXLPP

D0_RXLPN

TXHSBYTECLK

REFCLK LOCK

* x = 1, 2, 3

y = 0, 1, 2, 3

D0_TXHSEN

CLK_TXHSEN

CLK_TXLPP

CLK_TXLPN

PDPLL

USRSTDBY

Dx_TXLPP

Dx_TXLPN

Figure 3.3. MIPI DSI Transmit Interface with Hard D-PHY Module

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FPGA-DS-02013-1.2 11

Bidirectional clk and data

TX – CLK HS ports

TX – Data HS ports

TX – Data LP ports

TX – CLK LP ports

Control Ports

PLL Ports

MIPIDPHYA

CLKP

CLKN

DP0

DN0

DP[3:1]

DN[3:1]

Dy_HSTXDATA[15:0]

D0_TXLPEN

CLK_TXHSGATE

TXHSBYTECLK

REFCLK LOCK

* x = 1, 2, 3

y = 0, 1, 2, 3

D0_TXHSEN

CLK_TXHSEN

CLK_TXLPEN

CLK_TXLPP

CLK_TXLPN

PDPLL

USRSTDBY

Figure 3.4. MIPI CSI-2 Transmit Interface with Hard D-PHY Module

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12 FPGA-DS-02013-1.2

Bidirectional clk and data

RX - Data HS ports

RX - CLK HS ports

RX - CLK LP ports

RX - Data LP ports

TX – Data LP ports

Control Ports

MIPIDPHYA

CLKP

CLKN

DP0

DN0

DPx

DNx

D0_TXLPP

D0_TXLPN

D0_RXLPP

D0_RXLPN

* x = 1, 2, 3

y = 0, 1, 2, 3

USRSTDBY

DO_RXHSEN

DO_RXLPEN

CLKRXHSEN

CLKRXLPEN

Dy_HSRXDATA[15:0]

RXHSBYTECLK

CLK_RXLPP

CLKHSBYTE

CLK_RXLPN

CLK_CD

D0_CD

Figure 3.5. MIPI DSI Receive Interface with Hard D-PHY Module

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FPGA-DS-02013-1.2 13

Bidirectional clk and data

RX - Data HS ports

RX - CLK HS ports

RX - CLK LP ports

RX - Data LP ports

Control Ports

MIPIDPHYA

CLKP

CLKN

DP0

DN0

DPx

DNx

D0_RXLPP

D0_RXLPN

* x = 1, 2, 3

y = 0, 1, 2, 3

USRSTDBY

Dy_HSRXDATA[15:0]

RXHSBYTECLK

D0_CD

CLK_RXLPP

CLKHSBYTE

CLK_RXLPN

CLK_CD

Figure 3.6. MIPI CSI-2 Receive Interface with Hard D-PHY Module

3.2. Programmable I/O Banks

CrossLink Automotive devices provide programmable I/O which can be used to interface to a variety of external

standards on Banks 1 and 2. CrossLink Automotive devices also provide dedicated CMOS GPIOs on Bank 0. Bank 0

GPIOs only support Single Data Rate (SDR) interfaces, while Bank 1 and Bank 2 support both SDR and Double Data Rate

(DDR) interfaces. The GPIOs on Bank 0 do not include differential signaling capabilities. The location of the three Banks

and their associated supplies are shown in Figure 3.2.

Bank 0 features:

 Support the following single ended standards (ratioed to VCCIO)

 LVCMOS33

 LVCMOS25

 LVCMOS18

 LVTTL33

 Tri-state control for output

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14 FPGA-DS-02013-1.2

 Input/output register blocks

 Open-drain option and programmable input hysteresis

 Internal pull-up resistors with configurable values of 3.3 kΩ, 6.8 kΩ and 10 kΩ

Bank 1 and Bank 2 features:

 Built-in support for the following differential standards

 LVDS – Tx and Rx

 SLVS200 – Rx

 SubLVDS – Rx

 MIPI – Rx (both LP and HS receive on a single differential pair)

 Support for the following single ended standards (ratioed to VCCIO)

 LVCMOS33

 LVCMOS25

 LVCMOS18

 LVCMOS12 (Outputs Only)

 LVTTL33

 Independent voltage levels per bank based on VCCIO supply

 Input/output gearboxes per LVDS pair supporting several ratios for video interface applications

 DDRX1, DDRX2, DDRX4, DDRX8 and DDRX71, DDRX141

 Programmable delay cells to support edge-aligned and center-aligned interfaces

 Programmable differential termination (~ 100 Ω) with dynamic enable control

 Tri-state control for output

 Input/output register blocks

 Single-ended standards support open-drain and programmable input hysteresis

 Optional weak pull-up resistors

Table 3.1. CrossLink Automotive Output Support per Bank Basis

OUTPUT

BANK 0

BANK 1

BANK 2

LVCMOS12

—



LVCMOS18



LVCMOS25



LVCMOS33



LVTTL33



LVDS25

—



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FPGA-DS-02013-1.2 15

Table 3.2. CrossLink Automotive Input Support per Bank Basis

INPUT

BANK 0

BANK 1

BANK 2

LVCMOS12

—

LVCMOS18



LVCMOS25



LVCMOS33



LVTTL33



LVDS25

—



MIPI D-PHY

—



SLVS200

—



subLVDS

—



3.3. sysI/O Buffers

The CrossLink Automotive sysI/O buffers are distributed across three banks located at the bottom of the CrossLink

Automotive device as shown in Figure 3.2. The sysI/O buffers support a wide variety of standards to interface to a

range of systems including LVDS, subLVDS, LVCMOS, LVTTL, SLVS200 and MIPI. CrossLink Automotive supports single-

ended buffers on all three banks. Differential I/O is supported on Bank 1 and Bank 2.

3.3.1. Programmable PULLMODE Settings

The CrossLink Automotive sysI/O buffers offer multiple programmable value pull-up resistors on the three banks. The

pull-up values are programmable on a “per-pin” basis. The default state of the I/O pins prior to configuration is tri-

stated with a weak pull-up to VCCIOx. The I/O pins convert to the software user-defined settings after the configuration

bitstream has been successfully downloaded to the device. Each sysIO buffer can be programmed with a 100 kΩ (weak

pull-up), 3.3 kΩ, 6.8 kΩ, 10 kΩ or no pull-up. These pull-up options allow an I2C interface to be place on the majority of

the pins on the device. These options are not exclusively for I2C protocol and may be used for other functions.

3.3.2. Output Drive Strength

Each CrossLink Automotive output can have its own individual drive strength setting, but is predefined based on the

VCCIOx setting. Table 3.3 lists the drive settings for the corresponding I/O type.

Table 3.3. Drive Strength Values

VCCIOx (V)

I/O Type

Drive Strength (mA)

3.3

LVTTL33

3.3

LVCMOS33

2.5

LVCMOS25

1.8

LVCMOS18

1.2

LVCMOS12

3.3.3. On-Chip Termination

Bank 1 and bank 2 of CrossLink Automotive support LVDS, SLVS200 subLVDS and MIPI D-PHY inputs. These two banks

support on-chip 100 Ω input differential termination between LVDS, SLVS200 and subLVDS pairs. For MIPI D-PHY

inputs, the on-chip 100 Ω termination is dynamically enabled based on the HSSEL (High Speed Select) signal.

See CrossLink High-Speed I/O Interface (FPGA-TN-02012) and CrossLink sysI/O Usage Guide (FPGA-TN-02016) for

details.

CrossLink Automotive Family

Data Sheet

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16 FPGA-DS-02013-1.2

3.4. Programmable FPGA Fabric

CrossLink Automotive is built around a programmable logic fabric consisting of 5936 four input lookup tables (LUT4)

arranged alongside dedicated registers in Programmable Functional Units (PFU). These PFU blocks are the building

blocks for logic, arithmetic, RAM and ROM functions. The PFU blocks are connected via a programmable routing

network. The Lattice Diamond design software configures the PFU blocks and the programmable routing for each

unique design. Interspersed between rows of PFU are rows of sysMEM™ Embedded Block RAM (EBR), with

programmable I/O banks, embedded I2C and embedded MIPI D-PHY arranged on the top and bottom of the device as

shown in Figure 3.7.

PFUPFU

PFU PFU

PFUPFU

PFU PFU

PFU

MIPI D-PHY 0 MIPI D-PHY 1

Bank 2 Bank 1 Bank 0

4 EBR Blocks (9 kb each)

PMU

CONFIG

DDRDLL1

DDRDLL2

OSC

PLL

Clocking

I2C0

I2C1

NVCM

4 EBR Blocks (9 kb each) 4 EBR Blocks (9 kb each) 4 EBR Blocks (9 Kb each) 4 EBR Blocks (9 kb each)

Figure 3.7. CrossLink Automotive Device Simplified Block Diagram (Top Level)

3.4.1. PFU Blocks

The core of the CrossLink Automotive device consists of PFU blocks. Each PFU block consists of four interconnected slices

numbered 0 – 3 as shown in Figure 3.8. Each slice contains two LUTs. All the interconnections to and from PFU blocks are

from routing. The PFU block can be used in Distributed RAM or ROM function, or used to perform Logic, Arithmetic or ROM

functions.

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FPGA-DS-02013-1.2 17

Slice 0

LUT4 &

CARRY

D D

Slice 1 Slice 2

From

Routing

Slice 3

D D D D

FF FF FF FF FF FF

Routing

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

Figure 3.8. CrossLink Automotive PFU Diagram

3.4.2. Slice

Each slice contains two LUT4s feeding two registers. Each PFU contains logic that allows the LUTs to be combined to

perform functions such as LUT5, LUT6, LUT7 and LUT8. There is control logic to perform set/reset functions

(programmable as synchronous/asynchronous), clock select, chip-select and wider RAM/ROM functions. Figure 3.9.

shows an overview of the internal logic of the slice. The registers in the slice can be configured for positive/negative

and edge triggered or level sensitive clocks.

Each slice has 14 input signals: 13 signals from routing and 1 signal from the carry-chain routed from the adjacent slice

PFU. There are five outputs: four to routing and one to carry-chain (to the adjacent PFU). There are two inter

slice/PFU output signals that are used to support wider LUT functions, such as LUT6, LUT7, and LUT8. Table 3.4 and

Figure 3.9. list the signals associated with all the slices. Figure 3.10 shows the connectivity of the inter-slice/PFU signals

that support LUT5, LUT6, LUT7, and LUT8.

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18 FPGA-DS-02013-1.2

LUT4 &

CARRY*

LUT4 &

CARRY*

FXA

FXB

FCO

FCI

CLK

LSR

For Slices 0 and 1, memory control signals are generated from Slice 2 as follows:

WCK is CLK

WRE is from LSR

DI[3:2] for Slice 1 and DI[1:0] for Slice 0 data from Slice 2

WAD [A:D] is a 4-bit address from slice 2 LUT input

Notes:

From Different Slice/PFU

Figure 3.9. Slice Diagram

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FPGA-DS-02013-1.2 19

SLICE 3

FXB

FXA

SLICE 2

FXB

FXA

SLICE 1

FXB

FXA

SLICE 0

FXB

FXA

LUT8

LUT5

LUT6

LUT5

LUT6

LUT5

LUT7

LUT5

LUT7 Output

To Next PFU

PFU Col(n-1)

LUT7 Output

From Previous PFU

PFU Col(n) PFU Col(n+1)

SLICE 3

FXB

FXA

SLICE 2

FXB

FXA

SLICE 1

FXB

FXA

SLICE 0

FXB

FXA

LUT8

LUT5

LUT6

LUT5

LUT6

LUT5

LUT7

LUT5

SLICE 3

FXB

FXA

SLICE 2

FXB

FXA

SLICE 1

FXB

FXA

SLICE 0

FXB

FXA

LUT8

LUT5

LUT6

LUT5

LUT6

LUT5

LUT7

LUT5

Figure 3.10. Connectivity Supporting LUT5, LUT6, LUT7 and LUT8

Table 3.4. Slice Signal Descriptions

Function

Type

Signal Names

Description

Input

Data signal

A0, B0, C0, D0

Inputs to LUT4

Input

Data signal

A1, B1, C1, D1

Inputs to LUT4

Input

Multi-purpose

Multipurpose Input

Input

Multi-purpose

Multipurpose Input

Input

Control signal

Clock Enable

Input

Control signal

LSR

Local Set/Reset

Input

Control signal

CLK

System Clock

Input

Inter-PFU signal

FCI

Fast Carry-in1

Input

Inter-slice signal

FXA

Intermediate signal to generate LUT6, LUT7 and LUT82

Input

Inter-slice signal

FXB

Intermediate signal to generate LUT6, LUT7 and LUT82

Output

Data signals

F0, F1

LUT4 output register bypass signals

Output

Data signals

Q0, Q1

Output

Inter-PFU signal

FCO

Fast carry chain output1

Notes:

See Figure 3.9. for connection details.

Requires two adjacent PFUs.

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20 FPGA-DS-02013-1.2

3.5. Clocking Structure

The CrossLink Automotive device family provides resources to support a wide range of clocking requirements for

programmable video bridging. These resources are described below. For details, refer to CrossLink sysCLOCK PLL/DLL

Design and Usage Guide (FPGA-TN-02015).

3.5.1. sysCLK PLL

The CrossLink Automotive sysCLK PLL provides the ability to synthesis clock frequencies (See Table 4.14 for input

frequency range). The PLL provides features such as dynamic selectable clock input, clock injection delay removal,

independent dynamic output enable control, and programmable output phase adjustment. The architecture of the PLL

is shown in Figure 3.11 and followed by a description of the PLL blocks.

Figure 3.11. CrossLink Automotive PLL Block Diagram

Table 3.5 provides a description of the signals in the PLL block.

Table 3.5. CrossLink Automotive PLL Port Definition

Signal

I/O

Description

CLKI

Input clock to PLL

CLKFB

Feedback clock

USRSTDBY

User port to put the PLL to sleep mode

PHASESEL[1:0]

Select the output affected by Dynamic Phase adjustment

PHASEDIR

Dynamic phase adjustment direction

PHASESTEP

Dynamic phase adjustment step

PHASELOADREG

Load dynamic phase adjustment values into PLL

RST

Resets the whole PLL

ENCLKOP

Enable PLL output CLKOP

ENCLKOS

Enable PLL output CLKOS

ENCLKOS2

Enable PLL output CLKOS2

ENCLKOS3

Enable PLL output CLKOS3

PLLWAKESYNC

Enable PLL switching from internal to user feedback path when PLL wake up

CLKOP

PLL main output clock

CLKOS

PLL output clock

CLKOS2

PLL output clock

CLKOS3

PLL output clock

LOCK

PLL LOCK to CLKI, asynchronous signal. Active high indicates PLL lock

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FPGA-DS-02013-1.2 21

3.5.2. Primary Clocks

The primary clock routing network is made up of low skew clock routing resources with connectivity to every

synchronous element of the device. Primary clock sources are selected in the center mux and distributed on the

primary clock routing to clock the synchronous elements in the FPGA fabric. CrossLink Automotive family of devices

provide up to eight unique global primary clocks. Primary clock sources are:

 LVDS PIO pins

 GPIO pins

 PLL outputs

 Clock dividers

 Fabric internally generated clock signal

 Divided down clock from DPHY

 OSCI

The routing clock structure is shown in Figure 3.12.

Center Mux

(8 PCLKs out)

PLL

Bank 0

GRPIO LVDS

PIO GRPIO GPIO GPIO

CLKDIV CLKDIV CLKDIV CLKDIV

OSC

CLK_HS_BYTE_0 HS_BYTE_CLK0 (RX and TX) CLK_HS_BYTE_0HS_BYTE_CLK1 (RX and TX)

MIPI_DPHY0 MIPI_DPHY1

Fabric

Entry

Bank 2

Edge Clocks Edge Clocks

Bank 1

Fabric

Entry

OSC_HF OSC_LF

LVDS

PIO

LVDS

PIO

LVDS

PIO

LVDS

PIO

LVDS

PIO

Figure 3.12. CrossLink Automotive Clocking Structure

3.5.3. Edge Clocks

The CrossLink Automotive device has Edge Clock (ECLK) at the bottom 2 banks (Bank 1 and Bank 2) of the device (Figure

3.2). The CrossLink Automotive device has 2 edge clocks per Programmable I/O bank. These clocks, which have low

injection time and skew, are used to clock I/O registers. Edge clock resources are designed for high speed I/O interfaces

with high fan-out capability. The sources of edge clocks are:

 Dedicated Clock (PCLK) pins muxed with the DLLDEL output

 PLL outputs (CLKOP and CLKOS)

 Internal nodes

ELCK input MUX collects all clock sources as shown in Figure 3.13 below. There are two ECLK Input MUXs, one on each

bank. It drives the ECLK SYNC modules and the ECLK Clock Divider through a 2 to 1 MUX.

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22 FPGA-DS-02013-1.2

Bank 1 or Bank 2 LVDS PCLK Pin

Bank 1 or Bank 2 DLLDEL Output

PLL CLKOP

PLL CLKOS

From Routing

ECLKSYNCB

To ECLK of other

bank on same side

From ECLKSYNC of

other bank on

same side

ECLK Tree

Figure 3.13. CrossLink Automotive Edge Clock Sources per Bank

3.5.4. Dynamic Clock Enables

Each PLL output has a user input signal to dynamically enable/disable its output to provide a glitch free clock. Then the

clock enable signal is set to logic ‘0’, the corresponding output clock is held to logic ‘0’. This allows the user to save

power by stopping the corresponding output clock when not in use.

3.5.5. Internal Oscillator (OSCI)

The OSCI element performs multiple functions on the CrossLink Automotive device. It is used for configuration and

available during user mode. OSCI element has the following features in user mode:

 Always-on low frequency clock output (LFCLKOUT) with nominal frequency of 10 kHz

 High-frequency clock output (HFCLKOUT) with nominal frequency of 48 MHz that can be enabled or disabled using

HFOUTEN input

 Programmable output dividers (HFCLKDIV) for 48 MHz, 24 MHz, 12 MHz or 6 MHz HFCLKOUT output

 Both output clocks have a direct connection to primary clock routing

Figure 3.14, Table 3.6 and Table 3.7 below show the OSCI definitions

Figure 3.14. CrossLink Automotive OSCI Component Symbol

Table 3.6. OSCI Component Port Definition

Port Name

I/O

Description

HFOUTEN

High frequency clock output enable

HFCLKOUT

High frequency clock output

LFCLKOUT

Low Frequency clock output

Table 3.7. OSCI Component Attribute Definition

Defparam Name

Description

Value

Default

HFCLKDIV

Configure HF oscillator output divider

1, 2, 4, 8

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FPGA-DS-02013-1.2 23

3.6. Embedded Block RAM Overview

CrossLink Automotive devices contain sysMEM Embedded Block RAM (EBR). The EBR consists of a 9 kB RAM with

memory core, dedicated input registers and output registers with separate clock and clock enable.

Support for different memory configurations:

 Single Port

 True Dual Port

 Pseudo Dual Port

 ROM

 FIFO (logic wrapper added automatically by design tools)

Flexible customization features:

 Initialization of RAM/ROM

 Memory cascading (handled automatically by design tools)

 Optional parity bit support

 Byte-enable

 Multiple block size options

 RAM modes support optional Write Through or Read-Before-Write modes

For details, refer to CrossLink Memory Usage Guide (FPGA-TN-02017).

Table 3.8. sysMEM Block Configurations

Memory Mode

Memory Size Configurations

Single Port

8,192 x 1

4,096 x 2

2,048 x 4

1,024 x 9

512 x 18

True Dual Port

8,192 x 1

4,096 x 2

2,048 x 4

1,024 x 9

Pseudo Dual Port

8,192 x 1

4,096 x 2

2,048 x 4

1,024 x 9

512 x 18

ROM

8,192 x 1

4,096 x 2

2,048 x 4

1,024 x 9

512 x 18

3.7. Power Management Unit

The embedded Power Management Unit (PMU) allows low-power Sleep State of the device. Figure 3.15

shows the

block diagram of the PMU IP.

When instantiated in the design, PMU is always on, and uses the low-speed clock from oscillator of the device to

perform its operations.

The typical use case for the PMU is through a user implemented state machine that controls the sleep and

wake up of

the device. The state machine implemented in the FPGA fabric identifies when the device needs to

go into sleep mode,

issues the command through PMU’s FPGA fabric interface, assigns the parameters for sleep

(time to wake up and so

on) and issues Sleep command.

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24 FPGA-DS-02013-1.2

The device can be woken up externally using the PMU Wake-Up (USRWKUP) pin, or from the PMU Watch

Dog Timer

expiry or from I2C0 (address decoding detection or FIFO full in one of hardened I2C).

Power Management Unit (PMU)

Watch Dog

Timer

Power Control Unit

External User Wake-up

(USRWKUPN)

PMU Wake-up from I2C0

(PMUWKUP)

8-bit Addressable Fabric Interface

PMU Sleep Signal, SLEEP

PMU Control

Watch Dog Timer

User Mode Signals

PMU Clock (From Oscillator)

(PMUCLK)

From FPGA Fabric

Figure 3.15. CrossLink Automotive MIPI D-PHY Block

3.7.1. PMU State Machine

PMU can place the device in two mutually exclusive states – Normal State and Sleep State. Figure 3.16 shows the

PMU

State Machine triggers for transition from one state to the other.

 Normal state – All elements of the device are active to the extent required by the design. In this state,

the device is

at fully active and performing as required by the application. Note that the power consumption of the device is

highest in this state.

 Sleep state – The device is power gated such that the device is not operational. The configuration of

the device and

the EBR contents are retained; thus in Sleep mode, the device does not lose configuration

SRAM and EBR contents.

When it transitions to Normal state, device operates with these contents preserved. The PMU is active along with

the associated GPIOs. The power consumption of the device is lowest in this state. This helps reduce the overall

power consumption for the device.

Sleep Mode Normal Mode

User Logic Initiated

User I2

External Wake-up/

WDT Expiry Wake-up

Figure 3.16. CrossLink Automotive PMU State Machine

For more details, refer to Power Management and Calculation for CrossLink Devices (FPGA-TN-02018).

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Data Sheet

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FPGA-DS-02013-1.2 25

3.8. User I2C IP

CrossLink Automotive devices have two I2C IP cores that can be configured either as an I2C master or as

an I2C slave. The

I2C0 core has pre-assigned pins, and supports PMU wakeup over I2C. The pins for the I2C1 interface are not pre-assigned –

user can use any General Purpose I/O pins.

The I2C cores support the following functionality:

 Master and Slave operation

 7-bit and 10-bit addressing

 Multi-master arbitration support

 Clock stretching

 Up to 1 MHz data transfer speed

 General call support

 Optionally delaying input or output data, or both

 Optional FIFO mode

 Transmit FIFO size is 10 bits x 16 bytes, receive FIFO size is 10 bits x 32 bytes

For further information on the User I2C, refer to CrossLink I2C Hardened IP Usage Guide (FPGA-TN-02019).

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26 FPGA-DS-02013-1.2

3.9. Programming and Configuration

CrossLink Automotive is a SRAM-based programmable logic device that includes an internal Non-Volatile Configuration

Memory (NVCM), as well as flexible SPI and I2C configuration modes. CrossLink Automotive provides four modes for

loading the configuration data into the SRAM memory.

 Self-Download (NVCM) mode – CrossLink Automotive retrieves bitstream from internal NVCM

 Master SPI mode – CrossLink Automotive retrieves bitstream from an external SPI Flash

 Slave SPI mode – System microprocessor writes bitstream to CrossLink Automotive through SPI port

 Slave I2C mode – System microprocessor writes bitstream to CrossLink Automotive through I2C port

CrossLink Automotive provides a set of sysCONFIG I/O pins to program and configure the FPGA. The sysCONFIG pins are

grouped together to create ports (I2C, SSPI or MSPI) that are used to interact with the FPGA for programming,

configuration, and access of resources inside the FPGA. The sysCONFIG pins (Table 3.9) in a configuration group may be

active and used for programming the FPGA or they can be reconfigured to act as general purpose I/Os.

Table 3.9. CrossLink Automotive sysCONFIG Pins

Pin Name

Associated sysCONFIG Port

CRESETB

Self Download Mode/SSPI/MSPI/I2C

CDONE

Self Download Mode/SSPI/MSPI/I2C

SPI_SCK/MCK/SDA

SSPI/MSPI/I2C

SPI_SS/CSN/SCL

SSPI/MSPI/I2C

MOSI

SSPI/MSPI

MISO

SSPI/MSPI

As external power ramps up, a Power On Reset (POR) circuit inside the FPGA becomes active. When POR conditions are

met, the POR circuit releases an internal reset strobe, allowing the device to begin its initialization process. After

CrossLink Automotive drives CDONE low, CrossLink Automotive enters the memory initialization phase where it clears

all of the SRAM memory inside the FPGA. CrossLink Automotive remains in initialization state until the CRESETB pin is

deasserted or after SSPI/SI2C activation code is received.

 After CRESETB goes from low to high, the Configuration Logic puts the device into master auto booting mode

where it boots either from the internal NVRAM or an external SPI boot PROM.

 Holding the CRESETB low postpones the master auto booting event and allows the slave configuration ports (Slave

SPI or Slave I2C) to detect a ‘Slave Active’ condition where the SPI or I2C Master sends an Activation Key code to

CrossLink Automotive. An external SPI Master or I2C Master needs to write the Activation Key to the FPGA while

CRESETB is held LOW and within 9.5 ms from Vcc min during power up to enter into one of the slave configuration

modes.

 Sources should not drive output to CrossLink Automotive until configuration has been completed to ensure

CrossLink Automotive is in a known state.

In addition to the flexible configuration modes, the CrossLink Automotive configuration engine supports the following

special features:

 TransFR (Transparent Field Reconfiguration) allowing users to update logic in field without interrupting system

operation by freezing I/O states during configuration

 Dual-Boot Support for primary and golden bitstreams provides automatic recovery from configuration failures

 Security and One-Time Programmable (OTP) modes protect bitstream integrity and prevent readback

 64-bit unique TraceID per device

For more information,

refer to CrossLink Programming and Configuration Usage Guide (FPGA-TN-02014).

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FPGA-DS-02013-1.2 27

4. DC and Switching Characteristics

4.1. Absolute Maximum Ratings

Table 4.1. Absolute Maximum Ratings1, 2, 3

Symbol

Parameter

Min

Max

Unit

VCC

Core Supply Voltage

–0.5

1.32

VCCGPLL

PLL Supply Voltage

–0.5

1.32

VCCAUX

Auxiliary Supply Voltage for Bank 1, 2 and NVCM - @ 2.5 V

–0.5

2.75

Auxiliary Supply Voltage for Bank 1, 2 and NVCM - @ 3.3 V

–0.5

3.63

CCIO

I/O Driver Supply Voltage for Banks 0, 1, 2

–0.5

3.63

—

Input or I/O Transient Voltage Applied

–0.5

3.63

VCCA_DPHYx

VCCPLL_DPHY

MIPI D-PHY Supply Voltages

–0.5

1.32

—

Voltage Applied on MIPI D-PHY Pins

–0.5

1.32

Storage Temperature (Ambient)

–65

150

°C

Junction Temperature (TJ)

—

+125

°C

Notes:

Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional

operation of the device at these or any other conditions above those indicated in the operational sections of this specification is

not implied.

Compliance with the Lattice Thermal Management document is required.

All voltages referenced to GND.

4.2. Recommended Operating Conditions

Table 4.2. Recommended Operating Conditions1, 2

Symbol

Parameter

Min

Max

Unit

VCC

Core Supply Voltage

1.14

1.26

VCCGPLL

PLL Supply Voltage

1.14

1.26

VCCAUX3

Auxiliary Supply Voltage for Bank 1, 2 and NVCM - @ 2.5 V

2.375

2.625

Auxiliary Supply Voltage for Bank 1, 2 and NVCM - @ 3.3 V

3.135

3.465

CCIO0

I/O Driver Supply Voltage for Bank 0

1.71

3.465

CCIO1/2

I/O Driver Supply Voltage for Bank 1, 2

1.14

3.465

TJAUTO

Junction Temperature, Automotive Operation

–40

125

°C

D-PHY External Power Supply

VCCA_DPHYx

Analog Supply Voltage for D-PHY

1.14

1.26

VCCPLL_DPHYx

PLL Supply voltage for D-PHY

1.14

1.26

Notes:

For correct operation, all supplies must be held in their valid operation range.

Like power supplies, must be tied together if they are at the same supply voltage. Follow the noise filtering recommendations in

CrossLink Hardware Checklist (FPGA-TN-02013).

VCCAUX can operate at either 2.5 V +/- 5% or 3.3 V +/- 5%.

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28 FPGA-DS-02013-1.2

4.3. Power Supply Ramp Rates

Table 4.3. Power Supply Ramp Rates*

Symbol

Parameter

Min

Max

Unit

tRAMP

Power supply ramp rates for all power supplies

0.6

V/ms

*Note: Assume monotonic ramp rates.

4.4. Power-On-Reset Voltage Levels

Table 4.4. Power-On-Reset Voltage Levels1, 3, 4

Symbol

Parameter

Min

Max

Unit

VPORUP

Power-On-Reset ramp up trip point

(Monitoring VCC, VCCIO0, and VCCAUX)

VCC

0.62

0.93

VCCIO02

0.87

1.50

VCCAUX

0.90

1.53

VPORDN

Power-On-Reset ramp down trip point

(Monitoring VCC, VCCIO0, and VCCAUX)

VCC

—

0.79

VCCIO02

—

1.50

VCCAUX

—

1.53

Notes:

These POR ramp up trip points are only provided for guidance. Device operation is only characterized for power supply voltages

specified under recommended operating conditions.

Only VCCIO0 (Config Bank) has a Power-On-Reset ramp up trip point. All other VCCIOs do not have Power-On-Reset ramp up

detection.

VCCIO supplies

should be powered-up before or together with the VCC and VCCAUX supplies.

Configuration starts after VCC, VCCIO0 and VCCAUX reach VPORUP. For details, see tCONFIGURATION time in Table 4.21.

4.5. ESD Performance

Refer to LIFMD Product Family Qualification Summary for complete qualification data, including ESD

performance.

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Data Sheet

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FPGA-DS-02013-1.2 29

4.6. DC Electrical Characteristics

Over recommended operating conditions.

Table 4.5. DC Electrical Characteristics

Symbol

Parameter

Condition

Min

Typ

Max

Unit

IIL, IIH1, 4, 5

Input or I/O Leakage

0 ≤ VIN ≤ VCCIO

−10

—

+10

µA

IPU4

Internal Pull-Up Current

VCCIO = 1.8 V between 0 ≤ VIN ≤ 0.65 * VCCIO

−3

—

−31

µA

VCCIO = 2.5 V between 0 ≤ VIN ≤ 0.65 * VCCIO

−8

—

−72

µA

VCCIO = 3.3 V between 0 ≤ VIN ≤ 0.65 * VCCIO

−11

—

−128

µA

C12

I/O Capacitance2

VCCIO = 3.3 V, 2.5 V, 1.8 V, 1.2 V,

VCC = 1.2 V, VIO = 0 to VIH (MAX)

—

C22

Dedicated Input

Capacitance2

VCCIO = 3.3 V, 2.5 V, 1.8 V, 1.2 V,

VCC = 1.2 V, VIO = 0 to VIH (MAX)

—

C32

MIPI D-PHY High Speed IO

Capacitance

VCCIO = 2.5V,VCC = 1.2V, VCC*_DPHY = 1.2V , VIO

= 0 to VIH (MAX)

—

VHYST3

Hysteresis for Single-

Ended Inputs

VCCIO = 3.3 V, 2.5 V, 1.8 V

VCC = 1.2 V, VIO = 0 to VIH (MAX)

—

200

—

Notes:

Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tristated. It is

not measured with the output driver active. Bus maintenance circuits are disabled.

TA = 25 oC, f = 1.0 MHz.

Hysteresis is not available for VCCIO = 1.2 V.

Weak pull-up setting. Programmable pull-up resistors on Bank 0 will see higher current. Refer to CrossLink sysI/O Usage Guide

(FPGA-TN-02016) for details on programmable pull-up resistors.

Input pins are clamped to VCCIO and GND by a diode. When input is higher than VCCIO, or lower than GND, the Input Leakage

current will be higher than the IIL and IIH.

CrossLink Automotive Family

Data Sheet

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30 FPGA-DS-02013-1.2

4.7. CrossLink Automotive Supply Current

Over recommended operating conditions.

Table 4.6. CrossLink Automotive Supply Current

Symbol

Parameter

Typ

Unit

Normal Operation1

ICC

Vcc Power Supply Current

ICCPLL

PLL Power Supply Current

µA

ICCAUX

Auxiliary Power Supply Current for Bank 1, 2 and NVCM Programming Supply Current

ICCIOx

Bank x Power Supply Current (per Bank)

µA

ICCA_DPHYx

VCCA_DPHYx Power Supply Current

8.5

ICCPLL_DPHYx

VCCPLL_DPHYx Power Supply Current

1.5

Standby Current2

ICC_STDBY

Vcc Power Supply Standby Current

ICCPLL_STDBY

PLL Power Supply Standby Current

µA

ICCAUX_STDBY

Auxiliary Power Supply Current for Bank 1, 2 and NVCM Programming Supply Standby Current

0.2

ICCIOx_STDBY

Bank Power Supply Standby Current (per Bank)

µA

ICCA_DPHYx_STDBY

VCCA_DPHYx Power Supply Standby Current

µA

ICCPLL_DPHYx_STDBY

VCCPLL_DPHYx Power Supply Standby Current

µA

Sleep/Power Down Mode Current3

ICC_SLEEP

Vcc Power Supply Sleep Current

0.2

ICCPLL_SLEEP

PLL Power Supply Current

µA

ICCAUX_SLEEP

Auxiliary Power Supply Current for Bank 1, 2 and NVCM Programming Supply Current

µA

ICCIOx_SLEEP

Bank Power Supply Current (per Bank)

µA

ICCA_DPHY_SLEEP

VCCA_DPHYx Power Supply Sleep Current

µA

ICCPLL_DPHY_SLEEP

VCCPLL_DPHYx Power Supply Sleep Current

µA

Notes:

Normal Operation

2:1 MIPI CSI-2 Image Sensor Aggregator Bridge design under the following conditions:

a. TJ = 25 °C, all power supplies at nominal voltages.

b. Typical processed device in ctfBGA80 package.

c. To determine power for all other applications and operating conditions, use Power Calculator in Lattice Diamond design

software

Standby Operation

A typically processed device in ctfBGA80 package with blank pattern programmed, under the following conditions:

a. All outputs are tri-stated, all inputs are held at either VCCIO, or GND.

b. All clock inputs are at 0 MHz.

c. TJ = 25 °C, all power supplies at nominal voltages.

d. No pull-ups on I/O.

Sleep/Power Down Mode

2:1 MIPI CSI-2 Image Sensor Aggregator Bridge design under the following conditions:

a. Design is put into Sleep/Power Down Mode with user logic powers down D-PHY, and enters into Sleep Mode in PMU.

b. TJ = 25 °C, all power supplies at nominal voltages.

c. Typical processed device in ctfBGA80 package.

To determine the CrossLink Automotive start-up peak current, use the Power Calculator tool in the Lattice Diamond design

software.

CrossLink Automotive Family

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02013-1.2 31

4.8. Power Management Unit (PMU) Timing

Table 4.7. PMU Timing*

Symbol

Parameter

Device

Max

Unit

tPMUWAKE

Time for PMU to wake from Sleep mode

All Devices

0.5

*Note: For details on PMU usage, refer to Power Management and Calculation for CrossLink Devices (FPGA-TN-02018).

4.9. sysI/O Recommended Operating Conditions

Table 4.8. sysI/O Recommended Operating Conditions1

Standard

VCCIO

Min

Typ

Max

LVCMOS33/LVTTL33

3.135

3.30

3.465

LVCMOS25

2.375

2.50

2.625

LVCMOS18

1.710

1.80

1.890

LVCMOS12 (Output only)2

1.140

1.20

1.260

subLVDS (Input only)

1.710

1.80

1.890

2.375

2.50

2.625

3.135

3.30

3.465

SLVS200 (Input only)3

1.140

1.20

1.260

1.710

1.80

1.890

2.375

2.50

2.625

3.135

3.30

3.465

LVDS (Input only)

1.710

1.80

1.890

2.375

2.50

2.625

3.135

3.30

3.465

LVDS (Output only)

2.375

2.50

2.625

MIPI (Input only)

1.140

1.20

1.260

Note:

For input voltage compatibility, refer to CrossLink sysI/O Usage Guide (FPGA-TN-02016).

For VCCIO1 and VCCIO2 only.

For SLVS200/MIPI interface I/O placement, see the Programmable I/O Banks section.

4.10. sysI/O Single-Ended DC Electrical Characteristics

Table 4.9. sysI/O Single-Ended DC Electrical Characteristics

Input/Output

Standard

VIL

VIH

VOL Max

(V)

VOH Min

(V)

IOL

(mA)

IOH

(mA)

Min (V)

Max (V)

Min (V)

Max (V)

LVCMOS33/

LVTTL33

–0.3

0.8

2.0

VCCIO+0.2

0.40

VCCIO − 0.4

–8

0.20

VCCIO − 0.2

0.1

–0.1

LVCMOS25

–0.3

0.7

1.7

VCCIO+0.2

0.40

VCCIO − 0.4

–6

0.20

VCCIO − 0.2

0.1

–0.1

LVCMOS18

–0.3

0.35 VCCIO

0.67 VCCIO

VCCIO+0.2

0.40

VCCIO − 0.4

–4

0.20

VCCIO − 0.2

0.1

–0.1

LVCMOS12*

(Output only)

—

0.40

VCCIO − 0.4

–2

0.20

VCCIO − 0.2

0.1

–0.1

*Note: For VCCIO1 and VCCIO2 only.

CrossLink Automotive Family

Data Sheet

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32 FPGA-DS-02013-1.2

4.11. sysI/O Differential Electrical Characteristics

4.11.1. LVDS/subLVDS/SLVS200

Over recommended operating conditions.

Table 4.10. LVDS/subLVDS1/SLVS2001, 2

Parameter

Description

Test Conditions

Min

Typ

Max

Unit

VINP, VINN

Input Voltage

—

0.00

—

2.40

VCM

Input Common Mode Voltage

Half the sum of the two inputs

0.05

—

2.35

VTHD(LVDS)

Differential Input Threshold

ǀVINP - VINNǀ

100

—

VTHD(subLVDS)

Differential Input Threshold

ǀVINP - VINNǀ

—

VTHD(SLVS200)

Differential Input Threshold

ǀVINP - VINNǀ

—

IIN

Input Current

Normal Mode

−10

—

µA

Standby Mode

−10

—

µA

VOH

Output High Voltage for VOP or VOM

RT = 100 Ω

—

1.43

1.60

VOL

Output Low Voltage for VOP or VOM

RT = 100 Ω

0.90

1.08

—

VOD

Output Voltage Differential

|VOP - VOM|, RT = 100 Ω

250

350

450

∆VOD

Change in VOD between High and

Low

—

VOS

Output Voltage Offset (Common

Mode Voltage)

(VOP + VOM)/2, RT = 100 Ω

1.125

1.250

1.375

∆VOS

Change in VOS between H and L

—

ISAB

Output Short Circuit Current

VOD = 0 V driver outputs shorted to

each other

—

Notes:

1. Inputs only for subLVDS and SLVS200.

2. For SLVS200/MIPI interface I/O placement, see the Programmable I/O Banks section.

CrossLink Automotive Family

Data Sheet

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FPGA-DS-02013-1.2 33

4.11.2. Hardened MIPI D-PHY I/Os

Table 4.11. MIPI D-PHY

Symbol

Description

Min

Typ

Max

Unit

Receiver

High Speed

VCMRX

Common-Mode Voltage HS Receive Mode

—

330

VIDTH

Differential Input High Threshold

—

VIDTL

Differential Input Low Threshold

−70

—

VIHHS

Single-ended input High Voltage

—

460

VILHS

Single-ended Input Low Voltage

−40

—

VTERM-EN

Single-ended Threshold for HS Termination Enable

—

450

ZID

Differential Input Impedance

100

125

Ω

Low Power

VIH

Logic 1 Input Voltage

880

—

VIL

Logic 0 Input Voltage, not in ULP State

—

550

VIL-ULPS

Logic 0 Input Voltage, in ULP State

—

300

VHYST

Input Hysteresis

23.0

—

Transmitter

High Speed

VCMTX

HS Transmit Static Common Mode Voltage

150

200

250

VOD

HS Transmit Differential Voltage

140

200

270

VOHHS

HS Single-ended Output High Voltage

—

360

ZOS

Single-ended Output Impedance

62.5

Ω

ΔZOS

Single-ended Output Impedance Mismatch

—

Low Power

VOH

Output High Voltage

1.1

1.2

1.3

VOL

Output Low Voltage

−50

—

ZOLP

Output Impedance in LP Mode

110

—

Ω

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Data Sheet

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34 FPGA-DS-02013-1.2

4.12. CrossLink Automotive Maximum General Purpose I/O Buffer Speed

Over recommended operating conditions.

Table 4.12. CrossLink Automotive Maximum I/O Buffer Speed

Buffer

Description

Max

Unit

Maximum Input Frequency

LVDS25

LVDS, VCCIO = 2.5 V, VID = 200 mV

600

MHz

subLVDS

subLVDS, VCCIO = 2.5 V, VID = 150 mV

600

MHz

MIPI D-PHY (HS Mode)6

MIPI D-PHY

600

MHz

MIPI D-PHY (LP Mode)

MIPI D-PHY

MHz

SLVS200

SLVS200, VCCIO=2.5 V

600

MHz

LVCMOS33/LVTTL33

LVCMOS/LVTTL, VCCIO = 3.3 V

300

MHz

LVCMOS25D

Differential LVCMOS, VCCIO = 2.5 V

300

MHz

LVCMOS25

LVCMOS, VCCIO = 2.5 V

300

MHz

LVCMOS18

LVCMOS, VCCIO = 1.8 V

155

MHz

Maximum Output Frequency

LVDS25

LVDS, VCCIO = 2.5 V

555

MHz

LVCMOS33/LVTTL33

LVCMOS/LVTTL, VCCIO = 3.3 V

300

MHz

LVTTL33D

Differential LVTTL, VCCIO = 3.3 V

300

MHz

LVCMOS33D

Differential LVCMOS, 3.3 V

300

MHz

LVCMOS25

LVCMOS, 2.5 V

215

MHz

LVCMOS25D

Differential LVCMOS, 2.5 V

215

MHz

LVCMOS18

LVCMOS, 1.8 V

155

MHz

LVCMOS12

LVCMOS, VCCIO1/2 = 1.2 V

MHz

Notes:

These maximum speeds are characterized but not tested on every device.

Maximum I/O speed for differential output standards emulated with resistors depends on the layout.

LVCMOS timing is measured with the load specified in Table 4.22.

Actual system operation may vary depending on user logic implementation.

Maximum data rate equals two times the clock rate when utilizing DDR.

6. This is the maximum MIPI D-PHY input rate on the programmable I/O banks 1 and 2. The hardened MIPI D-PHY input and

output rates are described in Hardened MIPI D-PHY Performance section. For SLVS200/MIPI interface I/O placement, see the

Programmable I/O Banks section.

7. To ensure the MIPI Rx interface is implemented optimally in the FPGA fabric with the Programmable I/Os, follow the guidelines

of assigning I/Os to the bank for the MIPI Rx inputs: When an SLVS200/MIPI Rx interface is placed in Bank 1 or 2, do not place

LVCMOS outputs on both Banks 1 and 2.

CrossLink Automotive Family

Data Sheet

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FPGA-DS-02013-1.2 35

4.13. CrossLink Automotive External Switching Characteristics

Table 4.13. CrossLink Automotive External Switching Characteristics4, 5

Parameter

Description

Conditions

–6

Unit

Min

Max

Clocks

Primary Clock

fMAX_PRI

Frequency for Primary Clock Tree

—

150

MHz

tW_PRI

Clock Pulse Width for Primary Clock

—

0.8

—

tSKEW_PRI

Primary Clock Skew Within a Clock

—

450

Edge Clock

fMAX_EDGE

Frequency for Edge Clock Tree

—

600

MHz

tW_EDGE

Clock Pulse Width for Edge Clock

—

0.783

—

tSKEW_EDGE

Edge Clock Skew Within a Bank

—

140

Generic SDR Interface1

General Purpose I/O Pin Parameters Using Clock Tree Without PLL

tCO

Clock to Output – PIO Input Register

—

5.53

tSU

Clock to Data Setup – PIO Input

—

−0.93

—

tHD

Clock to Data Hold – PIO Input

—

1.83

—

tSU_DELAY

Clock to Data Setup – PIO Input

tHD

With data input delay

for hold time = 0

1.28

—

tHD_DELAY

Clock to Data Hold – PIO Input

tHD

With data input delay

for hold time = 0

-0.34

—

General Purpose I/O Pin Parameters Using Clock Tree With PLL

tCO

Clock to Output – PIO Input Register

—

4.12

tSU

Clock to Data Setup – PIO Input

—

0.20

—

tHD

Clock to Data Hold – PIO Input

—

0.42

—

tSU_DELAY

Clock to Data Setup – PIO Input

tHD

With data input delay

for hold time = 0

1.67

—

tHD_DELAY

Clock to Data Hold – PIO Input

tHD

With data input delay

for hold time = 0

-1.03

—

Generic DDR Interfaces2

Generic DDRX8 or DDRX4 or DDRX2 I/O with Clock and Data Centered at General Purpose Pins (GDDRX8_RX/TX.ECLK.Centered

or GDDRX4_RX/TX.ECLK.Centered or GDDRX2_RX/TX.ECLK.Centered)

tSU_GDDRX2_4_8_CENTERED

Input Data Set-Up Before CLK Rising

and Falling edges

—

0.167

—

tHD_GDDRX2_4_8_CENTERED

Input Data Hold After CLK Rising

and Falling edges

—

0.167

—

tDVB_GDDRX2_4_8_CENTERED

Output Data Valid Before CLK

Output Rising and Falling edges

Data Rate = 1.2 Gb/s6

0.297

—

Other Data Rates6

−0.120

—

ns+1/2UI

tDVA_GDDRX2_4_8_CENTERED

Output Data Valid After CLK Output

Rising and Falling edges

Data Rate = 1.2 Gb/s6

0.297

—

Other Data Rates6

−0.120

—

ns+1/2UI

fMAX_GDDRX2_4_8_CENTERED

Frequency for ECLK3

GDDRX2

—

300

MHz

GDDRX4 and GDDRX8

—

600

MHz

CrossLink Automotive Family

Data Sheet

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36 FPGA-DS-02013-1.2

Table 4.13. CrossLink Automotive External Switching Characteristics (Continued)

Parameter

Description

Conditions

–6

Unit

Min

Max

Generic DDRX1 I/O with Clock and Data Centered at General Purpose Pins (GDDRX1_RX/TX.SCLK.Centered)

tSU_GDDRX1_CENTERED

Input Data Set-Up Before CLK

Rising and Falling edges

—

0.917

—

tHD_GDDRX1_CENTERED

Input Data Hold After CLK Rising

and Falling edges

—

0.917

—

tDVB_GDDRX1_CENTERED

Output Data Valid Before CLK

Output Rising and Falling edges

Data Rate =

300 Mb/s

1.217

—

ns+1/2UI

Other Data Rates

−0.450

—

ns+1/2UI

tDVA_GDDRX1_CENTERED

Output Data Valid After CLK

Output Rising and Falling edges

Data Rate =

300 Mb/s

1.217

—

ns+1/2UI

Other Data Rates

−0.450

—

ns+1/2UI

fMAX_GDDRX1_CENTERED

Frequency for PCLK3

—

150

MHz

Generic DDRX8 or DDRX4 or DDRX2 I/O with Clock and Data Aligned at General Purpose Pins (GDDRX8_RX/TX.ECLK.Aligned or

GDDRX4_RX/TX.ECLK.Aligned or GDDRX2_RX/TX.ECLK.Aligned)

tSU_GDDRX2_4_8_ALIGNED

Input Data Valid After CLK Rising

and Falling edges

Data Rate =

1.2 Gb/s6

—

0.188

Other Data Rates6

—

−0.229

ns+1/2UI

THD_GDDRX2_4_8_ALIGNED

Input Data Hold After CLK Rising

and Falling edges

Data Rate =

1.2 Gb/s6

0.646

—

Other Data Rates6

0.229

—

ns+1/2UI

tDIA_GDDRX2_4_8_ALIGNED

Output Data Invalid After CLK

Rising and Falling edges Output

—

0.120

tDIB_GDDRX2_4_8_ALIGNED

Output Data Invalid Before CLK

Output Rising and Falling edges

—

0.120

fMAX_GDDRX2_4_8_ALIGNED

Frequency for ECLK3

GDDRX2

—

300

MHz

GDDRX4 and GDDRX8

—

600

MHz

Generic DDRX1 I/O with Clock and Data Aligned at General Purpose Pins (GDDRX1_RX/TX.SCLK.Aligned)

TSU_GDDRX1_ALIGNED

Input Data Valid After CLK Rising and

Falling edges

Data Rate =

300 Mb/s

—

0.750

Other Data Rates

—

−0.917

ns+1/2UI

THD_GDDRX1_ALIGNED

Input Data Hold After CLK Rising and

Falling edges

Data Rate =

300 Mb/s

2.583

—

Other Data Rates

0.916

—

ns+1/2UI

tDIA_GDDRX1_ALIGNED

Output Data Invalid After CLK Rising

and Falling edges Output

—

0.450

tDIB_GDDRX1_ALIGNED

Output Data Invalid Before CLK

Output Rising and Falling edges

—

0.450

fMAX_GDDRX1_ALIGNED

Frequency for ECLK3

—

150

MHz

General Purpose I/O MIPI D-PHY Rx with 1:8 or 1:16 Gearing

tSU_GDDRX_MP

Input Data Set-Up Before CLK

900 Mb/s < Data Rate

≤ 1.2 Gb/s and

VID = 140 mV

0.200

—

600 Mb/s < Data Rate

≤ 900 Mb/s and

VID = 140 mV

0.150

—

Data Rate ≤ 600 Mb/s

and

VID = 70 mV

0.150

—

CrossLink Automotive Family

Data Sheet

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FPGA-DS-02013-1.2 37

Table 4.13. CrossLink Automotive External Switching Characteristics (Continued)

Generic DDRX141 Outputs with Clock and Data Aligned at Pin (GDDRX141_TX.ECLK)

Notes:

General I/O timing numbers based on LVCMOS 2.5, 0 pF load.

Generic DDRX8, DDRX71 and DDRX141 timing numbers based on LVDS I/O.

Maximum clock frequencies are tested under best case conditions. System performance may vary upon the user environment

These numbers are generated using best case PLL located.

All numbers are generated with the Lattice Diamond design software.

Maximum data rate for GDDRX2 mode is 600 Mbps.

Parameter

Description

Conditions

–6

Unit

Min

Max

tHO_GDDRX_MP

Input Data Hold After CLK

900 Mb/s < Data

Rate ≤ 1.2 Gb/s and

VID = 140 mV

0.200

—

600 Mb/s < Data

Rate ≤ 900 Mb/s

and

VID = 140 mV

0.150

—

Data Rate ≤ 600

Mb/s and

VID = 70 mV

0.150

—

fMAX_GDDRX_MP

Frequency for ECLK3

—

600

MHz

Generic DDRX71 or DDRX141 Inputs (GDDRX71_RX.ECLK or GDDRX141_RX.ECLK)

tRPBi_DVA

Input Valid Bit "i" switching from CLK

Rising Edge

("i" = 0 to 6, 0 aligns with CLK)

—

0.3

—

−0.222

ns+

(i+ 1/2)*UI

tRPBi_DVE

Input Hold Bit "i" switching from CLK

Rising Edge

("i" = 0 to 6, 0 aligns with CLK)

—

0.7

—

0.222

—

ns+

(i+ 1/2)*UI

fMAX_RX71_141

DDR71/DDR141 ECLK Frequency3

—

450

MHz

Generic DDRX71 Outputs with Clock and Data Aligned at Pin (GDDRX71_TX.ECLK)

tTPBi_DOV

Data Output Valid Bit "i" switching from

CLK Rising Edge ("i" = 0 to 6, 0 aligns with

CLK)

—

0.143

ns+i*UI

tTPBi_DOI

Data Output Invalid Bit "i" switching from

CLK Rising Edge ("i" = 0 to 6, 0 aligns with

CLK)

—

−0.143

—

ns+i*UI

tTPBi_skew_UI

Tx skew in UI

—

0.15

fMAX_TX71

DDR71 ECLK Frequency3

—

525

MHz

tTPBi_DOV

Data Output Valid Bit "i" switching from CLK

Rising Edge ("i" = 0 to 6, 0 aligns with CLK)

All Devices

—

0.125

ns+i*UI

tTPBi_DOI

Data Output Invalid Bit "i" switching from

CLK Rising Edge ("i" = 0 to 6, 0 aligns with

CLK)

All Devices

−0.125

—

ns+i*UI

tTPBi_skew_UI

TX skew in UI

All Devices

—

0.15

fMAX_TX141

DDR141 ECLK Frequency3

—

600

MHz

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Data Sheet

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38 FPGA-DS-02013-1.2

tSU/tDVBDQ

Rx CLK (in)

Rx DATA (in)

tHD/tDVADQ

tSU/tDVBDQ

tHD/tDVADQ

Figure 4.1. Receiver RX.CLK.Centered Waveforms

tSU

Rx CLK (in)

Rx DATA (in)

tHD

tSU

tHD

1/2 UI 1/2 UI

1 UI

Figure 4.2. Receiver RX.CLK.Aligned Input Waveforms

Tx CLK (out)

Tx DATA (out)

tDVB

1/2 UI 1/2 UI

tDVA

tDVB

tDVA

Figure 4.3. Transmit TX.CLK.Centered Output Waveforms

CrossLink Automotive Family

Data Sheet

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FPGA-DS-02013-1.2 39

Tx CLK (out)

Tx DATA (out)

1 UI

tDIA

tDIB

tDIA

tDIB

Figure 4.4. Transmit TX.CLK.Aligned Waveforms

Figure 4.5. DDRX71, DDRX141 Video Timing Waveforms

CrossLink Automotive Family

Data Sheet

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40 FPGA-DS-02013-1.2

4.14. sysCLOCK PLL Timing

Over recommended operating conditions.

Table 4.14. sysCLOCK PLL Timing

Parameter

Descriptions

Conditions

Min

Max

Unit

fIN

Input Clock Frequency (CLKI, CLKFB)

—

400

MHz

fPD

Phase Detector Input Clock Frequency

—

400

MHz

fOUT

Output Clock Frequency (CLKOP, CLKOS)

—

4.6875

600

MHz

fVCO

PLL VCO Frequency

—

600

1200

MHz

AC Characteristics

tDT

Output Clock Duty Cycle

—

45.0

55.5

tPH

Output Phase Accuracy

—

−5

tOPJIT1

Output Clock Period Jitter3

fOUT ≥ 100 MHz

—

100

ps p-p

fOUT < 100 MHz

—

0.025

UIPP

Output Clock Cycle-to-Cycle Jitter3

fOUT ≥ 100 MHz

—

200

ps p-p

fOUT < 100 MHz

—

0.05

UIPP

Output Clock Phase Jitter

fPD > 100 MHz

—

200

ps p-p

fPD < 100 MHz

—

0.05

UIPP

tSPO

Static Phase Offset

Divider ratio = integer

—

400

ps p-p

tLOCK2

PLL Lock-in Time

—

tUNLOCK

PLL Unlock Time

—

tIPJIT

Input Clock Period Jitter

fPD ≥ 20 MHz

—

500

ps p-p

fPD < 20 MHz

—

0.02

UIPP

tHI

Input Clock High Time

90% to 90%

0.5

—

tLO

Input Clock Low Time

10% to 10%

0.5

—

Notes:

Jitter sample is taken over 10,000 samples for Periodic jitter, and 2,000 samples for Cycle-to-Cycle jitter of the primary PLL

output with

clean reference clock with no additional I/O toggling.

Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment.

Period jitter and cycle-to-cycle jitter numbers are guaranteed for fPD ≥ 10 MHz. For fPD < 10 MHz, the jitter numbers may not be

met in certain conditions.

CrossLink Automotive Family

Data Sheet

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FPGA-DS-02013-1.2 41

4.15. Hardened MIPI D-PHY Performance

Table 4.15. 1500 Mb/s MIPI_DPHY_X8_RX/TX Timing Table (1500 Mb/s > MIPI D-PHY Data Rate > 1200 Mb/s)

Parameter

Description

Min

Max

Unit

tSU_MIPIX8

Input Data Setup before CLK

0.200

—

tHO_MIPIX8

Input Data Hold after CLK

0.200

—

tDVB_MIPIX8

Output Data Valid before CLK Output

0.300

—

tDVA_MIPIX8

Output Data Valid after CLK Output

0.300

—

Table 4.16. 1200 Mb/s MIPI_DPHY_X4_RX/TX Timing Table (1200 Mb/s > MIPI D-PHY Data Rate > 1000 Mb/s)

Parameter

Description

Min

Max

Unit

tSU_MIPIX4

Input Data Setup before CLK

0.200

—

tHO_MIPIX4

Input Data Hold after CLK

0.200

—

tDVB_MIPIX4

Output Data Valid before CLK Output

0.300

—

tDVA_MIPIX4

Output Data Valid after CLK Output

0.300

—

Table 4.17. 1000 Mb/s MIPI_DPHY_X4_RX/TX Timing Table (1000 Mb/s > MIPI D-PHY Data Rate > 10 Mb/s)

Parameter

Description

Min

Max

Unit

tSU_MIPIX4

Input Data Setup before CLK

0.150

—

tHO_MIPIX4

Input Data Hold after CLK

0.150

—

tDVB_MIPIX4

Output Data Valid before CLK Output

0.350

—

tDVA_MIPIX4

Output Data Valid after CLK Output

0.350

—

4.16. Internal Oscillators (HFOSC, LFOSC)

Table 4.18. Internal Oscillators

Parameter

Parameter Description

Min

Typ

Max

Unit

fCLKHF

HFOSC CLKK Clock Frequency

43.2

52.8

MHz

fCLKLF

LFOSC CLKK Clock Frequency

kHz

DCHCLKHF

HFOSC Duty Cycle (Clock High Period)

DCHCLKLF

LFOSC Duty Cycle (Clock High Period)

4.17. User I2C1

Table 4.19. User I2C1

Symbol

Parameter

STD Mode

FAST Mode

FAST Mode Plus2

Units

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

fscl

SCL Clock Frequency

—

100

—

400

—

10002

kHz

TDELAY

Optional delay

through delay block

—

Notes:

Refer to the I2C Specification for timing requirements.

Fast Mode Plus maximum speed may be achieved by using external pull up resistor on I2C bus. Internal pull up may not be

sufficient to support the maximum speed.

CrossLink Automotive Family

Data Sheet

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42 FPGA-DS-02013-1.2

4.18. CrossLink Automotive sysCONFIG Port Timing Specifications

Over recommended operating conditions.

Table 4.20. CrossLink Automotive sysCONFIG Port Timing Specifications

Symbol

Parameter

Min

Max

Unit

All Configuration Mode

tPRGM

Minimum CRESETB LOW pulse width required to

restart configuration (from falling edge to rising edge)

145

—

Slave SPI1

fCCLK

SPI_SCK Input Clock Frequency

—

110

MHz

tSTSU

MOSI Setup Time

0.5

—

tSTH

MOSI Hold Time

2.0

—

tSTCO

SPI_SCK Falling Edge to Valid MISO Output

—

13.3

tSCS

Chip Select HIGH Time

—

tSCSS

Chip Select Setup Time

0.5

—

tSCSH

Chip Select Hold Time

0.5

—

Master SPI

fCCLK

MCK Output Clock Frequency

—

52.8

MHz

I2C2

fMAX

Maximum SCL Clock Frequency (Fast-Mode Plus)

—

MHz

Notes:

1. Refer to CrossLink Programming and Configuration Usage Guide (FPGA-TN-02014), for timing requirements to enable CrossLink

Automotive SSPI Mode.

2. Refer to the I2C specification for timing requirements when configuring with I2C port.

4.19. SRAM Configuration Time from NVCM

Over recommended operating conditions.

Table 4.21. SRAM Configuration Time from NVCM

Symbol

Parameter

Typ

Unit

TCONFIGURATION

POR/CRESET_B to Device I/O Active*

*Note: Before and during configuration, the I/Os are held in tristate with weak internal pullups enabled. I/Os are released to user

functionality when the device has finished configuration.

CrossLink Automotive Family

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02013-1.2 43

4.20. Switching Test Conditions

Figure 4.6 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,

voltage, and other test conditions are listed in Table 4.22.

DUT

CL*

*CL Includes Test Fixture and Probe Capacitance

Test Point

Figure 4.6. Output Test Load, LVTTL and LVCMOS Standards

Table 4.22. Test Fixture Required Components, Non-Terminated Interfaces

Test Condition

Timing Ref.

LVTTL and other LVCMOS settings (L ≥ H, H ≥ L)

∞

0 pF

LVCMOS 3.3 = 1.5 V

—

LVCMOS 2.5 = VCCIO/2

—

LVCMOS 1.8 = VCCIO/2

—

LVCMOS 1.2 = VCCIO/2

—

LVCMOS 2.5 I/O (Z ≥ H)

∞

1 MΩ

0 pF

VCCIO/2

—

LVCMOS 2.5 I/O (Z ≥ L)

1 MΩ

∞

0 pF

VCCIO/2

VCCIO

LVCMOS 2.5 I/O (H ≥ Z)

∞

100

0 pF

VOH – 0.10

—

LVCMOS 2.5 I/O (L ≥ Z)

100

∞

0 pF

VOL + 0.10

VCCIO

Note: Output test conditions for all other interfaces are determined by the respective standards.

CrossLink Automotive Family

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

44 FPGA-DS-02013-1.2

5. Pinout Information

The pinout tables below correspond to CrossLink LIF-MD6000 Pinout Version 1.4. GND pins are referenced as VSS in

Lattice Diamond Software.

5.1. ctfBGA80/cktBGA80 Pinout

Pin Number

Pin Function

Bank

Dual Function

Differential

DPHY1_DN2

DPHY1

—

Comp_OF_DPHY1_DP2

DPHY1_DN0

DPHY1

—

Comp_OF_DPHY1_DP0

DPHY1_CKN

DPHY1

—

Comp_OF_DPHY1_CKP

DPHY1_DN1

DPHY1

—

Comp_OF_DPHY1_DP1

DPHY1_DN3

DPHY1

—

Comp_OF_DPHY1_DP3

DPHY0_DN2

DPHY0

—

Comp_OF_DPHY0_DP2

DPHY0_DN0

DPHY0

—

Comp_OF_DPHY0_DP0

DPHY0_CKN

DPHY0

—

Comp_OF_DPHY0_CKP

DPHY0_DN1

DPHY0

—

Comp_OF_DPHY0_DP1

A10

DPHY0_DN3

DPHY0

—

Comp_OF_DPHY0_DP3

DPHY1_DP2

DPHY1

—

True_OF_DPHY1_DN2

DPHY1_DP0

DPHY1

—

True_OF_DPHY1_DN0

DPHY1_CKP

DPHY1

—

True_OF_DPHY1_CKN

DPHY1_DP1

DPHY1

—

True_OF_DPHY1_DN1

DPHY1_DP3

DPHY1

—

True_OF_DPHY1_DN3

DPHY0_DP2

DPHY0

—

True_OF_DPHY0_DN2

DPHY0_DP0

DPHY0

—

True_OF_DPHY0_DN0

DPHY0_CKP

DPHY0

—

True_OF_DPHY0_CKN

DPHY0_DP1

DPHY0

—

True_OF_DPHY0_DN1

B10

DPHY0_DP3

DPHY0

—

True_OF_DPHY0_DN3

GND

—

GNDA_DPHY1

DPHY1

—

GNDA_DPHY0

DPHY0

—

C10

GND

—

PB48

PCLKT0_1/USER_SCL

—

VCCPLL_DPHY1

DPHY1

—

VCCA_DPHY1

DPHY1

—

VCCAUX

—

GNDPLL_DPHYx

GND

—

VCCPLL_DPHY0

DPHY0

—

PB16A

PCLKT2_0

True_OF_PB16B

D10

PB16B

PCLKC2_0

Comp_OF_PB16A

PB34A

GR_PCLK1_0

True_OF_PB34B

PB34B

—

Comp_OF_PB34A

VCC

—

GND

—

VCC

—

VCCA_DPHY0

DPHY0

—

PB12A

GPLLT2_0

True_OF_PB12B

E10

PB12B

GPLLC2_0

Comp_OF_PB12A

PB38A

—

True_OF_PB38B

PB38B

—

Comp_OF_PB38A

CrossLink Automotive Family

Data Sheet

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FPGA-DS-02013-1.2 45

Pin Number

Pin Function

Bank

Dual Function

Differential

VCCIO0

—

VCCIO1

—

VCCIO2

—

VCCIO2

—

PB6A

GR_PCLK2_0

True_OF_PB6B

F10

PB6B

—

Comp_OF_PB6A

PB50

MOSI

—

GND

—

VCCIO1

—

GND

—

VCCGPLL

—

GNDGPLL

GND

—

PB2A

—

True_OF_PB2B

G10

PB2B

—

Comp_OF_PB2A

PB52

SPI_SS/CSN/SCL

—

CRESET_B

—

PB2D

MIPI_CLKC2_0

Comp_OF_PB2C

H10

PB2C

MIPI_CLKT2_0

True_OF_PB2D

PB53

SPI_SCK/MCK/SDA

—

PB49

PMU_WKUPN/CDONE

—

PB43D

—

Comp_OF_PB43C

PB38D

—

Comp_OF_PB38C

PB34D

MIPI_CLKC1_0

Comp_OF_PB34C

PB29D

PCLKC1_1

Comp_OF_PB29C

PB29A

PCLKT1_0

True_OF_PB29B

PB16D

PCLKC2_1

Comp_OF_PB16C

PB6D

—

Comp_OF_PB6C

J10

PB6C

—

True_OF_PB6D

PB51

MISO

—

PB47

PCLKT0_0/USER_SDA

—

PB43C

—

True_OF_PB43D

PB38C

—

True_OF_PB38D

PB34C

MIPI_CLKT1_0

True_OF_PB34D

PB29C

PCLKT1_1

True_OF_PB29D

PB29B

PCLKC1_0

Comp_OF_PB29A

PB16C

PCLKT2_1

True_OF_PB16D

PB12D

—

Comp_OF_PB12C

K10

PB12C

—

True_OF_PB12D

CrossLink Automotive Family

Data Sheet

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46 FPGA-DS-02013-1.2

5.2. Dual Function Pin Descriptions

The following table describes the dual functions available to certain pins on the CrossLink Automotive device. These

pins may alternatively be used as general purpose I/O when the described dual function is not enabled.

Signal Name

I/O

Description

General Purpose

USER_SCL

I/O

User Slave I2C0 clock input and Master I2C0 clock output. Enables PMU

wake-up via I2C0.

USER_SDA

I/O

User Slave I2C0 data input and Master I2C0 data output. Enables PMU

wakeup via I2C0.

PMU_WKUPN

—

This pin wakes the PMU from sleep mode when toggled low.

Clock Functions

GPLL2_0[T, C]_IN

General Purpose PLL (GPLL) input pads: T = true and C = complement. These

pins can be used to input a reference clock directly to the General Purpose

PLL. These pins do not provide direct access to the primary clock network.

GR_PCLK[Bank]0

These pins provide a short General Routing path to the primary clock

network. Refer to CrossLink sysCLOCK PLL/DLL Design and Usage Guide

(FPGA-TN-02015) for details.

PCLK[T/C][Bank]_[num]

I/O

General Purpose Primary CLK pads: [T/C] = True/Complement, [Bank] = (0, 1

and 2). These pins provide direct access to the primary and edge clock

networks.

MIPI_CLK[T/C][Bank]_0

I/O

MIPI D-PHY Reference CLK pads: [T/C] = True/Complement, [Bank] = (0, 1

and 2). These pins can be used to input a reference clock directly to the

D-PHY PLLs. These pins do not provide direct access to the primary clock

network.

Configuration

CDONE

I/O

Open Drain pin. Indicates that the configuration sequence is complete, and

the startup sequence is in progress. Holding CDONE delays configuration.

SPI_SCK

Input Configuration Clock for configuring CrossLink Automotive in Slave SPI

mode (SSPI).

MCK

Output Configuration Clock for configuring CrossLink Automotive in Master

SPI mode (MSPI).

SPI_SS

Input Chip Select for configuring CrossLink Automotive in Slave SPI mode

(SSPI).

CSN

Output Chip Select for configuring CrossLink Automotive in Master SPI mode

(MSPI).

MOSI

I/O

Data Output when configuring CrossLink Automotive in Master SPI mode

(MSPI), data input when configuring CrossLink Automotive in Slave SPI mode

(SSPI).

MISO

I/O

Data Input when configuring CrossLink Automotive in Master SPI mode

(MSPI), data output when configuring CrossLink Automotive in Slave SPI

mode (SSPI).

SCL

I/O

Slave I2C clock I/O when configuring CrossLink Automotive in I2C mode.

SDA

I/O

Slave I2C data I/O when configuring CrossLink Automotive in I2C mode.

CrossLink Automotive Family

Data Sheet

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FPGA-DS-02013-1.2 47

5.3. Dedicated Function Pin Descriptions

Signal Name

I/O

Description

Configuration

CRESET_B

Configuration Reset, active LOW.

MIPI D-PHY

DPHY[num]_CK[P/N]

I/O

MIPI D-PHY Clock [num] = D-PHY 0 or 1, P = Positive, N = Negative.

DPHY[num]_D[P/N][lane]

I/O

MIPI D-PHY Data [num] = D-PHY 0 or 1, P = Positive, N = Negative,

Lane = data lane in the D-PHY block 0, 1, 2 or 3.

5.4. Pin Information Summary

Pin Type

CrossLink Automotive

ctfBGA80

ckfBGA80

Total General Purpose I/O

VCC/VCCIOx/VCCAUX/VCCGPLL

GND

D-PHY Clock/Data

D-PHY VCC

D-PHY GND

CRESETB

Total Balls

General Purpose I/O per Bank

Bank 0

Bank 1

Bank 2

Total General Purpose Single Ended I/O

Differential I/O pairs per Bank

Bank 0

Bank 1

Bank 2

Total General Purpose Differential I/O pairs

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48 FPGA-DS-02013-1.2

6. CrossLink Automotive Part Number Description

Logic Capacity

6000 = 6000 LUTs

Speed

Package

JMG80 = 80-ball ctfBGA

KMG80 = 80-ball ckfBGA

Device Family

CrossLink Automotive FPGA

LIA-MD XXXX-X XXXXX X

Grade

E = Automotive

6 = Fastest

6.1. Ordering Part Numbers

Automotive

Part Number

Speed

Package

Pins

Temp. Grade

LUTs (K)

LIA-MD6000-6JMG80E

–6

Lead free ctfBGA

Automotive

5.9

LIA-MD6000-6KMG80E

–6

Lead free ckfBGA

Automotive

5.9

CrossLink Automotive Family

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02013-1.2 49

References

For more information, refer to the following technical notes:

 CrossLink High-Speed I/O Interface (FPGA-TN-02012)

 CrossLink Hardware Checklist (FPGA-TN-02013)

 CrossLink Programming and Configuration Usage Guide (FPGA-TN-02014)

 CrossLink sysCLOCK PLL/DLL Design and Usage Guide (FPGA-TN-02015)

 CrossLink sysI/O Usage Guide (FPGA-TN-02016)

 CrossLink Memory Usage Guide (FPGA-TN-02017)

 Power Management and Calculation for CrossLink Devices (FPGA-TN-02018)

 CrossLink I2C Hardened IP Usage Guide (FPGA-TN-02019)

 Advanced CrossLink I2C Hardened IP Reference Guide (FPGA-TN-02020)

For package information, refer to the following technical notes:

 PCB Layout Recommendations for BGA Packages (TN1074)

 Solder Reflow Guide for Surface Mount Devices (FPGA-TN-12041, previously TN1076)

 Wafer-Level Chip-Scale Package Guide (TN1242)

 Thermal Management

 Package Diagrams

For further information on interface standards refer to the following websites:

 JEDEC Standards (LVTTL, LVCMOS): www.jedec.org

 MIPI Standards (D-PHY): www.mipi.org

Technical Support

For assistance, submit a technical support case at www.latticesemi.com/techsupport.

CrossLink Automotive Family

Data Sheet

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50 FPGA-DS-02013-1.2

Revision History

Date

Version

Change Summary

March 2018

1.2

 Added entries to the Acronyms in This Document section.

 In Features section:

 Changed footprint to 80-ball ctfBGA (42 mm2)

 Updated Applications examples

 Removed Application Examples section and its associated references throughout the

document

 Updated packages in Table 2.1.

 Updated the Architecture Overview section (general update)

 Revised introductory paragraph.

 Reordered the list of features supported by the hard D-PHY quads

 Added Figure 3.3 to Figure 3.6 to the MIPI D-PHY Blocks section

 Updated the Programmable I/O Banks section

 Added Bank 0 list of features

 Added Table 3.1, Table 3.2, Table 3.3 and Table 3.4

 Updated Programmable FPGA Fabric section

 Removed FPGA Fabric Overview header

 Added PFU Blocks section

 Added Slice section

 Moved Clocking Overview as a new Clocking Structure (heading 2) section and

added contents

 Moved Embedded Block RAM Overview as a new (heading 2) section and added

contents

 Removed System Resources section

 Moved Power Management Unit section under Embedded Block RAM Overview

 Removed Device Configuration section

 Moved User I2C IP as a new (heading 2) section

 Added Programming and Configuration section

 Revised footnotes in Table 4.6

 Corrected alignment of arrows in Figure 4.4

 Revised Min and Max values in Table 4.15, Table 4.16, and Table 4.17

 Revised footnote in Table 4.20

 Added web link in Pinout Information section

 Placed captions to pinout table

December 2017

1.1

 Changed document status from preliminary to final

 Added items to Acronyms in This Document

 Updated the Features section

 Added 80-ball ckfBGA (49 mm2) under Small footprint

 Removed LVDS under Programmable CMOS I/O

 Updated note in Table 2.1, Table 2.2, Table 2.3, Table 2.4, Table 2.5, Table 2.6, Table 2.7,

Table 2.8, and Table 2.9

 Moved Product Feature Summary from section to 2 to section 3. Added 80 ckfBGA (7.0 x

7.0 mm2, 1 mm) in Table 3.1. CrossLink Automotive Feature Summary

 Updated System Resources section

 Removed LVCMOS12 (Outputs Only) from CMOS GPIO (Bank 0) section

 Added information in Device Configuration section

 Updated Table 5.1. Absolute Maximum Ratings1, 2, 3

 Changed symbol from VCCPLL to VCCGPLL

CrossLink Automotive Family

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02013-1.2 51

Date

Version

Change Summary

 Removed VCC_DPHY, VCCA_DPHY, and VCCMU_DPHY symbol; added VCCA_DPHYx

 Updated Table 5.2. Recommended Operating Conditions1, 2

 Revised symbols to VCCGPLL, VCCAUX, and VCCIO0

 Added parameter to VCCAUX

 Added row of VCCIO1/2 symbol

 Removed row of VCC_DPHYx and VCCMU_DPHY1 symbol

 Revised note

 Updated Power-On-Reset Voltage Levels section. Added VPORDN to Table 5.4. Power-On-

Reset Voltage Levels1, 3, 4 and revised footnotes

 Updated LIFMD Product Family Qualification Summary link in ESD Performance section

 Removed VCCIO = 1.2 V between 0 ≤ VIN ≤ 0.65 * VCCIO condition from Table 5.5. DC

Electrical Characteristics

 Updated Table 5.6. CrossLink Automotive Supply Current (general update)

 Removed Preliminary MIPI D-PHY Supply Current section.

 Added notes to Table 5.8. sysI/O Recommended Operating Conditions1

 Added note to Table 5.9. sysI/O Single-Ended DC Electrical Characteristics

 Added notes to Table 5.10. LVDS/subLVDS1/SLVS2001, 2

 Updated Table 5.12. CrossLink Automotive Maximum I/O Buffer Speed (general update)

 Updated Table 5.13. CrossLink Automotive External Switching Characteristics4, 5 (general

update)

 Updated Figure 5.4. Transmit TX.CLK.Aligned Waveforms

 Updated Table 5.20. CrossLink Automotive sysCONFIG Port Timing Specifications (general

update)

 Changed TREFRESH to TCONFIGURATION in Table 5.21. SRAM Configuration Time from NVCM

 Updated Pinout Information section

 Updated section introduction

 Updated section to ctfBGA80/cktBGA80 Pinout

 Updated Pin Information Summary section (general update)

 Added KMG80 package to CrossLink Automotive Part Number Description section

 Modified heading and added LIA-MD6000-6KMG80E part number to Ordering Part

Numbers section

 Updated reference to the Solder Reflow Guide for Surface Mount Devices document in

References section

September 2016

1.0

First preliminary release.

7th Floor, 111 SW 5th Avenue

Portland, OR 97204, USA

T 503.268.8000