CD4514BM - National Semiconductor

TL/F/5994

CD4514BM/CD4514BC, CD4515BM/CD4515BC 4-Bit Latched/4-to-16 Line Decoders

February 1988

CD4514BM/CD4514BC, CD4515BM/CD4515BC

4-Bit Latched/4-to-16 Line Decoders

General Description

The CD4514B and CD4515B are 4-to-16 line decoders with

latched inputs implemented with complementary MOS

(CMOS) circuits constructed with N- and P-channel en-

hancement mode transistors. These circuits are primarily

used in decoding applications where low power dissipation

and/or high noise immunity is required.

The CD4514B (output active high option) presents a logical

‘‘1’’ at the selected output, whereas the CD4515B presents

a logical ‘‘0’’ at the selected output. The input latches are

R–S type flip-flops, which hold the last input data presented

prior to the strobe transition from ‘‘1’’ to ‘‘0’’. This input data

is decoded and the corresponding output is activated. An

output inhibit line is also available.

Features

YWide supply voltage range 3.0V to 15V

YHigh noise immunity 0.45 VDD (typ.)

YLow power TTL fan out of 2

compatibility driving 74L

YLow quiescent power dissipation 0.025 mW/package

@5.0 VDC

YSingle supply operation

YInput impedance e1012Xtypically

YPlug-in replacement for MC14514, MC14515

Logic and Connection Diagrams

TL/F/5994–1

Dual-In-Line Package

TL/F/5994– 2

Top View

Order Number CD4514B or CD4515B

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Notes 1 and 2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

DC Supply Voltage (VDD)b0.5V to a18V

Input Voltage (VIN)b0.5V to VDD a0.5V

Storage Temperature Range (TS)b65§Ctoa

150§C

Power Dissipation (PD)

Dual-In-Line 700 mW

Small Outline 500 mW

Lead Temperature (TL)

(Soldering, 10 seconds) 260§C

Recommended Operating

Conditions (Note 2)

DC Supply Voltage (VDD) 3Vto15V

Input Voltage (VIN) 0VtoV

Operating Temperature Range (TA)

CD4514BM, CD4515BM b55§Ctoa

125§C

CD4514BC, CD4515BC b40§Ctoa

85§C

DC Electrical Characteristics CD4514BM, CD4515BM (Note 2)

Symbol Parameter Conditions b55§Ca25§Ca125§CUnits

Min Max Min Typ Max Min Max

IDD Quiescent Device VDD e5V, VIN eVDD or VSS 5 0.005 5 150 mA

Current VDD e10V, VIN eVDD or VSS 10 0.010 10 300 mA

VDD e15V, VIN eVDD or VSS 20 0.015 20 600 mA

VOL Low Level VIH eVDD,

k1mA

Output Voltage VDD e5V, VIL e0V 0.05 0 0.05 0.05 V

VDD e10V 0.05 0 0.05 0.05 V

VDD e15V 0.05 0 0.05 0.05 V

VOH High Level VIH eVDD,

k1mA

Output Voltage VDD e5V, VIL e0V 4.95 4.95 5 4.95 V

VDD e10V 9.95 9.95 10 9.95 V

VDD e15V 14.95 14.95 15 14.95 V

VIL Low Level VOe0.5V or 4.5V

Input Voltage VDD e5V,

k1mA 1.5 2.25 1.5 1.5 V

VDD e10V, VOe1.0V or 9.0V 3.0 4.50 3.0 3.0 V

VDD e15V, VOe1.5V or 13.5V 4.0 6.75 4.0 4.0 V

VIH High Level VOe0.5V or 4.5V

Input Voltage VDD e5V,

k1mA 3.5 3.5 2.75 3.5 V

VDD e10V, VOe1.0V or 9.0V 7.0 7.0 5.50 7.0 V

VDD e15V, VOe1.5V or 13.5V 11.0 11.0 8.25 11.0 V

IOL Low Level Output VDD e5V, VOe0.4V 0.64 0.51 0.88 0.36 mA

Current (Note 3) VDD e10V, VOe0.5V 1.6 1.3 2.25 0.90 mA

VDD e15V, VOe1.5V 4.2 3.4 8.80 2.40 mA

IOH High Level Output VDD e5V, VOe4.6V b0.64 b0.51 b0.88 b0.36 mA

Current (Note 3) VDD e10V, VOe9.5V b1.6 b1.3 b2.25 b0.90 mA

VDD e15V, VOe13.5V b4.2 b3.4 b8.80 b2.40 mA

IIN Input Current VDD e15V, VIN e0V b0.1 b10b5b0.1 b1.0 mA

VDD e15V, VIN e15V 0.1 10b50.1 1.0 mA

DC Electrical Characteristics CD4514BC, CD4515BC (Note 2)

Symbol Parameter Conditions b40§Ca25§Ca85§CUnits

Min Max Min Typ Max Min Max

IDD Quiescent Device VDD e5V, VIN eVDD or VSS 20 0.005 20 150 mA

Current VDD e10V, VIN eVDD or VSS 40 0.010 40 300 mA

VDD e15V, VIN eVDD or VSS 80 0.015 80 600 mA

VOL Low Level VIL e0V, VIH eVDD,

Output Voltage

k1mA

VDD e5V 0.05 0 0.05 0.05 V

VDD e10V 0.05 0 0.05 0.05 V

VDD e15V 0.05 0 0.05 0.05 V

VOH High Level VIL e0V, VIH eVDD,

Output Voltage

k1mA

VDD e5V 4.95 4.95 5.0 4.95 V

VDD e10V 9.95 9.95 10.0 9.95 V

VDD e15V 14.95 14.95 15.0 14.95 V

DC Electrical Characteristics CD4514BC, CD4515BC (Note 2) (Continued)

Symbol Parameter Conditions b40§Ca25§Ca85§CUnits

Min Max Min Typ Max Min Max

VIL Low Level

k1mA

Input Voltage VDD e5V, VOe0.5V or 4.5V 1.5 2.25 1.5 1.5 V

VDD e10V, VOe1.0V or 9.0V 3.0 4.50 3.0 3.0 V

VDD e15V, VOe1.5V or 13.5V 4.0 6.75 4.0 4.0 V

VIH High Level

k1mA

Input Voltage VDD e5V, VOe0.5V or 4.5V 3.5 3.5 2.75 3.5 V

VDD e10V, VOe1.0V or 9.0V 7.0 7.0 5.50 7.0 V

VDD e15V, VOe1.5V or 13.5V 11.0 11.0 8.25 11.0 V

IOL Low Level Output VDD e5V, VOe0.4V 0.52 0.44 0.88 0.36 mA

Current (Note 3) VDD e10V, VOe0.5V 1.3 1.1 2.25 0.90 mA

VDD e15V, VOe1.5V 3.6 3.0 8.8 2.4 mA

IOH High Level Output VDD e5V, VOe4.6V b0.52 b0.44 b0.88 b0.36 mA

Current (Note 3) VDD e10V, VOe9.5V b1.3 b1.1 b2.25 b0.90 mA

VDD e15V, VOe13.5V b3.6 b3.0 b8.8 b2.4 mA

IIN Input Current VDD e15V, VIN e0V b0.3 b10b5b0.3 b1.0 mA

VDD e15V, VIN e15V 0.3 10b50.3 1.0 mA

AC Electrical Characteristics*

All types CLe50 pF, TAe25§C, tretfe20 ns unless otherwise specified

Symbol Parameter Conditions Min Typ Max Units

tTHL,t

TLH Transition Times VDD e5V 100 200 ns

VDD e10V 50 100 ns

VDD e15V 40 80 ns

tPLH,t

PHL Propagation Delay Times VDD e5V 550 1100 ns

VDD e10V 225 450 ns

VDD e15V 150 300 ns

tPLH,t

PHL Inhibit Propagation VDD e5V 400 800 ns

Delay Times VDD e10V 150 300 ns

VDD e15V 100 200 ns

tSU Setup Time VDD e5V 125 250 ns

VDD e10V 50 100 ns

VDD e15V 38 75 ns

tWH Strobe Pulse Width VDD e5V 175 350 ns

VDD e10V 50 100 ns

VDD e15V 38 75 ns

CPD Power Dissipation Capacitance Per Package (Note 5) 150 pF

CIN Input Capacitance Any Input (Note 4) 5 7.5 pF

*AC Parameters are guaranteed by DC correlated testing.

Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’

they are not meant to imply that the devices should be operated at these limits. The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteris-

tics’’ provide conditions for actual device operation.

Note 2: VSS e0V unless otherwise specified.

Note 3: IOH and IOL are tested one output at a time.

Note 4: Capacitance is guaranteed by periodic testing.

Note 5: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see 54C and 74C Family Characteristics application

note, AN-90.

Truth Table

Decode Truth Table (Strobe e1)

Data Inputs Selected Output

Inhibit

DCBA

CD4514 eLogic ‘‘1’’

CD4515 eLogic ‘‘0’’

00000 S0

00001 S1

00010 S2

00011 S3

00100 S4

00101 S5

00110 S6

00111 S7

01000 S8

01001 S9

0 1 0 1 0 S10

0 1 0 1 1 S11

0 1 1 0 0 S12

0 1 1 0 1 S13

0 1 1 1 0 S14

0 1 1 1 1 S15

1 X X X X All Outputs e0, CD4514

All Outputs e1, CD4515

XeDon’t Care

AC Test Circuit and Switching Time Waveforms

TL/F/5994– 3

TL/F/5994– 4

FIGURE 1

Applications

Two CD4512 8-channel data selectors are used here with

the CD4514B 4-bit latch/decoder to effect a complex data

routing system. A total of 16 inputs from data registers are

selected and transferred via a TRI-STATEÉdata bus to a

data distributor for rearrangement and entry into 16 output

registers. In this way sequential data can be re-routed or

intermixed according to patterns determined by data select

and distribution inputs.

Data is placed into the routing scheme via the 8 inputs on

both CD4512 data selectors. One register is assigned to

each input. The signals on A0, A1 and A2 choose 1-of-8

inputs for transfer out to the TRI-STATE data bus. A fourth

signal, labelled Dis, disables one of the CD4512 selectors,

assuring transfer of data from only one register.

In addition to a choice of input registers, 1–16, the rate of

transfer of the sequential information can also be varied.

That is, if the CD4512 were addressed at a rate that is

8 times faster than the shift frequency of the input registers,

the most significant bit (MSB) from each register could be

selected for transfer to the data bus. Therefore, all of the

most significant bits from all of the registers can be trans-

ferred to the data bus before the next most significant bit is

presented for transfer by the input registers.

Information from the TRI-STATE bus is redistributed by the

CD4514B 4-bit latch/decoder. Using the 4-bit address,

INA–IND, the information on the inhibit line can be trans-

ferred to the addressed output line to the desired output

registers, A–P. This distribution of data bits to the output

registers can be made in many complex patterns. For exam-

ple, all of the most significant bits from the input registers

can be routed into output register A, all of the next most

significant bits into register B, etc. In this way horizontal,

vertical, or other methods of data slicing can be implement-

ed.

TL/F/5994– 5

CD4514BM/CD4514BC, CD4515BM/CD4515BC 4-Bit Latched/4-to-16 Line Decoders

Physical Dimensions inches (millimeters)

Ceramic Dual-In-Line Package (J)

Order Number CD4514BMJ, CD4514BCJ, CD4515BMJ or CD4515BCJ

NS Package Number J24A

Molded Dual-In-Line Package (N)

Order Number CD4514BMN, CD4514BCN, CD4515BMN or CD4515BCN

NS Package Number N24A

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failure to perform, when properly used in accordance support device or system, or to affect its safety or

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