SLCS119B − DECEMBER 1986 − REVISED DECEMBER 2006
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DVery Low Power . . . 200 µW Typ at 5 V
DFast Response Time . . . 2.5 µs Typ With
5-mV Overdrive
DSingle Supply Operation:
TLC139M ...4 V to 16 V
TLC339M ...4 V to 16 V
TLC339C ...3 V to 16 V
TLC339I ...3 V to 16 V
DHigh Input Impedance ...10
12 Ω Typ
DInput Offset Voltage Change at Worst Case
Input at Condition Typically 0.23 µV/Month
Including the First 30 Days
DOn-Chip ESD Protection
description
The TLC139/TLC339 consists of four
independent differential-voltage comparators
designed to operate from a single supply. It is
functionally similar to the LM139/LM339 family but
uses 1/20th the power for similar response times.
The open-drain MOS output stage interfaces to a
variety of leads and supplies, as well as wired
logic functions. For a similar device with a
push-pull output configuration, see the TLC3704
data sheet.
The Texas Instruments LinCMOS process offers
superior analog performance to standard CMOS
processes. Along with the standard CMOS
advantages of low power without sacrificing
speed, high input impedance, and low bias
currents, the LinCMOS process offers
extremely stable input offset voltages, even with
differential input stresses of several volts. This
characteristic makes it possible to build reliable
CMOS comparators.
AVAILABLE OPTIONS
VIO
PACKAGE
TA
V
IO
max AT
25°C
SMALL
OUTLINE
(D)
CHIP CARRIER
(FK) CERAMIC DIP
(J) PLASTIC DIP
(P) TSSOP
(PW)
0°C to 70°C5 mV TLC339CD — — TLC339CN TLC339CPW
−40°C to 85°C5 mV TLC339ID — — TLC339IN TLC339IPW
−40°C to 125°C5 mV TLC339QD — — TLC339QN —
−55°C to 125°C5 mV TLC339MD TLC139MFK TLC139MJ TLC339MN —
The D and PW packages are available taped and reeled. Add the suffix R to the device type (e.g., TLC339CDR or TLC339CPWR).
Copyright 1991−2004, Texas Instruments Incorporated
! "#$ %!&
% "! "! '! ! !( !
%% )*& % "!+ %! !!$* $%!
!+ $$ "!!&
LinCMOS is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
2OUT
VDD
2IN−
2IN+
1IN−
1IN+
3OUT
4OUT
GND
4IN+
4IN−
3IN+
3IN−
D, J, N, OR PW PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
GND
NC
4IN+
NC
4IN−
VDD
NC
2IN−
NC
2IN+
FK PACKAGE
(TOP VIEW)
2OUT
1OUT
NC
3IN + 3OUT
1IN −
1IN +
NC
NC − No internal connection
3IN − 3OUT
symbol (each comparator)
IN+
IN− OUT
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description (continued)
The TLC139M and TLC339M are characterized for operation over the full military temperature range of −55°C
to 125°C. The TLC339C is characterized for operation over the commercial temperature range of 0°C to 70°C.
The TLC339I is characterized for operation over the industrial temperature range of −40°C to 85°C. The
TLC339Q is characterized for operation over the extended industrial temperature range of −40°C to 125°C.
output schematic
OPEN-DRAIN CMOS OUTPUT
Output
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VDD (see Note 1) −0.3 V to 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VID (see Note 2) ±18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI −0.3 V to VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO −0.3 V to VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current, II ±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, IO (each output) 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total supply current into VDD 40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total current out of GND 60 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: TLC139M −55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLC339C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLC339I −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLC339M −55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLC339Q −40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Case temperature for 60 seconds: FK package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package 260°C. . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package 300°C. . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.
2. Differential voltages are at IN+ with respect to IN −.
DISSIPATION RATING TABLE
PACKAGE
T
A
≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE T = 25 C
T
A
= 70°C
POWER RATING
T
A
= 85°C
POWER RATING
T
A
= 125°C
POWER RATING
PACKAGE
TA ≤ 25 C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70 C
POWER RATING
TA = 85 C
POWER RATING
TA = 125 C
POWER RATING
D
FK
950 mW
1375 mW
7.6 mW/°C
11.0 mW/ C
608 mW
880 mW
494 mW
715 mW
190 mW
275 mW
D
FK
J
950 mW
1375 mW
1375 mW
7.6 mW/ C
11.0 mW/°C
11.0 mW/
°
C
608 mW
880 mW
880 mW
494 mW
715 mW
715 mW
190 mW
275 mW
275 mW
J
N
1375 mW
1150 mW
11.0 mW/
°
C
9.2 mW/
°
C
880 mW
736 mW
715 mW
598 mW
275 mW
230 mW
N
PW
1150 mW
700 mW
9.2 mW/ C
5.6 mW/°C
736 mW
448 mW
598 mW
364 mW
230 mW
140 mW
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recommended operating conditions
TLC139M, TLC339M
UNIT
MIN NOM MAX
UNIT
Supply voltage, VDD 4 5 16 V
Common-mode input voltage, VIC 0 VDD−1.5 V
Low-level output current, IOL 20 mA
Operating free-air temperature, TA−55 125 °C
electrical characteristics at specified operating free-air temperature, VDD = 5 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS†
TA
TLC139M, TLC339M
UNIT
PARAMETER
TEST CONDITIONS†
TA
MIN TYP MAX
UNIT
VIC = VICRmin,
VDD = 5 V to 10 V,
25°C 1.4 5
VIO Input offset voltage VIC = VICRmin,
See Note 3 VDD = 5 V to 10 V, −55°C to
125°C10 mV
IIO
Input offset current
VIC = 2.5 V
25°C 1 pA
IIO Input offset current VIC = 2.5 V 125°C 15 nA
IIB
Input bias current
VIC = 2.5 V
25°C 5 pA
IIB Input bias current VIC = 2.5 V 125°C 30 nA
VICR
Common-mode input
25°C0 to
VDD−1
V
VICR
Common-mode input
voltage range −55°C to
125°C0 to
VDD−1.5
V
25°C 84
CMRR Common-mode rejection ratio V
IC
= V
ICR
min 125°C 84 dB
CMRR
Common-mode rejection ratio
VIC = VICRmin
−55°C 84
dB
25°C 85
k
SVR
Supply-voltage rejection ratio V
DD
= 5 V to 10 V 125°C 84 dB
kSVR
Supply-voltage rejection ratio
VDD = 5 V to 10 V
−55°C 84
dB
VOL
Low-level output voltage
VID = −1 V,
IOL = 6 mA
25°C 300 400
mV
VOL Low-level output voltage VID = −1 V, IOL = 6 mA 125°C800 mV
IOH
High-level output current
VID = −1 V,
VO = 5 V
25°C 0.8 40 nA
IOH High-level output current VID = −1 V, VO = 5 V 125°C1µA
Supply current (four
25°C 44 80
IDD
Supply current (four
comparators) Outputs low, No load −55°C to
125°C175 µA
†All characteristics are measured with zero common-mode voltage unless otherwise noted.
NOTE 3: The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V with a 2.5-kΩ load to
VDD.
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recommended operating conditions
TLC339C
UNIT
MIN NOM MAX
UNIT
Supply voltage, VDD 3 5 16 V
Common-mode input voltage, VIC −0.2 VDD−1.5 V
Low-level output current, IOL 8 20 mA
Operating free-air temperature,TA0 70 °C
electrical characteristics at specified operating free-air temperature, VDD = 5 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS†
TA
TLC339C
UNIT
PARAMETER
TEST CONDITIONS†
TA
MIN TYP MAX
UNIT
VIO
Input offset voltage
VIC = VICRmin,
VDD = 5 V to 10 V,
25°C 1.4 5
mV
VIO Input offset voltage
VIC = VICRmin,
See Note 3
VDD = 5 V to 10 V,
0°C to 70°C 6.5 mV
IIO
Input offset current
VIC = 2.5 V
25°C 1 pA
IIO Input offset current VIC = 2.5 V 70°C 0.3 nA
IIB
Input bias current
VIC = 2.5 V
25°C 5 pA
IIB Input bias current VIC = 2.5 V 70°C 0.6 nA
VICR
Common-mode input
25°C0 to
VDD−1
V
VICR
Common-mode input
voltage range 0°C to 70°C0 to
VDD−1.5
V
Common-mode rejection
25°C 84
CMRR Common-mode rejection
ratio
V
IC
= V
ICR
min 70°C 84 dB
CMRR
ratio
VIC = VICRmin
0°C 84
dB
Supply-voltage rejection
25°C 85
k
SVR
Supply-voltage rejection
ratio
V
DD
= 5 V to 10 V 70°C 85 dB
kSVR
ratio
VDD = 5 V to 10 V
0°C 85
dB
VOL
Low-level output voltage
VID = −1 V,
IOL = 6 mA
25°C 300 400
mV
VOL Low-level output voltage VID = −1 V, IOL = 6 mA 70°C650 mV
IOH
High-level output current
VID = −1 V,
VO = 5 V
25°C 0.8 40 nA
IOH High-level output current VID = −1 V, VO = 5 V 70°C1µA
IDD
Supply current (four
Outputs low,
No load
25°C 44 80
µA
I
DD
Supply current (four
comparators)
Outputs low,
No load
0°C to 70°C 100 µ
A
†All characteristics are measured with zero common-mode voltage unless otherwise noted.
NOTE 4: The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V with a 2.5-kΩ load to
VDD.
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recommended operating conditions
TLC339I
UNIT
MIN NOM MAX
UNIT
Supply voltage, VDD 3 5 16 V
Common-mode input voltage, VIC −0.2 VDD−1.5 V
Low-level output current, IOL 8 20 mA
Operating free-air temperature,TA0 70 °C
electrical characteristics at specified operating free-air temperature, VDD = 5 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS†
TA
TLC339I
UNIT
PARAMETER
TEST CONDITIONS†
TA
MIN TYP MAX
UNIT
VIO
Input offset voltage
VIC = VICRmin,
VDD = 5 V to 10 V,
25°C 1.4 5
mV
VIO Input offset voltage
VIC = VICRmin,
See Note 3
VDD = 5 V to 10 V,
−40°C to 85°C 7 mV
IIO
Input offset current
VIC = 2.5 V
25°C 1 pA
IIO Input offset current VIC = 2.5 V 85°C 1 nA
IIB
Input bias current
VIC = 2.5 V
25°C 5 pA
IIB Input bias current VIC = 2.5 V 85°C 2 nA
VICR
Common-mode input
25°C0 to
VDD−1
V
VICR
Common-mode input
voltage range −40°C to 85°C0 to
VDD−1.5
V
Common-mode rejection
25°C 84
CMRR Common-mode rejection
ratio
V
IC
= V
ICR
min 85°C 84 dB
CMRR
ratio
VIC = VICRmin
−40°C 84
dB
Supply-voltage rejection
25°C 85
k
SVR
Supply-voltage rejection
ratio
V
DD
= 5 V to 10 V 85°C 85 dB
kSVR
ratio
VDD = 5 V to 10 V
−40°C 84
dB
VOL
Low-level output voltage
VID = −1 V,
IOL = 6 mA
25°C 300 400
mV
VOL Low-level output voltage VID = −1 V, IOL = 6 mA 85°C700 mV
IOH
High-level output current
VID = −1 V,
VO = 5 V
25°C 0.8 40 nA
IOH High-level output current VID = −1 V, VO = 5 V 85°C1µA
IDD
Supply current (four
Outputs low,
No load
25°C 44 80
µA
I
DD
Supply current (four
comparators)
Outputs low,
No load
−40°C to 85°C 125 µ
A
†All characteristics are measured with zero common-mode voltage unless otherwise noted.
NOTE 3: The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V with a 2.5-kΩ load to
VDD.
6WWW.TI.COM
recommended operating conditions
TLC339Q
UNIT
MIN NOM MAX
UNIT
Supply voltage, VDD 4 5 16 V
Common-mode input voltage, VIC 0 VDD−1.5 V
Low-level output current, IOL 20 mA
Operating free-air temperature,TA− 40 125 °C
electrical characteristics at specified operating free-air temperature, VDD = 5 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS†
TA
TLC339Q
UNIT
PARAMETER
TEST CONDITIONS†
TA
MIN TYP MAX
UNIT
VIO
Input offset voltage
VIC = VICRmin,
VDD = 5 V to 10 V,
25°C 1.4 5
mV
VIO Input offset voltage
VIC = VICRmin,
See Note 3
VDD = 5 V to 10 V,
−40°C to 125°C 10 mV
IIO
Input offset current
VIC = 2.5 V
25°C 1 pA
IIO Input offset current VIC = 2.5 V 125°C 15 nA
IIB
Input bias current
VIC = 2.5 V
25°C 5 pA
IIB Input bias current VIC = 2.5 V 125°C 30 nA
VICR
Common-mode input
25°C0 to
VDD−1
V
VICR
Common-mode input
voltage range −40°C to 125°C0 to
VDD−1.5
V
Common-mode rejection
25°C 84
CMRR Common-mode rejection
ratio
V
IC
= V
ICR
min 125°C 84 dB
CMRR
ratio
VIC = VICRmin
−40°C 84
dB
Supply-voltage rejection
25°C 85
k
SVR
Supply-voltage rejection
ratio
V
DD
= 5 V to 10 V 125°C 84 dB
kSVR
ratio
VDD = 5 V to 10 V
−40°C 84
dB
VOL
Low-level output voltage
VID = −1 V,
IOL = 6 mA
25°C 300 400
mV
VOL Low-level output voltage VID = −1 V, IOL = 6 mA 125°C800 mV
IOH
High-level output current
VID = −1 V,
VO = 5 V
25°C 0.8 40 nA
IOH High-level output current VID = −1 V, VO = 5 V 125°C1µA
IDD
Supply current (four
Outputs low,
No load
25°C 44 80
µA
I
DD
Supply current (four
comparators)
Outputs low,
No load
−40°C to 125°C 125 µ
A
†All characteristics are measured with zero common-mode voltage unless otherwise noted.
NOTE 4: The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V with a 2.5-kΩ load to
VDD.
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switching characteristics, VDD = 5 V, TA = 25°C (see Figure 3)
PARAMETER TEST CONDITIONS
TLC139M, TLC339C
TLC339I, TLC339M
TLC339Q UNIT
MIN TYP MAX
Overdrive = 2 mV 4.5
f = 10 kHz,
Overdrive = 5 mV 2.5
tPLH
Propagation delay time, low-to-high output
f = 10 kHz,
CL = 15 pF
Overdrive = 10 mV 1.7
s
tPLH Propagation delay time, low-to-high output
CL = 15 pF
Overdrive = 20 mV 1.2 µs
Overdrive = 40 mV 1.0
VI = 1.4 V step at IN+ 1.1
Overdrive = 2 mV 3.6
f = 10 kHz,
Overdrive = 5 mV 2.1
tPHL
Propagation delay time, high-to-low level output
f = 10 kHz,
CL = 15 pF
Overdrive = 10 mV 1.3
s
tPHL Propagation delay time, high-to-low level output
CL = 15 pF
Overdrive = 20 mV 0.85 µs
Overdrive = 40 mV 0.55
VI = 1.4 V step at IN+ 0.10
tTHL
Transition time, high-to-low level output
f = 10 kHz,
Overdrive = 50 mV
20
ns
t
THL
Transition time, high-to-low level output
f = 10 kHz,
CL = 15pF
Overdrive = 50 mV
20
ns
PARAMETER MEASUREMENT INFORMATION
The TLC139 and TLC339 contain a digital output stage that, if held in the linear region of the transfer curve, can cause
damage to the device. Conventional operational amplifier/comparator testing incorporates the use of a servo-loop
that is designed to force the device output to a level within this linear region. Since the servo-loop method of testing
cannot be used, the following alternatives for testing parameters such as input offset voltage, common-mode
rejection, etc., are suggested.
To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown
in Figure 1(a). With the noninverting input positive with respect to the inverting input, the output should be high. With
the input polarity reversed, the output should be low.
A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages can
be slewed as shown in Figure 1(b) for the VICR test, rather than changing the input voltages, to provide greater
accuracy.
(a) VIO WITH VIC = 0 V (b) VIO WITH VIC = 4 V
5 V 1 V
5.1 kΩ5.1 kΩ
Applied VIO
Limit Applied VIO
Limit
VOVO
−4 V
Figure 1. Method for Verifying That Input Offset Voltage Is Within Specified Limits
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PARAMETER MEASUREMENT INFORMATION
A close approximation of the input offset voltage can be obtained by using a binary search method to vary the
differential input voltage while monitoring the output state. When the applied input voltage differential is equal but
opposite in polarity to the input offset voltage, the output changes state.
Figure 2 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the
comparator into the linear region. The circuit consists of a switching mode servo loop in which U1A generates a
triangular waveform of approximately 20-mV amplitude. U1B acts as a buf fer, with C2 and R4 removing any residual
dc offset. The signal is then applied to the inverting input of the comparator under test, while the noninverting input
is driven by the output of the integrator formed by U1C through the voltage divider formed by R9 and R10. The loop
reaches a stable operating point when the output of the comparator under test has a duty cycle of exactly 50%, which
can only occur when the incoming triangle wave is sliced symmetrically or when the voltage at the noninverting input
exactly equals the input offset voltage.
Voltage divider R9 and R10 provides a step-up of the input offset voltage by a factor of 100 to make measurement
easier. The values of R5, R8, R9, and R10 can significantly influence the accuracy of the reading; therefore, it is
suggested that their tolerance level be 1% or lower.
+
−
+
−
+
−
Dut
Buffer
R1
240 kΩ
R2
10 kΩ
R3
100 kΩ
R4
47 kΩ
R5
1.8 kΩ, 1%
R3
5.1 kΩ
R7
1 MΩ
R8
1.8 kΩ, 1%
R9
10 kΩ, 1%
R10
100 Ω, 1%
C1
0.1 µF
C2
1 µF
C3 0.68 µF
C4
0.1 µF
U1C
1/4 TLC274CN
U1A
1/4 TLC274CN
Triangle
Generator
U1B
1/4 TLC274CN
Integrator
VIO
(X100)
VDD
Figure 2. Circuit for Input Offset Voltage Measurement
Measuring the extremely low values of input current requires isolation from all other sources of leakage current and
compensation for the leakage of the test socket and board. With a good picoammeter, the socket and board leakage
can be measured with no device in the socket. Subsequently, this open socket leakage value can be subtracted from
the measurement obtained, with a device in the socket to obtain the actual input current of the device.
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PARAMETER MEASUREMENT INFORMATION
Propagation delay time is defined as the interval between the application of an input step function and the instant when
the output reaches 50% of its maximum value. Propagation delay time, low-to-high-level output, is measured from
the leading edge of the input pulse, while propagation delay time, high-to-low-level output, is measured from the
trailing edge of the input pulse. Propagation delay time measurement at low input signal levels can be greatly af fected
by the input offset voltage. The of fset voltage should be balanced by the adjustment at the inverting input as shown
in Figure 3, so that the circuit is just at the transition point. Then a low signal, for example 105-mV or 5-mV overdrive,
causes the output to change state.
90%
Pulse
Generator
VDD
DUT
TEST CIRCUIT
Input Offset Voltage
Compensation Adjustment
Low-to-High-Level
Output
VOLTAGE WAVEFORMS
High-to-Low-Level
Output
1 µF
5.1 kΩ
50 Ω
1 kΩ
1 V
−1 V
10 Ω
10 Turn
0.1 µF
CL
(see Note A)
Overdrive
Input
Overdrive
Input
100 mV 100 mV
50% 50%
10%
tPLH tPHL
tTHL
NOTE A: CL includes probe and jig capacitance.
Figure 3. Propagation Delay, Rise, and Fall Times Test Circuit and Voltage Waveforms
10 WWW.TI.COM
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO Input offset voltage Distribution 4
IIB Input bias current vs Free-air temperature 5
CMRR Common-mode rejection ratio vs Free-air temperature 6
kSVR Supply-voltage rejection ratio vs Free-air temperature 7
IOH
High-level output current
vs High-level output voltage 8
IOH High-level output current
vs High-level output voltage
vs Free-air temperature
8
9
VOL
Low-level output voltage
vs Low-level output current 10
VOL Low-level output voltage
vs Low-level output current
vs Free-air temperature
10
11
IDD
Supply current
vs Supply voltage 12
IDD Supply current
vs Supply voltage
vs Free-air temperature
12
13
tPLH Low-to-high level output propagation delay time vs Supply voltage 14
tPHL Low-to-high level output propagation delay time vs Supply voltage 15
Overdrive voltage vs Low-to-high-level output propagation delay time 16
tfOutput fall time vs Supply voltage 17
Overdrive voltage vs High-to-low-level output propagation delay time 18
11
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TYPICAL CHARACTERISTICS†
Figure 4
50
40
20
10
−5 −4 −3 −2 −1 0 1
Number of Units
60
80
90
2345
30
70
0
DISTRIBUTION OF INPUT
OFFSET VOLTAGE
100 VDD = 5 V
VIC = 2.5 V
TA = 25°C
VIO − Input Offset Voltage − mV
Figure 5
0
0.001
10
25 50 75 100 125
0.01
1
TA − Free-Air Temperature − °C
IIB − Input Bias Current − nA
IIB
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
VDD = 5 V
VIC = 2.5 V
Figure 6
84
82
81
80
− 75 − 50 − 25 0 25 50
86
87
88
75 100 125
85
83
89
TA − Free-Air Temperature − °C
CMMR − Common-Mode Rejection Ratio − dB
COMMON-MODE REJECTION
RATIO
vs
FREE-AIR TEMPERATURE
VDD = 5 V
90
Figure 7
85
83
82
81
− 75 − 50 − 25 0 25 50
87
88
89
75 100 125
86
84
90
TA − Free-Air Temperature − °C
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
kSVR − Supply-Voltage Rejection Ratio − dB
kSVR
VDD = 5 V to 10 V
80
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
12 WWW.TI.COM
TYPICAL CHARACTERISTICS†
Figure 8
10
0.1
1000
02468
1
100
VOH − High-Level Output Voltage − V
HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
10 12 14 16
V0H − High-Level Output Current − nA
IOH
TA = 125°C
TA = 85°C
TA = 70°C
TA = 25°C
VOH = VDD
Figure 9
TA − Free-Air Temperature − °C
10
0.1
1000
25 50 75 100 125
1
100
HIGH-LEVEL OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
V0H − High-Level Output Current − nA
IOH
VDD = VOH = 5 V
Figure 10
0.75
0.5
0.25
00 2 4 6 8 10 12
1
1.25
1.5
14 16 18 20
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
VOL − Low-Level Output Voltage − V
VOL
IOL − Low-Level Output Current − mA
16 V
VDD = 3 V
4 V
5 V 10 V
TA = 25°C
Figure 11
300
200
100
002550
400
500
600
75 100 125
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
TA − Free-Air Temperature − °C
VOL − Low-Level Output Voltage − V
VOL
VDD = 5 V
IOL = 6 mA
−75 −50 −25
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
13
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TYPICAL CHARACTERISTICS†
Figure 12
40
20
10
00246810
60
70
80
12 14 16
50
30
90
VDD − Supply Voltage − V
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
100
ICC − Supply Current − xA
DD
IAµ
Outputs Low
No Load
−40°C
25°C
85°C
125°C
TA = −55°C
Figure 13
40
20
10
002550
60
70
80
75 100 125
50
30
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
TA − Free-Air Temperature − °C
ICC − Supply Current − xA
DD
IAµ
Outputs Low
Outputs High
−75 −50 −25
VDD = 5 V
No Load
Figure 14
3
2
1
00246810
4
5
LOW-TO-HIGH-LEVEL
OUTPUT RESPONSE TIME
vs
SUPPLY VOLTAGE
6
12 14 16
VDD − Supply Voltage − V
IDD − Low-to-High-Level
tPLH
Output Propagation Delay Time − sµ
5 mV
10 mV
20 mV
40 mV
CL = 15 pF
RL = 5.1 kΩ (pullup to VDD)
TA = 25°C
Overdrive = 2 mV
Figure 15
1.5
1
0.5
00246810
2
2.5
HIGH-TO-LOW-LEVEL
OUTPUT RESPONSE TIME
vs
SUPPLY VOLTAGE
3
12 14 16
VDD − Supply Voltage − V
IDD − HIgh-to-Low-Level
tPHL
Output Propagation Delay Time − sµ
3.5
4
4.5
5
5 mV
20 mV
10 mV
40 mV
CL = 15 pF
RL = 5.1 kΩ (pullup to VDD)
TA = 25°C
Overdrive = 2 mV
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
14 WWW.TI.COM
TYPICAL CHARACTERISTICS
Figure 16
0
100
0
01
5
LOW-TO-HIGH-LEVEL OUTPUT
PROPAGATION DELAY
FOR VARIOUS OVERDRIVE VOLTAGES
2345
Differential
Input Voltage − mV V) − Output
VO
IDD − Low-to-High-Level
tPLH
Output Propagation Delay Time − sµ
40 mV
20 mV
10 mV
5 mV
2 mV
VDD = 5 V
CL = 15 pF
RL = 5.1 kΩ (pullup to VDD)
TA = 25°C
Voltage − V
Figure 17
30
20
10
00246810
40
50
60
12 14 16
OUTPUT FALL TIME
vs
SUPPLY VOLTAGE
t − Time − ns
VDD − Supply Voltage − V
CL = 100 pF
50 pF
15 pF
RL = 5.1 kΩ (pullup to VDD)
TA = 25°C
0
100
0
01
5
HIGH-TO-LOW-LEVEL OUTPUT
PROPAGATION DELAY
FOR VARIOUS OVERDRIVE VOLTAGES
2345
Differential
Input Voltage − mV V) − Output
VO
Output Propagation Delay Time − sµ
VDD = 5 V
CL = 15 pF
RL = 5.1 kΩ (pullup to VDD)
TA = 25°C
40 mV
20 mV
10 mV
5 mV
2 mV
tPHL − High-to-Low-Level
Voltage − V
Figure 18
15
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APPLICATION INFORMATION
The inputs should always remain within the supply rails in order to avoid forward biasing the diodes in the electrostatic
discharge (ESD) protection structure. If either input exceeds this range, the device is not damaged as long as the
input current is limited to less than 5 mA. To maintain the expected output state, the inputs must remain within the
common-mode range. For example, at 25°C with VDD = 5 V, both inputs must remain between −0.2 V and 4 V to
assure proper device operation. To assure reliable operation, the supply should be decoupled with a capacitor (0.1
µF) positioned as close to the device as possible.
The output and supply currents require close observation since the TLC139/TLC339 does not provide current
protection. For example, each output can source or sink a maximum of 20 mA; however, the total current to ground
has an absolute maximum of 60 mA. This prohibits sinking 20 mA from each of the four outputs simultaneously since
the total current to ground would be 80 mA.
The TLC139 and TLC339 have internal ESD-protection circuits that prevent functional failures at voltages up to
2000 V as tested under MIL-STD-883C, Method 3015.2; however, exercise care when handling these devices as
exposure to ESD may result in the degradation of the device parametric performance.
Table of Applications
FIGURE
Pulse-width-modulated motor speed controller 19
Enhanced supply supervisor 20
Two-phase nonoverlapping clock generator 21
5 V 10 kΩ
10 kΩ
10 kΩ
12 V
5.1 kΩ
100 kΩ
5 V
5 V
5 V
12 V
12 V
5.1 kΩ
10 kΩ
1/4
TLC139/TLC339 C1
0.01 µF
(see Note B)
(see Note A)
1/4
TLC139/339
Motor Speed Control
Potentiometer
Direction
Control S1
SPDT
Half-H Driver
Half-H Driver
SN75603
DIR
EN
Motor
SN75604
NOTES: A. The recommended minimum capacitance is 10 µF to eliminate common ground switching noise.
B. Select C1 for change in oscillator frequency.
Figure 19. Pulse-Width-Modulated Motor Speed Controller
16 WWW.TI.COM
TYPICAL APPLICATION DATA
12 V
Sense 3.3 kΩ
5.1 kΩ
1 kΩ
12 V
12 V
2.5 V
1/4 TLC139/TLC339
1/4
TLC139/TLC339
5.1 kΩ
R1
R2
To µP Interrupt
Early Power Fail
5 V 5 V
10 kΩ
1 µFC
t
(see Note B)
To µP
Reset
VCC SENSE
RESIN RESET
REF CTGND
TL7705A
NOTES:A. VUNREG =
B. The value of Ct determines the time delay of reset.
2.5 ǒR1 )R2
R2 Ǔ
Monitors 5-V Rail
Monitors 12-V Rail
Early Power Fail Warning
VUNREG
(see Note A)
Figure 20. Enhanced Supply Supervisor
12 V
12 V
12 V
5.1 kΩ
100 kΩ
100 kΩ
100 kΩ
22 kΩ
1/4
TLC139/TLC339
1/4 TLC139/TLC339
1/4 TLC139/TLC339
R1
100 kΩ
(see Note B)
R3
100 kΩ
(see Note B)
R3
5 kΩ
(see Note C) 12 V
12 V
5.1 kΩ
5.1 kΩ
Output 1
Output 2
Output 1
Output 2
C1
0.01 µF
(see Note A)
NOTES:A. Select C1 for a change in oscillator frequency where:
1/f = 1.85 (100 kΩ)C1
B. Select R1 and R3 to change duty cycle
C. Select R2 to change deadtime
Figure 21. Two-Phase Nonoverlapping Clock Generator
PACKAGE OPTION ADDENDUM
www.ti.com 27-Apr-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
5962-87659022A ACTIVE LCCC FK 20 1 TBD Call TI Call TI
5962-8765902CA ACTIVE CDIP J 14 1 TBD Call TI Call TI
5962-9555001NXD ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
5962-9555001NXDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC139MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
TLC139MJ ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
TLC139MJB ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
TLC339CD ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC339CDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC339CDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC339CDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC339CN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC339CN10 OBSOLETE PDIP N 14 TBD Call TI Call TI
TLC339CNE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC339CNSR ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC339CNSRG4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC339CPW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC339CPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC339CPWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI
TLC339CPWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC339CPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 27-Apr-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLC339ID ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC339IDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC339IDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC339IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC339IN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC339INE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC339IPW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC339IPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC339IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC339IPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC339MD ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC339MDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC339MDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC339MDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC339MN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 27-Apr-2012
Addendum-Page 3
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
5962-9555001NXDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TLC339CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TLC339CNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
TLC339CPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TLC339IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TLC339IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TLC339MDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
5962-9555001NXDR SOIC D 14 2500 367.0 367.0 38.0
TLC339CDR SOIC D 14 2500 367.0 367.0 38.0
TLC339CNSR SO NS 14 2000 367.0 367.0 38.0
TLC339CPWR TSSOP PW 14 2000 367.0 367.0 35.0
TLC339IDR SOIC D 14 2500 333.2 345.9 28.6
TLC339IPWR TSSOP PW 14 2000 367.0 367.0 35.0
TLC339MDR SOIC D 14 2500 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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