1
IDT74FCT16543AT/CT/ET
FAST CMOS 16-BIT LATCHED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE
SEPTEMBER 2009INDUSTRIAL TEMPERATURE RANGE
FEATURES:
• 0.5 MICRON CMOS Technology
• High-speed, low-power CMOS replacement for ABT functions
• Typical tSK(o) (Output Skew) < 250ps
• Low input and output leakage ≤≤
≤≤
≤1µA (max.)
•VCC = 5V ±10%
• High drive outputs (–32mA IOH, 64mA IOL)
• Power off disable outputs permit “live insertion”
• Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V,
TA = 25°C
• Available in SSOP, TSSOP, and TVSOP packages
FUNCTIONAL BLOCK DIAGRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
© 2009 Integrated Device Technology, Inc. DSC-5444/5
IDT74FCT16543AT/CT/ET
FAST CMOS
16-BIT LATCHED
TRANSCEIVER
DESCRIPTION:
The FCT16543T 16-bit latched transceivers are built using advanced
dual metal CMOS technology. These high-speed, low-power devices are
organized as two independent 8-bit D-type latched transceivers with
separate input and output control to permit independent control of data flow
in either direction. For example, the A-to-B Enable (xCEAB) must be low
in order to enter data from the A port or to output data from the B port. xLEAB
controls the latch function. When xLEAB is low, the latches are transparent.
A subsequent low-to-high transition of xLEAB signal puts the A latches in
the storage mode. xOEAB performs output enable function on the B port.
Data flow from the B port to the A port is similar but requires using xCEBA,
xLEBA, and xOEBA inputs. Flow-through organization of signal pins
simplifies layout. All inputs are designed with hysteresis for improved noise
margin.
The FCT16543T is ideally suited for driving high-capacitance loads
and low-impedance backplanes. The output buffers are designed with
power off disable capability to allow "live insertion" of boards when used
as backplane drivers.
C
D
1B1
1LEAB
1CEAB
1OEAB
1LEBA
1CEBA
1OEBA
TO SEVEN OTHER CHANNELS
1A1
2B1
2LEAB
2CEAB
2OEAB
2LEBA
2CEBA
2OEBA
TO SEVEN OTHER CHANNELS
2A1
C
D
C
D
C
D
56
54
55
1
3
2
5
29
31
30
28
26
27
15
52 42
2
INDUSTRIAL TEMPERATURE RANGE
IDT74FCT16543AT/CT/ET
FAST CMOS 16-BIT LATCHED TRANSCEIVER
PIN CONFIGURATION
Symbol Description Max Unit
VTERM(2) Terminal Voltage with Respect to GND –0.5 to 7 V
VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V
TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –60 to +120 mA
ABSOLUTE MAXIMUM RATINGS(1)
NOTES:
1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Outputs and I/O terminals for FCT162XXX.
Symbol Parameter(1) Conditions Typ. Max. Unit
CIN Input Capacitance VIN = 0V 3.5 6 pF
COUT Output Capacitance VOUT = 0V 3.5 8 pF
CAPACITANCE (TA = +25°C, f = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested.
SSOP/ TSSOP/ TVSOP
TOP VIEW
1
B
1
1
B
2
GND
1
B
3
1
B
4
V
CC
1
B
5
1
B
6
1
OEBA
1
B
7
1
B
8
2
B
1
2
B
2
GND
2
B
3
2
B
4
V
CC
2
B
5
GND
2
B
7
2
B
6
2
B
8
GND
2
OEBA
GND
1
A
1
1
A
2
V
CC
1
A
3
1
A
4
GND
1
A
5
1
A
6
1
A
7
1
A
8
GND
2
A
1
2
A
2
V
CC
2
A
3
2
A
5
2
A
4
2
A
7
GND
2
A
8
2
A
6
2
OEAB
2
LEAB
2
CEAB
1
CEAB
1
LEAB
1
OEAB
1
LEBA
1
CEBA
2
LEBA
2
CEBA
47
37
38
39
40
41
42
43
44
45
46
33
34
35
36
56
55
49
50
51
52
53
54
48
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
11
21
22
23
24
29
30
31
3225
26
27
28
NOTES:
1. * Before xLEAB LOW-to-HIGH Transition
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
2 . A-to-B data flow shown; B-to-A flow control is the same, except using xCEBA, xLEBA
and xOEBA.
FUNCTION TABLE(1, 2)
For A-to-B (Symmetric with B-to-A) Latch Output
Inputs Status Buffers
xCEAB xLEAB xOEAB xAx to xBx xBx
H X X Storing Z
X H X Storing X
L L L Transparent Current A Inputs
L H L Storing Previous* A Inputs
L L H Transparent Z
L H H Storing Z
PIN DESCRIPTION
Pin Names Description
xOEAB A-to-B Output Enable Input (Active LOW)
xOEBA B-to-A Output Enable Input (Active LOW)
xCEAB A-to-B Enable Input (Active LOW)
xCEBA B-to-A Enable Input (Active LOW)
xLEAB A-to-B Latch Enable Input (Active LOW)
xLEBA B-to-A Latch Enable Input (Active LOW)
xAx A-to-B Data Inputs or B-to-A 3-State Outputs
xBx B-to-A Data Inputs or A-to-B 3-State Outputs
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IDT74FCT16543AT/CT/ET
FAST CMOS 16-BIT LATCHED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
IOOutput Drive Current VCC = Max., VO = 2.5V(3) –50 — –180 mA
VOH Output HIGH Voltage VCC = Min. IOH = –3mA 2 .5 3.5 — V
VIN = VIH or VIL IOH = –15mA 2 . 4 3. 5 — V
IOH = –32mA(4) 23—V
VOL Output LOW Voltage VCC = Min. IOL = 64mA — 0.2 0.55 V
VIN = VIH or VIL
IOFF Input/Output Power Off Leakage(5) VCC = 0V, VIN = or VO ≤ 4.5V — — ±1 μA
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
VIH Input HIGH Level Guaranteed Logic HIGH Level 2 — — V
VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
IIH Input HIGH Current (Input pins)(5) VCC = Max. VI = VCC ——±1µA
Input HIGH Current (I/O pins)(5) ——±1
IIL Input LOW Current (Input pins)(5) VI = GND — — ± 1
Input LOW Current (I/O pins)(5) ——±1
IOZH High Impedance Output Current VCC = Max. VO = 2.7V — — ± 1 µA
IOZL (3-State Output pins)(5) VO = 0.5V — — ± 1
VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V
IOS Short Circuit Current VCC = Max., VO = GND(3) –80 –140 –250 mA
VHInput Hysteresis — — 100 — mV
ICCL Quiescent Power Supply Current VCC = Max — 5 500 µA
ICCH VIN = GND or VCC
ICCZ
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: TA = –40°C to +85°C, VCC = 5.0V ±10%
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. This test limit for this parameter is ±5µA at TA = –55°C.
OUTPUT DRIVE CHARACTERISTICS
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INDUSTRIAL TEMPERATURE RANGE
IDT74FCT16543AT/CT/ET
FAST CMOS 16-BIT LATCHED TRANSCEIVER
POWER SUPPLY CHARACTERISTICS
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
ΔICC Quiescent Power Supply VCC = Max. — 0.5 1.5 mA
Current TTL Inputs HIGH VIN = 3.4V(3)
ICCD Dynamic Power Supply Current(4) VCC = Max., Outputs Open VIN = VCC — 60 100 µA/
xCEAB and xOEAB = GND VIN = GND M H z
xCEBA = VCC
One Input Toggling
50% Duty Cycle
ICTotal Power Supply Current(6) VCC = Max., Outputs Open VIN = VCC — 0.6 1.5 mA
fi = 10MHz VIN = GND
50% Duty Cycle
xLEAB, xCEAB and
xOEAB = GND VIN = 3.4V — 0.9 2.3
xCEBA = VCC VIN = GND
One Bit Toggling
VCC = Max., Outputs Open VIN = VCC — 2.4 4.5(5)
fi = 2.5MHz VIN = GND
50% Duty Cycle
xLEAB, xCEAB and
xOEAB = GND VIN = 3.4V — 6.4 16.5(5)
xCEBA = VCC VIN = GND
Sixteen Bits Toggling
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ΔICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
ΔICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
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IDT74FCT16543AT/CT/ET
FAST CMOS 16-BIT LATCHED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
4. This limit is guaranteed but not tested.
74FCT16543AT 74FCT16543CT 74FCT16543ET
Symbol Parameter Condition(2) Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit
tPLH Propagation Delay CL = 50pF 1.5 6.5 1.5 5.1 1.5 3.4 ns
tPHL Transparent Mode RL = 500 Ω
xAx to xBx or xBx to xAx
tPLH Propagation Delay 1.5 8 1.5 5.6 1.5 3.7 ns
tPHL xLEBA to xAx, xLEAB to xBx
tPHZ Output Enable Time 1.5 9 1.5 7.8 1.5 4.8 ns
tPLZ xOEBA or xOEAB to xAx or xBx
xCEBA or xCEAB to xAx or xBx
tPZH Output Disable Time 1.5 7.5 1.5 6.5 1.5 4 ns
tPZL xOEBA or xOEAB to xAx or xBx
xCEBA or xCEAB to xAx or xBx
tSU Set-up Time HIGH or LOW 2 — 2 — 1 — ns
xAx or xBx to xLEAB or xLEBA
tHHold Time HIGH or LOW 2 — 2 — 1 — ns
xAx or xBx to xLEAB or xLEBA
tWxLEAB or xLEBA Pulse Width LOW 4 — 4 — 3(4) —ns
tSK(o) Output Skew(3) — 0.5 — 0.5 — 0.5 ns
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INDUSTRIAL TEMPERATURE RANGE
IDT74FCT16543AT/CT/ET
FAST CMOS 16-BIT LATCHED TRANSCEIVER
Pulse
Generator
R
T
D.U.T.
V
CC
V
IN
C
L
V
OUT
50pF 500Ω
500Ω
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
t
SU
t
H
t
REM
t
SU
t
H
PRESET
CLEAR
CLOCK ENABLE
ETC.
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
t
W
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
1.5V
V
OH
t
PLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
t
PLH
t
PHL
t
PHL
V
OL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
V
OL
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
3.5V
0V
1.5V
1.5V
ENABLE DISABLE
V
OH
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuits for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
Pulse Width
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
Test Switch
Open Drain
Disable Low Closed
Enable Low
All Other Tests Open
SWITCH POSITION
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
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IDT74FCT16543AT/CT/ET
FAST CMOS 16-BIT LATCHED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
XX
Temp. Range
XXXX
Device Type
XX
Package
PVG
PAG
PFG
Shrink Small Outline Package - Green
Thin Shrink Small Outline Package - Green
Thin Very Small Outline Package - Green
16-Bit Latched Transceiver
74 40C to +85C
16 Double-Density, 5 Volt, High Drive
FCT XXX
Family
543AT
543CT
543ET
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 logichelp@idt.com
San Jose, CA 95138 fax: 408-284-2775
www.idt.com
Datasheet Document History
09/28/09 Pg. 7 Updated the ordering information by removing the "IDT" notation and non RoHS part.
