TSC2004
®
 
  
1
FEATURES APPLICATIONS
DESCRIPTION
Pre-Processing
PINTDAV
I C
2
Serial
Interface
and
Control
SDA
AD0
RESET
VREF
X+
X-
Y+
Y-
AUX
TEMP
Mux
PENIRQ
DAV
SAR
ADC
Internal
Clock
Touch
Screen
Drivers
Interface
SCL
AD1
TSC2004
SBAS408E – JUNE 2007 – REVISED MARCH 2008
1.2V to 3.6V, 12-Bit, Nanopower, 4-WireTOUCH SCREEN CONTROLLER with I
2
C™ Interface
•Cellular Phones23
•4-Wire Touch Screen Interface
•Portable Instruments•Ratiometric Conversion
•MP3 Players, Pagers•Single 1.2V to 3.6V Supply
•Multiscreen Touch Control•Preprocessing to Reduce Bus Activity•High-Speed I
2
C-Compatible Interface•Internal Detection of Screen Touch
The TSC2004 is a very low-power touch screen•Register-Based Programmable:
controller designed to work with power-sensitive,– 10-Bit or 12-Bit Resolution
handheld applications that are based on advancedlow-voltage processors. It works with a supply voltage– Sampling Rates
as low as 1.2V, which can be supplied by a– System Timing
single-cell battery. It contains a complete,•On-Chip Temperature Measurement
ultralow-power, 12-bit, analog-to-digital (A/D) resistivetouch screen converter, including drivers and the•Touch Pressure Measurement
control logic to measure touch pressure.•Auto Power-Down Control
In addition to these standard features, the TSC2004•Low Power:
offers preprocessing of the touch screen– 760 µW at 1.8V, 50SSPS
measurements to reduce bus loading, thus reducing– 580 µW at 1.6V, 50SSPS
the consumption of host processor resources that canthen be redirected to more critical functions.– 285 µW at 1.2V, 50SSPS– 74 µW at 1.6V, 8.2kSPS Eq. Rate
The TSC2004 supports an I
2
C serial bus and datatransmission protocol in all three defined modes:– 47 µW at 1.2V, 8.2kSPS Eq. Rate
standard, fast, and high-speed. It offers•Enhanced ESD Protection:
programmable resolution of 10 or 12 bits to– ± 8kV HBM
accommodate different screen sizes and performanceneeds.– ± 1kV CDM– ± 25kV Air Gap Discharge
The TSC2004 is available in a miniature, 18-lead,5 x 5 array, (2.554 ± 0.54)mm x (2.554 ± 0.54)mm– ± 12kV Contact Discharge
wafer chip-scale package (WCSP), and a 20-pin, 4 x•2.5 x 2.5 WCSP-18 and 4 x 4 QFN-20 Packages
4 QFN package. Both packages are characterized forU.S. Patent No. 6,246,394; other patents pending.
the – 40 °C to +85 °C industrial temperature range.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2I2C is a trademark of NXP Semiconductors.3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007 – 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS
(1)
TSC2004
SBAS408E – JUNE 2007 – REVISED MARCH 2008
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
TYPICAL TYPICAL NO MISSINGINTEGRAL GAIN CODES SPECIFIED TRANSPORTLINEARITY ERROR RESOLUTION PACKAGE PACKAGE TEMPERATURE PACKAGE ORDERING MEDIA,PRODUCT (LSB) (LSB) (BITS) TYPE DESIGNATOR RANGE MARKING NUMBER QUANTITY
Small TapeTSC2004IRTJT20-Pin,
and Reel, 2500.8 x 4 x 4 RTJ – 40 °C to +85 °C TSC2004I
Tape andThin QFN
TSC2004IRTJR
Reel, 3000TSC2004 – 0.8 to +1.4 +0.1 11
18-Pin, Small Ta\peTSC2004IYZKT5 x 5 Matrix, and Reel, 2502.5 x 2.5 YZK – 40 °C to +85 °C TSC2004I
Tape andDSBGA
TSC2004IYZKR
Reel, 3000(WCSP)
(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or seethe TI website at www.ti.com.
Over operating free-air temperature range (unless otherwise noted).
TSC2004 UNIT
Analog input X+, Y+, AUX to SNSGND – 0.4 to SNSVDD + 0.1 VAnalog input X – , Y – to SNSGND – 0.4 to SNSVDD + 0.1 VSNSVDD to SNSGND – 0.3 to 5 VVoltage range
SNSVDD to AGND – 0.3 to 5 VI/OVDD to DGND – 0.3 to 5 VSNSVDD to I/OVDD – 2.40 to +0.3 VDigital input voltage to DGND – 0.3 to I/OVDD + 0.3 VDigital output voltage to DGND – 0.3 to I/OVDD + 0.3 VPower dissipation (T
J
Max - T
A
)/ θ
JA
Low-K 113 °C/WWCSP packageThermal impedance, θ
JA
High-K 62 °C/WQFN package 39.97 °C/WOperating free-air temperature range, T
A
– 40 to +85 °CStorage temperature range, T
STG
– 65 to +150 °CJunction temperature, T
J
Max +150 °CVapor phase (60 sec) +215 °CLead temperature
Infrared (15 sec) +220 °CIEC contact discharge
(2)
X+, X – , Y+, Y – ± 12 kVIEC air discharge
(2)
X+, X – , Y+, Y – ± 25 kV
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure toabsolute-maximum rated conditions for extended periods may affect device reliability.(2) Test method based on IEC standard 61000-4-2. Contact Texas Instruments for test details.
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ELECTRICAL CHARACTERISTICS
TSC2004
SBAS408E – JUNE 2007 – REVISED MARCH 2008
At T
A
= – 40 °C to +85 °C, SNSVDD = V
REF
= +1.2V to +3.6V, I/OVDD
(1)
= +1.2V to +3.6V, unless otherwise noted.
TSC2004
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AUXILIARY ANALOG INPUT
Input voltage range 0 VREF V
Input capacitance 12 pF
Input leakage current – 1 +1 µA
A/D CONVERTER
Resolution Programmable: 10 or 12 bits 12 Bits
No missing codes 12-bit resolution 11 Bits
Integral linearity – 3 – 0.8 to +1.4 +3 LSB
(2)
Differential linearity – 2 – 0.6 to +0.7 +4 LSB
TSC2004IRTJ – 5 2.2 5 LSBSNSVDD = 1.6V, V
REF
= 1.6V,Offset error
High-Speed mode, filter off
TSC2004IYZK 2.2 LSB
TSC2004IRTJ – 3 0.1 +3SNSVDD = 1.6V, V
REF
= 1.6V,Gain error LSBHigh-Speed mode, filter off
TSC2004IYZK 0.1
REFERENCE INPUT
V
REF
range 1.2 SNSVDD V
Non-continuous AUX mode, SNSVDD = V
REF
= 1.6V,VREF input current drain 1.2 µAT
A
= +25 °C, f
ADC
= 2MHz, High-Speed mode
Input impedance A/D converter not converting 1 G Ω
TOUCH SENSORS
PENIRQ 50k Ωpull-up
T
A
= +25 °C, SNSVDD = V
REF
= 1.6V 47 k Ωresistor, R
IRQ
Y+, X+ T
A
= +25 °C, SNSVDD = V
REF
= 1.6V 6 ΩSwitch
on-resistance
Y – , X – T
A
= +25 °C, SNSVDD = V
REF
= 1.6V 5 Ω
Switch drivers drive
100ms duration 50 mAcurrent
(3)
INTERNAL TEMPERATURE SENSOR
Temperature range – 40 +85 °C
SNSVDD = 1.6V 0.3 °C/LSBDifferential method
(4)
SNSVDD = 3V 1.6 °C/LSBResolution
SNSVDD = 1.6V 0.3 °C/LSBTEMP1
(5)
SNSVDD = 3V 1.6 °C/LSB
SNSVDD = 1.6V ± 3 °C/LSBDifferential method
(4)
SNSVDD = 3V ± 2 °C/LSBAccuracy
SNSVDD = 1.6V ± 3 °C/LSBTEMP1
(5)
SNSVDD = 3V ± 2 °C/LSB
INTERNAL OSCILLATOR
SNSVDD = 1.2V, T
A
= +25 °C 3.2 MHz
Clock frequency, f
OSC
SNSVDD = 1.6V 3.3 3.7 4.3 MHz
SNSVDD = 3.0V, T
A
= +25 °C 4.1 MHz
SNSVDD = 1.2V 0.118 %/ °C
Frequency drift SNSVDD = 1.6V – 0.018 %/ °C
SNSVDD = 3.0V – 0.032 %/ °C
(1) I/OVDD must be ≤SNSVDD.(2) LSB means Least Significant Bit. With V
REF
= +2.5V, one LSB is 610 µV.(3) Assured by design, but not tested. Exceeding 50mA source current may result in device degradation.(4) Difference between TEMP1 and TEMP2 measurement; no calibration necessary.(5) Temperature drift is – 2.1mV/ °C.
Copyright © 2007 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 3
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TSC2004
SBAS408E – JUNE 2007 – REVISED MARCH 2008
ELECTRICAL CHARACTERISTICS (continued)At T
A
= – 40 °C to +85 °C, SNSVDD = V
REF
= +1.2V to +3.6V, I/OVDD = +1.2V to +3.6V, unless otherwise noted.
TSC2004
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUT/OUTPUT
Logic family CMOS
1.2V ≤I/OVDD < 1.6V 0.7 ×I/OVDD I/OVDD + 0.3 VV
IH
1.6V ≤I/OVDD ≤3.6V 0.7 ×I/OVDD I/OVDD + 0.3 V
1.2V ≤I/OVDD < 1.6V – 0.3 0.2 ×I/OVDD VV
IL
1.6V ≤I/OVDD ≤3.6V – 0.3 0.3 ×I/OVDD V
I
IL
SCL and SDA pins – 1 1 µALogic level
C
IN
SCL and SDA pins 10 pF
V
OH
I
OH
= 2 TTL loads I/OVDD – 0.2 I/OVDD V
V
OL
I
OL
= 2 TTL loads 0 0.2 V
I
LEAK
Floating output – 1 1 µA
C
OUT
Floating output 10 pF
Data format Straight Binary
POWER-SUPPLY REQUIREMENTS
Power-supply voltage
SNSVDD Specified performance 1.2 3.6 V
I/OVDD
(6)
1.2 SNSVDD V
Filter off, M = W = 1, C[3:0] =(1,0,0,0), RM = 1, CL[1:0] = (0,1),cont AUX mode, f
ADC
= 2MHz, SNSVDD = I/OVDD = V
REF
= 1.6V 506 625 µAHigh-Speed mode, withoutreading data register
T
A
= +25 °C, filter on, M = 15, W = SNSVDD = I/OVDD = V
REF
= 1.2V
237 µA7, PSM = 1, C[3:0] = (0,0,0,0), xRM = 1, CL[1:0] = (0,1), BTD[2:0]
SNSVDD = I/OVDD = V
REF
= 1.6V= (1,0,1), 50SSPS, MAVEX =
364 µAxMAVEY = MAVEZ = 1, f
ADC
=2MHz, High-Speed mode, sensor
SNSVDD = I/OVDD = V
REF
= 3.0V
797 µAdrivers supply included
T
A
= +25 °C, filter off, M = W = 1, SNSVDD = I/OVDD = V
REF
= 1.2V
237 µAPSM = 1, C[3:0] = (0,0,0,0), RM = x1, CL[1:0] = (0,1), BTD[2:0] =
SNSVDD = I/OVDD = V
REF
= 1.6V(1,0,1), 50SSPS, MAVEX =
342 µAxMAVEY = MAVEZ = 1, f
ADC
=2MHz, High-Speed mode, sensor
SNSVDD = I/OVDD = V
REF
= 3.0V
757 µAQuiescent supply
drivers supply includedcurrent
(7) (8)
SNSVDD = I/OVDD = V
REF
= 1.2V 176 µAT
A
= +25 °C, filter off, M = W = 1,C[3:0] = (0,1,0,1), RM = 1, CL[1:0]
SNSVDD = I/OVDD = V
REF
= 1.6V 268 µA= (0,1), non-cont AUX mode, f
ADC= 2MHz, High-Speed mode
SNSVDD = I/OVDD = V
REF
= 3.0V 526 µA
SNSVDD = I/OVDD = V
REF
= 1.2V,
347 µAT
A
= +25 °C, filter on, M = 7, W =
~10.3kSPS effective rate3, C[3:0] = (0,1,0,1), RM = 1,CL[1:0] = (0,1), MAVEAUX = 1, SNSVDD = I/OVDD = V
REF
= 1.6V,
468 µAnon-cont AUX mode, f
ADC
= ~11.8kSPS effective rate2MHz, High-Speed mode, full
SNSVDD = I/OVDD = V
REF
= 3.0V,speed
897 µA~12.3kSPS effective rate
SNSVDD = I/OVDD = V
REF
= 1.2V,T
A
= +25 °C, filter on, M = 7, W =
39.4 µA~1.17kSPS effective rate3, C[3:0] = (0,1,0,1), RM = 1,CL[1:0] = (0,1), MAVEAUX = 1,
SNSVDD = I/OVDD = V
REF
= 1.6V,non-cont AUX mode, f
ADC
= 46.4 µA~1.17kSPS effective rate2MHz, High-Speed mode,reduced speed (8.2kSPS
SNSVDD = I/OVDD = V
REF
= 3.0V,
85.3 µAequivalent rate)
~1.17kSPS effective rate
T
A
= +25 °C, Not addressed, SCL = SDA = 1,Power-down supply current 0.023 0.8 µASNSVDD = I/OVDD = V
REF
= 1.6V
(6) I/OVDD must be ≤SNSVDD.(7) Supply current from SNSVDD.(8) For detailed information on test condition parameter and bit settings, see the Digital Interface section.
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PIN CONFIGURATIONS
X
Y
SNSGND
NC
AD0
-
-
TSC2004
16
17
18
19
20
10
9
8
7
6
ThermalPad
12345
15 14 13 12 11
AGND
AUX
NC
I/OVDD
DGND
SUBGND
Y+
X+
SNSVDD
VREF
SDA
SCL
AD1
PINTDAV
RESET
Columns
(FRONT VIEW)
ACEB D
NCAD1 SNSGNDNCDGND
4
NCNC Y-
I/OVDD
3
SUBGNDNC
X-
AUX
2
X+VREF Y+
SNSVDD
AGND
1
SDA
PINTDAV
AD0
SCL
RESET
5
Rows
NC
TSC2004
SBAS408E – JUNE 2007 – REVISED MARCH 2008
RTJ PACKAGE
(1)
YZK PACKAGEQFN-20
WCSP-18(TOP VIEW)
(TOP VIEW, SOLDER BUMPS ON BOTTOM SIDE)
(1) The thermal pad is internally connected toSUBGND. The thermal pad can beconnected to the analog ground or leftfloating. Keep the thermal pad separatefrom the digital ground, if possible.
PIN ASSIGNMENTSPIN NO.
PINQFN WCSP NAME I/O A/D DESCRIPTION
1 D1 SDA I/O D Serial data I/O
2 C1 SCL I D Serial clock.
3 B2 AD1 I D Address input bit 1
4 A1 PINTDAV O D Interrupt output. Data available or PENIRQ, depending on setting. Pin polarity with active low.
5 B1 RESET I D System reset. All register values reset to default values.
6 A2 DGND Digital ground
7 A3 I/OVDD Digital I/O interface voltage
B3, B4,
No internal connection, but solder bumps are populated. These pins may be connected to analog ground8, 19 C2, C3, NC
for mechanical stability.D2, D3
9 A4 AUX I A Auxiliary channel input
10 A5 AGND Analog ground
11 B5 VREF I A External reference input
12 C5 SNSVDD Power supply for sensor drivers and other analog blocks.
13 D5 X+ I A X+ channel input
14 E5 Y+ I A Y+ channel input
15 D4 SUBGND Substrate ground (for ESD current). Connection to AGND (on the PCB) is recommended.
16 E4 X – I A X – channel input
17 E3 Y – I A Y – channel input
18 E2 SNSGND Sensor driver return
20 E1 AD0 I D Address input bit 0
— C4 NC No solder bump for this location.
Copyright © 2007 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 5
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TIMING INFORMATION
tHD, STA
tSU, DAT
tHD, DAT
tSU, STA
tSU, STO
tHD, STA
tLOW
tHIGH
tRtF
tBUF
SDA
SCL
S Sr P S
S=STARTCondition
Sr=RepeatedSTARTCondition
P=STOPCondition
=ResistorPull-Up
SDA
Sr
Sr
tFDA
tRDA
tSU, STA tHD, STA
P
SCL
tHD, DAT
tSU, DAT
tRCL1
(1) tRCL1
(1)
tHIGH tLOW tLOW
tRCL
tFCL
tHIGH
tSU, STO
=CurrentSourcePull-Up
=ResistorPull-Up
NOTE:(1)FirstrisingedgeoftheSCLsignalafterSrandaftereachacknowledgebit.
Sr=RepeatedSTARTCondition
P=STOPCondition
TSC2004
SBAS408E – JUNE 2007 – REVISED MARCH 2008
Figure 1. Detailed I/O Timing for Standard and Fast Modes
Figure 2. Detailed I/O Timing for High-Speed Mode
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TIMING REQUIREMENTS for Figure 1 : I
2
C Standard Mode (f
SCL
= 100kHz)
(1)
TSC2004
SBAS408E – JUNE 2007 – REVISED MARCH 2008
All specifications typical at – 40 °C to +85 °C, SNSVDD = I/OVDD = +1.2V to +3.6V, unless otherwise noted.
2-WIRE STANDARD MODE PARAMETERS TEST CONDITIONS MIN MAX UNIT
SNSVDD ≥1.6V 10 µsReset low time
(2)
t
WL(RESET)
1.2V ≤SNSVDD < 1.6V 13 µs
SCL clock frequency f
SCL
100 kHz
Bus free time between a STOP and START
t
BUF
4.7 µscondition
Hold time (repeated) START condition t
HD, STA
4.0 µs
Low period of SCL clock t
LOW
4.7 µs
High period of the SCL clock t
HIGH
4.0 µs
Setup time for a repeated START condition t
SU, STA
4.7 µs
Data hold time t
HD, DAT
0 3.45 µs
Data setup time t
SU, DAT
250 ns
Rise time of both SDA and SCL signals t
R
C
b
= total bus capacitance 1000 ns
Fall time of both SDA and SCL signals t
F
C
b
= total bus capacitance 300 ns
Setup time for STOP condition t
SU, STO
4.0 µs
Capacitive load for each bus line C
b
C
b
= total capacitance of one bus line in pF 400 pF
Pulse width of spike suppressed t
SP
N/A N/A ns
(1) All input signals are specified with t
R
= t
F
= 5ns (30% to 70% of I/OVDD) and timed from a voltage level of (V
IL
+ V
IH
)/2.(2) Refer to Figure 38 .
TIMING REQUIREMENTS for Figure 1 : I
2
C Fast Mode (f
SCL
= 400kHz)
(1)
All specifications typical at – 40 °C to +85 °C, SNSVDD = I/OVDD = +1.2V to +3.6V, unless otherwise noted.
2-WIRE FAST MODE PARAMETERS TEST CONDITIONS MIN MAX UNIT
SNSVDD ≥1.6V 10 µsReset low time
(2)
t
WL(RESET)
1.2V ≤SNSVDD < 1.6V 13 µs
SCL clock frequency f
SCL
400 kHz
Bus free time between a STOP and START
t
BUF
1.3 µscondition
Hold time (repeated) START condition t
HD, STA
0.6 µs
Low period of SCL clock t
LOW
1.3 µs
High period of the SCL clock t
HIGH
0.6 µs
Setup time for a repeated START condition t
SU, STA
0.6 µs
Data hold time t
HD, DAT
0 0.9 µs
Data setup time t
SU, DAT
100 ns
Rise time of both SDA and SCL signals t
R
C
b
= total bus capacitance 20 + 0.1 ×C
b
300 ns
Fall time of both SDA and SCL signals t
F
C
b
= total bus capacitance 20 + 0.1 ×C
b
300 ns
Setup time for STOP condition t
SU, STO
0.6 µs
Capacitive load for each bus line C
b
C
b
= total capacitance of one bus line in pF 400 pF
Pulse width of spike suppressed t
SP
0 50 ns
(1) All input signals are specified with t
R
= t
F
= 5ns (30% to 70% of I/OVDD) and timed from a voltage level of (V
IL
+ V
IH
)/2.(2) Refer to Figure 38 .
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TIMING REQUIREMENTS for Figure 2 : I
2
C High-Speed Mode (f
SCL
= 1.7MHz)
(1)
TSC2004
SBAS408E – JUNE 2007 – REVISED MARCH 2008
All specifications typical at – 40 °C to +85 °C, SNSVDD = I/OVDD = +1.2V to +3.6V, unless otherwise noted.
2-WIRE HIGH-SPEED MODE PARAMETERS TEST CONDITIONS MIN MAX UNIT
SNSVDD ≥1.6V 10 µsReset low time
(2)
t
WL(RESET)
1.2V ≤SNSVDD < 1.6V 13 µs
SCL clock frequency f
SCL
1.7 MHz
Hold time (repeated) START condition t
HD, STA
160 ns
Low period of SCL clock t
LOW
320 ns
High period of the SCL clock t
HIGH
120 ns
Setup time for a repeated START condition t
SU, STA
160 ns
Data hold time t
HD, DAT
0 150 ns
Data setup time t
SU, DAT
10 ns
Rise time of SCL signal t
RCL
C
b
= total bus capacitance 20 80 ns
Rise time of SDA signal t
RDA
C
b
= total bus capacitance 20 160 ns
Fall time of SCL signal t
FCL
C
b
= total bus capacitance 20 80 ns
Fall time of SDA signal t
FDA
C
b
= total bus capacitance 20 160 ns
Rise time of SCL signal after a repeated START
t
RCL1
C
b
= total bus capacitance 20 160 nscondition and after an acknowledge bit
Setup time for STOP condition t
SU, STO
160 ns
Capacitive load for each bus line C
b
C
b
= total capacitance of one bus line in pF 400 pF
Pulse width of spike suppressed t
SP
0 10 ns
(1) All input signals are specified with t
R
= t
F
= 5ns (30% to 70% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.(2) Refer to Figure 38 .
TIMING REQUIREMENTS for Figure 2 : I
2
C High-Speed Mode (f
SCL
= 3.4MHz)
(1)
All specifications typical at – 40 °C to +85 °C, SNSVDD = I/OVDD = +1.2V
(2)
to +3.6V, unless otherwise noted.
2-WIRE HIGH-SPEED MODE PARAMETERS TEST CONDITIONS MIN MAX UNIT
SNSVDD ≥1.6V 10 µsReset low time
(3)
t
WL(RESET)
1.2V ≤SNSVDD < 1.6V 13 µs
SCL clock frequency f
SCL
3.4 MHz
Hold time (repeated) START condition t
HD, STA
160 ns
Low period of SCL clock t
LOW
160 ns
High period of the SCL clock t
HIGH
60 ns
Setup time for a repeated START condition t
SU, STA
160 ns
Data hold time t
HD, DAT
0 70 ns
Data setup time t
SU, DAT
10 ns
Rise time of SCL signal t
RCL
C
b
= total bus capacitance 10 40 ns
Rise time of SDA signal t
RDA
C
b
= total bus capacitance 10 80 ns
Fall time of SCL signal t
FCL
C
b
= total bus capacitance 10 40 ns
Fall time of SDA signal t
FDA
C
b
= total bus capacitance 10 80 ns
Rise time of SCL signal after a repeated START
t
RCL1
C
b
= total bus capacitance 10 80 nscondition and after an acknowledge bit
Setup time for STOP condition t
SU, STO
160 ns
Capacitive load for each bus line C
b
C
b
= total capacitance of one bus line in pF 100 pF
Pulse width of spike suppressed t
SP
0 10 ns
(1) All input signals are specified with t
R
= t
F
= 5ns (30% to 70% of I/OVDD) and timed from a voltage level of (V
IL
+ V
IH
)/2.(2) Because of the low supply voltage of 1.2V and the wide temperature range of – 40 °C to +85 °C, the I
2
C system devices may not reachthe maximum specification of I
2
C High-Speed mode, and f
SCL
may not reach 3.4Mhz.(3) Refer to Figure 38 .
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TYPICAL CHARACTERISTICS
1.2 1.6 2.0 2.4 2.8 3.2 3.6
SNSVDD(V)
1.00
0.75
0.50
0.25
0
SNSVDDSupplyCurrent(mA)
I/OVDD=SNSVDD=VREF
T =+25 C°
A
f =2MHz
ADC
f =1MHz
ADC
1.2 1.6 2.0 2.4 2.8 3.2 3.6
SNSVDD(V)
1.2
1.0
0.8
0.6
0.4
0.2
0
SNSVDDSupplyCurrent(mA)
TouchSensorModeledBy:
2k forY-PlaneW
2k forY-PlaneW
1kWforZ(TouchResistance)(2)
M=15,W=7(1)
M=1,W=1(1)
I/OVDD=SNSVDD=VREF
TA=+25°C
t ,t ,t
PVS PRE SNS =defaultvalues
TSC-InitiatedModeScanX,Y,Zat50SSPS
TSC2004
SBAS408E – JUNE 2007 – REVISED MARCH 2008
At T
A
= – 40 °C to +85 °C, SNSVDD = V
REF
= +1.2V to +3.6V, I/OVDD = +1.2V to +3.6V, f
ADC
= f
OSC
/2,High-Speed mode (f
SCL
= 3.4MHz), 12-bit mode, and non-continuous AUX measurement, unless otherwise noted.
CHANGE IN OFFSET CHANGE IN GAINvs TEMPERATURE vs TEMPERATURE
Figure 3. Figure 4.
SNSVDD SUPPLY CURRENT SNSVDD SUPPLY CURRENTvs TEMPERATURE vs SNSVDD SUPPLY VOLTAGE
Figure 5. Figure 6.
SNSVDD SUPPLY CURRENTvs SNSVDD SUPPLY VOLTAGE
(1) See Table 1(2) See Figure 26
Figure 7.
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-40 -20 0 20 40 60 80 100
Temperature(°C)
Power-DownSupplyCurrent(nA)
1000
800
600
400
200
0
SNSVDD=1.6V
SNSVDD=3.6V
SNSVDD=3.0V
SNSVDD=I/OVDD=VREF
1.2 1.6 2.0 2.4 2.8 3.2 3.6
SNSVDD(V)
Power-DownSupplyCurrent(nA)
60
45
30
15
0
SNSVDD=I/OVDD=VREF
T =+25 C°
A
-40 -20 0 20 40 60 80 100
Temperature( C)°
25
20
15
10
5
0
I/OVDDSupplyCurrent( A)m
I/OVDD=SNSVDD=VREF
I/OVDD=1.6V
I/OVDD=1.2V
1.2 1.6 2.0 2.4 2.8 3.2 3.6
I/OVDD(V)
80
70
60
50
40
30
20
10
0
I/OVDDSupplyCurrent( A)m
I/OVDD=SNSVDD=VREF
T =+25 C
A°
f =2MHz
ADC
f =1MHz
ADC
-40 -20 0 20 40 60 80 100
Temperature(°C)
2.0
1.5
1.0
0.5
0
ReferenceInputCurrent( A)m
SNSVDD=I/OVDD=VREF
SNSVDD=1.2V
SNSVDD=1.6V
1.2 1.6 2.0 2.4 2.8 3.2 3.6
SNSVDD(V)
4.0
3.0
2.0
1.0
0
ReferenceInputCurrent( A)m
SNSVDD=I/OVDD=VREF
TSC2004
SBAS408E – JUNE 2007 – REVISED MARCH 2008
TYPICAL CHARACTERISTICS (continued)At T
A
= – 40 °C to +85 °C, SNSVDD = V
REF
= +1.2V to +3.6V, I/OVDD = +1.2V to +3.6V, f
ADC
= f
OSC
/2,High-Speed mode (f
SCL
= 3.4MHz), 12-bit mode, and non-continuous AUX measurement, unless otherwise noted.
POWER-DOWN SUPPLY CURRENT POWER-DOWN SUPPLY CURRENTvs TEMPERATURE vs SNSVDD SUPPLY VOLTAGE
Figure 8. Figure 9.
I/OVDD SUPPLY CURRENT I/OVDD SUPPLY CURRENTvs TEMPERATURE vs I/OVDD SUPPLY VOLTAGE
Figure 10. Figure 11.
REFERENCE INPUT CURRENT REFERENCE INPUT CURRENTvs TEMPERATURE vs SNSVDD SUPPLY VOLTAGE
Figure 12. Figure 13.
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Temperature( C)°
R( )W
ON
-40 -20
7
6
5
4
3
2
1
0 20 40 60 80 100
X+
X-
Y+
Y-
X+,Y+:SNSVDD=3VtoPin
X ,Y :PintoGND- -
Temperature( C)°
R( )W
ON
-40 -20
9
8
7
6
5
4
3
2
0 20 40 60 80 100
X+
X-
Y+
Y-
X+,Y+:SNSVDD=1.8VtoPin
X ,Y :PintoGND- -
Temperature( C)°
TEMPDiodeVoltage(mV)
-40 -20
850
800
750
700
650
600
550
500
450
400
0 20 40 60 80 100
95.3mV
138.2mV
TEMP2
TEMP1
I/OVDD=SNSVDD=3V
V =2.5V
REF
MeasurementIncludes
A/DConverterOffset
andGainErrors
1.2 1.6 2.0 2.4 2.8 3.2 3.6
SNSVDD(V)
11
10
9
8
7
6
5
4
3
R ( )W
ON
X+,Y+:SNSVDDtoPin
X ,Y :PintoGND- -
T =+25 C°
A
X+
Y+
Y-
X-
1.2 1.6 2.0 2.4 2.8 3.2 3.6
SNSVDD(V)
590
588
586
584
582
580
578
TEMP1DiodeVoltage(mV)
SNSVDD=IOVDD=VREF
TA=+25°C
MeasurementIncludes
A/DConverterOffset
andGainErrors
1.2 1.6 2.0 2.4 2.8 3.2 3.6
SNSVDD(V)
706
704
702
700
698
696
694
TEMP2DiodeVoltage(mV)
SNSVDD=IOVDD=VREF
TA=+25°C
MeasurementIncludes
A/DConverterOffset
andGainErrors
TSC2004
SBAS408E – JUNE 2007 – REVISED MARCH 2008
TYPICAL CHARACTERISTICS (continued)At T
A
= – 40 °C to +85 °C, SNSVDD = V
REF
= +1.2V to +3.6V, I/OVDD = +1.2V to +3.6V, f
ADC
= f
OSC
/2,High-Speed mode (f
SCL
= 3.4MHz), 12-bit mode, and non-continuous AUX measurement, unless otherwise noted.
SWITCH ON-RESISTANCE SWITCH ON-RESISTANCEvs TEMPERATURE vs TEMPERATURE
Figure 14. Figure 15.
SWITCH ON-RESISTANCE TEMP DIODE VOLTAGEvs SNSVDD SUPPLY VOLTAGE vs TEMPERATURE
Figure 16. Figure 17.
TEMP1 DIODE VOLTAGE TEMP2 DIODE VOLTAGEvs SNSVDD SUPPLY VOLTAGE vs SNSVDD SUPPLY VOLTAGE
Figure 18. Figure 19.
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-40 -20 0 20 40 60 80 100
Temperature( C)°
4.20
4.15
4.10
4.05
4.00
3.95
InternalClockFrequency(MHz)
SNSVDD=I/OVDD=V =3.0V
REF
-40 -20 0 20 40 60 80 100
Temperature( C)°
3.90
3.85
3.80
3.75
3.70
InternalClockFrequency(MHz)
SNSVDD=I/OVDD=V =1.6V
REF
-40 -20 0 20 40 60 80 100
Temperature( C)°
3.50
3.40
3.30
3.20
3.10
3.00
2.90
InternalClockFrequency(MHz)
SNSVDD=I/OVDD=V =1.2V
REF
1.2 1.6 2.0 2.4 2.8 3.2 3.6
SNSVDD(V)
4.20
4.10
4.00
3.90
3.80
3.70
3.60
3.50
3.40
3.30
3.20
InternalClockFrequency(MHz)
SNSVDD=I/OVDD=VREF
T =+25 C°
A
TSC2004
SBAS408E – JUNE 2007 – REVISED MARCH 2008
TYPICAL CHARACTERISTICS (continued)At T
A
= – 40 °C to +85 °C, SNSVDD = V
REF
= +1.2V to +3.6V, I/OVDD = +1.2V to +3.6V, f
ADC
= f
OSC
/2,High-Speed mode (f
SCL
= 3.4MHz), 12-bit mode, and non-continuous AUX measurement, unless otherwise noted.
INTERNAL OSCILLATOR CLOCK FREQUENCY INTERNAL OSCILLATOR CLOCK FREQUENCYvs TEMPERATURE vs TEMPERATURE
Figure 20. Figure 21.
INTERNAL OSCILLATOR CLOCK FREQUENCY INTERNAL OSCILLATOR CLOCK FREQUENCYvs TEMPERATURE vs SNSVDD SUPPLY VOLTAGE
Figure 22. Figure 23.
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OVERVIEW
TSC2004
SBAS408E – JUNE 2007 – REVISED MARCH 2008
The TSC2004 is an analog interface circuit for a human interface touch screen device. A register-basedarchitecture eases integration with microprocessor-based systems through a standard I
2
C bus. All peripheralfunctions are controlled through the registers and onboard state machines. The TSC2004 features include:•Very low-power touch screen controller•Very small onboard footprint•Relieves host from tedious routine tasks by flexible preprocessing, saving resources for more critical tasks•Ability to work on very low supply voltage•Minimal connection interface allows easiest isolation and reduces the number of dedicated I/O pins required•Miniature, yet complete; requires no external supporting component. ( NOTE: Although the TSC2004 can usean external reference, it is also possible to use SNSVDD as the reference.)•Enhanced ESD protection
The TSC2004 consists of the following blocks (refer to the block diagram on the front page):•Touch Screen Interface•Auxiliary Input (AUX)•Temperature Sensor•Acquisition Activity Preprocessing•Internal Conversion Clock•I
2
C Interface
Communication with the TSC2004 is done via an I
2
C serial interface. The TSC2004 is an I
2
C slave device;therefore, data are shifted into or out of the TSC2004 under the control of the host microprocessor, which alsoprovides the serial data clock.
Control of the TSC2004 and its functions is accomplished by writing to different registers in the TSC2004. Asimple command protocol (compatible with I
2
C) is used to address these registers. This protocol can be an I
2
Cwrite-addressing followed by multiple control bytes, or multiple combinations of control/data bytes to be writteninto different registers (two bytes each). Reading from registers is performed by writing an I
2
C read-addressing tothe TSC, followed by one or multiple sequential reads from the registers.
The address of the register to be read can be written in TSC Control Byte 0 with the register address andread-bit (as described in the previous paragraph), and serves as a pointer to the register map where the firstread starts. This designated register address is static; there is no need to write a register address again unless itis overwritten by a new register address, or if the TSC is reset (by a software reset or by the RESET pin).
The measurement result is placed in the TSC2004 registers and may be read by the host at any time. Thispreprocessing frees up the host so that resources can be redirected for more critical tasks. Two optional signalsare also available from the TSC2004 to indicate that data are available for the host to read. PINTDAV is aprogrammable interrupt/status output pin. When PINTDAV is programmed as a DAV output, it indicates that anA/D conversion has completed and that data are available. When this pin is programmed as a PENIRQ output, itindicates that a touch has been detected on the touch screen. The status register of the TSC2004 provides anextended status reading including the state of DAV and PENIRQ without the cost of any dedicated pin. Figure 24shows a typical application of the TSC2004.
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X+
Y+
X-
Y-
AuxilaryInput
AGND
AGND
TSC2004
SNSGND
DGND
1 Fm
1.6VDC
0.1 Fm
Touch
Screen
GPIO
GPIO
SDA
SCL
Host
Processor
PINTDAV
RESET
SDA
SCL
SNSVDD
VREF
I/OVDD
AUX
SNSGND
AGND
SUBGND
DGND
1 Fm0.1 Fm
1 Fm0.1 Fm
( isoptional;
softwareimplementation
pollingoftheStatus
registerispossible)
PINTDAV
AD1
AD0
1.2kW
1.6VDC
1.2kW
TOUCH SCREEN OPERATION
4-WIRE TOUCH SCREEN COORDINATE PAIR MEASUREMENT
ConductiveBar
InsulatingMaterial(Glass)
Silver
Ink
TransparentConductor(ITO)
BottomSide
Transparent
Conductor(ITO)
TopSide
X+
X-
Y+
Y-
ITO=IndiumTinOxide
TSC2004
SBAS408E – JUNE 2007 – REVISED MARCH 2008
Figure 24. Typical Circuit Configuration
A resistive touch screen operates by applying a voltage across a resistor network and measuring the change inresistance at a given point on the matrix where the screen is touched by an input (stylus, pen, or finger). Thechange in the resistance ratio marks the location on the touch screen.
The TSC2004 supports the resistive 4-wire configurations, as shown in Figure 25 . The circuit determines locationin two coordinate pair dimensions, although a third dimension can be added for measuring pressure.
A 4-wire touch screen is typically constructed as shown in Figure 25 . It consists of two transparent resistivelayers separated by insulating spacers.
Figure 25. 4-Wire Touch Screen Construction
The 4-wire touch screen panel works by applying a voltage across the vertical or horizontal resistive network.
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RTOUCH +RX−plate @XPostition
4096 ǒZ2
Z1*1Ǔ
(1)
RTOUCH +RX−plate @XPostition
4096 ǒ4096
Z1*1Ǔ*RY−plate @ǒ1*YPosition
4096 Ǔ
(2)
X-Position
MeasureX-Position
MeasureZ -Position
1
Touch
X+ Y+
X-Y-
Z -Position
1
Touch
X+ Y+
Y-X-
MeasureZ -Position
2
Z -Position
2
Touch
X+ Y+
Y-X-
TSC2004
SBAS408E – JUNE 2007 – REVISED MARCH 2008
The A/D converter converts the voltage measured at the point where the panel is touched. A measurement of theY position of the pointing device is made by connecting the X+ input to a data converter chip, turning on the Y+and Y – drivers, and digitizing the voltage seen at the X+ input. The voltage measured is determined by thevoltage divider developed at the point of touch. For this measurement, the horizontal panel resistance in the X+lead does not affect the conversion because of the high input impedance of the A/D converter.
Voltage is then applied to the other axis, and the A/D converter converts the voltage representing the X positionon the screen. This process provides the X and Y coordinates to the associated processor.
Measuring touch pressure (Z) can also be done with the TSC2004. To determine pen or finger touch, thepressure of the touch must be determined. Generally, it is not necessary to have very high performance for thistest; therefore, 10-bit resolution mode is recommended (however, data sheet calculations are shown using the12-bit resolution mode). There are several different ways of performing this measurement. The TSC2004supports two methods. The first method requires knowing the X-plate resistance, the measurement of theX-Position, and two additional cross panel measurements (Z
2
and Z
1
) of the touch screen (see Figure 26 ).Equation 1 calculates the touch resistance:
The second method requires knowing both the X-plate and Y-plate resistance, measurement of X-Position andY-Position, and Z
1
.Equation 2 also calculates the touch resistance:
Figure 26. Pressure Measurement
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TSC2004
SBAS408E – JUNE 2007 – REVISED MARCH 2008
When the touch panel is pressed or touched and the drivers to the panel are turned on, the voltage across thetouch panel often overshoots and then slowly settles down (decays) to a stable dc value. This effect is a result ofmechanical bouncing caused by vibration of the top layer sheet of the touch panel when the panel is pressed.This settling time must be accounted for, or else the