TSC2004IRTJR - Texas Instruments - Datasheet.Directory

TSC2004

 

  

FEATURES APPLICATIONS

DESCRIPTION

Pre-Processing

PINTDAV

I C

Serial

Interface

and

Control

SDA

AD0

RESET

VREF

X+

X-

Y+

Y-

AUX

TEMP

Mux

PENIRQ

DAV

SAR

ADC

Internal

Clock

Touch

Screen

Drivers

Interface

SCL

AD1

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

1.2V to 3.6V, 12-Bit, Nanopower, 4-WireTOUCH SCREEN CONTROLLER with I

C™ Interface

•Cellular Phones23

•4-Wire Touch Screen Interface

•Portable Instruments•Ratiometric Conversion

•MP3 Players, Pagers•Single 1.2V to 3.6V Supply

•Multiscreen Touch Control•Preprocessing to Reduce Bus Activity•High-Speed I

C-Compatible Interface•Internal Detection of Screen Touch

The TSC2004 is a very low-power touch screen•Register-Based Programmable:

controller designed to work with power-sensitive,– 10-Bit or 12-Bit Resolution

handheld applications that are based on advancedlow-voltage processors. It works with a supply voltage– Sampling Rates

as low as 1.2V, which can be supplied by a– System Timing

single-cell battery. It contains a complete,•On-Chip Temperature Measurement

ultralow-power, 12-bit, analog-to-digital (A/D) resistivetouch screen converter, including drivers and the•Touch Pressure Measurement

control logic to measure touch pressure.•Auto Power-Down Control

In addition to these standard features, the TSC2004•Low Power:

offers preprocessing of the touch screen– 760 µW at 1.8V, 50SSPS

measurements to reduce bus loading, thus reducing– 580 µW at 1.6V, 50SSPS

the consumption of host processor resources that canthen be redirected to more critical functions.– 285 µW at 1.2V, 50SSPS– 74 µW at 1.6V, 8.2kSPS Eq. Rate

The TSC2004 supports an I

C serial bus and datatransmission protocol in all three defined modes:– 47 µW at 1.2V, 8.2kSPS Eq. Rate

standard, fast, and high-speed. It offers•Enhanced ESD Protection:

programmable resolution of 10 or 12 bits to– ± 8kV HBM

accommodate different screen sizes and performanceneeds.– ± 1kV CDM– ± 25kV Air Gap Discharge

The TSC2004 is available in a miniature, 18-lead,5 x 5 array, (2.554 ± 0.54)mm x (2.554 ± 0.54)mm– ± 12kV Contact Discharge

wafer chip-scale package (WCSP), and a 20-pin, 4 x•2.5 x 2.5 WCSP-18 and 4 x 4 QFN-20 Packages

4 QFN package. Both packages are characterized forU.S. Patent No. 6,246,394; other patents pending.

the – 40 °C to +85 °C industrial temperature range.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2I2C is a trademark of NXP Semiconductors.3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Copyright © 2007 – 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

www.ti.com

ABSOLUTE MAXIMUM RATINGS

(1)

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION

(1)

TYPICAL TYPICAL NO MISSINGINTEGRAL GAIN CODES SPECIFIED TRANSPORTLINEARITY ERROR RESOLUTION PACKAGE PACKAGE TEMPERATURE PACKAGE ORDERING MEDIA,PRODUCT (LSB) (LSB) (BITS) TYPE DESIGNATOR RANGE MARKING NUMBER QUANTITY

Small TapeTSC2004IRTJT20-Pin,

and Reel, 2500.8 x 4 x 4 RTJ – 40 °C to +85 °C TSC2004I

Tape andThin QFN

TSC2004IRTJR

Reel, 3000TSC2004 – 0.8 to +1.4 +0.1 11

18-Pin, Small Ta\peTSC2004IYZKT5 x 5 Matrix, and Reel, 2502.5 x 2.5 YZK – 40 °C to +85 °C TSC2004I

Tape andDSBGA

TSC2004IYZKR

Reel, 3000(WCSP)

(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or seethe TI website at www.ti.com.

Over operating free-air temperature range (unless otherwise noted).

TSC2004 UNIT

Analog input X+, Y+, AUX to SNSGND – 0.4 to SNSVDD + 0.1 VAnalog input X – , Y – to SNSGND – 0.4 to SNSVDD + 0.1 VSNSVDD to SNSGND – 0.3 to 5 VVoltage range

SNSVDD to AGND – 0.3 to 5 VI/OVDD to DGND – 0.3 to 5 VSNSVDD to I/OVDD – 2.40 to +0.3 VDigital input voltage to DGND – 0.3 to I/OVDD + 0.3 VDigital output voltage to DGND – 0.3 to I/OVDD + 0.3 VPower dissipation (T

Max - T

)/ θ

Low-K 113 °C/WWCSP packageThermal impedance, θ

High-K 62 °C/WQFN package 39.97 °C/WOperating free-air temperature range, T

– 40 to +85 °CStorage temperature range, T

STG

– 65 to +150 °CJunction temperature, T

Max +150 °CVapor phase (60 sec) +215 °CLead temperature

Infrared (15 sec) +220 °CIEC contact discharge

(2)

X+, X – , Y+, Y – ± 12 kVIEC air discharge

(2)

X+, X – , Y+, Y – ± 25 kV

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure toabsolute-maximum rated conditions for extended periods may affect device reliability.(2) Test method based on IEC standard 61000-4-2. Contact Texas Instruments for test details.

Product Folder Link(s): TSC2004

www.ti.com

ELECTRICAL CHARACTERISTICS

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

At T

= – 40 °C to +85 °C, SNSVDD = V

REF

= +1.2V to +3.6V, I/OVDD

(1)

= +1.2V to +3.6V, unless otherwise noted.

TSC2004

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

AUXILIARY ANALOG INPUT

Input voltage range 0 VREF V

Input capacitance 12 pF

Input leakage current – 1 +1 µA

A/D CONVERTER

Resolution Programmable: 10 or 12 bits 12 Bits

No missing codes 12-bit resolution 11 Bits

Integral linearity – 3 – 0.8 to +1.4 +3 LSB

(2)

Differential linearity – 2 – 0.6 to +0.7 +4 LSB

TSC2004IRTJ – 5 2.2 5 LSBSNSVDD = 1.6V, V

REF

= 1.6V,Offset error

High-Speed mode, filter off

TSC2004IYZK 2.2 LSB

TSC2004IRTJ – 3 0.1 +3SNSVDD = 1.6V, V

REF

= 1.6V,Gain error LSBHigh-Speed mode, filter off

TSC2004IYZK 0.1

REFERENCE INPUT

REF

range 1.2 SNSVDD V

Non-continuous AUX mode, SNSVDD = V

REF

= 1.6V,VREF input current drain 1.2 µAT

= +25 °C, f

ADC

= 2MHz, High-Speed mode

Input impedance A/D converter not converting 1 G Ω

TOUCH SENSORS

PENIRQ 50k Ωpull-up

= +25 °C, SNSVDD = V

REF

= 1.6V 47 k Ωresistor, R

IRQ

Y+, X+ T

= +25 °C, SNSVDD = V

REF

= 1.6V 6 ΩSwitch

on-resistance

Y – , X – T

= +25 °C, SNSVDD = V

REF

= 1.6V 5 Ω

Switch drivers drive

100ms duration 50 mAcurrent

(3)

INTERNAL TEMPERATURE SENSOR

Temperature range – 40 +85 °C

SNSVDD = 1.6V 0.3 °C/LSBDifferential method

(4)

SNSVDD = 3V 1.6 °C/LSBResolution

SNSVDD = 1.6V 0.3 °C/LSBTEMP1

(5)

SNSVDD = 3V 1.6 °C/LSB

SNSVDD = 1.6V ± 3 °C/LSBDifferential method

(4)

SNSVDD = 3V ± 2 °C/LSBAccuracy

SNSVDD = 1.6V ± 3 °C/LSBTEMP1

(5)

SNSVDD = 3V ± 2 °C/LSB

INTERNAL OSCILLATOR

SNSVDD = 1.2V, T

= +25 °C 3.2 MHz

Clock frequency, f

OSC

SNSVDD = 1.6V 3.3 3.7 4.3 MHz

SNSVDD = 3.0V, T

= +25 °C 4.1 MHz

SNSVDD = 1.2V 0.118 %/ °C

Frequency drift SNSVDD = 1.6V – 0.018 %/ °C

SNSVDD = 3.0V – 0.032 %/ °C

(1) I/OVDD must be ≤SNSVDD.(2) LSB means Least Significant Bit. With V

REF

= +2.5V, one LSB is 610 µV.(3) Assured by design, but not tested. Exceeding 50mA source current may result in device degradation.(4) Difference between TEMP1 and TEMP2 measurement; no calibration necessary.(5) Temperature drift is – 2.1mV/ °C.

Product Folder Link(s): TSC2004

www.ti.com

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

ELECTRICAL CHARACTERISTICS (continued)At T

= – 40 °C to +85 °C, SNSVDD = V

REF

= +1.2V to +3.6V, I/OVDD = +1.2V to +3.6V, unless otherwise noted.

TSC2004

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DIGITAL INPUT/OUTPUT

Logic family CMOS

1.2V ≤I/OVDD < 1.6V 0.7 ×I/OVDD I/OVDD + 0.3 VV

1.6V ≤I/OVDD ≤3.6V 0.7 ×I/OVDD I/OVDD + 0.3 V

1.2V ≤I/OVDD < 1.6V – 0.3 0.2 ×I/OVDD VV

1.6V ≤I/OVDD ≤3.6V – 0.3 0.3 ×I/OVDD V

SCL and SDA pins – 1 1 µALogic level

SCL and SDA pins 10 pF

= 2 TTL loads I/OVDD – 0.2 I/OVDD V

= 2 TTL loads 0 0.2 V

LEAK

Floating output – 1 1 µA

OUT

Floating output 10 pF

Data format Straight Binary

POWER-SUPPLY REQUIREMENTS

Power-supply voltage

SNSVDD Specified performance 1.2 3.6 V

I/OVDD

(6)

1.2 SNSVDD V

Filter off, M = W = 1, C[3:0] =(1,0,0,0), RM = 1, CL[1:0] = (0,1),cont AUX mode, f

ADC

= 2MHz, SNSVDD = I/OVDD = V

REF

= 1.6V 506 625 µAHigh-Speed mode, withoutreading data register

= +25 °C, filter on, M = 15, W = SNSVDD = I/OVDD = V

REF

= 1.2V

237 µA7, PSM = 1, C[3:0] = (0,0,0,0), xRM = 1, CL[1:0] = (0,1), BTD[2:0]

SNSVDD = I/OVDD = V

REF

= 1.6V= (1,0,1), 50SSPS, MAVEX =

364 µAxMAVEY = MAVEZ = 1, f

ADC

=2MHz, High-Speed mode, sensor

SNSVDD = I/OVDD = V

REF

= 3.0V

797 µAdrivers supply included

= +25 °C, filter off, M = W = 1, SNSVDD = I/OVDD = V

REF

= 1.2V

237 µAPSM = 1, C[3:0] = (0,0,0,0), RM = x1, CL[1:0] = (0,1), BTD[2:0] =

SNSVDD = I/OVDD = V

REF

= 1.6V(1,0,1), 50SSPS, MAVEX =

342 µAxMAVEY = MAVEZ = 1, f

ADC

=2MHz, High-Speed mode, sensor

SNSVDD = I/OVDD = V

REF

= 3.0V

757 µAQuiescent supply

drivers supply includedcurrent

(7) (8)

SNSVDD = I/OVDD = V

REF

= 1.2V 176 µAT

= +25 °C, filter off, M = W = 1,C[3:0] = (0,1,0,1), RM = 1, CL[1:0]

SNSVDD = I/OVDD = V

REF

= 1.6V 268 µA= (0,1), non-cont AUX mode, f

ADC= 2MHz, High-Speed mode

SNSVDD = I/OVDD = V

REF

= 3.0V 526 µA

SNSVDD = I/OVDD = V

REF

= 1.2V,

347 µAT

= +25 °C, filter on, M = 7, W =

~10.3kSPS effective rate3, C[3:0] = (0,1,0,1), RM = 1,CL[1:0] = (0,1), MAVEAUX = 1, SNSVDD = I/OVDD = V

REF

= 1.6V,

468 µAnon-cont AUX mode, f

ADC

= ~11.8kSPS effective rate2MHz, High-Speed mode, full

SNSVDD = I/OVDD = V

REF

= 3.0V,speed

897 µA~12.3kSPS effective rate

SNSVDD = I/OVDD = V

REF

= 1.2V,T

= +25 °C, filter on, M = 7, W =

39.4 µA~1.17kSPS effective rate3, C[3:0] = (0,1,0,1), RM = 1,CL[1:0] = (0,1), MAVEAUX = 1,

SNSVDD = I/OVDD = V

REF

= 1.6V,non-cont AUX mode, f

ADC

= 46.4 µA~1.17kSPS effective rate2MHz, High-Speed mode,reduced speed (8.2kSPS

SNSVDD = I/OVDD = V

REF

= 3.0V,

85.3 µAequivalent rate)

~1.17kSPS effective rate

= +25 °C, Not addressed, SCL = SDA = 1,Power-down supply current 0.023 0.8 µASNSVDD = I/OVDD = V

REF

= 1.6V

(6) I/OVDD must be ≤SNSVDD.(7) Supply current from SNSVDD.(8) For detailed information on test condition parameter and bit settings, see the Digital Interface section.

Product Folder Link(s): TSC2004

www.ti.com

PIN CONFIGURATIONS

SNSGND

AD0

TSC2004

ThermalPad

12345

15 14 13 12 11

AGND

AUX

I/OVDD

DGND

SUBGND

Y+

X+

SNSVDD

VREF

SDA

SCL

AD1

PINTDAV

RESET

Columns

(FRONT VIEW)

ACEB D

NCAD1 SNSGNDNCDGND

NCNC Y-

I/OVDD

SUBGNDNC

X-

AUX

X+VREF Y+

SNSVDD

AGND

SDA

PINTDAV

AD0

SCL

RESET

Rows

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

RTJ PACKAGE

(1)

YZK PACKAGEQFN-20

WCSP-18(TOP VIEW)

(TOP VIEW, SOLDER BUMPS ON BOTTOM SIDE)

(1) The thermal pad is internally connected toSUBGND. The thermal pad can beconnected to the analog ground or leftfloating. Keep the thermal pad separatefrom the digital ground, if possible.

PIN ASSIGNMENTSPIN NO.

PINQFN WCSP NAME I/O A/D DESCRIPTION

1 D1 SDA I/O D Serial data I/O

2 C1 SCL I D Serial clock.

3 B2 AD1 I D Address input bit 1

4 A1 PINTDAV O D Interrupt output. Data available or PENIRQ, depending on setting. Pin polarity with active low.

5 B1 RESET I D System reset. All register values reset to default values.

6 A2 DGND Digital ground

7 A3 I/OVDD Digital I/O interface voltage

B3, B4,

No internal connection, but solder bumps are populated. These pins may be connected to analog ground8, 19 C2, C3, NC

for mechanical stability.D2, D3

9 A4 AUX I A Auxiliary channel input

10 A5 AGND Analog ground

11 B5 VREF I A External reference input

12 C5 SNSVDD Power supply for sensor drivers and other analog blocks.

13 D5 X+ I A X+ channel input

14 E5 Y+ I A Y+ channel input

15 D4 SUBGND Substrate ground (for ESD current). Connection to AGND (on the PCB) is recommended.

16 E4 X – I A X – channel input

17 E3 Y – I A Y – channel input

18 E2 SNSGND Sensor driver return

20 E1 AD0 I D Address input bit 0

— C4 NC No solder bump for this location.

Product Folder Link(s): TSC2004

www.ti.com

TIMING INFORMATION

tHD, STA

tSU, DAT

tHD, DAT

tSU, STA

tSU, STO

tHD, STA

tLOW

tHIGH

tRtF

tBUF

SDA

SCL

S Sr P S

S=STARTCondition

Sr=RepeatedSTARTCondition

P=STOPCondition

=ResistorPull-Up

SDA

tFDA

tRDA

tSU, STA tHD, STA

SCL

tHD, DAT

tSU, DAT

tRCL1

(1) tRCL1

(1)

tHIGH tLOW tLOW

tRCL

tFCL

tHIGH

tSU, STO

=CurrentSourcePull-Up

=ResistorPull-Up

NOTE:(1)FirstrisingedgeoftheSCLsignalafterSrandaftereachacknowledgebit.

Sr=RepeatedSTARTCondition

P=STOPCondition

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

Figure 1. Detailed I/O Timing for Standard and Fast Modes

Figure 2. Detailed I/O Timing for High-Speed Mode

Product Folder Link(s): TSC2004

www.ti.com

TIMING REQUIREMENTS for Figure 1 : I

C Standard Mode (f

SCL

= 100kHz)

(1)

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

All specifications typical at – 40 °C to +85 °C, SNSVDD = I/OVDD = +1.2V to +3.6V, unless otherwise noted.

2-WIRE STANDARD MODE PARAMETERS TEST CONDITIONS MIN MAX UNIT

SNSVDD ≥1.6V 10 µsReset low time

(2)

WL(RESET)

1.2V ≤SNSVDD < 1.6V 13 µs

SCL clock frequency f

SCL

100 kHz

Bus free time between a STOP and START

BUF

4.7 µscondition

Hold time (repeated) START condition t

HD, STA

4.0 µs

Low period of SCL clock t

LOW

4.7 µs

High period of the SCL clock t

HIGH

4.0 µs

Setup time for a repeated START condition t

SU, STA

4.7 µs

Data hold time t

HD, DAT

0 3.45 µs

Data setup time t

SU, DAT

250 ns

Rise time of both SDA and SCL signals t

= total bus capacitance 1000 ns

Fall time of both SDA and SCL signals t

= total bus capacitance 300 ns

Setup time for STOP condition t

SU, STO

4.0 µs

Capacitive load for each bus line C

= total capacitance of one bus line in pF 400 pF

Pulse width of spike suppressed t

N/A N/A ns

(1) All input signals are specified with t

= t

= 5ns (30% to 70% of I/OVDD) and timed from a voltage level of (V

+ V

)/2.(2) Refer to Figure 38 .

TIMING REQUIREMENTS for Figure 1 : I

C Fast Mode (f

SCL

= 400kHz)

(1)

All specifications typical at – 40 °C to +85 °C, SNSVDD = I/OVDD = +1.2V to +3.6V, unless otherwise noted.

2-WIRE FAST MODE PARAMETERS TEST CONDITIONS MIN MAX UNIT

SNSVDD ≥1.6V 10 µsReset low time

(2)

WL(RESET)

1.2V ≤SNSVDD < 1.6V 13 µs

SCL clock frequency f

SCL

400 kHz

Bus free time between a STOP and START

BUF

1.3 µscondition

Hold time (repeated) START condition t

HD, STA

0.6 µs

Low period of SCL clock t

LOW

1.3 µs

High period of the SCL clock t

HIGH

0.6 µs

Setup time for a repeated START condition t

SU, STA

0.6 µs

Data hold time t

HD, DAT

0 0.9 µs

Data setup time t

SU, DAT

100 ns

Rise time of both SDA and SCL signals t

= total bus capacitance 20 + 0.1 ×C

300 ns

Fall time of both SDA and SCL signals t

= total bus capacitance 20 + 0.1 ×C

300 ns

Setup time for STOP condition t

SU, STO

0.6 µs

Capacitive load for each bus line C

= total capacitance of one bus line in pF 400 pF

Pulse width of spike suppressed t

0 50 ns

(1) All input signals are specified with t

= t

= 5ns (30% to 70% of I/OVDD) and timed from a voltage level of (V

+ V

)/2.(2) Refer to Figure 38 .

Product Folder Link(s): TSC2004

www.ti.com

TIMING REQUIREMENTS for Figure 2 : I

C High-Speed Mode (f

SCL

= 1.7MHz)

(1)

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

All specifications typical at – 40 °C to +85 °C, SNSVDD = I/OVDD = +1.2V to +3.6V, unless otherwise noted.

2-WIRE HIGH-SPEED MODE PARAMETERS TEST CONDITIONS MIN MAX UNIT

SNSVDD ≥1.6V 10 µsReset low time

(2)

WL(RESET)

1.2V ≤SNSVDD < 1.6V 13 µs

SCL clock frequency f

SCL

1.7 MHz

Hold time (repeated) START condition t

HD, STA

160 ns

Low period of SCL clock t

LOW

320 ns

High period of the SCL clock t

HIGH

120 ns

Setup time for a repeated START condition t

SU, STA

160 ns

Data hold time t

HD, DAT

0 150 ns

Data setup time t

SU, DAT

10 ns

Rise time of SCL signal t

RCL

= total bus capacitance 20 80 ns

Rise time of SDA signal t

RDA

= total bus capacitance 20 160 ns

Fall time of SCL signal t

FCL

= total bus capacitance 20 80 ns

Fall time of SDA signal t

FDA

= total bus capacitance 20 160 ns

Rise time of SCL signal after a repeated START

RCL1

= total bus capacitance 20 160 nscondition and after an acknowledge bit

Setup time for STOP condition t

SU, STO

160 ns

Capacitive load for each bus line C

= total capacitance of one bus line in pF 400 pF

Pulse width of spike suppressed t

0 10 ns

(1) All input signals are specified with t

= t

= 5ns (30% to 70% of V

) and timed from a voltage level of (V

+ V

)/2.(2) Refer to Figure 38 .

TIMING REQUIREMENTS for Figure 2 : I

C High-Speed Mode (f

SCL

= 3.4MHz)

(1)

All specifications typical at – 40 °C to +85 °C, SNSVDD = I/OVDD = +1.2V

(2)

to +3.6V, unless otherwise noted.

2-WIRE HIGH-SPEED MODE PARAMETERS TEST CONDITIONS MIN MAX UNIT

SNSVDD ≥1.6V 10 µsReset low time

(3)

WL(RESET)

1.2V ≤SNSVDD < 1.6V 13 µs

SCL clock frequency f

SCL

3.4 MHz

Hold time (repeated) START condition t

HD, STA

160 ns

Low period of SCL clock t

LOW

160 ns

High period of the SCL clock t

HIGH

60 ns

Setup time for a repeated START condition t

SU, STA

160 ns

Data hold time t

HD, DAT

0 70 ns

Data setup time t

SU, DAT

10 ns

Rise time of SCL signal t

RCL

= total bus capacitance 10 40 ns

Rise time of SDA signal t

RDA

= total bus capacitance 10 80 ns

Fall time of SCL signal t

FCL

= total bus capacitance 10 40 ns

Fall time of SDA signal t

FDA

= total bus capacitance 10 80 ns

Rise time of SCL signal after a repeated START

RCL1

= total bus capacitance 10 80 nscondition and after an acknowledge bit

Setup time for STOP condition t

SU, STO

160 ns

Capacitive load for each bus line C

= total capacitance of one bus line in pF 100 pF

Pulse width of spike suppressed t

0 10 ns

(1) All input signals are specified with t

= t

= 5ns (30% to 70% of I/OVDD) and timed from a voltage level of (V

+ V

)/2.(2) Because of the low supply voltage of 1.2V and the wide temperature range of – 40 °C to +85 °C, the I

C system devices may not reachthe maximum specification of I

C High-Speed mode, and f

SCL

may not reach 3.4Mhz.(3) Refer to Figure 38 .

Product Folder Link(s): TSC2004

www.ti.com

TYPICAL CHARACTERISTICS

-40 -20 0 20 40 60 80 100

Temperature( C)°

1.5

1.0

0.5

-0.5

-1.0

-1.5

Deltafrom+25 C(LSB)°

SNSVDD=IOVDD=VREF

SNSVDD=1.2V

SNSVDD=1.6V

SNSVDD=3.0V

-40 -20 0 20 40 60 80 100

Temperature( C)°

1.5

1.0

0.5

-0.5

-1.0

-1.5

Deltafrom+25 C(LSB)°

SNSVDD=I/OVDD=VREF

SNSVDD=1.2V

SNSVDD=1.6V

SNSVDD=3.0V

-40 -20 0 20 40 60 80 100

Temperature( C)°

650

550

450

350

250

150

SNSVDDSupplyCurrent( A)m

SNSVDD=3.0V

I/OVDD=SNSVDD=VREF

SNSVDD=1.6V

SNSVDD=1.2V

1.2 1.6 2.0 2.4 2.8 3.2 3.6

SNSVDD(V)

1.00

0.75

0.50

0.25

SNSVDDSupplyCurrent(mA)

I/OVDD=SNSVDD=VREF

T =+25 C°

f =2MHz

ADC

f =1MHz

ADC

1.2 1.6 2.0 2.4 2.8 3.2 3.6

SNSVDD(V)

1.2

1.0

0.8

0.6

0.4

0.2

SNSVDDSupplyCurrent(mA)

TouchSensorModeledBy:

2k forY-PlaneW

1kWforZ(TouchResistance)(2)

M=15,W=7(1)

M=1,W=1(1)

I/OVDD=SNSVDD=VREF

TA=+25°C

t ,t ,t

PVS PRE SNS =defaultvalues

TSC-InitiatedModeScanX,Y,Zat50SSPS

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

At T

= – 40 °C to +85 °C, SNSVDD = V

REF

= +1.2V to +3.6V, I/OVDD = +1.2V to +3.6V, f

ADC

= f

OSC

/2,High-Speed mode (f

SCL

= 3.4MHz), 12-bit mode, and non-continuous AUX measurement, unless otherwise noted.

CHANGE IN OFFSET CHANGE IN GAINvs TEMPERATURE vs TEMPERATURE

Figure 3. Figure 4.

SNSVDD SUPPLY CURRENT SNSVDD SUPPLY CURRENTvs TEMPERATURE vs SNSVDD SUPPLY VOLTAGE

Figure 5. Figure 6.

SNSVDD SUPPLY CURRENTvs SNSVDD SUPPLY VOLTAGE

(1) See Table 1(2) See Figure 26

Figure 7.

Product Folder Link(s): TSC2004

www.ti.com

-40 -20 0 20 40 60 80 100

Temperature(°C)

Power-DownSupplyCurrent(nA)

1000

800

600

400

200

SNSVDD=1.6V

SNSVDD=3.6V

SNSVDD=3.0V

SNSVDD=I/OVDD=VREF

1.2 1.6 2.0 2.4 2.8 3.2 3.6

SNSVDD(V)

Power-DownSupplyCurrent(nA)

SNSVDD=I/OVDD=VREF

T =+25 C°

-40 -20 0 20 40 60 80 100

Temperature( C)°

I/OVDDSupplyCurrent( A)m

I/OVDD=SNSVDD=VREF

I/OVDD=1.6V

I/OVDD=1.2V

1.2 1.6 2.0 2.4 2.8 3.2 3.6

I/OVDD(V)

I/OVDDSupplyCurrent( A)m

I/OVDD=SNSVDD=VREF

T =+25 C

A°

f =2MHz

ADC

f =1MHz

ADC

-40 -20 0 20 40 60 80 100

Temperature(°C)

2.0

1.5

1.0

0.5

ReferenceInputCurrent( A)m

SNSVDD=I/OVDD=VREF

SNSVDD=1.2V

SNSVDD=1.6V

1.2 1.6 2.0 2.4 2.8 3.2 3.6

SNSVDD(V)

4.0

3.0

2.0

1.0

ReferenceInputCurrent( A)m

SNSVDD=I/OVDD=VREF

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

TYPICAL CHARACTERISTICS (continued)At T

= – 40 °C to +85 °C, SNSVDD = V

REF

= +1.2V to +3.6V, I/OVDD = +1.2V to +3.6V, f

ADC

= f

OSC

/2,High-Speed mode (f

SCL

= 3.4MHz), 12-bit mode, and non-continuous AUX measurement, unless otherwise noted.

POWER-DOWN SUPPLY CURRENT POWER-DOWN SUPPLY CURRENTvs TEMPERATURE vs SNSVDD SUPPLY VOLTAGE

Figure 8. Figure 9.

I/OVDD SUPPLY CURRENT I/OVDD SUPPLY CURRENTvs TEMPERATURE vs I/OVDD SUPPLY VOLTAGE

Figure 10. Figure 11.

REFERENCE INPUT CURRENT REFERENCE INPUT CURRENTvs TEMPERATURE vs SNSVDD SUPPLY VOLTAGE

Figure 12. Figure 13.

Product Folder Link(s): TSC2004

www.ti.com

Temperature( C)°

R( )W

-40 -20

0 20 40 60 80 100

X+

X-

Y+

Y-

X+,Y+:SNSVDD=3VtoPin

X ,Y :PintoGND- -

Temperature( C)°

R( )W

-40 -20

0 20 40 60 80 100

X+

X-

Y+

Y-

X+,Y+:SNSVDD=1.8VtoPin

X ,Y :PintoGND- -

Temperature( C)°

TEMPDiodeVoltage(mV)

-40 -20

850

800

750

700

650

600

550

500

450

400

0 20 40 60 80 100

95.3mV

138.2mV

TEMP2

TEMP1

I/OVDD=SNSVDD=3V

V =2.5V

REF

MeasurementIncludes

A/DConverterOffset

andGainErrors

1.2 1.6 2.0 2.4 2.8 3.2 3.6

SNSVDD(V)

R ( )W

X+,Y+:SNSVDDtoPin

X ,Y :PintoGND- -

T =+25 C°

X+

Y+

Y-

X-

1.2 1.6 2.0 2.4 2.8 3.2 3.6

SNSVDD(V)

590

588

586

584

582

580

578

TEMP1DiodeVoltage(mV)

SNSVDD=IOVDD=VREF

TA=+25°C

MeasurementIncludes

A/DConverterOffset

andGainErrors

1.2 1.6 2.0 2.4 2.8 3.2 3.6

SNSVDD(V)

706

704

702

700

698

696

694

TEMP2DiodeVoltage(mV)

SNSVDD=IOVDD=VREF

TA=+25°C

MeasurementIncludes

A/DConverterOffset

andGainErrors

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

TYPICAL CHARACTERISTICS (continued)At T

= – 40 °C to +85 °C, SNSVDD = V

REF

= +1.2V to +3.6V, I/OVDD = +1.2V to +3.6V, f

ADC

= f

OSC

/2,High-Speed mode (f

SCL

= 3.4MHz), 12-bit mode, and non-continuous AUX measurement, unless otherwise noted.

SWITCH ON-RESISTANCE SWITCH ON-RESISTANCEvs TEMPERATURE vs TEMPERATURE

Figure 14. Figure 15.

SWITCH ON-RESISTANCE TEMP DIODE VOLTAGEvs SNSVDD SUPPLY VOLTAGE vs TEMPERATURE

Figure 16. Figure 17.

TEMP1 DIODE VOLTAGE TEMP2 DIODE VOLTAGEvs SNSVDD SUPPLY VOLTAGE vs SNSVDD SUPPLY VOLTAGE

Figure 18. Figure 19.

Product Folder Link(s): TSC2004

www.ti.com

-40 -20 0 20 40 60 80 100

Temperature( C)°

4.20

4.15

4.10

4.05

4.00

3.95

InternalClockFrequency(MHz)

SNSVDD=I/OVDD=V =3.0V

REF

-40 -20 0 20 40 60 80 100

Temperature( C)°

3.90

3.85

3.80

3.75

3.70

InternalClockFrequency(MHz)

SNSVDD=I/OVDD=V =1.6V

REF

-40 -20 0 20 40 60 80 100

Temperature( C)°

3.50

3.40

3.30

3.20

3.10

3.00

2.90

InternalClockFrequency(MHz)

SNSVDD=I/OVDD=V =1.2V

REF

1.2 1.6 2.0 2.4 2.8 3.2 3.6

SNSVDD(V)

4.20

4.10

4.00

3.90

3.80

3.70

3.60

3.50

3.40

3.30

3.20

InternalClockFrequency(MHz)

SNSVDD=I/OVDD=VREF

T =+25 C°

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

TYPICAL CHARACTERISTICS (continued)At T

= – 40 °C to +85 °C, SNSVDD = V

REF

= +1.2V to +3.6V, I/OVDD = +1.2V to +3.6V, f

ADC

= f

OSC

/2,High-Speed mode (f

SCL

= 3.4MHz), 12-bit mode, and non-continuous AUX measurement, unless otherwise noted.

INTERNAL OSCILLATOR CLOCK FREQUENCY INTERNAL OSCILLATOR CLOCK FREQUENCYvs TEMPERATURE vs TEMPERATURE

Figure 20. Figure 21.

INTERNAL OSCILLATOR CLOCK FREQUENCY INTERNAL OSCILLATOR CLOCK FREQUENCYvs TEMPERATURE vs SNSVDD SUPPLY VOLTAGE

Figure 22. Figure 23.

Product Folder Link(s): TSC2004

www.ti.com

OVERVIEW

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

The TSC2004 is an analog interface circuit for a human interface touch screen device. A register-basedarchitecture eases integration with microprocessor-based systems through a standard I

C bus. All peripheralfunctions are controlled through the registers and onboard state machines. The TSC2004 features include:•Very low-power touch screen controller•Very small onboard footprint•Relieves host from tedious routine tasks by flexible preprocessing, saving resources for more critical tasks•Ability to work on very low supply voltage•Minimal connection interface allows easiest isolation and reduces the number of dedicated I/O pins required•Miniature, yet complete; requires no external supporting component. ( NOTE: Although the TSC2004 can usean external reference, it is also possible to use SNSVDD as the reference.)•Enhanced ESD protection

The TSC2004 consists of the following blocks (refer to the block diagram on the front page):•Touch Screen Interface•Auxiliary Input (AUX)•Temperature Sensor•Acquisition Activity Preprocessing•Internal Conversion Clock•I

C Interface

Communication with the TSC2004 is done via an I

C serial interface. The TSC2004 is an I

C slave device;therefore, data are shifted into or out of the TSC2004 under the control of the host microprocessor, which alsoprovides the serial data clock.

Control of the TSC2004 and its functions is accomplished by writing to different registers in the TSC2004. Asimple command protocol (compatible with I

C) is used to address these registers. This protocol can be an I

Cwrite-addressing followed by multiple control bytes, or multiple combinations of control/data bytes to be writteninto different registers (two bytes each). Reading from registers is performed by writing an I

C read-addressing tothe TSC, followed by one or multiple sequential reads from the registers.

The address of the register to be read can be written in TSC Control Byte 0 with the register address andread-bit (as described in the previous paragraph), and serves as a pointer to the register map where the firstread starts. This designated register address is static; there is no need to write a register address again unless itis overwritten by a new register address, or if the TSC is reset (by a software reset or by the RESET pin).

The measurement result is placed in the TSC2004 registers and may be read by the host at any time. Thispreprocessing frees up the host so that resources can be redirected for more critical tasks. Two optional signalsare also available from the TSC2004 to indicate that data are available for the host to read. PINTDAV is aprogrammable interrupt/status output pin. When PINTDAV is programmed as a DAV output, it indicates that anA/D conversion has completed and that data are available. When this pin is programmed as a PENIRQ output, itindicates that a touch has been detected on the touch screen. The status register of the TSC2004 provides anextended status reading including the state of DAV and PENIRQ without the cost of any dedicated pin. Figure 24shows a typical application of the TSC2004.

Product Folder Link(s): TSC2004

www.ti.com

X+

Y+

X-

Y-

AuxilaryInput

AGND

TSC2004

SNSGND

DGND

1 Fm

1.6VDC

0.1 Fm

Touch

Screen

GPIO

SDA

SCL

Host

Processor

PINTDAV

RESET

SDA

SCL

SNSVDD

VREF

I/OVDD

AUX

SNSGND

AGND

SUBGND

DGND

1 Fm0.1 Fm

( isoptional;

softwareimplementation

pollingoftheStatus

PINTDAV

AD1

AD0

1.2kW

1.6VDC

1.2kW

TOUCH SCREEN OPERATION

4-WIRE TOUCH SCREEN COORDINATE PAIR MEASUREMENT

ConductiveBar

InsulatingMaterial(Glass)

Silver

Ink

TransparentConductor(ITO)

BottomSide

Transparent

Conductor(ITO)

TopSide

X+

X-

Y+

Y-

ITO=IndiumTinOxide

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

Figure 24. Typical Circuit Configuration

A resistive touch screen operates by applying a voltage across a resistor network and measuring the change inresistance at a given point on the matrix where the screen is touched by an input (stylus, pen, or finger). Thechange in the resistance ratio marks the location on the touch screen.

The TSC2004 supports the resistive 4-wire configurations, as shown in Figure 25 . The circuit determines locationin two coordinate pair dimensions, although a third dimension can be added for measuring pressure.

A 4-wire touch screen is typically constructed as shown in Figure 25 . It consists of two transparent resistivelayers separated by insulating spacers.

Figure 25. 4-Wire Touch Screen Construction

The 4-wire touch screen panel works by applying a voltage across the vertical or horizontal resistive network.

Product Folder Link(s): TSC2004

www.ti.com

RTOUCH +RX−plate @XPostition

4096 ǒZ2

Z1*1Ǔ

(1)

RTOUCH +RX−plate @XPostition

4096 ǒ4096

Z1*1Ǔ*RY−plate @ǒ1*YPosition

4096 Ǔ

(2)

X-Position

MeasureX-Position

MeasureZ -Position

Touch

X+ Y+

X-Y-

Z -Position

Touch

X+ Y+

Y-X-

MeasureZ -Position

Z -Position

Touch

X+ Y+

Y-X-

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

The A/D converter converts the voltage measured at the point where the panel is touched. A measurement of theY position of the pointing device is made by connecting the X+ input to a data converter chip, turning on the Y+and Y – drivers, and digitizing the voltage seen at the X+ input. The voltage measured is determined by thevoltage divider developed at the point of touch. For this measurement, the horizontal panel resistance in the X+lead does not affect the conversion because of the high input impedance of the A/D converter.

Voltage is then applied to the other axis, and the A/D converter converts the voltage representing the X positionon the screen. This process provides the X and Y coordinates to the associated processor.

Measuring touch pressure (Z) can also be done with the TSC2004. To determine pen or finger touch, thepressure of the touch must be determined. Generally, it is not necessary to have very high performance for thistest; therefore, 10-bit resolution mode is recommended (however, data sheet calculations are shown using the12-bit resolution mode). There are several different ways of performing this measurement. The TSC2004supports two methods. The first method requires knowing the X-plate resistance, the measurement of theX-Position, and two additional cross panel measurements (Z

and Z

) of the touch screen (see Figure 26 ).Equation 1 calculates the touch resistance:

The second method requires knowing both the X-plate and Y-plate resistance, measurement of X-Position andY-Position, and Z

.Equation 2 also calculates the touch resistance:

Figure 26. Pressure Measurement

Product Folder Link(s): TSC2004

www.ti.com

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

When the touch panel is pressed or touched and the drivers to the panel are turned on, the voltage across thetouch panel often overshoots and then slowly settles down (decays) to a stable dc value. This effect is a result ofmechanical bouncing caused by vibration of the top layer sheet of the touch panel when the panel is pressed.This settling time must be accounted for, or else the converted value will be in error. Therefore, a delay must beintroduced between the time the driver for a particular measurement is turned on, and the time a measurement ismade.

In some applications, external capacitors may be required across the touch screen for filtering noise picked up bythe touch screen (for example, noise generated by the LCD panel or back-light circuitry). The value of thesecapacitors provides a low-pass filter to reduce the noise, but will cause an additional settling time requirementwhen the panel is touched.

The TSC2004 offers several solutions to this problem. A programmable delay time is available that sets the delaybetween turning the drivers on and making a conversion. This delay is referred to as the panel voltagestabilization time, and is used in some of the TSC2004 modes. In other modes, the TSC2004 can becommanded to turn on the drivers only without performing a conversion. Time can then be allowed before thecommand is issued to perform a conversion.

The TSC2004 touch screen interface can measure position (X,Y) and pressure (Z). Determination of thesecoordinates is possible under three different modes of the A/D converter:•TSMode1 — conversion controlled by the TSC2004 initiated by the TSC;•TSMode2 — conversion controlled by the TSC2004 initiated by the host responding to the PENIRQ signal; or•TSMode3 — conversion completely controlled by the host processor.

Product Folder Link(s): TSC2004

www.ti.com

INTERNAL TEMPERATURE SENSOR

Converter

AGND

SNSVDD

TEMP1

TEMP2

+IN

-IN

DV+kT

q@ln(N)

(3)

T+q@DV

k@ln(N)

(4)

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

In some applications, such as battery recharging, an ambient temperature measurement is required. Thetemperature measurement technique used in the TSC2004 relies on the characteristics of a semiconductorjunction operating at a fixed current level. The forward diode voltage (V

) has a well-defined characteristicversus temperature. The ambient temperature can be predicted in applications by knowing the +25 °C value ofthe V

voltage and then monitoring the delta of that voltage as the temperature changes.

The TSC2004 offers two modes of temperature measurement. The first mode requires calibration at a knowntemperature, but only requires a single reading to predict the ambient temperature. The TEMP1 diode, shown inFigure 27 , is used during this measurement cycle. This voltage is typically 580mV at +25 °C with a 10 µA current.The absolute value of this diode voltage can vary by a few millivolts; the temperature coefficient (T

) of thisvoltage is very consistent at – 2.1mV/ °C. During the final test of the end product, the diode voltage is stored at aknown room temperature, in system memory, for calibration purposes by the user. The result is an equivalenttemperature measurement resolution of 0.3 °C/LSB (1LSB = 610 µV with V

REF

= 2.5V).

Figure 27. Functional Block Diagram of Temperature Measurement Mode

The second mode does not require a test temperature calibration, but uses a two-measurement (differential)method to eliminate the need for absolute temperature calibration and for achieving 2 °C/LSB accuracy. Thismode requires a second conversion of the voltage across the TEMP2 diode with a resistance 91 times largerthan the TEMP1 diode. The voltage difference between the first (TEMP1) and second (TEMP2) conversion isrepresented by:

Where:

N = the resistance ratio = 91.k = Boltzmann's constant = 1.3807 ×10

-23

J/K (joules/kelvins).q = the electron charge = 1.6022 ×10

-19

C (coulombs).T = the temperature in kelvins (K).

This method can provide much improved absolute temperature measurement, but a lower resolution of1.6 °C/LSB. The resulting equation to solve for T is:

Where:

ΔV = V

(TEMP2) – V

(TEMP1) (in mV).

∴T = 2.573 ⋅ΔV (in K),

or T = 2.573 ⋅ΔV – 273 (in °C).

Temperature 1 and/or temperature 2 measurements have the same timing as Figure 46 .

Product Folder Link(s): TSC2004

www.ti.com

ANALOG-TO-DIGITAL CONVERTER

Converter

-REF

+REF

+IN

-IN

AUX

SNSGND

AGND

X+

X-

SNSVDD

PenTouch

RIRQ

(1)

50kW

Y+

Y-

VREF PINTDAV

Preprocessing

Zone

Detect

Control

Logic

LevelShift

Data

Available

C3-C0

MAV

SNSVDD

AGND

TEMP1

TEMP2

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

Figure 28 shows the analog inputs of the TSC2004. The analog inputs (X, Y, and Z touch panel coordinates, chiptemperature and auxiliary inputs) are provided via a multiplexer to the Successive Approximation Register (SAR)Analog-to-Digital (A/D) converter. The A/D architecture is based on capacitive redistribution architecture, whichinherently includes a sample-and-hold function.

(1) Untrimmed resistor; see the typical value in the Electrical Characteristics

Figure 28. Simplified Diagram of the Analog Input Section

A unique configuration of low on-resistance switches allows an unselected A/D converter input channel toprovide power and an accompanying pin to provide ground for driving the touch panel. By maintaining adifferential input to the converter and a differential reference input architecture, it is possible to negate errorscaused by the driver switch on-resistances.

The A/D converter is controlled by two A/D Converter Control registers. Several modes of operation are possible,depending on the bits set in the control registers. Channel selection, scan operation, preprocessing, resolution,and conversion rate may all be programmed through these registers. These modes are outlined in the sectionsthat follow for each type of analog input. The conversion results are stored in the appropriate result register.

Product Folder Link(s): TSC2004

www.ti.com

Data Format

OutputCode

FS=Full-ScaleVoltage=VREF

(1)

1LSB=V /4096

REF

(1)

FS 1LSB-

11...111

11...110

11...101

00...010

00...001

00...000

1LSB

InputVoltage (V)

(2)

Reference

Variable Resolution

Conversion Clock and Conversion Time

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

The TSC2004 output data are in Straight Binary format as shown in Figure 29 . This figure shows the ideal outputcode for the given input voltage and does not include the effects of offset, gain, or noise.

(1) Reference voltage at converter: +REF – ( – REF). See Figure 28 .(2) Input voltage at converter, after multiplexer: +IN – ( – IN). See Figure 28 .

Figure 29. Ideal Input Voltages and Output Codes

The TSC2004 uses an external voltage reference that applied to the VREF pin. It is possible to use VDD as thereference voltage because the upper reference voltage range is the same as the supply voltage range.

The TSC2004 provides either 10-bit or 12-bit resolution for the A/D converter. Lower resolution is often practicalfor measuring slow changing signals such as touch pressure. Performing the conversions at lower resolutionreduces the amount of time it takes for the A/D converter to complete its conversion process, which also lowerspower consumption.

The TSC2004 contains an internal clock (oscillator) that drives the internal state machines that perform the manyfunctions of the part. This clock is divided down to provide a conversion clock for the A/D converter. The divisionratio for this clock is set in the A/D Converter Control register (see Table 15 ). The ability to change theconversion clock rate allows the user to choose the optimal values for resolution, speed, and power dissipation. Ifthe 4MHz (oscillator) clock is used directly as the A/D converter clock (when CL[1:0] = (0,0)), the A/D converterresolution is limited to 10 bits. Using higher resolutions at this speed does not result in more accurateconversions. 12-bit resolution requires that CL[1:0] is set to (0,1) or (1,0).

Regardless of the conversion clock speed, the internal clock runs nominally at 3.8MHz at a 3V supply (SNSVDD)and slows down to 3.6MHz at a 1.6V supply. The conversion time of the TSC2004 depends on several functions.While the conversion clock speed plays an important role in the time it takes for a conversion to complete, acertain number of internal clock cycles are needed for proper sampling of the signal. Moreover, additional times(such as the panel voltage stabilization time), can add significantly to the time it takes to perform a conversion.Conversion time can vary depending on the mode in which the TSC2004 is used. Throughout this data sheet,internal and conversion clock cycles are used to describe the amount of time that many functions take. Thesetimes must be taken into account when considering the total system design.

Product Folder Link(s): TSC2004

www.ti.com

Touch Detect

SNSGND

TEMP1

TEMP2

SNSVDD

PenTouch

X+

Y+

Y-

HighwhentheX+orY+

driverison,orwhenany

sensorconnection/short

circuittestsareactivated.

AGND

Sense

Viasgotosystemanaloggroundplane.

DGND

Highwhen

theX+orY+

driverison.

Control

Logic

DataAvailable

Level

Shifter

50k

IRQ

(1)

SNSVDD

PINTDAV

AnalogVDD

Plane

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

PINTDAV can be programmed to generate an interrupt to the host. Figure 30 details an example for theY-position measurement. While in the power-down mode, the Y – driver is on and connected to GND. The internalpen-touch signal depends on whether or not the X+ input is driven low. When the panel is touched, the X+ inputis pulled to ground through the touch screen and the internal pen-touch output is set to low because of thedetection on the current path through the panel to GND, which initiates an interrupt to the processor. During themeasurement cycles for X- and Y-Position, the X+ input is disconnected, which eliminates any leakage currentfrom the pull-up resistor to flow through the touch screen, thus causing no errors.

(1) Untrimmed resistor; see the typical value in the Electrical Characteristics

Figure 30. Example of a Pen-Touch Induced Interrupt via the PINTDAV Pin

In modes where the TSC2004 must detect whether or not the screen is still being touched (for example, whendoing a pen-touch initiated X, Y, and Z conversion), the TSC2004 must reset the drivers so that the R

IRQ

resistoris connected again. Because of the high value of this pull-up resistor, any capacitance on the touch screen inputscauses a long delay time, and may prevent the detection from occurring correctly. To prevent this possible delay,the TSC2004 has a circuit that allows any screen capacitance to be precharged, so that the pull-up resistor doesnot have to be the only source for the charging current. The time allowed for this precharge, as well as the timeneeded to sense if the screen is still touched, can be set in the configuration register.

This configuration underscores the need to use the minimum possible capacitor values on the touch screeninputs. These capacitors may be needed to reduce noise, but too large a value will increase the neededprecharge and sense times, as well as the panel voltage stabilization time.

Product Folder Link(s): TSC2004

www.ti.com

Preprocessing

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

The TSC2004 offers an array of powerful preprocessing operations that reduce unnecessary traffic on the busand reduce the host processor loading. This reduction is especially critical for the serial interface, where limitedbandwidth is a tradeoff, keeping the connection lines to a minimum.

All data acquisition tasks are looking for specific data that meet certain criteria. Many of these tasks fall into apredefined range, while other tasks may be looking for a value in a noisy environment. If these data are all to beretrieved by host processor for processing, the limited bus bandwidth quickly saturates, along with the hostprocessor processing capability. In any case, the host processor must always be reserved for more critical tasks,not for routine work.

The preprocessing unit consists of two main functions: the combined MAV filter (median value filter andaveraging filter), followed by the zone detection.

Preprocessing — Median Value Filter and Averaging Value Filter

The first preprocessing function, a combined MAV filter, can be operated independently as a median value filter(MVF), an averaging value filter (AVF), and a combined filter (MAVF).

If the acquired signal source is noisy because of the digital switching circuit, it may be necessary to evaluate thedata without noise. In this case, the median value filter (MVF) operation helps to discard the noise. The array ofNconverted results is first sorted. The return value is either the middle (median value) of an array of Mconvertedresults, or the average value of a window size of Wof converted results:•N = the total number of converted results used by the MAV filter•M = the median value filter size programmed•W = the averaging window size programmed

If M = 1, then N = W. A special case is W = 1, which means the MAVF is bypassed. Otherwise, if W > 1, onlyaveraging is performed on these converted results. In either case, the return value is the averaged value ofwindow size W of converted results. If M > 1 and W = 1, then N = M, meaning only the median value filter isoperating. The return value is the middle position converted result from the array of M converted results. If M > 1and W > 1, then N = M. In this case, W < M. The return value is the averaged value of middle portion W ofconverted results out of the array of M converted results. Since the value of W is an odd number in this case, theaveraging value is calculated with the middle position converted result counted twice (so a total of W + 1converted results are averaged).

Table 1. Median Value Filter Size Selection

MEDIAN VALUE FILTER POSSIBLE AVERAGING WINDOW SIZEM1 M0 M = W =

0 0 1 1, 4, 8, 160 1 3 11 0 7 1, 31 1 15 1, 3, 7

Table 2. Averaging Value Filter Size Selection

AVERAGING VALUE FILTER SIZE SELECTIONW =

W1 W0 M = 1 (Averaging Only) M > 1

0 0 1 10 1 4 31 0 8 71 1 16 Reserved

Product Folder Link(s): TSC2004

www.ti.com

NAcquired

Data

Nm asue rementsinput

intotemporaryarray

Sortby

descendingorder

Averagingoutp tu

fromwindowW

M=1

M>1andW=1 M

NMedian value

fromarrayM

M>1andW>1

Averagingoutp tu

fromwindowW

Zone Detection

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

NOTE: The default setting for MAVF is MVF (median value filter with averaging bypassed) for any invalidconfiguration. For example, if (M1, M0, W1, W0) = (1,0,1,0), the MAVF performs as it was configured for(1,0,0,0), median filter only with filter size = 7 and no averaging. The only exception is M > 1 and (W1, W0) =(1,1). This setting is reserved and should not be used.

Table 3. Combined MAV Filter Setting

M W INTERPRETATION N = OUTPUT

= 1 = 1 Bypass both MAF and AVF W The converted result= 1 > 1 Bypass MVF only W Average of W converted results> 1 = 1 Bypass AVF only M Median of M converted resultsAverage of middle W of M converted results with the median> 1 > 1 M > W M

counted twice

The MAV filter is available for all analog inputs including the touch screen inputs, temperature measurementsTEMP1 and TEMP2, and the AUX measurement.

Figure 31. MAV Filter Operation (patent pending)

The Zone Detection unit is capable of screening all processed data from the MAVF and retaining only the data ofinterest (data that fit the prerequisite). This unit can be programmed to send an alert if a predefined condition setby two threshold value registers is met. Three different zones may be set:1. Above the upper limit (X ≥Threshold High)2. Between the two thresholds (Threshold Low < X < Threshold High)3. Below the lower limit (X ≤Threshold Low)

The AUX and temperatures TEMP1 and TEMP2 have separate threshold value registers that can be enabled ordisabled. This function is not available to the touch screen inputs. Once the preset condition is met, the DAVoutput to the PINTDAV pin is pulled low and the corresponding DAV bit is set.

Product Folder Link(s): TSC2004

www.ti.com

C INTERFACE

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

The TSC2004 supports the I

C serial bus and data transmission protocol in all three defined modes: standard,fast, and high-speed. A device that sends data onto the bus is defined as a transmitter, and a device receivingdata as a receiver. The device that controls the message is called a master. Devices controlled by the master areslaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the busaccess, and generates the START and STOP conditions. The TSC2004 operates as a slave on the I

C bus.Connections to the bus are made via the open-drain I/O lines, SDA and SCL.

The following bus protocol has been defined (see Figure 32 ):•Data transfer may be initiated only when the bus is not busy.•During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the dataline while the clock line is HIGH will be interpreted as control signals.

Accordingly, the following bus conditions have been defined:

Bus Not Busy Both data and clock lines remain HIGH.

Start Data Transfer A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines aSTART condition.

Stop Data Transfer A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH,defines the STOP condition.

Data Valid The state of the data line represents valid data, when, after a START condition, the data line is stablefor the duration of the HIGH period of the clock signal. There is one clock pulse per bit of data.Each data transfer is initiated with a START condition and terminated with a STOP condition.The number of data bytes transferred between START and STOP conditions is not limitedand is determined by the master device. The information is transferred byte-wise and eachreceiver acknowledges with a ninth-bit.Within the I

C bus specifications, a standard mode (100kHz clock rate), a fast mode (400kHzclock rate), and a high-speed mode (3.4MHz clock rate) are each defined. The TSC2004works in all three modes.

Acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge after thereception of each byte. The master device must generate an extra clock pulse that is associated with thisacknowledge bit.

A device that acknowledges must pull down the SDA line during the acknowledge clockpulse in such a way that the SDA line is stable LOW during the HIGH period of theacknowledge clock pulse. Of course, setup and hold times must be taken into account. Amaster must signal an end of data to the slave by not generating an acknowledge bit on thelast byte that has been clocked out of the slave. In this case, the slave must leave the dataline HIGH to enable the master to generate the STOP condition.

Product Folder Link(s): TSC2004

www.ti.com

C Fast or Standard Mode (F/S Mode)

SDA

SCL

1 2 76 8 9 1 2 3-8 8 9

SlaveAddress

MSB

RepeatedIfMoreBytesAreTransferred

R/W

DirectionBit

Acknowledgement

SignalfromReceiver

Acknowledgement

SignalfromReceiver

ACK ACK

S=STARTCondition

Sr=RepeatedSTARTCondition

P=STOPCondition

=ResistorPull-Up

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

Figure 32 details how data transfer is accomplished on the I

C bus. Depending upon the state of the R/ W bit, twotypes of data transfer are possible:1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is theslave address. Next follows a number of data bytes. The slave returns an acknowledge bit after the slaveaddress and each received byte.2. Data transfer from a slave transmitter to a master receiver. The first byte, the slave address, istransmitted by the master. The slave then returns an acknowledge bit. Next, a number of data bytes aretransmitted by the slave to the master. The master returns an acknowledge bit after all received bytes otherthan the last byte. At the end of the last received byte, a not-acknowledge is returned.

The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer endswith a STOP condition or a repeated START condition. Because a repeated START condition is also thebeginning of the next serial transfer, the bus will not be released.

The TSC2004 may operate in the following two modes:1. Slave Receiver Mode: Serial data and clock are received through SDA and SCL. After each byte isreceived, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginningand end of a serial transfer. Address recognition is performed by hardware after reception of the slaveaddress and direction bit.2. Slave Transmitter Mode: The first byte (the slave address) is received and handled as in the slave receivermode. However, in this mode the direction bit indicates that the transfer direction is reversed. Serial data aretransmitted on SDA by the TSC2004 while the serial clock is input on SCL. START and STOP conditions arerecognized as the beginning and end of a serial transfer.

In I

C Fast or Standard (F/S) mode, serial data transfer must meet the timing shown in the Timing Informationsection.

In the serial transfer format of F/S mode, the master signals the beginning of a transmission to a slave with aSTART condition (S), which is a high-to-low transition on the SDA input while SCL is high. When the master hasfinished communicating with the slave, the master issues a STOP condition (P), which is a low-to-high transitionon SDA while SCL is high, as shown in Figure 32 . The bus is free for another transmission after a stop conditionhas occurred. Figure 32 shows the complete F/S mode transfer on the I

C, two-wire serial interface. The addressbyte, control byte, and data byte are transmitted between the START and STOP conditions. The SDA state isonly allowed to change while SCL is low, except for the START and STOP conditions. Data are transmitted in8-bit words. Nine clock cycles are required to transfer the data into or out of the device (8-bit word plusacknowledge bit).

Figure 32. Complete Fast- or Standard-Mode Transfer

Product Folder Link(s): TSC2004

www.ti.com

C High-Speed Mode (Hs Mode)

8-BitMasterCode00001xxx

IfPthen

FastorStandardMode

IfSr(dottedlines)

thenHigh-SpeedMode

1 6 7 8 92to5

2to51 6 7 8 9 1 6 7 8 9

2to5

SDA

SCL

SDA

SCL

=CurrentSourcePull-Up

=ResistorPull-Up

A=Acknowledge(SD LOWA )

N=NotAckno ledgew (SDAHIGH)

S START= Condition

P=STOP Con iiond t

Sr=RepeatedSTAR CondT iti no

NtH

High-SpeedMode

FastorStandardMode

tFS

Sr P

7-BitSlaveAddress R/WA nx(8-BitDATA + A/N)

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

Serial data transfer format in High-Speed (Hs) mode meets the Fast or Standard (F/S) mode I

C busspecification. Hs mode can only commence after the following conditions (all of which are in F/S mode) exist:1. START condition (S)2. 8-bit master code (00001xxx)3. not-acknowledge bit (N)

Figure 33 shows this sequence in more detail. Hs-mode master codes are reserved 8-bit codes used only fortriggering Hs mode, and are not to be used for slave addressing or any other purpose. The master codeindicates to other devices that an Hs-mode transfer is about to begin and the connected devices must meet theHs mode specification. Because no device is allowed to acknowledge the master code, the master code isfollowed by a not-acknowledge bit (N).

After the not-acknowledge bit (N) and SCL have been pulled up to a HIGH level, the master switches to Hs-modeand enables (at time t

; shown in Figure 33 ) the current-source pull-up circuit for SCL. Because other devicescan delay the serial transfer before t

by stretching the LOW period of SCL, the master enables itscurrent-source pull-up circuit when all devices have released SCL, and SCL has reached a HIGH level, thusspeeding up the last part of the rise time of the SCL.

The master then sends a repeated START condition (Sr) followed by a 7-bit slave address with a R/ W bitaddress, and receives an acknowledge bit (A) from the selected slave. After a repeated START (Sr) conditionand after each acknowledge bit (A) or not-acknowledge bit (N), the master disables its current-source pull-upcircuit. This disabling enables other devices to delay the serial transfer by stretching the LOW period of SCL. Themaster re-enables its current-source pull-up circuit again when all devices have released, and SCL reaches aHIGH level, which speeds up the last part of the SCL signal rise time.

Data transfer continues in Hs mode after the next repeated START (Sr), and only switches back to F/S modeafter a STOP condition (P). To reduce the overhead of the master code, it is possible that a master links anumber of Hs mode transfers, separated by repeated START conditions (Sr).

Figure 33. Complete High-Speed Mode Transfer

Product Folder Link(s): TSC2004

www.ti.com

DIGITAL INTERFACE

ADDRESS BYTE

I CWrite-AddressingByte

AD11 0 0 1 0 AD0 0 A

I CRead-AddressingByte

AD1S/Sr 1 0 0 1 0 AD0 1 A

STARTor

RepeatedSTART

ACK

S/Sr

STARTor

RepeatedSTART

ACK

FromMastertoSlave A=Acknowledge(SDALOW)

S=STARTCondition

Sr=RepeatedSTARTCondition

FromSlavetoMaster

CONTROL BYTE

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

The TSC2004 has a 7-bit slave address word. The first five bits (MSBs) of the slave address are factory-preset tocomply with the I

C standard for A/D converters and are always set at '10010'. The logic state of the addressinput pins (AD1-AD0) determine the two LSBs of the device address to activate communication. Therefore, amaximum of four devices with the same preset code can be connected on the same bus at one time.

The AD1-AD0 address inputs are only read during a power-up of the device, and should be connected to a digitalsupply (I/OVDD), or digital ground (DGND). The slave address is latched into the TSC2004 on the falling edge ofSCL after the read/write bit has been received by the slave.

The last bit of the address byte (R/ W) defines the operation to be performed. When set to a '1', a read operationis selected; when set to a ‘ 0 ’ , a write operation is selected. Following the START condition, the TSC2004monitors the SDA bus, checking the device type identifier being transmitted. Upon receiving the '10010' code, theappropriate device select bits, and the R/ W bit, the slave device outputs an acknowledge signal on the SDA line.

Table 4. I

C Slave Address Byte

MSB LSBD7 D6 D5 D4 D3 D2 D1 D0

1 0 0 1 0 AD1 AD0 R/ W

Bit D0: R/ W

1: I

C master read from TSC (I

C read addressing).

0: I

C master write to TSC (I

C write addressing).

Figure 34. I

C Bus Addressing (Slave Address Byte Format)

Table 5. Control Byte Format:Start a Conversion and Mode Setting

MSB LSBD7 D6 D5 D4 D3 D2 D1 D0

C3 C2 C1 C0 RM SWRST STS(Control Byte 1)

0ReservedA3 A2 A1 A0 PND0 R/ W(Control Byte 0) (Write '0')

Product Folder Link(s): TSC2004

www.ti.com

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

Table 6. Control Byte 1 Bit Register Description (D7 = 1)

BIT NAME DESCRIPTION

D7 Control Byte ID 1D6-D3 C3:C0 Converter Function Select as detailed in Table 70: 10 BitD2 RM

1: 12 BitSoftware Reset. This bit is self-clearing.D1 SWRST

1: Reset all register values to defaultD0 STS Stop bit for all converter functions. This bit is self-clearing.

Bit D7: Control Byte ID

1: Control Byte 1 (start conversion and channel select and conversion-related configuration).

0: Control Byte 0 (read/write data registers and non-conversion-related controls).

Bits D6-D3: C3-C0

Converter function select bits. These bits select the input to be converted, and the converter function to beexecuted. Table 7 lists the possible converter functions.

Table 7. Converter Function Select

C3 C2 C1 C0 FUNCTION

Touch screen scan function: X, Y, Z

, and Z

coordinates converted and the results returned0 0 0 0 to X, Y, Z

, and Z

data registers. Scan continues until either the pen is lifted or a stop bit issent.

Touch screen scan function: X and Y coordinates converted and the results returned to X and0001

Y data registers. Scan continues until either the pen is lifted or a stop bit is sent.Touch screen scan function: X coordinate converted and the results returned to X data0010

Touch screen scan function: Y coordinate converted and the results returned to Y data0011

Touch screen scan function: Z

and Z

coordinates converted and the results returned to Z

10100

and Z

data registers.0 1 0 1 Auxiliary input converted and the results returned to the AUX data register.A temperature measurement is made and the results returned to the Temperature0110

Measurement 1 data register.A differential temperature measurement is made and the results returned to the Temperature0111

Measurement 2 data register.1 0 0 0 Auxiliary input is converted continuously and the results returned to the AUX data register.Touch screen panel connection to X-axis drivers is tested. The test result is output to1001

PINTDAV and shown in STATUS register.Touch screen panel connection to Y-axis drivers is tested. The test result is output to1010

PINTDAV and shown in STATUS register.RESERVED (Note: any condition caused by this command can be cleared by setting the STS1011

bit to 1).Touch screen panel short-circuit (between X and Y plates) is tested through Y-axis. The test1100

result is output to PINTDAV and shown in the STATUS register.1 1 0 1 X+, X – drivers status1 1 1 0 Y+, Y – drivers status1 1 1 1 Y+, X – drivers status

Product Folder Link(s): TSC2004

www.ti.com

Touch Screen Scan Function for XYZ or XY

Touch Screen Sensor Connection Tests for X-Axis and Y-Axis

Touch Sensor Short-Circuit Test

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

C3-C0 = 0000 or 0001: These scan functions can collaborate with the PSM bit that defines the control mode ofconverter functions. If the PSM bit is set to '1', these scan function select commands are recommended to beissued before a pen touch is detected in order to allow the TSC2004 to initiate and control the scan processesimmediately after the screen is touched. If these functions are not issued before a pen touch is detected, theTSC2004 waits for the host to write these functions before starting a scan process. If PSM stays as '1' after aTSC-initiated scan function is complete, the host is not required to write these function select bits again for eachof the following pen touches after the detected touch. In the host-controlled converter function mode (PSM = 0),the host must send these functions select bits repeatedly for each scan function after a detected pen touch.

Note that the data registers may be updated while a host reading is in progress. Using the sequential read cycle(see Figure 36 ) prevents the TSC from updating registers while a host reading is in progress. To ensure that theXYZ or XY coordinates are correctly read, use the sequential read cycle to read the coordinates after the scan.

Range of resistances of different touch screen panels can be selected by setting the TBM bits in CFR1; seeTable 20 . Once the resistance of the sensor panel is selected, two continuity tests are run separately for theX-axis and Y-axis. The unit under test must pass both connection tests to ensure that a proper connection issecured.

C3-C0 = 1001: PINTDAV = 0 during this connection test. A '1' shown at end of the test indicates the X-axisdrivers are well-connected to the sensor; otherwise, X-axis drivers are poorly connected. If drivers fail to connect,then PINTDAV stays low until a stop bit (STS set to '1') is issued.

C3-C0 = 1010: PINTDAV = 0 during this connection test. A '1' shown at end of the test indicates the Y-axisdrivers are well-connected to the sensor; otherwise, Y-axis drivers are poorly connected. If the drivers are fail toconnect, then PINTDAV stays low until a stop bit (STS set to '1') is issued.

If the TBM bits of CFR1 detailed in Table 20 are all set to '1', a short-circuit in the touch sensor can be detected.

C3-C0 = 1011: Reserved.

C3-C0 = 1100: PINTDAV = 0 during this short-circuit test. A '1' shown at end of the test indicates there is noshort-circuit detected (through Y-axis) between the flex and stable layers. If there is a short-circuit detected,PINTDAV stays low until a stop bit (STS set to '1') is issued.

RM— Resolution select. If RM = 1, the conversion result resolution is 12-bit; otherwise, the resolution is 10-bit.This bit is the same RM bit shown in CFR0.

SWRST— Software reset input. All register values are set to default value if a '1' is written to this bit. This bit isautomatically set to '0' in order to cancel the software reset and resume normal operation.

STS— Stop bit for all converter functions. When writing a '1' to this register, this bit aborts the converter functioncurrently running in the TSC2004. A '0' is automatically written to this register in order to end the stop bit. This bitcan only stop converter functions; it does not reset any data, status, or configuration registers. This bit is thesame STS bit shown in CFR0, but can only be read through the CFR0 register with different interpretations.

Table 8. STS Bit Operation

OPERATION VALUE DESCRIPTION

Write 0 Normal operationWrite 1 Stop converter functions and power down

Product Folder Link(s): TSC2004

www.ti.com

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

Table 9. Control Byte 0 Bit Register Description (D7 = 0)

BIT NAME DESCRIPTION

1: Control Byte 1 — start conversion, channel select, and converison-related configurationD7 Control Byte ID

0: Control Byte 0 — read/write data registers and non-conversion-related controlsD6-D3 A3-A0 Register Address Bits as detailed in Table 10D2 RESERVED A '0' must be set in this bit for normal operationPower Not Down Control1: A/D converter biasing circuitry is always on between conversions but is shut downD1 PND0 after the converter function stops0: A/D converter biasing circuitry is shut down either between conversions or after theconverter function stopsTSC Internal Register Data Flow Control1: Set the starting address of the TSC internal registers for a register read (seeD0 R/ W

Figure 35 )0: Write to TSC internal registers

Table 10. Internal Register Map

A3 A2 A1 A0 REGISTER CONTENT READ/WRITE

0 0 0 0 X measurement result R0 0 0 1 Y measurement result R0 0 1 0 Z

measurement result R0 0 1 1 Z

measurement result R0 1 0 0 AUX measurement result R0 1 0 1 Temp1 measurement result R0 1 1 0 Temp2 measurement result R0 1 1 1 Status R1 0 0 0 AUX high threshold R/W1 0 0 1 AUX low threshold R/W1 0 1 0 Temp high threshold (apply to both TEMP1 and TEMP2) R/W1 0 1 1 Temp low threshold (apply to both TEMP1 and TEMP2) R/W1 1 0 0 CFR0 R/W1 1 0 1 CFR1 R/W1 1 1 0 CFR2 R/W1 1 1 1 Converter function select status R

R/ W— Register read and write control. A '1' indicates that the value of the internal register address bits A3-A0 isstored internally as the starting address for a register read (see Figure 35 ). The content of the addressed registeris sent to SDA by using I

C read addressing (see Figure 36 and Figure 37 ). A '0' indicates that the data followingControl Byte 0 on SDA are written into the internal register addressed by bits A3-A0 (see Figure 35 ).

Product Folder Link(s): TSC2004

www.ti.com

START A WRITE CYCLE

WriteCycle

I CSlaveAddress

I C

2Write-

AddressingByte ACK STOP(1)

START 1 C3 C2 C1 C0

SWRST

STS

ControlByte1A AS P0

17 8

I C

2SlaveAddress

I CWrite-

AddressingByte

2ACK

STOP(1)

0 0A3 A2 A1 A0

Rsvd

PND0

ControlByte0 DataByte1/2

(HIGHByte)

DataByte2/2

(LOWByte)

AA A A PS 0

I C

2SlaveAddress

I CWrite-

AddressingByte

2MixedM(ControlByte1orControlByte0withReadBit)

PlusN(ControlByte0withDataBytes),SeparatedbyTSC ACKs

(M+Nx3)x8

AA A A PS 0

8 8 8

ConverterFunction Select

TSCInternalRegisterAddressforWriteData

I C

2SlaveAddress

I CWrite-

AddressingByte

2ACK STOP(1)

0 1A3 A2 A1 A0

Rsvd

PND0

ControlByte0A A P

S 0

17 8

TSCInternalRegisterStartingAddressmh(2)

START

FromMastertoSlave A=Acknowledge(SDALOW)

N=NotAcknowledge(SDAHIGH)

S=STARTCondition

P=STOPCondition

Sr=RepeatedSTARTCondition

FromSlavetoMaster

NOTES: (1)Inordertostartthenextsequence,aSTOPconditionmustbefollowedbyaSTARTcondition.IfnoSTOPis

used,thenaRepeatedSTARTmustbeused.AlsonotethatisaSTOPconditionisissuedinHigh-Speed

mode,themodewillreverttothepreviousmode:FastorStandard.

(2)mhisahexadecimalnumber.

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

A write cycle begins when the master issues the slave address to the TSC2004. The slave address consists ofseven address bits and a write bit (R/ W = 0; see Table 5 ). When the eighth bit has been received and theaddress matches the AD1-AD0 address input pin setting, the TSC2004 issues an acknowledge bit by pullingSDA low for one additional clock cycle (ACK = 0); see Figure 34 .

When the master receives the acknowledge bit from the TSC2004, the master writes the input control byte to theslave; see Table 5 . After the control byte is received by the slave, the slave issues another acknowledge bit bypulling SDA low for one clock cycle (ACK = 0). The master then ends the write cycle by issuing a STOP orrepeated START condition; see Figure 35 .

Figure 35. Write Cycle

Product Folder Link(s): TSC2004

www.ti.com

ReadCycle:Sequential,fromRegisterAddressmh to(m+n)h

(2) (3)

I C

2Read-AddressingByte Register(Address=mh)Content

START

I C

2SlaveAddressS 1 AA DataByte1/2

(HIGHByte)

DataByte2/2

(LOWByte) A

8 8

DataByte1/2

(HIGHByte)

DataByte2/2

(LOWByte) A

8 8

DataByte1/2

(HIGHByte)

DataByte2/2

(LOWByte) NP

8 8 NACK

STOP(1)

FromMastertoSlave A=Acknowledge(SDALOW)

N=NotAcknowledge(SDAHIGH)

S=STARTCondition

P=STOPCondition

Sr=RepeatedSTARTCondition

FromSlavetoMaster

NOTES: (1)Inordertostartthenextsequence,aSTOPconditionmustbefollowedbyaSTARTcondition.IfnoSTOPis

used,thenaRepeatedSTARTmustbeused.AlsonotethatisaSTOPconditionisissuedinHigh-Speed

mode,themodewillreverttothepreviousmode:FastorStandard.

(2)mhisahexadecimalnumber.

(3)If(m+n)hisgreaterthanFh,then(m+n)hismodulo16.

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

Data access begins with the master issuing a START (or repeated START) condition followed by the 7-bitaddress and a read bit (R/ W = 1; see Table 5 ). When the eighth bit has been received and the address matches,the slave issues an acknowledge by pulling SDA low for one clock cycle (ACK = 0). The first byte of serial datathen follows. After the first byte has been sent by the slave, it releases the SDA line for the master to issue anacknowledge (ACK = 0). The slave issues the second byte of serial data upon receiving the acknowledgementfrom the master (D7-D0), followed by a not-acknowledge bit (ACK = 1) from the master to indicate that the lastdata byte has been received. The master then issues a STOP condition (P) or repeated START (Sr), which endsthe read cycle, as shown in Figure 36 and Figure 37 . If the master issues a not-acknowledge (ACK = 1) afterreceipt of the first data byte, the master must then issue a stop condition (P) to reset the registers. If the masteris not ready to receive the second data byte, it should issue the acknowledge (ACK = 0), or the master shouldstretch the clock. Upon restart of the clock, the second byte of data can be received by the master.

Figure 36. Sequential Read Cycle

Product Folder Link(s): TSC2004

www.ti.com

ReadCycle:Repeated,RegisterAddressmh(2)

I C

2Read-AddressingByte Register(Address=mh)Content

START

I C

2SlaveAddressS 1 AA DataByte1/2

(HIGHByte)

DataByte2/2

(LOWByte) P

8 8 NACK

I C

2SlaveAddressS 1 AA DataByte1/2

(HIGHByte)

DataByte2/2

(LOWByte) P

8 8 NACK

I C

2SlaveAddressS 1 AA DataByte1/2

(HIGHByte)

DataByte2/2

(LOWByte) P

8 8 NACK

Or...

I CRead-AddressingByte

Repeated

START

I C

2SlaveAddressSr 1 AA DataByte1/2

(HIGHByte)

DataByte2/2

(LOWByte)

8 8 NACK

I C

2SlaveAddressSr 1 AA DataByte1/2

(HIGHByte)

DataByte2/2

(LOWByte)

8 8 NACK

I C

2SlaveAddressSr 1 AA DataByte1/2

(HIGHByte)

DataByte2/2

(LOWByte) P

8 8 NACK

STOP(1)

Repeated

START

Repeated

START

STOP(1)

I C

2Read-AddressingByte

I C

2Read-AddressingByte

START

STOP(1)

I CRead-AddressingByte

FromMastertoSlave A=Acknowledge(SDALOW)

N=NotAcknowledge(SDAHIGH)

S=STARTCondition

P=STOPCondition

Sr=RepeatedSTARTCondition

FromSlavetoMaster

NOTES: (1)Inordertostartthenextsequence,aSTOPconditionmustbefollowedbyaSTARTcondition.IfnoSTOPis

used,thenaRepeatedSTARTmustbeused.AlsonotethatisaSTOPconditionisissuedinHigh-Speed

mode,themodewillreverttothepreviousmode:FastorStandard.

(2)mhisahexadecimalnumber.

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

Figure 37. Repeated Read Cycle

Product Folder Link(s): TSC2004

www.ti.com

COMMUNICATION PROTOCOL

Configuration Register 0

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

The TSC2004 is controlled entirely by registers. Reading and writing to these registers are accomplished by theuse of Control Byte 0, which includes a 4-bit address plus one read/write TSC register control bit. The dataregisters defined in Table 10 are all 16-bit, right-adjusted. NOTE: Except for some configuration registers and theStatus register that are full 16-bit registers, the rest of the value registers are 12-bit (or 10-bit) data preceded byfour (or six) zeros.

Table 11. Configuration Register 0 (Reset Value = 4000h for Read; 0000h for Write)MSB LSBD15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

PSM STS RM CL1 CL0 PV2 PV1 PV0 PR2 PR1 PR0 SN2 SN1 SN0 DTW LSM

PSM— Pen status/control mode. Reading this bit allows the host to determine if the screen is touched. Writing tothis bit selects the mode used to control the flow of converter functions that are either initiated and/or controlledby host or under control of the TSC2004 responding to a pen touch. When reading, the PSM bit indicates if thepen is down or not. When writing to this register, this bit determines if the TSC2004 controls the converterfunctions, or if the converter functions are host-controlled. The default state is the host-controlled converterfunction mode (0). The other state (1) is the TSC-initiated scan function mode that must only collaborate withC3-C0 = 0000 or 0001 in order to allow the TSC2004 to initiate and control the scan function for XYZ or XY whena pen touch is detected.

Table 12. PSM Bit Operation

OPERATION VALUE DESCRIPTION

Read 0 No screen touch detectedRead 1 Screen touch detectedWrite 0 Converter functions initiated and/or controlled by hostWrite 1 Converter functions initiated and controlled by the TSC2004

STS— A/D converter status. When reading, this bit indicates if the converter is busy or not busy. Continuousscans or conversions can be stopped by writing a '1' to this bit, immediately aborting the running converterfunction (even if the pen is still down) and causing the A/D converter to power down. The default state for write is0 (normal operation), and the default state for read is 1 (converter is not busy). NOTE: The same bit can bewritten through Control Byte 1. This bit is self-clearing.

Table 13. STS Bit Operation

OPERATION VALUE DESCRIPTION

Read 0 Converter is busyRead 1 Converter is not busyWrite 0 Normal operationWrite 1 Stop converter function and power down

RM— Resolution control. The A/D converter resolution is specified with this bit. See Table 14 for a description ofthese bits. This bit is the same whether reading or writing, and defaults to 0. Note that the same bit can bewritten through Control Byte 1.

Table 14. A/D Converter Resolution Control

RM FUNCTION

0 10-bit resolution. Power-up and reset default.1 12-bit resolution

Product Folder Link(s): TSC2004

www.ti.com

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

CL1, CL0— Conversion clock control. These two bits specify the clock rate that the A/D converter uses toperform conversion, as shown in Table 15 .

Table 15. A/D Converter Conversion Clock Control

CL1 CL0 FUNCTION

0 0 f

ADC

= f

OSC

/1. This is referred to as the 4MHz A/D converter clock rate, 10-bit resolution only

(1)

.0 1 f

ADC

= f

OSC

/2. This is referred to as the 2MHz A/D converter clock rate.1 0 f

ADC

= f

OSC

/4. This is referred to as the 1MHz A/D converter clock rate.1 1 f

ADC

= f

OSC

/4. This is referred to as the 1MHz A/D converter clock rate.

(1) For SNSVDD = 1.2V at – 40 °C, a lower A/D converter clock rate should be used to allow enough time for conversion settling.

PV2-PV0— Panel voltage stabilization time control. These bits specify a delay time from the moment the touchscreen drivers are enabled to the time the voltage is sampled and a conversion is started. These bits allow theuser to adjust the appropriate settling time for the touch panel and external capacitances. See Table 16 forsettings of these bits. The default state is 000, indicating a 0 µs stabilization time. These bits are the samewhether reading or writing.

Table 16. Panel Voltage Stabilization Time Control

PV2 PV1 PV0 STABILIZATION TIME (t

PVS

)

0 0 0 0 µs0 0 1 100 µs0 1 0 500 µs0 1 1 1ms1 0 0 5ms1 0 1 10ms1 1 0 50ms1 1 1 100ms

PR2-PR0— Precharge time selection. These bits set the amount of time allowed for precharging any pincapacitance on the touch screen prior to sensing if a pen touch is happening.

Table 17. Precharge Time Selection

PR2 PR1 PR0 PRECHARGE TIME(t

PRE

)

0 0 0 20 µs0 0 1 84 µs0 1 0 276 µs0 1 1 340 µs1 0 0 1.044ms1 0 1 1.108ms1 1 0 1.300ms1 1 1 1.364ms

SNS2-SNS0— Sense time selection. These bits set the amount of time the TSC2004 waits to sense whether thescreen is touched after converting a coordinate.

Product Folder Link(s): TSC2004

www.ti.com

Configuration Register 1

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

Table 18. Sense Time Selection

SNS2 SNS1 SNS0 SENSE TIME (t

SNS

)

0 0 0 32 µs0 0 1 96 µs0 1 0 544 µs0 1 1 608 µs1 0 0 2.080ms1 0 1 2.144ms1 1 0 2.592ms1 1 1 2.656ms

DTW— Detection of pen touch in wait (patent pending). Writing a '1' to this bit enables the pen touch detection inthe background while waiting for the host to issue the converter function in host-initiated/controlled modes. Thisbackground detection allows the TSC2004 to pull high at PINTDAV to indicate no pen touch detected whilewaiting for the host to issue the converter function. If the host polls a high state at PINTDAV before the convertfunction is sent, the host can abort the issuance of the convert function and stay in the polling PINTDAV modeuntil the next pen touch is detected.

LSM— Longer sampling mode. When this bit is set to '1', the extra 500ns of sampling time is added to the normalsampling cycles of each conversion. This additional time is represented as approximately two internal oscillatorclock cycles. For SNSVDD = 1.2V at – 40 °C, the LSM bit should be set to '1' so that the sampled signal hasenough time to settle.

Configuration register 1 (CFR1) defines the connection test-bit modes configuration and batch delay selection.

Table 19. Configuration Register 1 (Reset Value = 0000h)MSB LSBD15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Resrvd Resrvd Resrvd Resrvd TBM3 TBM2 TBM1 TBM0 Resrvd Resrvd Resrvd Resrvd Resrvd BTD2 BTD1 BTD0

TBM3-TBM0— Connection test-bit modes (patent pending). These bits specify the mode of test bits used for thepredefined range of the combined X-axis and Y-axis touch screen panel resistance (R

Table 20. Touch Screen Resistance Range and Test-Bit Modes

TEST-BIT MODES

TSTBM3 TBM2 TBM1 TBM0 (k Ω)

0 0 0 0 0.170 0 0 1 0.17 < R

≤0.520 0 1 0 0.52 < R

≤0.860 0 1 1 0.86 < R

≤1.60 1 0 0 1.6 < R

≤2.20 1 0 1 2.2 < R

≤3.60 1 1 0 3.6 < R

≤5.00 1 1 1 5.0 < R

≤7.81 0 0 0 7.8 < R

≤10.51 0 0 1 10.5 < R

≤16.01 0 1 0 16.0 < R

≤21.61 0 1 1 21.6 < R

≤32.61 1 0 0 Reserved1 1 0 1 Reserved1 1 1 0 Reserved1 1 1 1 Only for short-circuit panel test

Product Folder Link(s): TSC2004

www.ti.com

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

BTD2-BTD0— Batch Time Delay mode. These are the selection bits that specify the delay before asample/conversion scan cycle is triggered. When it is set, Batch Time Delay mode uses a set of timers toautomatically trigger a sequence of sample-and-conversion events. The mode works for both TSC-initiated scans(XYZ or XY) and host-initiated scans (XYZ or XY).

A TSC-initiated scan (XYZ or XY) can be configured by setting the PSM bit in CFR0 to '1' and C[3:0] in ControlByte 1 to '0000' or '0001'. In the case of a TSC-initiated scan (XYZ or XY), the sequence begins with the TSCresponding to a pen touch. After the first processed sample set completes during the batch delay, the scanenters a wait mode until the end of the batch delay is reached. If a pen touch is still detected at that moment, thescan continues to process the next sample set, and the batch delay is resumed. The throughput of the processedsample sets (shown in Table 21 as sample sets per second, or SSPS) is regulated by the selected batch delayduring the time of the detected pen touch. A TSC-initiated scan (XYZ or XY) can be configured by setting thePSM bit in CFR0 to '1' and C[3:0] in Control Byte 1 to '0000' or '0001'. Note that the throughput of the processedsample set also depends on the settings of stabilization, precharge, and sense times, and the total number ofsamples to be processed per coordinates. If the accrual time of these factors exceeds the batch delay time, theaccrual time dominates. Batch delay time starts when the pen touch initiates the scan function that convertscoordinates.

A host-initiated scan (XYZ or XY) can be configured by setting the PSM bit in CFR0 to '0' and C[3:0] in ControlByte 1 to '0000' or '0001'. For the host-initiated scan (XYZ or XY), the host must set TSC internal register C[3:0]in Control Byte 1 to '0000' or '0001' initially after a pen touch is detected; see Conversion Controlled by TSC2004Initiated by Host (TSMode 2) , in the Theory of Operation section. After the scan (XYZ or XY) is engaged, thethroughput of the processed sample sets is regulated by the selected batch delay timer, as long as the initialdetected touch is not interrupted.

Table 21. Touch Screen Throughput and Batch Selection Bits

BATCH DELAY SELECTION THROUGHPUT FOR TSC-INITIATEDDELAY TIME OR HOST-INITIATED SCAN, XYZ OR XYBTD2 BTD1 BTD0 (ms) (SSPS)

0 0 0 0 Normal operation throughput depends on settings.0 0 1 1 10000 1 0 2 5000 1 1 4 2501 0 0 10 1001 0 1 20 501 1 0 40 251 1 1 100 10

For example, if stabilization time, precharge time, and sense time are selected as 100 µs, 84 µs, and 96 µs,respectively, and the batch delay time is 2ms, then the scan function enters wait mode after the first processedsample set until the 2ms of batch delay time is reached. When the scan function starts to process the secondsample set (if the screen is still touched), the batch delay restarts at 2ms (in this example). This procedureremains regulated by 2ms until the pen touch is not detected or the scan function is stopped by a stop bit or anyreset form.

Product Folder Link(s): TSC2004

www.ti.com

Configuration Register 2

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

Configuration register 2 (CFR2) defines the preprocessor configuration.

Table 22. Configuration Register 2 (Reset Value = 0000h)MSB LSBD15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

MAVE MAVE MAVE MAVE MAVEPINTS1 PINTS0 M1 M0 W1 W0 TZ1 TZ0 AZ1 AZ0 Resrvd

X Y Z AUX TEMP

PINTS1 (default 0) — This bit controls the output format of the PINTDAV pin. When this bit is set to '0', the outputformat is shown as the AND-form of internal signals of PENIRQ and DAV). When this bit is set to '1', PINTDAVoutputs PENIRQ only.

PINTS0 (default 0) — This bit selects what is output on the PINTDAV pin. If this bit set to '0', the output format ofPINTDAV depends on the selection made on the PINTS1 bit. If this bit set to '1', the internal signal of DAV isoutput on PINTDAV.

Table 23. PINTSx Selection

PINTS1 PINTS0 PINTDAV PIN OUTPUT =

0 0 AND combination of PENIRQ (active low) and DAV (active high).0 1 Data available, DAV (active low).1 0 Interrupt, PENIRQ (active low) generated by pen-touch.1 1 Data available, DAV (active low).

M1, M0, W1, W0 (default 0000) — Preprocessing MAV filter control. Note that when the MAV filter is processingdata, the STS bit and the corresponding DAV bits in the status register indicate that the converter is busy until allconversions necessary for the preprocessing are complete. The default state for these bits is 0000, whichbypasses the preprocessor. These bits are the same whether reading or writing.

TZ1 and TZ0, or AZ1 and AZ0 (default 00) — Zone detection bit definition (for TEMP or AUX measurements).TZ1 and TZ0 are for the TEMP measurement. AZ1 and AZ0 are for the AUX measurement. The action taken inzone detection is to store the processed data in the corresponding data registers and to update thecorresponding DAV bits in status register. If the processed data do not meet the selected criteria, these data areignored and the corresponding DAV bits are not updated. When zone detection is disabled, the processed dataare simply stored in the corresponding data registers and the corresponding DAV bits are updated without anycomparison of criteria. Note that the converted samples are always processed according to the setting of theMAVE bits for AUX/TEMP before zone detection takes effect. See Table 30 for thresholds.

Table 24. Zone Detection Bit Definition

TZ1/AZ1 TZ0/AZ0 FUNCTION

0 0 Zone detection is disabled.0 1 When the processed data are below low threshold1 0 When the processed data are between low and high thresholds1 1 When the processed data are above high threshold

MAVE (default is 00000) — MAV filter function enable bit. When the corresponding bit is set to '1', the MAV filtersetup is applied to the corresponding measurement.

Product Folder Link(s): TSC2004

www.ti.com

Converter Function Select Register

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

The Converter Function Select (CFN) register reflects the converter function select status.

Table 25. Converter Function Select Status Register (Reset Value = 0000h)MSB LSBD15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

CFN15 CFN14 CFN13 CFN12 CFN11 CFN10 CFN9 CFN8 CFN7 CFN6 CFN5 CFN4 CFN3 CFN2 CFN1 CFN0

CFN15-CFN13— Touch screen drivers status. These bits represent the current status of the touch screen driversthat are turned on. CFN13 is set to '1' if both X+ and X- drivers are turned on. CFN14 is set to '1' if both Y+ andY- drivers are turned on. CFN15 is set to '1' if Y+ and X- drivers are turned on. Otherwise, these bits are set to'0'. These bits are reset to 0h whenever the converter function is either complete, stopped by the STS bit, orreset (by a hardware reset from the RESET pin or a software reset from SWRST bit in Control Byte 1).

CFN12-CFN0— Converter function select status. These bits represent the converter function currently running,which is set in bits C3-C0 of Control Byte 1. When the CFNx bit shows '1', where x is the decimal value ofconverter function select bits C3-C0, it indicates that the converter function that is set in bits C3-C0 is running.For example, when CFN2 shows '1', it indicates the converter function set in bits C3-C0 ('0010') is running. TheCFNx bits are reset to 0000h whenever the converter function is complete, stopped by STS bit, or reset (by thehardware reset from the RESET pin or the software reset from SWRST bit in Control Byte 1). However, if theTSC-initiated scan function mode is issued (by setting the PSM bit in the CFR0 register to '1'), the CFN0 orCFN1 bit will not be reset when the corresponding converter function is complete because there is no pen touch.This event allows the TSC2004 to immediately initiate the scan process (corresponding to CFN0 or CFN1 set to'1') when the next pen touch is detected.

Table 26. STATUS Register (Reset Value = 0004h)MSB LSBD15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DAV DAV DAV DAV DAV DAV DAV

RESRVD RESET X Y RESRVD YDue Due Due Due Due Due Due PDST ID1 ID0(read '0') Flag CON CON (read '0') SHRX Y Z1 Z2 AUX TEMP1 TEMP2

DAV Bits— Data available bits. These seven bits mirror the operation of the internal signals of DAV. When anyprocessed data are stored in data registers, the corresponding DAV bit is set to '1'. It stays at '1' until theregister(s) updated to the processed data have been read out by the host.

Table 27. DAV Function

DAV DESCRIPTION

0 No new processed data are available.1 Processed data are available. This will stay at 1 until the host has read out all updated registers.

RESET Flag— See Table 28 for the interpretation of the RESET flag bits.

Table 28. RESET Flag Bits

RESET Flag DESCRIPTION

0 Device was reset since last status poll (hardware or software reset).1 Device has not been reset since last status poll.

X CON— This bit is '1' if the X axis of the touch screen panel is properly connected to the X drivers. This bit is theconnection test result.

Y CON— This bit is '1' if the Y axis of the touch screen panel is properly connected to the Y drivers. This bit is theconnection test result.

Y SHR— This bit is '1' if there is no short-circuit tested at the Y axis of the touch screen panel. This bit is theshort-circuit test result.

Product Folder Link(s): TSC2004

www.ti.com

DATA REGISTERS

X, Y, Z1, Z2, AUX, TEMP1 and TEMP2 REGISTERS

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

PDST— Power down status. This bit reflects the setting of the PND0 bit in Control Byte 0. When this bit shows '0',it indicates A/D converter bias circuitry is still powered on after each conversion and before the next sampling;otherwise, it indicates A/D converter bias circuitry is powered down after each conversion and before the nextsampling. However, it is powered down between conversion sets. Because this status bit is synchronized withthe internal clock, it does not reflect the setting of the PND0 bit until a pen touch is detected or a converterfunction is running.

ID[1:0] Device ID bits: These bits represent the version ID of TSC2004. This version defaults to '00'.

The data registers of the TSC2004 hold data results from conversions. All of these registers default to 0000hupon reset.

The results of all A/D conversions are placed in the appropriate data registers, as described in Table 10 . Thedata format of the result word (R) of these registers is right-justified, as shown in Table 29 .

Table 29. Internal Register FormatMSB LSBD15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0

The TSC2004 has several 16-bit registers that allow control of the device, as well as providing a location to storeresults from the TSC2004 until read out by the host microprocessor. Table 30 shows the memory map.

Table 30. Register Content and Reset Values

(1)

RESETA3-A0 REGISTER VALUE(HEX) NAME D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (HEX)

0 X 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000

1 Y 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000

2 Z1 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000

3 Z2 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000

4 AUX 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000

5 Temp1 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000

6 Temp2 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000

Rsvd7 Status S15 S14 S13 S12 S11 S10 S9 0 S7 S6 S5 S3 S2 S1 S0 0004(2)

8 AUX High 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0FFF

9 AUX Low 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000

A Temp High 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0FFF

B Temp Low 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000

C CFR0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 4000

D CFR1 0 0 0 0 R11 R10 R9 R8 0 0 0 0 0 R2 R1 R0 0000

E CFR2 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 0 R4 R3 R2 R1 R0 0000

Converter

RsvdF Function R15 R14 R13 R12 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000(2)Select Status

(1) For all combination bits, the pattern marked as Rsvd (reserved) must not be used. The default pattern is read back after reset.(2) This bit is reserved.

Product Folder Link(s): TSC2004

www.ti.com

RESET

State Nor am l erai nOp t o Resetting InitialCondition

t <5 sm

WL(RESET)

t 10³ m

WL(RESET) s

tRtR

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

There are three way to reset the TSC2004. First, at power-on, a power good signal generates a prolonged resetpulse internally to all registers.

Second, an external pin, RESET, is available to perform a system reset or allow other peripherals (such as adisplay) to reset the device if the pulse meets the timing requirement (at least 10 µs wide). Any RESET pulse lessthan 5 µs will be rejected. To accommodate the timing drift between devices because of process variation, aRESET pulse width between 5 µs to 10 µs falls into the gray area that is not recognized, and the result isundetermined; this situation should be avoided. Refer to Figure 38 for details. A good reset pulse must be low forat least 10 µs. There is an internal spike filter to reject spikes up to 20ns wide.

NOTE: See Timing Requirements for more information.

Figure 38. External Reset Timing

Finally, a software reset can be activated by writing a '1' to CB1.1 (bit 1 of control byte 1). It should be noted thisreset is not self-clearing so the user must write a '0' to remove the software reset.

A reset clears all registers and loads default values. A power-on reset and external (hardware) reset takeprecedence over a software reset. If a software reset is not cleared by the user, it is cleared by either a power-onreset or an external (hardware) reset.

Product Folder Link(s): TSC2004

www.ti.com

THEORY OF OPERATION

TOUCH SCREEN MEASUREMENTS

Conversion Controlled by TSC2004 Initiated by TSC2004 (TSMode 1)

tCOORDINATE +OH1

fOSC )2@ǒtPVS)tPRE)tSNS)OHDLY1

fOSC Ǔ)2@ǒN@ǒ(B)2)@fOSC

fADC )OHCONVǓ@ǒ1

fOSCǓ)ǒLPPRO

fOSC ǓǓ

(5)

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

As noted previously in the discussion of the A/D converter, several operating modes can be used that allow greatflexibility for the host processor. This section examines these different modes.

In TSMode 1, before a pen touch can be detected, the TSC2004 must be programmed with PSM = 1 and one oftwo scan modes:1. X-Y-Z Scan (converter function select bits C[3:0] = Control Byte 1 D[6:3] = 0000); or2. X-Y Scan (converter function select bits C[3:0] = Control Byte 1 D[6:3] = 0001).

See Table 7 for more information on the converter function select bits.

When the touch panel is touched, and the internal pen-touch signal activates, the PINTDAV output is lowered if itis programmed as PENIRQ. The TSC2004 then executes the preprogrammed scan function without a hostintervention.

At the same time, the TSC2004 starts up its internal clock. It then turns on the Y-drivers, and after a programmedpanel voltage stabilization time, powers up the A/D converter and converts the Y coordinate. If preprocessing isselected, several conversions may take place. When data preprocessing is complete, the Y coordinate result isstored in a temporary register.

If the screen is still touched at this time, the X-drivers are enabled, and the process repeats, but measures the Xcoordinate instead, and stores the result in a temporary register.

If only X and Y coordinates are to be measured, then the conversion process is complete. A set of X and Ycoordinates are stored in the X and Y registers. Figure 39 shows a flowchart for this process. The time it takes togo through this process depends upon the selected resolution, internal conversion clock rate, panel voltagestabilization time, precharge and sense times, and whether preprocessing is selected. The time needed to get acomplete X and Y coordinate (sample set) reading can be calculated by:

Where:

COORDINATE

= time to complete X/Y coordinate reading.t

PVS

= panel voltage stabilization time, as given in Table 16 .t

PRE

= precharge time, as given in Table 17 .t

SNS

= sense time, as given in Table 18 .N = number of measurements for MAV filter input, as given in Table 3 as N.(For no MAV: M1-0[1:0] = '00', W1-0[1:0] = '00', N = 1.)B = number of bits of resolution.f

OSC

= TSC onboard OSC clock frequency. See Electrical Characteristics for supply frequency (SNSVDD).f

ADC

= A/D converter clock frequency, as given in Table 15 .OH1 = overhead time #1 = 2.5 internal clock cycles.OH

DLY1

= total overhead time for t

PVS

, t

PRE

, and t

SNS

= 10 internal clock cycles.OH

CONV

= total overhead time for A/D conversion = 3 internal clock cycles.L

PPRO

= preprocessor preprocessing time as given in Table 31 .

Product Folder Link(s): TSC2004

www.ti.com

Programmedfor

Self-Control

X-YScanMode

(PSM=1)

(ControlByte1

D[6:3]=0001)

TSC

NotAddressed

DetectingTouch

Sample,Conversion,and

Preprocessingfor

YCoordinate

Detecting

Touch

Sample,Conversion,and

Preprocessingfor

XCoordinate

Sample,Conversion,and

Preprocessingfor

YCoordinate

Detecting

Touch

Detecting

Touch

Reading

X-Data

Reading

Y-Data

TouchisDetected TouchisDetected

TouchisDetected

PINTDAV Programmed:

As ,

CFR2,D[15:14]=10

PENIRQ

CFR2,D[15:14]=11or01

DAV,

As and ,

CFR2,D[15:14]=00

PENIRQ DAV

tCOORDINATE

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

Table 31. Preprocessing Delay

PPRO

M = W = FOR B = 12 BIT FOR B = 10 BIT

1 1, 4, 8, 16 2 23, 7 1 28 247 3 31 2715 1 31 2915 3 34 3215 7 38 36

Figure 39. Example of an X and Y Coordinate Touch Screen Scan using TSMode 1

Product Folder Link(s): TSC2004

www.ti.com

tCOORDINATE +OH2

fOSC )3@ǒtPVS)tPRE)tSNS)OHDLY1

fOSC Ǔ)4@ǒN@ǒ(B)2)@fOSC

fADC )OHCONVǓ@ǒ1

fOSCǓ)ǒLPPRO

fOSC ǓǓ

(6)

Programmedfor

Self-Control

(PSM=1)

X-Y-Z -Z ScanMode

(ControlByte1

D[6:3]=0000)

1 2

TSC

NotAddressed

Sample,Conversion,

andPreprocessingfor

YCoordinate

Sample,Conversion,

andPreprocessingfor

XCoordinate

Sample,Conversion,

andPreprocessingfor

Z CoordinateandZ Coordinate

1 2

Sample,Conversion,

andPreprocessingfor

YCoordinate

Reading

X-Data

TouchisDetected

Detecting

Touch

Detecting

Touch

Detecting

Touch

Detecting

Touch

Reading

Y-Data

Reading

Z -Data

Reading

Z -Data

TouchisDetected TouchisDetected

TouchisDetected

PINTDAV Programmed:

As ,

CFR2,D[15:14]=10

PENIRQ

As ,

CFR2,D[15:14]=11or01

DAV

As and ,

CFR2,D[15:14]=00

PENIRQ DAV

tCOORDINATE

Detecting

Touch

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

If the pressure of the touch is also to be measured, the process continues in the same way, but measuring the Z

1and Z

values instead, and storing the results in temporary registers. Once the complete sample set of data (X,Y, Z

, and Z

) are available, they are loaded in the X, Y, Z

, and Z

registers. This process is illustrated inFigure 40 . As before, this process time depends upon the settings described above. The time for a complete X,Y, Z

, and Z

coordinate reading is given by:

Where:

OH2 = overhead time #2 = 3.5 internal clock cycles.

Figure 40. Example of an X, Y, and Z Coordinate Touch Screen Scan using TSMode 1

Product Folder Link(s): TSC2004

www.ti.com

Conversion Controlled by TSC2004 Initiated by Host (TSMode 2)

tCOORDINATE +OH1

fOSC )2@ǒtPVS)tPRE)tSNS)OHDLY1

fOSC Ǔ)2@ǒN@ǒ(B)2)@fOSC

fADC )OHCONVǓ@ǒ1

fOSCǓ)ǒLPPRO

fOSC ǓǓ

(7)

Detecting

Touch

PINTDAV Programmed:

As ,

CFR2,D[15:14]=10

PENIRQ

As ,

CFR2,D[15:14]=11or01

DAV

As and ,

CFR2,D[15:14]=00

PENIRQ DAV

Programmed

for

Host-

Controlled

Mode

(PSM=0)

TSC

Not

Addressed

P ograr mm d

for

X-Y

ScanMode

eReading

X-Data

WaitingforHostto

WriteInto

ControlByte1D[6:3]

Sample,Conversion,

andPreprocessingfor

YCoordinate

TouchisStillHere

Reading

Y-Data

TSC

NotAddressed

TSC

NotAddressed

Detecting

Touch

TouchisDetected

Sample,Conversion,

andPreprocessingfor

XCoordinate

Detecting

Touch

tCOORDINATE

Detecting

Touch

Sample,Conversion,

andPreprocessingfor

YCoordinate

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

In TSMode 2, the TSC2004 detects when the touch panel is touched and causes the internal Pen-Touch signalto activate, which lowers the PINTDAV output if it is programmed as PENIRQ. The host recognizes the interruptrequest, and then writes to the A/D Converter Control register to select one of the two touch screen scanfunctions:

1. X-Y-Z Scan (converter function select bits C[3:0] = Control Byte 1 D[6:3] = 0000); or2. X-Y Scan (converter function select bits C[3:0] = Control Byte 1 D[6:3] = 0001).

See Table 7 for more information on the converter function select bits.

The conversion process then proceeds as shown in Figure 41 ; see the previous sections for more details.

The main difference between this mode and the previous mode is that the host, not the TSC2004, decides whenthe touch screen scan begins.

The time needed to convert both X and Y coordinates under host control (not including the time needed to sendthe command over the I

C bus) is given by:

Figure 41. Example of an X and Y Coordinate Touch Screen Scan using TSMode 2

Product Folder Link(s): TSC2004

www.ti.com

Conversion Controlled by Host (TSMode 3)

tCOORDINATE +OH1

fOSC )ǒtPRE)tSNS)OHDLY2

fOSC Ǔ)N@ǒ(B)2)@fOSC

fADC )OHCONVǓ@ǒ1

fOSCǓ)ǒLPPRO

fOSC Ǔ

(8)

Programmed

forHost-

Controlled

Mode

(PSM=0)

Scan

Mode

Programmedfor:

TurnOn

X+and

Drivers

(1)

Reading

Y-Data

TouchisDetected

NOTE:(1)Optional.Ifnotturnedon,itwillbeturnedonbytheScanmode,oncedetected.

Scan

Mode

Programmedfor:

TurnOn

Y+and

Drivers

(1)

Reading

X-Data

Detecting

Touch

WaitingforHosttoWriteInto

ControlByte1D[6:3]

PINTDAV Programmed:

As ,

CFR2,D[15:14]=10

PENIRQ

As ,

CFR2,D[15:14]=11or01

DAV

As and ,

CFR2,D[15:14]=00

PENIRQ DAV

TouchisDetected TouchisDetected

Sample,Conversion,

andPreprocessing

forXCoordinate

Detecting

Touch

Sample,Conversion,

andPreprocessing

forYCoordinate

Detecting

Touch

WaitingforHostto

WriteIntoControl

Byte1D[6:3]

WaitingforHosttoWriteInto

ControlByte1D[6:3]

tCOORDINATE tCOORDINATE

TSC

Not

Addressed

TSC

Not

Addressed

TSC

Not

Addressed

TSC

Not

Addressed

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

In TSMode 3, the TSC2004 detects when the touch panel is touched and causes the internal Pen-Touch signalto be active, which lowers the PINTDAV output if it is programmed as PENIRQ. The host recognizes the interruptrequest. Instead of starting a sequence in the TSC2004, which then reads each coordinate in turn, the host mustnow control all aspects of the conversion. Generally, upon receiving the interrupt request, the host turns on the Xdrivers. ( NOTE: If drivers are not turned on, the device detects this condition and turns them on before the scanstarts. This situation is why the event of Turn On Drivers is shown as optional in Figure 42 and Figure 43 .) Afterwaiting for the settling time, the host then addresses the TSC2004 again, this time requesting an X coordinateconversion.

The process is then repeated for the Y and Z coordinates. The processes are outlined in Figure 42 andFigure 43 .Figure 42 shows two consecutive scans on X and Y. Figure 43 shows a single Z scan.

The time needed to convert any single coordinate X or Y under host control (not including the time needed tosend the command over the I

C bus) is given by:

Where:

DLY2

= total overhead time for t

PRE

and t

SNS

= 6 internal clock cycles.

Figure 42. Example of X and Y Coordinate Touch Screen Scan using TSMode 3

Product Folder Link(s): TSC2004

www.ti.com

tCOORDINATE +OH2

fOSC )ǒtPRE)tSNS)OHDLY2

fOSC Ǔ)N@ǒ(B)2)@fOSC

fADC )OHCONVǓ@ǒ1

fOSCǓ)ǒLPPRO

fOSC Ǔ

(9)

NOTE:(1)Optional.Ifnotturnedon,itwillbeturnedonbytheScanmode,oncedetected.

Detecting

Touch

PINTDAV Programmed:

As ,

CFR2,D[15:14]=10

PENIRQ

As ,

CFR2,D[15:14]=11or01

DAV

As and ,

CFR2D[15:14]=00

PENIRQ DAV

Programmed

for

Host-Controlled

Mode

(PSM=0)

TSC

Not

Addressed Z

Scan

Mode

Reading

Z -Data

WaitingforHosttoWrite

IntoControlByte1D[6:3]

TouchisDetected

Reading

Z -Data

TSC

NotAddressed

TSC

NotAddressed

Detecting

Touch

WaitingforHosttoWrite

IntoControlByte1D[6:3]

TouchisDetected

tCOORDINATE

TurnOn

Y+

and

Drivers

(1)

Programmedfor:

Sample,Conversion,

andPreprocessing

forZ Coordinate

Sample,Conversion,

andPreprocessing

forZ Coordinate

tCOORDINATE +OH2

fOSC )ǒtPVS)tPRE)tSNS)OHDLY1

fOSC Ǔ)N@ǒ(B)2)@fOSC

fADC )OHCONVǓ@ǒ1

fOSCǓ)ǒLPPRO

fOSC Ǔ

(10)

Detecting

Touch

PINTDAV Programmed:

As ,

CFR2,D[15:14]=10

PENIRQ

As ,

CFR2,D[15:14]=11or01

DAV

As and ,

CFR2D[15:14]=00

PENIRQ DAV

Programmedfor

Host-Controlled

Mode

(PSM=0)

TSC

NotAddressed P ograr mm d

for

Z -Z

ScanMode

1 2

Reading

Z -Data

WaitingforHosttoWrite

IntoControlByte1D[6:3]

Sample,Conversion,and

PreprocessingforZ ,Z Coordinates

1 2

TouchisStillHere

Reading

Z -Data

TSC

NotAddressed

TSC

NotAddressed

Detecting

Touch

WaitingforHosttoWrite

IntoControlByte1D[6:3]

TouchisDetected

tCOORDINATE

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

The time needed to convert any Z

and Z

coordinate under host control (not including the time needed to sendthe command over the I

C bus) is given by:

Figure 43. Example of Z

and Z

Coordinate Touch Screen Scan(without Panel Stabilization Time) using TSMode 3

If the drivers are not turned on before the touch screen scan mode is programmed, the panel stabilization timeshould be included. In this case, the time needed to convert any single X or Y under host control (not includingthe time needed to send the command over the I

C bus) is given by:

Figure 44. Example of a Z

and Z

Coordinate Touch Screen Scan(with Panel Stabilization Time) using TSMode 3

Product Folder Link(s): TSC2004

www.ti.com

tCOORDINATE +OH1

fOSC )ǒtPVS)tPRE)tSNS)OHDLY1

fOSC Ǔ)N@ǒ(B)2)@fOSC

fADC )OHCONVǓ@ǒ1

fOSCǓ)ǒLPPRO

fOSC Ǔ

(11)

Detecting

Touch

PINTDAV Programmed:

As ,

CFR2,D[15:14]=10

PENIRQ

As ,

CFR2,D[15:14]=11or01

DAV

As and ,

CFR2,D[15:14]=00

PENIRQ DAV

Programmedfor

Host-Controlled

Mode

(PSM=0)

TSC

NotAddressed

TSC

NotAddressed

TSC

NotAddressed

P ograr mm d

for

ScanMode

eReading

X-Data

Detecting

Touch

WaitingforHosttoWrite

IntoControlByte1D[6:3]

Sample,Conversion,and

PreprocessingforXCoordinate

WaitingforHosttoWrite

IntoControlByte1D[6:3]

TouchisDetected

TouchisStillHere

tCOORDINATE

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

The time needed to convert any single coordinate (either X or Y) under host control (not including the timeneeded to send the command over the I

C bus) is given by:

Figure 45. Example of a Single X Coordinate Touch Screen Scan(with Panel Stabilization Time) using TSMode 3

Product Folder Link(s): TSC2004

www.ti.com

AUXILIARY AND TEMPERATURE MEASUREMENT

tCOORDINATE +OH3

fOSC )N@ǒ(B)2)@fOSC

fADC )OHCONVǓ@ǒ1

fOSCǓ)ǒLPPRO

fOSC Ǔ

(12)

TSC

NotAddressed

NoTouch

Detected

HostWriteto

ControlByte1D[6:3]

As DAV

WaitingforHostto

ReadAUXData

TSC

NotAddressed Reading

AUX-Data

Sample,Conversion,and

AveragingforAUXMeasurement

TSC

NotAddressed

P ograr mm dfor

Non-Continuous

AUXMeasurement

tCOORDINATE

NoTouch

Detected

tCOORDINATE +OH3

fOSC )N@ǒ(B)2)@fOSC

fADC )OHCONVǓ@ǒ1

fOSCǓ)ǒLPPRO

fOSC Ǔ

(13)

TSC

NotAddressed

NoTouch

Detected

HosttoWriteto

ControlByte1D[6:3]

As DAV

TSC

NotAddressed Reading

AUX-Data

Sample,Conversion,

andAveragingfor

AUXMeasurement

TSC

NotAddressed

P ograr mm dfor

Continuous

AUXMeasurement

TSC

Not

Addressed

Reading

AUX-Data

tCOORDINATE tCOORDINATE tCOORDINATE

Sample,Conversion,

andAveragingfor

AUXMeasurement

Sample,Conversion,

andAveragingfor

AUXMeasurement

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

The TSC2004 can measure the voltage from the auxiliary input (AUX) and from the internal temperature sensor.Applications for the AUX can include external temperature sensing, ambient light monitoring for controllingbacklighting, or sensing the current drawn from batteries. There are two converter functions that can be used forthe measurement of the AUX:1. Non-continuous AUX measurement shown in Figure 46 (converter function select bits C[3:0] = Control Byte 1D[6:3] = 0101); or2. Continuous AUX Measurement shown in Figure 47 (converter function select bits C[3:0] = Control Byte 1D[6:3] = 1000).

See Table 7 for more information on the converter function select bits.

There are also two converter functions for the measurement of the internal temperature sensor:1. TEMP1 measurement (converter function select bits C[3:0] = Control Byte 1 D[6:3] = 0110); or2. TEMP2 measurement (converter function select bits C[3:0] = Control Byte 1 D[6:3] = 0111).

See Table 7 for more information on the converter function select bits.

For the detailed calculation of the internal temperature sensor, please see the Internal Temperature Sensorsection. These two converter functions have the same timing as the non-continuous AUX measurementoperation as shown in Figure 46 ; therefore, Equation 12 can also be used for internal temperature sensormeasurement. The time needed to make a non-continuous auxiliary measurement or an internal temperaturesensor measurement is given by:

Where:

OH3 = overhead time #3 = 3.5 internal clock cycles.

Figure 46. Non-Touch Screen, Non-Continuous AUX Measurement

The time needed to make continuous auxiliary measurement is given by:

Figure 47. Non-Touch Screen, Continuous AUX Measurement

Product Folder Link(s): TSC2004

www.ti.com

LAYOUT

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

The following layout suggestions should obtain optimum performance from the TSC2004. However, manyportable applications have conflicting requirements for power, cost, size, and weight. In general, most portabledevices have fairly clean power and grounds because most of the internal components are very low power. Thissituation would mean less bypassing for the converter power and less concern regarding grounding. Still, eachapplication is unique and the following suggestions should be reviewed carefully.

For optimum performance, care should be taken with the physical layout of the TSC2004 circuitry. The basicSAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections,and digital inputs that occur just prior to latching the output of the analog comparator. Therefore, during anysingle conversion for an n-bit SAR converter, there are nwindows in which large external transient voltages caneasily affect the conversion result. Such glitches might originate from switching power supplies, nearby digitallogic, and high power devices. The degree of error in the digital output depends on the reference voltage, layout,and the exact timing of the external event. The error can change if the external event changes in time withrespect to the SCL input.

With this in mind, power to the TSC2004 should be clean and well-bypassed. A 0.1 µF ceramic bypass capacitorshould be added between (SNSVDD to AGND and SNSGND) or (I/OVDD to DGND). A 0.1 µF decouplingcapacitor between VREF to AGND is also needed unless the SNSVDD is used as a reference input and isconnected to VREF. These capacitors must be placed as close to the device as possible. A 1 µF to 10 µFcapacitor may also be needed if the impedance of the connection between SNSVDD and the power supply ishigh. The I/OVDD needs to be shorted to the same supply plane as the SNSVDD. Short both SNSVDD andI/OVDD to the analog VDD plane.

The A/D converter architecture offers no inherent rejection of noise or voltage variation in regards to using anexternal reference input, which is of particular concern when the reference input is tied to the power supply forauxiliary input and temperature measurements. Any noise and ripple from the supply appears directly in thedigital results. While high-frequency noise can be filtered out by the built-in MAV filter, voltage variation as aresult of line frequency (50Hz or 60Hz) can be difficult to remove. Some package options have pins labeled asNC (no connection). It is recommended that these NC pins be connected to the ground plane. Avoid any activetrace going under the analog pins listed in the Pin Assignments table, unless they are shielded by a ground orpower plane.

All GND (AGND, DGND, SUBGND and SNSGND) pins should be connected to a clean ground point. In manycases, this point is the analog ground. Avoid connections that are too near the grounding point of amicrocontroller or digital signal processor. If needed, run a ground trace directly from the converter to thepower-supply entry or battery connection point. The ideal layout includes an analog ground plane dedicated tothe converter and associated analog circuitry.

In the specific case of use with a resistive touch screen, care should be taken with the connection between theconverter and the touch screen. Because resistive touch screens have fairly low resistance, the interconnectionshould be as short and robust as possible. Loose connections can be a source of error when the contactresistance changes with flexing or vibrations.

As indicated previously, noise can be a major source of error in touch-screen applications (for example,applications that require a back-lit LCD panel). This electromagnetic interfence (EMI) noise can be coupledthrough the LCD panel to the touch screen and cause flickering of the converted A/D converter data. Severalthings can be done to reduce this error, such as using a touch screen with a bottom-side metal layer connectedto ground, which couples the majority of noise to ground. Another way to filter out this type of noise is by usingthe TSC2004 built-in MAV filter (see the Preprocessing section). Filtering capacitors, from Y+, Y – , X+, and X – toground, can also help. Note, however, that the use of these capacitors increases screen settling time andrequires longer panel voltage stabilization times, and also increases precharge and sense times for the PINTADVcircuitry of the TSC2004. The resistor value varies depending on the touch screen sensor used. The internal50k Ωpull-up resistor (R

IRQ

) may be adequate for most of sensors.

Product Folder Link(s): TSC2004

www.ti.com

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision D (February 2008) to Revision E ............................................................................................. Page

•Changed air gap discharge from 18kV to 25kV in the ESD protection discharge sub-bullets of Features ........................... 1•Deleted "Target" from the ESD protection discharge sub-bullets of Features ...................................................................... 1•Changed IEC air discharge in the Absolute Maximum Ratings from ± 18 to ± 25 .................................................................. 2•Changed resistance ratio from 80 to 91 .............................................................................................................................. 17•Changed resistance ratio from 80 to 91 .............................................................................................................................. 17•Changed T factor from 2.648 to 2.573 ................................................................................................................................. 17

Changes from Revision C (October 2007) to Revision D ............................................................................................... Page

•Deleted references to WCSP package availability ................................................................................................................ 1•Changed HBM ESD protection from 6kV to 8kV in Features bullet ...................................................................................... 1•Changed clock frequency for SNSVDD = 1.2V from 3.3 to 3.2 ............................................................................................. 3•Changed clock frequency (for SNSVDD = 1.6V) min value from 3.6 to 3.3 and typ value from 3.9 to 3.7 ........................... 3•Added SNSVDD = I/OVDD = V

REF

= 1.6V condition to power-down supply current ............................................................. 3•Changed power-down supply current typ value from 0 to 0.023 ........................................................................................... 3•Changed Figure 9 ............................................................................................................................................................... 10•Changed Equation 8 ; moved paren ..................................................................................................................................... 45•Changed Equation 9 ; moved paren ..................................................................................................................................... 46•Changed Equation 10 ; moved paren ................................................................................................................................... 46•Changed Equation 11 ; moved paren ................................................................................................................................... 47•Changed Equation 12 ; moved paren ................................................................................................................................... 48•Changed Equation 13 ; moved paren ................................................................................................................................... 48

Product Folder Link(s): TSC2004

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

TSC2004IRTJR ACTIVE QFN RTJ 20 3000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

TSC2004IRTJRG4 ACTIVE QFN RTJ 20 3000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

TSC2004IRTJT ACTIVE QFN RTJ 20 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

TSC2004IRTJTG4 ACTIVE QFN RTJ 20 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

TSC2004IYZKR ACTIVE DSBGA YZK 24 3000 Green (RoHS &

no Sb/Br) SNAGCU Level-1-260C-UNLIM

TSC2004IYZKT ACTIVE DSBGA YZK 24 250 Green (RoHS &

no Sb/Br) SNAGCU Level-1-260C-UNLIM

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 12-May-2009

Addendum-Page 1

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TSC2004IRTJR QFN RTJ 20 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2

TSC2004IRTJT QFN RTJ 20 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2

TSC2004IYZKR DSBGA YZK 24 3000 180.0 8.4 2.75 2.75 0.81 4.0 8.0 Q1

TSC2004IYZKR DSBGA YZK 24 3000 178.0 8.4 2.75 2.75 0.81 4.0 8.0 Q1

TSC2004IYZKT DSBGA YZK 24 250 180.0 8.4 2.75 2.75 0.81 4.0 8.0 Q1

TSC2004IYZKT DSBGA YZK 24 250 178.0 8.4 2.75 2.75 0.81 4.0 8.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TSC2004IRTJR QFN RTJ 20 3000 367.0 367.0 35.0

TSC2004IRTJT QFN RTJ 20 250 210.0 185.0 35.0

TSC2004IYZKR DSBGA YZK 24 3000 210.0 185.0 35.0

TSC2004IYZKR DSBGA YZK 24 3000 217.0 193.0 35.0

TSC2004IYZKT DSBGA YZK 24 250 210.0 185.0 35.0

TSC2004IYZKT DSBGA YZK 24 250 217.0 193.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 2

D: Max =

E: Max =

2.598 mm, Min =

2.538 mm

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All

semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time

of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or

other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information

published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or

endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the

third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration

and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered

documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service

voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.

TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements

concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support

that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which

anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause

harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use

of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and

requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in

military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components

which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and

regulatory requirements in connection with such use.

TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which

have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such

components to meet such requirements.

Products Applications

Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive

Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications

Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers

DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps

DSP dsp.ti.com Energy and Lighting www.ti.com/energy

Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial

Interface interface.ti.com Medical www.ti.com/medical

Logic logic.ti.com Security www.ti.com/security

Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense

Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video

RFID www.ti-rfid.com

OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com

Wireless Connectivity www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265