64/256/5 12/1K/2K/4K x18 Low-Voltage Synchronous FIFO
s
CY7C4225V/4205V/4215
V
CY7C4425V/4235V/4245
V
Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600
Document #: 38-06029 Rev. *B Revised August 20, 2003
Features
• 3.3V operation for low power consumption and easy
integration into low-voltage systems
• High-speed, low-power, first-in first-out (FIFO)
memories
• 64 x 18 (CY7C4425V)
• 256 x 18 (CY7C4205V)
• 512 x 18 (CY7C4215V)
• 1K x 18 (CY7C4225V)
• 2K x 18 (CY7C4235V)
• 4K x 18 (CY7C4245V)
•0.65µ CMOS
• High-speed 67-MHz operation (15-ns read/write cycle
times)
• Low power
—ICC = 30 mA
• 5V tolerant inputs (VIH MAX = 5V)
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, Half Full, and programmable Almost Empty
and Almost Full status flags
• TTL-compatible
• Retransmit function
• Output Enable (OE) pin
• Independent read and write enable pins
• Supports free-running 50% duty cycle clock inputs
• Width-Expansion Capability
• Depth-Expansion Capability
• 64-pin 14 × 14 TQFP and 64-pin 10 × 10 STQFP
Functional Description
The CY7C42X5V are high-speed, low-power, first-in first-out
(FIFO) memories with clocked read and write interfaces. All
are 18 bits wide. The CY7C42X5V can be cascaded to
increase FIFO depth. Programmable features include Almost
Full/Almost Empty flags. These FIFOs provide solutions for a
wide variety of data buffering needs, including high-speed data
acquisition, multiprocessor interfaces, and communications
buffering.
These FIFOs have 18-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a Free-Running Clock (WCLK) and a Write
Ena ble pin (WEN).
When WEN is asserted, data is written into the FIFO on the
rising edge of the WCLK signal. While WEN is held active, data
is continually written into the FIFO on each cycle. The output
port is c ontrol led in a simila r manne r by a Fr ee-Ru nning Re ad
Clock (RCLK) and a Read Enable pin (REN). In addition, the
CY7C42X5V have an Output Enable pin (OE). The re ad and
write c lo ck s may be ti ed to get her for single-clock o pera tio n or
the two clocks may be run independently for asynchronous
read/write applications. Clock frequencies up to 66 MHz are
achievable.
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
Depth expansion is possible using the Cascade Input (WXI,
RXI), Cascade Output (WXO, RXO), an d Firs t Load (FL) pins.
The WXO and RXO pins are connected to the WXI and RXI
pins of the next device, and the WXO a nd RXO pins of t he last
device should be connected to the WXI and RXI pins of the
firs t device. The FL pin of the first device is ti ed to VSS and the
FL pin of all the remaining devices should be tied to VCC.
The CY7C42X5V provides five status pins. These pins are
decoded to determine one of five states: Empty , Almost Empty ,
Half F ull, Almos t Full, an d Full (se e Table 2). The Half Full flag
shares the WXO pin. This flag is valid in the stand-alone and
width-expansion configurations. In the depth expansion, this
pin prov ides the exp ansion out (WXO ) information that is used
to signal the next FIFO when it will be activated.
The Empty and Full flags are synchronous, i.e., they change
state relative to either the Read Clock (RCLK) or the write
clock (WCLK). When entering or exiting the Empty states, the
flag i s updated exclusively by the RCLK. Th e flag denoting Full
sta tes is upda ted ex clus ivel y by WCLK. Th e syn chrono us fl ag
architecture guarantees that the flags will remain valid from
one clock cycle to the next. As mentioned previously, the
Almost Empty/Almost Full flags become synchronous if the
VCC/SMODE is tied to VSS. All configurations are fabricated
using an advanced 0.65µ P-Well CMOS technology. Input
ESD protection is greater than 2001V, and latch-up is
prevented by the use of guard rings.
CY7C4225V/4205V/4215
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Document #: 38-06029 Rev. *B Page 2 of 20
Logic Block Diagram
THREE–STATE
OUTPUT REGISTER READ
CONTROL
FLAG
LOGIC
WRITE
CONTROL
WRITE
POINTER READ
POINTER
RESET
LOGIC
EXPANSION
LOGIC
INPUT
REGISTER
FLAG
PROGRAM
REGISTER
D
0−17
RENRCLK
FF
EF
PAE
Q0−17
WEN
WCLK
RS
FL/RT
WXI
OE
RAM
ARRAY
64 x 18
256 x 18
512 x 18
1K x 18
2K x 18
4K x 18
PAF
WXO/HF
RXI
RXO
SMODE
Pin Configuration
EF
STQFP/TQFP
Top Vi e w
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 50
32 49
16
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
Q15
GND
Q16
Q17
GND
VCC
RS
OE
LD
REN
RCLK
GND
D17
D16
PAE
WCLK
WEN
WXI
VCC
PAF
RXI
FF
WXO/HF
RXO
Q0
Q1
GND
Q2
Q3
Q14
Q13
GND
Q12
Q11
VCC
Q10
Q9
GND
Q8
Q7
Q6
Q5
GND
Q4
VCC
VCC/SMOD
E
FL/RT
CY7C4425V
CY7C4205V
CY7C4215V
CY7C4225V
CY7C4235V
CY7C4245V
CY7C4225V/4205V/4215
V
CY7C4425V/4235V/4245
V
Document #: 38-06029 Rev. *B Page 3 of 20
Selection Guide
CY7C42X5V-15 CY7C42X5V-25 CY7C42X5V-35 Unit
Maximum Frequency 66.7 40 28.6 MHz
Maximum Access Time 11 15 20 ns
Minimum Cycle Time 15 25 35 ns
Minimum Data or Enable Set-up 4 6 7 ns
Minimum Data or Enable Hold 1 1 2 ns
Maximum Flag Delay 11 15 20 ns
Operating Current Commercial 30 30 30 mA
CY7C4425V CY7C4205V CY7C4215V CY7C4225V CY7C4235V CY7C4245V
Density 64 x 18 256 x 18 512 x 18 1K x 18 2K x 18 4K x 18
Packages 64-pin 14x14
TQFP
64-pin 10x10
STQFP
64-pin 14x14
TQFP
64-pin 10x10
STQFP
64-pin 14x14
TQFP
64-pin 10x10
STQFP
64-pin 14x14
TQFP
64-pin 10x10
STQFP
64-pin 14x14
TQFP
64-pin 10x10
STQFP
64-pin 14x14
TQFP
64-pin 10x10
STQFP
Pin Definitions
Signal Name Description I/O Function
D0−17 Data Inputs I Data inputs for an 18-bit bus.
Q0−17 Data Outputs O Data outputs for an 18-bit bus.
WEN Wri te Enab le I Enables the WCLK input.
REN Read Enable I Enables the RCLK input.
WCLK Wri te Cloc k I The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is
not Full. Whe n LD is ass ert ed, WC LK wr ites data into t he pr ogram mab le
flag-offset register.
RCLK Read Clock I The rising ed ge clock s dat a out of the FIFO whe n REN is LOW and the FIFO is
not Empty. When LD i s asser ted , RCLK read s data out of the progra mmab le
flag-offset register.
WXO/HF Wri te Expansion
Out/Half Full Flag ODual-Mod e Pin. Sin gle de vic e o r width expans io n - Half Full stat us fl ag. Casc ad ed –
Write Expansion Out signal, connected to WXI of next device.
EF Empty Flag O When EF is LOW, the FIFO is empty. EF is sync hro niz ed to R CLK.
FF Full Flag O When FF is LOW, the FIFO is full. FF is sync hroni zed to WCL K.
PAE Programmable
Almost Empty OWhen PAE is LOW, the FIFO is almo st e mpty base d on th e almo st emp ty
offset value programmed into the FIFO. PAE is async hro nous wh en
VCC/SMODE is ti ed to VCC; it is synchronized to RCLK when VCC/SMODE is tied
to VSS.
PAF Programmable
Almost Full OWhen PAF is LOW, the FIFO is almost full based on the almost full offset
val ue pro gram med i nto the FIFO. PAF is asynchronous when VCC/SMODE is
tied to VCC; it is sync hro nized to WCL K when VCC/SMODE is tied to VSS.
LD Load I When LD is LOW, D0−17 (O0−17) are written (read) into (from) the program-
mable-flag-offset register.
FL/RT First Load/
Retransmit IDual-Mode Pin. Cascaded – The first device in the daisy chain will have FL tied to
VSS; all other devices will have FL tied to V CC. In standard mode of width
expansion, FL is tied to VSS on all devices. Not Cascaded – T ied to VSS. Retransmit
function is also available in standalone mode by strobing RT.
WXI Wri te Expansion
Input ICascade d – Connecte d to WXO of previ ous device . Not Cascad ed – T ied to VSS.
CY7C4225V/4205V/4215
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Document #: 38-06029 Rev. *B Page 4 of 20
Architecture
The CY7 C 42X5 V co ns is t s o f an array of 6 4 to 4K words o f 18
bits each (imple mented by a du al-port a rray of SRAM cells ), a
read pointer, a write pointer, control signals (RCLK, WCLK,
REN, WEN, RS), and flags (EF, PAE, HF, PAF, FF). The
CY7C42X5V also includes the control signals WXI, RXI, WXO,
RXO for depth expansion.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS)
cycle. This causes the FIFO to enter the Empty condition
signified by EF being LOW. All dat a outputs go LO W aft er the
falling edge of RS only if OE is as se rted. In order for the FIFO
to reset to its default state, a falling edge must occur on RS
and the user must not read or write while RS is LOW.
FIFO Operation
When the WEN signal is active (LOW), data present on the
D0-17 pins is written into the FIFO on each rising edge of the
WCLK signal. Similarly, when the REN signal is active LOW,
data in the FIFO memory will be presented on the Q0−17
outputs. New data will be presented on each rising edge of
RCLK while REN is active LOW and OE is LOW. REN must
set up tENS before RCLK for it to be a valid read function. WEN
must occur tENS before WCLK for it to be a valid write function.
An Output Enable (OE) pin is provided to three-st ate the Q0–17
outputs when OE is deasserted. When OE is enabled (LOW),
data in the output register will be avail able to the Q0−17 outputs
after tOE. If devices are cascaded, the OE function will only
output data on the FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and und erflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q0−17 outputs
even after additional reads occur.
Programming
The CY7C42X5V devices contain two 12-bit offset registers.
Data present on D0–11 during a program write will determine
the distance from Empty (Full) that the Almost Empty (Almost
Full) flag s become ac tive. If the user elec ts not to prog ram the
FIFO’s fl ag s, the de f au l t off se t valu e s ar e us ed (see Table 2).
When the Loa d LD pin is set LOW and WEN is set LOW , da ta
on the inputs D0–11 is written into the Empty offset register on
the first LOW-to-HIGH transition of the write clock (WCLK).
When the LD pin and WEN ar e hel d LOW then data is written
into the Full offset register on the second LOW-to-HIGH
transiti on of the Write Clock (WCLK). The third transition of the
Write Clock (WCLK) again writes to the Empty offset register
(see Table 1). Writing all offset registers does not have to
occur at one time. One or two offset registers can be written
and then, by bring ing the LD pin HIGH, the FIF O is returned to
normal read/ write o peration. When the LD pin is set LOW , and
WEN is LOW, the next offset register in sequence is written.
The contents of the offset registers can be read on the output
lines when the LD pi n is set LOW and REN is set LOW; then,
data can be read on the LOW-to-HIGH transition of the Read
Clock (RCLK).
Note:
1. The same selection sequence applies to reading from the registers. R EN i s enab led and r ead is perf ormed on th e LOW -to- HIGH tr ansiti on of RC LK.
RXI Read Expansion
Input ICasc aded – Con nected to RXO of previous device. Not Casc aded – T ie d to VSS.
RXO Read Expansion
Output OCascaded – Connected to R XI of next device.
RS Reset I Reset s device to em pty condition. A re set is requi red befor e an initia l read or write
operation after power-up.
OE Output Enable I When OE is LOW, the FIFO’s data outputs drive the bus to which they are
connected. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance)
state.
VCC/SMODE Synchronous
Almost Empty/
Almost Full Flags
IDual-Mode Pin. Asynchronous Almost Empty/Almost Full flags – tied to VCC.
Synch ron ous Almo st Empt y/Almo st Fu ll flag s – tie d to VSS. (Almo st Em pty
sync hro nized to RCLK , Al most Ful l synch ron ized to WCLK .)
Pin Definitions (continued)
Signal Name Description I/O Function
Table 1. Write Offset Register
LD WEN WCLK[1] Selection
0 0 Writing to offset registers:
Empty Offs et
Full Offset
01 No Operation
1 0 Write Into FIFO
11 No Operation
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Document #: 38-06029 Rev. *B Page 5 of 20
Flag Operation
The CY7C42X5V devices provide five flag pins to indicate the
condition of the FIFO contents. Empty and Full are
synchr onous. PAE and PAF are synchronous if VCC/SMODE
is tied to VSS.
Full Flag
The Full Flag (FF) will go LOW when device is Full. Write
operations are inhibited whenever FF is LOW regardless of the
state of WEN. FF is synchronized to WCLK, i.e., it is exclu-
sively updated by each rising edge of WCLK.
Empty Flag
The E mpt y F lag ( EF) will go LOW when the device is empty.
Read operations are inhibited whenever EF is LOW,
regardless of the state of REN. EF is synchronized to RCLK,
i.e., it is exclusively updated by each rising edge of RCLK.
Programmable Almost Empty/Almost Full Flag
The CY7C42X5V features programmable Almost Empty and
Almost Full Flags. Each flag can be programmed (described
in the Programming section) a specific distance from the corre-
sponding boundary flags (Empty or Full). When the FIFO
contains the number of words or fewer for which the fla gs have
been programmed, the P AF or P AE will be asserted, signifying
that the FIFO is either Almost Full or Almost Empty. See
Table 2 for a description of programmable flags.
When the SMODE pin is tied LOW, the PAF flag signal
transition is caused by the rising edge of the write clock and
the PAE flag t ransition is caus ed by t he rising e dge of the read
clock.
Retransmit
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be ac knowledged by
the receiver and retransmitted if necessary.
The Retransmit (RT) input is active in the standalone and width
expansion modes. The retransmit feature is intended for use
when a num ber of writes e qua l to o r less than the dep th of t he
FIFO hav e occ urred si nce the last RS cycl e. A HIGH pulse on
R T reset s the intern al read pointe r to the f irst physic al locati on
of the FIFO. WCLK and RCLK may be free running but must
be disa bled dur ing and tRTR af ter the re transmit pulse. W ith
every valid read cycle after retransmit, previously accessed
data is read and the re ad pointer is in cremented until it is equal
to the write pointer. Flags are governed by the relative
locations of the read and write pointers and are updated during
a retransmit cycle. Data written to the FIFO after activation of
RT are transmitted also.
The full depth of the FIFO can be repeatedly retransmitted.
Table 2. Flag Truth Table
Number of Words in FIFO FF PAF HF PAE EF7C4425V - 64 x 18 7C4205V - 256 x 18 7C4215V - 512 x 18
000 HHHLL
1 to n[2] 1 to n[2] 1 to n[2] HHH LH
(n+1) to 32 (n+1) to 128 (n+1) to 256 H H H H H
33 to (64−(m+1)) 129 to (256−(m+1)) 257 to (512−(m+1)) H H L H H
(64−m)[3] to 63 (256−m)[3] to 2 5 5 (512-m)[3] to 511 H L L H H
64 256 512 L L L H H
Number of Words in FIFO FF PAF HF PAE EF 7C4225V - 1K x 18 7C4235V - 2K x 18 7C4245V - 4K x 18
000 HHHLL
1 to n[2] 1 to n[2] 1 to n[2] HHH LH
(n+1) to 512 (n+1) to 1024 (n+1) to 2048 H H H H H
513 to (1024 −(m+1)) 1025 to (2048 −(m+1)) 2049 to (4096 −(m+1)) H H L H H
(1024−m)[3] to 1023 (2048−m)[3] to 2047 (4096−m)[3] to 4095 H L L H H
1024 2048 4096 L L L H H
Note:
2. n = Empty Offset (Default Values: CY7C4425V n = 7, CY7C4205V n = 31, CY7C4215V n = 63, CY7C4225V/7C4235V/7C4245V n = 127).
3. m = Full Offset (Default Values: CY7C4425V n = 7, CY7C4205V n = 31, CY7C4215V n = 63, CY7C4225V/7C4235V/7C4245V n = 127).
CY7C4225V/4205V/4215
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CY7C4425V/4235V/4245
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Document #: 38-06029 Rev. *B Page 6 of 20
Width Expansion Configuration
The CY7C42X5V can be expanded in width to provide word
widths greater than 18 in increments of 18. During width
expansion mode all control line inputs are common and all
flags are available. Empty (Full) flags should be created by
ANDing the Empty (Full) flags of every FIFO. This technique
will a void re ady da t a fro m th e FI FO that is “s t a gge red” b y o ne
cloc k cycle due to the var iati ons in skew betwe en RCLK an d
WCLK. Figure 2 demonstrates a 36-word width by using two
CY7C42X5V .
Depth Exp ansion Configuration ( with Program-
mable Flags)
The CY7C42X5V can easily be adapted to applications
requiring more than 64/256/512/1024/2048/4096 words of
buffering. Figure 2 shows Depth Expansion using three
CY7C42X5Vs. Maximum depth is limited only by signal
loading. Follow these steps:
1. T he first device mu st be design ated by ground ing the First
Load (FL) control input.
2. All other devices must have FL in the HIGH stat e.
3. The Write Expansion Out (WXO) pin of each device must
be tied to the Write Expansion In (WXI) pin of the next de-
vice.
4. The Read Expansion Out (RXO) pin of each device must
be tied to the Read Expansion In (RXI) pin of the next de-
vice.
5. Al l Load (LD) pins are tied together.
6. T he Half-Full Fl ag (HF) is not avai lable in the De pth Expan-
sion Configuration.
7. EF, FF, PAE, and PAF are cre ated with c ompos ite flag s by
ORing together these respective flags for moni toring. The
composite PAE and PAF flags are not precise.
Figure 1. Block Diagram of Low-Voltage Synchronous FIFO Memories Used in a Width Expansion Configuration
FF
FF EF EF
WRITE CLOCK(WCLK)
WRITE ENABLE(WEN)
LOAD(LD)
PROGRAMMABLE(PAE)
HALF FULLFLAG(HF)
FULLFLAG(FF)
7C4425V
7C4205V
7C4215V
7C4225V
7C4235V
7C4245V
7C4425V
7C4205V
7C4215V
7C4225V
7C4235V
7C4245V
1836
DATAIN (D)
RESET(RS)
18
RESET(RS)
READCLOCK(RCLK)
READENABLE(REN)
OUTPUTENABLE(OE)
PROGRAMMABLE(PAF)
EMPTYFLAG(EF)
18
DATAOUT(Q)
18 36
FIRST LOAD(FL)
WRITE EXPANSION IN (WXI)
READ EXPANSION IN (RXI)
CY7C4225V/4205V/4215
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Document #: 38-06029 Rev. *B Page 7 of 20
Figure 2. Block Diagram of Low-Voltage Synchronous FIFO Memory
with Programmable Flags used in Depth Expansion Configuration
42X5V–23
WRITECLOCK(WCLK)
WRITE ENABLE(WEN)
RESET(RS)
LOAD(LD)
FF
PAF PAF
FF EF
PAE PAE
EF
WXI RXI
FIRSTLOAD(FL)
READCLOCK(RCLK)
READ ENABLE (REN)
OUTPUT ENABLE(OE)
WXO RXO
7C4425V
7C4205V
7C4215V
7C4225V
7C4235V
7C4245V
PAF
FF EF
PAE
WXI RXI
WXO RXO
7C4425V
7C4205V
7C4215V
7C4225V
7C4235V
7C4245V
VCC
FIRSTLOAD(FL)
PAF
FF EF
PAE
WXI RXI
WXO RXO
7C4425V
7C4205V
7C4215V
7C4225V
7C4235V
7C4245V
VCC
FIRSTLOAD(FL)
DATAIN (D) DATAOUT(Q)
CY7C4225V/4205V/4215
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Document #: 38-06029 Rev. *B Page 8 of 20
Maximum Ratings[4]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ....................................−65°C t o +15 0 °C
Ambient Temperature with
Pow er Applied.................................................−55°C t o + 12 5 °C
Supply Voltage to Ground Potential.................−0.5V to +5.0V
DC Voltage Applied to Outputs
in High-Z State.............................................−0.5V to VCC+0.5V
DC Input Voltage....................................................−0.5V to +5V
Output Current into Outpu t s (LO W)..................... ........20 mA
Static Discharge Voltage ...........................................>2001V
(per MIL-STD-883, Method 3015)
Latch-up Current......................................................>200 mA
Operating Range
Range Ambient Temperature VCC
Commercial 0°C to +70°C 3.3V ± 300 mV
Electri cal Characteristics Over the Op erating Range
Parameter Description Test Conditions
7C42X5V-15 7C42X5V-25 7C42X5V-35
UnitMin. Max. Min. Max. Min. Max.
VOH Output HI GH Voltage VCC = Min . ,
IOH = −2.0 m A 2.4 2.4 2.4 V
VOL Output LO W Volta ge VCC = Min . ,
IOL = 8.0 mA 0.4 0.4 0.4 V
VIH Input HIGH Voltage Low = 2.0V
High = VCC +0.5V 2.0 5.0 2.0 5.0 2.0 5.0 V
VIL[5] Input LOW Voltage Low = −3.0V
High = 0.8 V −0.5 0.8 −0.5 0.8 −0.5 0.8 V
IIX Input Leakage Current VCC = Max. −10 10 −10 10 −10 10 µA
IOZL
IOZH Output OFF,
High Z Current OE > VIH,
VSS < VO < VCC −10 +10 −10 +10 −10 +10 µA
ICC[6] Operati ng Curren t VCC = Max.,
IOUT = 0 mA Com’l 30 30 30 mA
ISB[7] Standby Current VCC = Max.,
IOUT = 0 mA Com’l 6 6 6 mA
Capacitance[8]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 5.0V 5pF
COUT Output Ca pacitance 7 pF
Notes:
4. The Voltage on any input or I/O pin cannot exceed the power pin during power-up
5. The VIH and VIL specifications apply for all inputs except WXI, RXI. The WXI, RXI pin is not a TTL input. It is connected to either RXO, WX O of the
previous device or VSS.
6. Input signals switch from 0V to 3V with a rise/fall time less than 3 ns, clocks and clock enables switch at 20 MHz, while the data inputs switch at 10 MHz. Outputs
are unloaded.
7. All inputs = VCC − 0.2V, exc ept WCLK and RC LK, wh ich are swit ching at 20 MH z.
8. Tested initially and after any design or process changes that may affect these parameters
CY7C4225V/4205V/4215
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Document #: 38-06029 Rev. *B Page 9 of 20
AC Test Loads and Waveforms[9, 10]
3.0V
3.3V
OUTPUT
R1= 330Ω
R2=510Ω
CL
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤3ns ≤3ns
OUTPUT Vth=2.0V
Equivale nt to: THÉ VENIN EQUIVALENT
Rth=200Ω
ALL INPUT PULSES
Switching Characteristics Over the Op erating Range
Parameter Description 7C42X5V-15 7C42X5V-25 7C42X5V-35 UnitMin. Max. Min. Max. Min. Max.
tSClock Cycle Frequency 66.7 40 28.6 MHz
tAData Access Time 211 215 220 ns
tCLK Clock Cyc le Time 15 25 35 ns
tCLKH Clock HIGH Time 610 14 ns
tCLKL Clock LOW Time. 610 14 ns
tDS Data Set-up Time 467ns
tDH Data Hold Time 122ns
tENS Enable Set-up Time 467ns
tENH Enable Hold Time 122ns
tRS Reset Pulse Width[11] 15 25 35 ns
tRSR Reset Recovery Time 10 15 20 ns
tRSF Reset to Flag and Output Time 18 25 35 ns
tPRT Retransmit Pulse Width 15 25 35 ns
tRTR Retransm it Reco very Time 15 25 35 ns
tOLZ Output Enable to Output in Low Z[12] 000ns
tOE Output Enable to Output Valid 38312 315 ns
tOHZ Output Enable to Output in High Z[12] 38312 315 ns
tWFF Write Clock t o Full Flag 11 15 20 ns
tREF Read Clock to Empty Flag 11 15 20 ns
tPAFasynch Clock to Programmable Almost-Full Flag[13]
(Asynchronous mode, VCC/SMODE tied to VCC)18 22 25 ns
tPAFsynch Clock to Programmable Almost-Full Flag
(Synchronous mode, VCC/SMODE tied to VSS)11 15 20 ns
tPAEasynch Clock to Programmable Almost-Empty Flag[13]
(Asynchronous mode, VCC/SMODE tied to VCC)18 22 25 ns
tPAEsynch Clock to Pro grammable Al most-F ull Flag
(Synchronous mode, VCC/SMODE tied to VSS)11 15 20 ns
tHF Clock to Half-Full Flag 16 20 25 ns
Notes:
9. CL = 30 pF for all AC parameters except for tOHZ.
10. CL = 5 pF for tOHZ.
11. Pulse widths less than minimum values are not allowed.
12. Values guaranteed by design, not currently tested.
13. tPAFasynch, tPAEasynch, after program register write will not be valid until 5 ns + tPAF(E).
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tXO Clock to Expansion Out 10 15 20 ns
tXI Expansion in Pulse Width 6.5 10 14 ns
tXIS Expansion in Set-up Time 510 15 ns
tSKEW1 Skew Time between Read Clock and Write Clock for
Full Flag 610 12 ns
tSKEW2 Skew Time between Read Clock and Write Clock for
Empty Flag 610 12 ns
tSKEW3 Skew Time between Read Clock and Write Clock for
Programmable Almost Empty and Programmable
Almost Full Flags.
15 18 20 ns
Switching Characteristics Over the Op erat ing Range (continued)
Parameter Description 7C42X5V-15 7C42X5V-25 7C42X5V-35 UnitMin. Max. Min. Max. Min. Max.
Switching Waveforms
Note:
14. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycl e. If th e time between the rising
edge of R CLK and the r ising edge of WCLK is less than t SKEW1, then FF may not ch ange s tate un til the n ext WCL K edge.
Write Cycle Timing
tCLKH tCLKL
NO OPERATION
tDS
tSKEW1
tENS
WEN
tCLK
tDH
tWFF tWFF
tENH
WCLK
D0–D17
FF
REN
RCLK
[14]
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Notes:
15. tSKEW2 is the minimum tim e between a risi ng WCLK edge and a rising RCLK edg e to guarantee that EF will go HIGH during the curren t clock cycl e. It the tim e between the rising
edge of W CLK and the rising edge of R CLK is l ess than t SKEW2, then EF may not change st ate until the next RCLK edge.
16. The clocks (RCLK, WCLK) can be free-running during reset.
17. After reset, the outputs will be LOW if OE = 0 and thre e-st ate if OE = 1.
Switching Waveforms (continued)
Read Cycle Timing
tCLKH tCLKL
NO OPERATION
tSKEW2
WEN
tCLK
tOHZ
tREF tREF
RCLK
Q0–Q17
EF
REN
WCLK
OE
tOE
tENS
tOLZ
tA
tENH
VALID DATA
[15]
tRS
tRSR
Q0- Q17
RS
tRSF
tRSF
tRSF OE=1
OE=0
REN,WEN,
LD
EF,PAE
FF,PAF,
HF
Reset Timing[16]
[17]
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Notes:
18. When tSKEW2 > minimum specif ication , tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specifi cation, t FRL ( maximu m) = eit her 2*tCLK + tSKEW2 or tCLK + tSKEW2.
The Latency T imin g applies only at the Empty Boundary (EF = LOW).
19. The first word is available the cycle after EF goes HI GH, always.
Switching Waveforms (continued)
D0(FIRSTVALIDWRITE)
First Data Word Latency after Resetwith Simultaneous Read and Write
tSKEW2
WEN
WCLK
Q0–Q17
EF
REN
OE tOE
tENS
tOLZ
tDS
RCLK
tREF
tA
tFRL
D1D2D3D4
D0D1
D0–D17
tA[19]
[18]
D1D0
tENS
tSKEW2
Empty Flag Timing
WEN
WCLK
Q0–Q17
EF
REN
OE
tDS
tENH
RCLK
tREF
tA
tFRL
D0–D17
D0
tSKEW2
tFRL
tREF
tDS
tENS tENH
tREF
[18]
[18]
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Switching Waveforms (continued)
NEXT DATA READ
DATA WRITE
NO WRITE
DATA IN OUTPUT REGISTER
Full Flag Timing
FF
WCLK
Q0–Q17
REN
OE
RCLK
tA
D0–D17
DATAREAD
tSKEW1 tDS
tENS tENH
WEN
tWFF
tA
tSKEW1
tENS tENH
tWFF
DATA WRITE
NO WRITE
tWFF
LOW
[14]
[14]
tENH
Half-Full Flag Timing
WCLK
HF
REN
RCLK
tCLKH
tHF
tENS
HALF FULL+1
OR MORE
tCLKL
tENS
HALFFULLORLESS HALFFULLORLESS
tHF
WEN
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Document #: 38-06029 Rev. *B Page 14 of 20
Notes:
20. PAE offset −n. Number of data w ords into FIFO already = n.
21. PAE offset −n.
22. tSKEW3 is the minimum t ime betw een a rising WCLK and a rising RCLK edge for PAE to cha nge st ate durin g that clock cycle. If the t ime be tween th e edge of WCLK and the
rising RCLK is less t han tSKEW3, then PAE may not change stat e until the next RCLK .
23. If a read is performed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW .
Switching Waveforms (continued)
tENH
Programmable Almost Empty Flag Timing
WCLK
PAE
REN
RCLK
tCLKH
tPAE
tENS
n+1 WORDS
IN FIFO
tCLKL
tENS
tPAE
n WORDS IN FIFO
[20]
WEN
tENH
WCLK
PAE
RCLK
tCLKH
tENS
tCLKL
tENS
tPAEsynch
N + 1 WORDS
INFIFO
tENH
tENS
tPAEsynch
REN
WEN
tSKEW3
Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW)
[22] Note
Note
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Document #: 38-06029 Rev. *B Page 15 of 20
Notes:
24. PAF offset = m. Number of data words written into FIFO already = 64 − m + 1 for the CY7C4425V, 256 − m + 1 for the CY7C4205V, 512 − m + 1 for the
CY7C4215V. 1024 − m + 1 for the CY7C4225V, 2048 − m + 1 for the CY7C4235V, and 4096 − m + 1 for the CY7C4245V.
25. PAF is offset = m.
26. 64 − m words in CY7C4425V, 256 – m words inCY7C4205V, 512 − m words in CY7C4215V. 1024 – m words in CY7C4225V, 2048 − m words in CY7C4235V,
and 4096 – m words in CY7C4245V.
27. 64 − m + 1 words in CY7C4425V, 256 − m + 1 words in CY7C4205V, 512 − m +1 words in CY7C4215V, 1024 − m + 1 CY7C4225V, 2048 − m + 1 in CY74235V ,
and 4096 − m + 1 words in CY7C4245V.
28. If a write is performed on this rising edge of the write clock, there will be Full – (m–1) words of the FIFO when PA F goes LOW .
29. PAF offset = m.
30. tSKEW3 is the minimum time between a rising RCLK and a rising WCLK edge for P AF to change state during that clock cycle. If the time between the edge of RCLK and the rising
edge of W CLK i s less than tSKEW3, then PAF m ay not change s tat e until the n ext WC LK risi ng ed ge.
Switching Waveforms (continued)
Note
tENH
WEN
WCLK
REN
RCLK
tCLKH
tPAF
tENS
tCLKL
tENS
tPAF
FULL −M WORDS
IN FIFO FULL −(M + 1) WORDS
IN FIFO
Programmable Almost Full Flag Timing
[27]
PAF
[25]
24
[26]
tENH
WCLK
PAF
RCLK
tCLKH
tENS
FULL −M WORDS
IN FIFO
tCLKL
tENS
FULL – (M+1) WORDS
IN FIFO
tENH
tENS
tPAF
REN
tSKEW3 tPAFsynch
[30]
Note 28
WEN
Programmable Almost Full Flag Timing (applies only in SMODE (SMODE in LOW))
[26]
Note 29
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Note:
31. Write to Last Physical Location.
Switching Waveforms (continued)
tENH
Write Programmable Registers
LD
WCLK
tCLKH
tENS
tCLKL
PAE OFF SET
D0–D17
WEN
tENS
PAF OFFSET
PAE OFFSET
tCLK
D0–D11
tDS tDH
tENH
Read Programmable Registers
LD
RCLK
tCLKH
tENS
tCLKL
PAE OFF SET
Q0–Q17
REN
tENS
PAF OFF SET PAE OFFSET
tCLK
UNKNOWN
tA
Write Expansion Out Timing
WEN
WCLK
WXO
tCLKH
tENS
Note tXO
tXO
31
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Note:
32. Read from Last Physical Location.
33. Clocks are free running in this case.
34. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR.
35. For the synchronous PAE and P AF flags (SMOD E), an appropriat e clock cycle is neces sary after tRTR to update these f lags.
Switching Waveforms (continued)
Read Expansion Out Timing
REN
RCLK
RXO
tCLKH
tENS
Note tXO
tXO
32
Write Expansion InTiming
WCLK
WXI
tXI
tXIS
Read Expansion In Timing
RCLK
RXI
tXI
tXIS
Retransmit Timing
REN/WEN
FL/RT
tPRT tRTR
EF/FF
and/all
async flags
HF/PAE/PAF
[33, 34, 35]
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Ordering Information
64 x 18 Low-Voltage Synchronous FIFO
Speed
(ns) Ordering Code Package
Name Package
Type Operating
Range
15 CY7C4425V-15ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial
25 CY7C4425V-25ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial
35 CY7C4425V-35ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial
256 x 18 Low-Voltage Synchronous FIFO
Speed
(ns) Ordering Code Package
Name Package
Type Operating
Range
15 CY7C4205V-15ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial
CY7C4205V-15AC A65 64-Lead 14x14 Thin Quad Flatpack
25 CY7C4205V-25ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial
35 CY7C4205V-35ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial
512 x 18 Low-Voltage Synchronous FIFO
Speed
(ns) Ordering Code Package
Name Package
Type Operating
Range
15 CY7C4215V-15ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial
25 CY7C4215V-25ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial
35 CY7C4215V-35ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial
1K x 18 Low-Voltage Synchronous FIFO
Speed
(ns) Ordering Code Package
Name Package
Type Operating
Range
15 CY7C4225V-15ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial
CY7C4225V-15AC A65 64-Lead 14x14 Thin Quad Flatpack
25 CY7C4225V-25ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial
35 CY7C4225V-35ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial
2K x 18 Low-Voltage Synchronous FIFO
Speed
(ns) Ordering Code Package
Name Package
Type Operating
Range
15 CY7C4235V-15ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial
25 CY7C4235V-25ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial
35 CY7C4235V-35ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial
4K x 18 Low-Voltage Synchronous FIFO
Speed
(ns) Ordering Code Package
Name Package
Type Operating
Range
15 CY7C4245V-15ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial
25 CY7C4245V-25ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial
35 CY7C4245V-35ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial
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Document #: 38-06029 Rev. *B Page 19 of 20
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any ci rcuitry other th an circuitry embod ied in a Cypr ess Semiconductor pr oduct. Nor does it convey or imply any licen se under p atent or other rights. C ypress Semicond uctor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
All product and company names mentioned in this document are the trademarks of their respective holders.
Package Diagrams
64-Pin Thin Plastic Quad Flat Pack (10 x 10 x 1.4 mm) A64
51-85051-*A
64-Lead Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm ) A65
51-85046-*B
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Document #: 38-06029 Rev. *B Page 20 of 20
Document History Page
Document Title: CY7C4425V/4205V/4215V CY7C4225V/4235V/4245V 64/256/512/1K/2K/4K x 18 Low-Voltage Synchro-
nous FIFOs
Document Number: 38-06029
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 109961 12/17/01 SZV Change from Spec number: 38-00609 to 38-06029
*A 122281 12/26/02 RBI Power up requirements added to Maximum Ratings Information
*B 127856 08/22/03 FSG Fixed read cycle timing diagram
Corrected switching waveform diagram typos
Page 12: WEN changed to REN (typo)
Page 13: WCLK changed to RCLK (typo)
