1
Radiation Hardened CMOS Dual SPDT Analog Switch
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH
The HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH analog
switches are monolithic devices fabricated using Intersil’s
dielectrically isolated Radiation Hardened Silicon Gate (RSG)
process technology to insure latch-up free operation. They are
pinout compatible and functionally equivalent to the
HS-303RH, but offer improved 300kRAD(Si) total dose
capability. These switches offers low-resistance switching
performance for analog voltages up to the supply rails. “ON”
resistance is low and stays reasonably constant over the full
range of operating voltage and current. “ON” resistance also
stays reasonably constant when exposed to radiation.
Break-before-make switching is controlled by 5V digital inputs.
The HS-303ARH should be operated with nominal ±15V
supplies, while the HS-303BRH should be operated with
nominal ±12V supplies.
Specifications
Specifications for Rad Hard QML devices are controlled by the
Defense Supply Center in Columbus (DSCC). The SMD numbers
listed below must be used when ordering.
Detailed Electrical Specifications for the HS-303ARH,
HS-303AEH, HS-303BRH, HS-303BEH are contained in
SMD 5962-95813. A “hot-link” is provided from our website for
downloading
Features
• QML, Per MIL-PRF-38535
• Radiation Performance
-Total Dose: 3x10
5 RAD(Si)
- SEE: For LET = 60MeV-mg/cm2 at 60° Incident Angle,
<150pC Charge Transferred to the Output of an Off Switch
• No Latch-Up, Dielectrically Isolated Device Islands
• Pinout and Functionally Compatible with Intersil HS-303RH
and HI-303 Series Analog Switches
• Analog Signal Range Equal to the Supply Voltage Range
• Low Leakage. . . . . . . . . . . . . . . . . . . . . 100nA (Max, Post-Rad)
•Low r
ON . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Ω (Max, Post-Rad)
• Low Standby Supply Current. . . . . . . . . . . . . +150µA/-100µA
(Max, Post-Rad)
Functional Diagram Pin Configurations
HS1-303ARH, HS-303BRH
(SBDIP), CDIP2-T14
TOP VIEW
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH
(FLATPACK) CDFP3-F14
TOP VIEW
TRUTH TABLE
LOGIC SW1 AND SW2 SW3 AND SW4
0OFFON
1ONOFF
N P
IN
D
NC
GND
V+
V-
1
2
3
4
5
6
7
14
13
12
11
10
9
8
IN1
S3
D3
D1
S4
D4
D2
IN2
S2
S1
NC
GND
IN1
S3
D3
D1
S1
V+
V-
S4
D4
D2
IN2
S2
14
13
12
11
10
9
8
2
3
4
5
6
7
1
December 12, 2012
FN6411.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2006, 2008, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH
2FN6411.2
December 12, 2012
Ordering Information
ORDERING NUMBER
(Note) PART NUMBER
TEMP. RANGE
(°C) PKG.
PKG.
DWG. #
5962F9581304QCC HS1-303ARH-8 -55 to +125 14 LD SBDIP D14.3
5962F9581304QXC HS9-303ARH-8 -55 to +125 14 LD Flatpack K14.A
5962F9581304V9A HS0-303ARH-Q -55 to +125 14 Ld SBDIP D14.3
5962F9581306V9A HS0-303AEH-Q -55 to +125 14 Ld SBDIP D14.3
5962F9581304VCC HS1-303ARH-Q -55 to +125 14 LD SBDIP D14.3
5962F9581306VCC HS1-303AEH-Q -55 to +125 14 LD SBDIP D14.3
5962F9581304VXC HS9-303ARH-Q -55 to +125 14 LD Flatpack K14.A
HS0-303ARH/SAMPLE HS0-303ARH/SAMPLE -55 to +125
HS1-303ARH/PROTO HS1-303ARH/PROTO -55 to +125 14 LD SBDIP D14.3
HS9-303ARH/PROTO HS9-303ARH/PROTO -55 to +125 14 LD Flatpack K14.A
5962F9581306VXC HS9-303AEH-Q -55 to +125 14 LD Flatpack K14.A
5962F9581305QCC HS1-303BRH-8 -55 to +125 14 LD SBDIP D14.3
5962F9581305QXC HS9-303BRH-8 -55 to +125 14 LD Flatpack K14.A
5962F9581305V9A HS0-303BRH-Q -55 to +125 14 LD SBDIP D14.3
5962F9581307V9A HS0-303BEH-Q -55 to +125 14 LD SBDIP D14.3
5962F9581305VCC HS1-303BRH-Q -55 to +125 14 LD SBDIP D14.3
5962F9581307VCC HS1-303BEH-Q -55 to +125 14 LD SBDIP D14.3
5962F9581305VXC HS9-303BRH-Q -55 to +125 14 LD Flatpack K14.A
HS0-303BRH/SAMPLE HS0-303BRH/SAMPLE -55 to +125
HS1-303BRH/PROTO HS1-303BRH/PROTO -55 to +125 14 LD SBDIP D14.3
HS9-303BRH/PROTO HS9-303BRH/PROTO -55 to +125 14 LD Flatpack K14.A
5962F9581307VXC HS9-303BEH-Q -55 to +125 14 LD Flatpack K14.A
NOTE: These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with
both SnPb and Pb-free soldering operations.
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH
3
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6411.2
December 12, 2012
For additional products, see www.intersil.com/product_tree
Die Characteristics
DIE DIMENSIONS:
2690µm x 5200µm (106mils x 205mils)
Thickness: 483µm ± 25.4µm (19mils ± 1mil)
INTERFACE MATERIALS:
Glassivation:
Type: PSG (Phosphorous Silicon Glass)
Thickness: 8.0kÅ ± 1.0kÅ
Top Metallization:
Type: AlSiCu
Thickness: 16.0kÅ ± 2kÅ
Substrate:
Radiation Hardened Silicon Gate,
Dielectric Isolation
Backside Finish:
Silicon
ASSEMBLY RELATED INFORMATION:
Substrate Potential:
Unbiased (DI)
ADDITIONAL INFORMATION:
Worst Case Current Density:
<2.0 x 105 A/cm2
Transistor Count:
196
Metallization Mask Layout
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH
D3
D1
S1
IN1
GND
V-
D4
D2
S2
IN2
S3
V+
S4
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH
4FN6411.2
December 12, 2012
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
NOTES:
1. Index area: A notch or a pin one identification mark shall be located ad-
jacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one identi-
fication mark.
2. The maximum limits of lead dimensions b and c or M shall be measured
at the centroid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension M
applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial
lead paddle. For this configuration dimension b3 replaces dimension
b2.
5. Dimension Q shall be measured from the seating plane to the base plane.
6. Measure dimension S1 at all four corners.
7. Measure dimension S2 from the top of the ceramic body to the nearest
metallization or lead.
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. Controlling dimension: INCH.
bbb C A - B
S
c
Q
L
A
SEATING
BASE
D
PLANE
PLANE
SS
-D-
-A-
-C-
eA
-B-
aaa CA - BM DS S
ccc CA - BMDS S
D
E
S1
b2 b
A
e
M
c1
b1
(c)
(b)
SECTION A-A
BASE
LEAD FINISH
METAL
eA/2
S2
M
A
D14.3 MIL-STD-1835 CDIP2-T14 (D-1, CONFIGURATION C)
14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.200 - 5.08 -
b 0.014 0.026 0.36 0.66 2
b1 0.014 0.023 0.36 0.58 3
b2 0.045 0.065 1.14 1.65 -
b3 0.023 0.045 0.58 1.14 4
c 0.008 0.018 0.20 0.46 2
c1 0.008 0.015 0.20 0.38 3
D - 0.785 - 19.94 -
E 0.220 0.310 5.59 7.87 -
e 0.100 BSC 2.54 BSC -
eA 0.300 BSC 7.62 BSC -
eA/2 0.150 BSC 3.81 BSC -
L 0.125 0.200 3.18 5.08 -
Q 0.015 0.060 0.38 1.52 5
S1 0.005 - 0.13 - 6
S2 0.005 - 0.13 - 7
α90o105o90o105o-
aaa - 0.015 - 0.38 -
bbb - 0.030 - 0.76 -
ccc - 0.010 - 0.25 -
M - 0.0015 - 0.038 2
N14 148
Rev. 0 4/94
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH
5FN6411.2
December 12, 2012
Ceramic Metal Seal Flatpack Packages (Flatpack)
NOTES:
1. Index area: A notch or a pin one identification mark shall be located ad-
jacent to pin one and shall be located within the shaded area shown.
The manufacturer’ s identification shall not be used as a pin one identi-
fication mark. Alternately, a tab (dimension k) may be used to identify
pin one.
2. If a pin one identification mark is used in addition to a tab, the limits of
dimension k do not apply.
3. This dimension allows for off-center lid, meniscus, and glass overrun.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension M ap-
plies to lead plating and finish thickness. The maximum limits of lead
dimensions b and c or M shall be measured at the centroid of the fin-
ished lead surfaces, when solder dip or tin plate lead finish is applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric materials
shall be molded to the bottom of the package to cover the leads.
8. Dimension Q shall be measured at the point of exit (beyond the menis-
cus) of the lead from the b ody . Dimension Q minimum shall be reduced
by 0.0015 inch (0.038mm) maximum when solder dip lead finish is
applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
-D-
-C-
0.004 H A - B
MD
S S
-A- -B-
0.036 H A - B
MD
S S
e
E
A
Q
L
D
A
E1
SEATING AND
LE2
E3 E3
BASE PLANE
-H-
b
C
S1
M
c1
b1
(c)
(b)
SECTION A-A
BASE
LEAD FINISH
METAL
PIN NO. 1
ID AREA
A
M
K14.A MIL-STD-1835 CDFP3-F14 (F-2A, CONFIGURATION B)
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.045 0.115 1.14 2.92 -
b 0.015 0.022 0.38 0.56 -
b1 0.015 0.019 0.38 0.48 -
c 0.004 0.009 0.10 0.23 -
c1 0.004 0.006 0.10 0.15 -
D - 0.390 - 9.91 3
E 0.235 0.260 5.97 6.60 -
E1 -0.290-7.11 3
E2 0.125 - 3.18 - -
E3 0.030 - 0.76 - 7
e 0.050 BSC 1.27 BSC -
k 0.008 0.015 0.20 0.38 2
L 0.270 0.370 6.86 9.40 -
Q 0.026 0.045 0.66 1.14 8
S1 0.005 - 0.13 - 6
M - 0.0015 - 0.04 -
N14 14-
Rev. 0 5/18/94
