ATTINY24A-SSU - Atmel - Datasheet.Directory

Features

•High Pe rformance, Low Power AVR® 8-Bit Microcontroller

•Advanced RISC Architecture

– 120 Po we rful Instructions – Most Single Clock Cy cle Execu tion

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

•High Endurance, Non-Volatile Memory Segments

– 2K/4K Bytes of In-System, Self-Pro grammable Flash Program Memory

• Endurance: 10,000 Write/Erase Cycles

– 128/256 Bytes of In-System Programmable EEPROM

• Endurance: 100,000 Write/Erase Cycles

– 128/256 Bytes of Internal SRAM

– Data retention: 20 years at 85°C / 100 years at 25°C

– Programming Lock for Self-Programming Flash & EEPROM Data Security

•Peripheral Features

– One 8-Bit and On e 16 -B it Timer/Counter with Two PWM Channels, Each

– 10-bit ADC

• 8 Single-Ended Channels

• 12 Differential ADC Channel Pairs with Programmable Gain (1x / 20x)

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-Chip Analog Comparator

– Universal Serial Interface

•Special Microcontroller Features

– debugWIRE On-chip Debug System

– In-System Programmable via SPI Port

– Internal and External Interrupt Sources

• Pin Change Interrupt on 12 Pins

– Low Power Idle, ADC Noise Reduction, Standby and Power-Down Modes

– Enhanced P ower-on Reset Circuit

– Programmable Brown-Out Detection Circuit with Software Disable Function

– Internal Calibrated Oscillator

– On-Chip Temperature Sensor

•I/O and Packages

– Available in 20-Pin QFN/ML F & 14-Pin SOIC and PDIP

– Twelve Programmable I/O Lines

•Operating Voltage:

– 1.8 – 5.5V

•Speed Grade:

– 0 – 4 MHz @ 1.8 – 5.5V

– 0 – 10 MHz @ 2.7 – 5.5V

– 0 – 20 MHz @ 4.5 – 5.5V

•Industrial Temperature Range: -40°C to +85°C

•Low Power Consumption

– Active Mode:

• 210 µA at 1.8V and 1MHz

–Idle Mode:

• 33 µA at 1.8V and 1MHz

– Power-Down Mode:

• 0.1 µA at 1.8V and 25°C

8-bit

Microcontroller

with 2K/4K

Bytes In-System

Programmable

Flash

ATtiny24A

(Preliminary)

ATtiny44A

Summary

Rev. 8183AS–AVR–12/08

28183AS–AVR–12/08

ATtiny24A/44A

1. Pin Configurations

Figure 1-1. Pinout of ATtiny24A/44A

1.1 Pin Descriptions

1.1.1 VCC Supply voltage.

1.1.2 GND Ground.

1.1.3 Port B (PB3...PB0)

Port B is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability except PB3 which has the RESET capability. To use pin PB3 as an I/O pin, instead of

RESET pin, program (‘0’) RST DISBL fuse. As inputs, Port B pins that are extern ally pulled low

will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a

reset condition be co me s active, even if the clock is not ru nn in g.

VCC

(PCINT8/XTAL1/CLKI) PB0

(PCINT9/XTAL2) PB1

(PCINT11/RESET/dW) PB3

(PCINT10/INT0/OC0A/CKOUT) PB2

(PCINT7/ICP/OC0B/ADC7) PA7

(PCINT6/OC1A/SDA/MOSI/DI/ADC6) PA6

GND

PA0 (ADC0/AREF/PCINT0)

PA1 (ADC1/AIN0/PCINT1)

PA2 (ADC2/AIN1/PCINT2)

PA3 (ADC3/T0/PCINT3)

PA4 (ADC4/USCK/SCL/T1/PCINT4)

PA5 (ADC5/DO/MISO/OC1B/PCINT5)

PDIP/SOIC

QFN/MLF

NOTE

Bottom pad should be

soldered to ground.

DNC: Do Not Connect

DNC

GND

VCC

DNC

PA7 (PCINT7/ICP/OC0B/ADC7)

PB2 (PCINT10/INT0/OC0A/CKOUT)

PB3 (PCINT11/RESET/dW)

PB1 (PCINT9/XTAL2)

PB0 (PCINT8/XTAL1/CLKI)

PA5

DNC

PA6

Pin 16: PA6 (PCINT6/OC1A/SDA/MOSI/DI/ADC6)

Pin 20: PA5 (ADC5/DO/MISO/OC1B/PCINT5)

(ADC4/USCK/SCL/T1/PCINT4) PA4

(ADC3/T0/PCINT3) PA3

(ADC2/AIN1/PCINT2) PA2

(ADC1/AIN0/PCINT1) PA1

(ADC0/AREF/PCINT0) PA0

8183AS–AVR–12/08

ATtiny24A/44A

Port B also serves the functions of various special features of the ATtiny24A/44A as listed in

Section 10.2 “Alternat e Port Functions” on page 57.

1.1.4 RESET Reset input. A low level on this pin for longer than the minimum pulse length will genera te a

reset, even if the clock is not r unning and pr ovided the reset pin has not be en disabled . The min-

imum pulse length is given in Table 20-4 on page 176. Shorter pulses are not guaranteed to

generate a reset.

The reset pin can also be used as a (weak) I/O pin.

1.1.5 Port A (PA7...PA0)

Port A is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port A output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up

resistors are activated. Th e Port A pins are tri-stated when a reset co ndition becomes active,

even if the clock is not running.

Port A has alternate functions as analog inputs for the ADC, analog comparator, timer/counter,

SPI and pin change interrupt as described in “Alternate Port Functions” on page 57.

48183AS–AVR–12/08

ATtiny24A/44A

2. Overview ATtiny24A/44A are low-power CMOS 8-bit microcontrollers based on the AVR enhanced RISC

architecture. By executing powerful instructions in a single clock cycle, the ATtiny24A/44A

achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize

power consumption versus proc essing speed.

Figure 2-1. Block Diagram

The AVR core combines a rich instruction set with 32 general purpose working registers. All 32

registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achiev ing throughputs up to ten times faster than con-

ventional CISC microcontrollers.

WATCHDOG

TIMER

MCU CONTROL

TIMER/

COUNTER0

DATA DIR.

REG.PORT A

DATA REGISTER

PORT A

PROGRAMMING

LOGIC

TIMING AND

CONTROL

MCU STATUS

PORT A DRIVERS

PA7-PA0

VCC

GND

ANALOG

COMPARATOR

8-BIT DATABUS

ADC

ISP INTERFACE

INTERRUPT

UNIT

EEPROM

INTERNAL

OSCILLATOR

OSCILLATORS

CALIBRATED

OSCILLATOR

INTERNAL

DATA DIR.

REG.PORT B

DATA REGISTER

PORT B

PORT B DRIVERS

PB3-PB0

PROGRAM

COUNTER

STACK

POINTER

PROGRAM

FLASH SRAM

GENERAL

PURPOSE

REGISTERS

INSTRUCTION

DECODER

STATUS

ALU

CONTROL

LINES

TIMER/

COUNTER1

8183AS–AVR–12/08

ATtiny24A/44A

The ATtiny24A/44A provid es the following features: 2K/4K byte of In-System Programmable

Flash, 128/256 bytes EEPROM, 128/256 bytes SRAM, 12 general purpose I/O lines, 32 general

purpose working registers, an 8-bit Timer/Counter with two PWM channels, a 16-bit timer/coun-

ter with two PWM channels, Internal and External Interrupts, a 8-channel 10-bit ADC,

programmable gain stage (1x, 20x) for 12 differential ADC channel pairs, a programmable

Watchdog Timer with internal oscillator, internal calibrated oscillator, and four software select-

able power saving modes. Idle mode stops the CPU while allowing the SRAM, Timer/Counter,

ADC, Analog Comparator, and Interrupt system to continue functioning. ADC Noise Reduction

mode minimizes switching noise during ADC conversions by stopping the CPU and all I/O mod-

ules except the ADC. In Power-down mode registers keep their contents and all chip functions

are disbaled until the next interrupt or hardware reset. In Standby mode, the crystal/resonator

oscillator is running while the rest of the device is sleeping, allowing very fast start-up combined

with low power consumption.

The device is manufactu red using Atmel’s hig h densit y non-vo latile mem ory te chnology. The o n-

chip ISP Flash allows the Program memory to be re-programmed in-system through an SPI

serial interface, by a conventional non-volatile memory program mer or by an on-chip b oot code

running on the AVR core.

The ATtiny24A/44A AVR is su pport ed with a f ull suite of pro gr am and syst em de ve lopmen t to ols

including: C Compilers, Macro Assemblers, Program Debugger/Simulators and Evaluation kits.

68183AS–AVR–12/08

ATtiny24A/44A

3. About

3.1 Resources A comprehensive set of driver s, applica tion note s, data sheets and de scription s on developme nt

tools are available for download at http://www.atmel.com/avr.

3.2 Code Examples

This documentatio n contains simple co de examples that br iefly sh ow how to u se various parts of

the device. These code examp les assume that the part specific header file is included b efore

compilation. Be aware that not all C compiler vendors include bit definitions in the header files

and interrupt ha ndlin g in C is com piler d epe nd ent. Please con firm wit h the C com piler d ocume n-

tation for more details.

For I/O Registers located in the extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”

instructions must be replaced with instructions that allow access to extended I/O. Typically, this

means “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. Note that not all

AVR devices include an exte nded I/O map.

3.3 Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less

than 1 PPM over 20 years at 85°C or 100 years at 25°C.

3.4 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of

other AVR micr ocontr ollers m anufa ct ured o n th e same proce ss tech nolo gy. Min a nd Ma x valu es

will be available after the device has been characterized.

8183AS–AVR–12/08

ATtiny24A/44A

4. Register Summary

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

0x3F (0x5F) SREG I T H S V N Z C Page 8

0x3E (0x5E) SPH – – – – – – SP9 SP8 Page 10

0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 Page 10

0x3C (0x5C) OCR0B Timer/Counter0 – Output Compare Register B Page 83

0x3B (0x5B) GIMSK – INT0 PCIE1 PCIE0 – – – – Page 49

0x3A (0x5A GIFR – INTF0 PCIF1 PCIF0 – – – – Page 50

0x39 (0x59) TIMSK0 – – – – – OCIE0B OCIE0A TOIE0 Page 83

0x38 (0x58) TIFR0 –––– OCF0B OCF0A TOV0 Page 83

0x37 (0x57) SPMCSR –– RSIG CTPB RFLB PGWRT PGERS SPMEN Page 156

0x36 (0x56) OCR0A Timer/Counter0 – Output Compare Registe r A Page 82

0x35 (0x55) MCUCR BODS PUD SE SM1 SM0 BODSE ISC01 ISC00 Pages 35, 49, and 65

0x34 (0x54) MCUSR – – – – WDRF BORF EXTRF PORF Page 43

0x33 (0x53) TCCR0B FOC0A FOC0B –– WGM02 CS02 CS01 CS00 Page 81

0x32 (0x52) TCNT0 Timer/Counter0 Pa ge 82

0x31 (0x51) OSCCALCAL7CAL6CAL5CAL4CAL3CAL2CAL1CAL0 Page 29

0x30 (0x50) TCCR0A COM 0A1 COM0A0 COM0B1 COM0B0 –WGM01 WGM00 Page 78

0x2F (0x4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 –WGM11 WGM10 Page 106

0x2E (0x4E) TCCR1B ICNC1 ICES1 –WGM13 WGM12 CS12 CS11 CS10 Page 108

0x2D (0x4D) TCNT1H Timer/Counter1 – Counter Register High Byte Page 110

0x2C (0x4C) TCNT1L Timer/Counter1 – Counter Register Low Byte Page 110

0x2B (0x4B) OCR1AH Timer/Counter1 – Compare Register A High Byte Page 110

0x2A (0x4A) OCR1AL Timer/Counter1 – Compare Register A Low Byte Page 110

0x29 (0x49) OCR1BH Timer/Counter1 – Compare Register B High By te Page 110

0x28 (0x48) OCR1BL Timer/Counter1 – Compare Register B Low Byte Page 110

0x27 (0x47) DWDR DWDR[7:0] Page 151

0x26 (0x46) CLKPR CLKPCE – – – CLKP S3 CLKPS2 CLKPS1 CLKPS0 Page 30

0x25 (0x45) ICR1H Timer/Counter1 - Input Capture Register High Byte Page 111

0x24 (0x44) ICR1L Timer/Counter1 - Input Capture Register Low Byte Page 111

0x23 (0x43) GTCCR TSM –––––– PSR10 P age 114

0x22 (0x42 ) TCCR1C FOC1A FOC1B – – – – – – Page 109

0x21 (0x41) WDTCSR WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 Page 43

0x20 (0x40) PCMSK1 – – – – PCINT11 PCINT10 PCINT9 PCINT8 Page 50

0x1F (0x3F) Reserved – – – – – – – –

0x1E (0x3E) EEARL EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 Page 20

0x1D (0x3D) EEDR EEPROM Data Register Page 21

0x1C (0x3C) EECR –– EEPM1 EEPM0 EERIE EEMPE EEPE EERE Page 21

0x1B (0x3B) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 Page 65

0x1A (0x3A) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 Page 65

0x19 (0x39) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 Page 66

0x18 (0x38) PORTB – – – – PORTB3 PORTB2 PORTB1 PORTB0 Page 66

0x17 (0x37) DDRB – – – – DDB3 DDB2 DDB1 DDB0 Page 66

0x16 (0x36) PINB – – – – PINB3 PINB2 PINB1 PINB0 Page 66

0x15 (0x35) GPIOR2 General Purpose I/O Register 2 Page 22

0x14 (0x34) GPIOR1 General Purpose I/O Register 1 Page 22

0x13 (0x33) GPIOR0 General Purpose I/O Register 0 Page 22

0x12 (0x32) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 Page 51

0x11 (0x31)) Reserved –

0x10 (0x30) USIBR USI Buffer Register Page 127

0x0F (0x2F) USIDR USI Data Register Page 123

0x0E (0x2E) USISR USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 Page 128

0x0D (0x2D) USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC Page 128

0x0C (0x2C) TIMSK1 ––ICIE1–– OCIE1B OCIE1A TOIE1 Page 111

0x0B (0x2B) TIFR1 ––ICF1–– OCF1B OCF1A TOV1 Page 112

0x0A (0x2A) Reserved –

0x09 (0x29) Reserved –

0x08 (0x28) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 Page 129

0x07 (0x27) ADMUX REFS1 REFS0 MUX5 MUX4 MUX3 MUX2 MUX1 MUX0 Page 144

0x06 (0x26) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 Page 146

0x05 (0x25) ADCH ADC Data Register High Byte Page 148

0x04 (0x24) ADCL ADC Data Register Low Byte Page 148

0x03 (0x23) ADCSRB BIN ACME –ADLAR– ADTS2 ADTS1 ADTS0 Page 130, Page 148

0x02 (0x22) Reserved –

0x01 (0x21) DIDR0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D Page 131, Page 149

0x00 (0x20) PRR – – – – PRTIM1 PRTIM0 PRUSI PRADC Page 36

88183AS–AVR–12/08

ATtiny24A/44A

Note: 1. For compatibili ty with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresse s

should never be written.

2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these

registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI

instructions will only operation the specified bit, and can ther efore be used on registers containing such Status Flags. The

CBI and SBI instructions work with registers 0x00 to 0x1F only.

8183AS–AVR–12/08

ATtiny24A/44A

5. Instruction Set Summary

Mnemonics Operands Description Operation Flags #Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1

ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1

ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2

SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1

SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1

SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1

SBCI Rd, K Sub tr act with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1

SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2

AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1

ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1

OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1

ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1

EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1

COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1

NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1

SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1

CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1

INC Rd Increment Rd ← Rd + 1 Z,N,V 1

DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1

TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1

CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1

SER Rd Set Register Rd ← 0xFF None 1

BRANCH INSTRUCTIONS

RJMP k Relative Jump PC ← PC + k + 1 None 2

IJMP Indirect Jump to (Z) PC ← Z None 2

RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3

ICALL Indirect Call to (Z) PC ← ZNone3

RET Subroutine Return PC ← STACK None 4

RETI Interrupt Return PC ← STACK I 4

CPSE Rd,R r Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3

CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1

CPC Rd,Rr Compa re with Carry Rd − Rr − C Z, N,V,C,H 1

CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H 1

SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3

SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3

SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2 /3

SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3

BRBS s, k Branch if Status Flag Set if (SREG(s ) = 1) then PC←PC+k + 1 None 1/2

BRBC s, k Branc h if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2

BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2

BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/ 2

BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2

BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2

BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2

BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1 /2

BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2

BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2

BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2

BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2

BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2

BRHC k Branch if Half Carry Flag Clear ed if (H = 0) then PC ← PC + k + 1 None 1/2

BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2

BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2

BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2

BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2

BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2

BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2

BIT AND BIT-TEST INSTRUCTIONS

SBI P,b Set Bit in I/O Register I/O(P,b) ← 1None2

CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0None2

LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1

LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1

ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1

10 8183AS–AVR–12/08

ATtiny24A/44A

ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1

ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1

SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1

BSET s Flag Set SREG(s) ← 1 SREG(s) 1

BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1

BST Rr, b Bit Store from Register to T T ← Rr(b) T 1

BLD Rd, b Bit load from T to Register Rd(b) ← TNone1

SEC Set Carry C ← 1C1

CLC Clear Carry C ← 0 C 1

SEN Set Negative Flag N ← 1N1

CLN Clear Negative Flag N ← 0 N 1

SEZ Set Zero Flag Z ← 1Z1

CLZ Clear Zero Flag Z ← 0 Z 1

SEI Global Interrupt Enable I ← 1I1

CLI Glo ba l Interru pt Disable I ← 0 I 1

SES Set Signed Test Flag S ← 1S1

CLS Clear Signed Test Flag S ← 0 S 1

SEV Set Twos Complement Overflow. V ← 1V1

CLV Clear Twos Complement Overflow V ← 0 V 1

SET Set T in SREG T ← 1T1

CLT Clear T in SREG T ← 0 T 1

SEH Set Half Carry Flag in SREG H ← 1H1

CLH Clear Half Carry Flag in SREG H ← 0 H 1

DATA TRANSFER INSTRUCTIONS

MOV Rd, Rr Move Between Registers Rd ← Rr None 1

MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:Rr None 1

LDI Rd, K Load Immediate Rd ← KNone1

LD Rd, X Load Indirect Rd ← (X) None 2

LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2

LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2

LD Rd, Y Load Indirect Rd ← (Y) None 2

LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2

LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2

LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2

LD Rd, Z Load Indirect Rd ← (Z) None 2

LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2

LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2

LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2

LDS Rd, k Load Direct from SRAM Rd ← (k) Non e 2

ST X, Rr Store Indirect (X) ← Rr None 2

ST X+, Rr Store Indirect and Post -In c. (X) ← Rr, X ← X + 1 None 2

ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2

ST Y, Rr Store Indirect (Y) ← Rr None 2

ST Y+, Rr Store Indirect and Post -In c. (Y) ← Rr, Y ← Y + 1 None 2

ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2

STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2

ST Z, Rr St ore Indirect (Z) ← Rr None 2

ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2

ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2

STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2

STS k, Rr Store Direct to SRAM (k) ← Rr None 2

LPM Load Program Memory R0 ← (Z) None 3

LPM Rd, Z Load Program Memory Rd ← (Z) None 3

LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3

SPM Store Program Memory (z) ← R1:R0 None

IN Rd, P In Port Rd ← PNone1

OUT P, Rr Out Port P ← Rr None 1

PUSH Rr Push Register on Stack STACK ← Rr None 2

POP Rd Pop Register from St ack Rd ← STACK None 2

MCU CONTROL INSTRUCTIONS

NOP No Operation None 1

SLEEP Sleep (see specific descr. for Sleep function) None 1

WDR Watchdog Reset (see specific descr. for WDR/Timer) None 1

BREAK Break For On-chip Debug Only None N/A

Mnemonics Operands Description Operation Flags #Clocks

8183AS–AVR–12/08

ATtiny24A/44A

6. Ordering Information

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

Halide free and fully Green.

6.1 ATtiny24A

Speed (MHz) Power Supply Ordering Code(1) Package(2) Operational Range

20 1.8 - 5.5V

ATtiny24A-SSU

ATtiny24A-PU

ATtiny24A-MU

ATtiny24A-MMH

14S1

14P3

20M1

20M2

Industrial

(-40°C to 85°C)

Package Type

14S1 14-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline Package (SOIC)

14P3 14-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

20M1 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No Lead / Micro Lead Frame Package (QFN/MLF)

20M2 20-pad, 3 x 3 x 0.85 mm Body, Very Thin Quad Flat No Lead Package (VQFN)

12 8183AS–AVR–12/08

ATtiny24A/44A

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

Halide free and fully Green.

6.2 ATtiny44A

Speed (MHz) Power Supply Ordering Code(1) Package(2) Operational Range

20 1.8 - 5.5V

ATtiny44A-SSU

ATtiny44A-PU

ATtiny44A-MU

ATtiny44A-MMH

14S1

14P3

20M1

20M2

Industrial

(-40°C to 85°C)

Package Type

14S1 14-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline Package (SOIC)

14P3 14-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

20M1 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

20M2 20-pad, 3 x 3 x 0.85 mm Body, Very Thin Quad Flat No Lead Package (VQFN)

8183AS–AVR–12/08

ATtiny24A/44A

7. Packaging Information

7.1 20M1

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm, A

20M1

10/27/04

2.6 mm Exposed Pad, Micro Lead Frame Package (MLF)

A 0.70 0.75 0.80

A1 – 0.01 0.05

A2 0.20 REF

b 0.18 0.23 0.30

D 4.00 BSC

D2 2.45 2.60 2.75

E 4.00 BSC

E2 2.45 2.60 2.75

e 0.50 BSC

L 0.35 0.40 0.55

SIDE VIEW

Pin 1 ID

Pin #1

Notch

(0.20 R)

BOTTOM VIEW

TOP VIEW

Note: Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5.

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

0.08 C

14 8183AS–AVR–12/08

ATtiny24A/44A

7.2 20M2

TITLE DRAWING NO. GPC REV.

Package Drawing Contact:

packagedrawings@atmel.com 20M2 ZFC B

20M2, 20-pad, 3 x 3 x 0.85 mm Body, Lead Pitch 0.45 mm,

1.55 x 1.55 mm Exposed Pad, Thermally Enhanced

Plastic Very Thin Quad Flat No Lead Package (VQFN)

10/24/08

16 17 18 19 20

10 9 8 7 6

E2 e

Pin #1 Chamfer

(C 0.3)

E SIDE VIEW

Pin 1 ID

BOTTOM VIEW

TOP VIEW A1

C0.18 (8X)

0.3 Ref (4x)

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A 0.75 0.80 0.85

A1 0.00 0.02 0.05

b 0.17 0.22 0.27

C 0.152

D 2.90 3.00 3.10

D2 1.40 1.55 1.70

E 2.90 3.00 3.10

E2 1.40 1.55 1.70

e – 0.45 –

L 0.35 0.40 0.45

K 0.20 – –

y 0.00 – 0.08

8183AS–AVR–12/08

ATtiny24A/44A

7.3 14P3

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

14P3, 14-lead (0.300"/7.62 mm Wide) Plastic Dual

Inline Package (PDIP) A

14P3

11/02/05

SEATING PLANE

eB eC

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A – – 5.334

A1 0.381 – –

D 18.669 – 19.685 Note 2

E 7.620 – 8.255

E1 6.096 – 7.112 Note 2

B 0.356 – 0.559

B1 1.143 – 1.778

L 2.921 – 3.810

C 0.203 – 0.356

eB – – 10.922

eC 0.000 – 1.524

e 2.540 TYP

Notes: 1. This package conforms to JEDEC reference MS-001, Variation AA.

2. Dimensions D and E1 do not include mold Flash or Protrusion.

Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

16 8183AS–AVR–12/08

ATtiny24A/44A

7.4 14S1

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

14S1, 14-lead, 0.150" Wide Body, Plastic Gull

Wing Small Outline Package (SOIC)

2/5/02

14S1 A

Side View

Top View End View

COMMON DIMENSIONS

(Unit of Measure = mm/inches)

SYMBOL MIN NOM MAX NOTE

Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-012, Variation AB for additional information.

2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusion and gate burrs shall not

exceed 0.15 mm (0.006") per side.

3. Dimension E does not include inter-lead Flash or protrusion. Inter-lead flash and protrusions shall not exceed 0.25 mm

(0.010") per side.

4. L is the length of the terminal for soldering to a substrate.

5. The lead width B, as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value

of 0.61 mm (0.024") per side.

A 1.35/0.0532 – 1.75/0.0688

A1 0.1/.0040 – 0.25/0.0098

b 0.33/0.0130 – 0.5/0.0200 5

D8.55/0.3367 – 8.74/0.3444 2

E3.8/0.1497 – 3.99/0.1574 3

H5.8/0.2284 – 6.19/0.2440

L 0.41/0.0160 – 1.27/0.0500 4

e 1.27/0.050 BSC

8183AS–AVR–12/08

ATtiny24A/44A

8. Errata The revision letters in this section refer to the revision of the corresponding ATtiny24A/44A

device.

8.1 ATtiny24A

8.1.1 Rev. G Not sampled.

8.1.2 Rev. F Not sampled.

18 8183AS–AVR–12/08

ATtiny24A/44A

8.2 ATtiny44A

8.2.1 Rev. F No known errata.

8.2.2 Rev. E Not sampled.

8183AS–AVR–12/08

ATtiny24A/44A

9. Datasheet Revision History

9.1 Rev A. 12/08 1. Initial revision. Created from document 8006H.

2. Updated "Ordering Information" on page 17 and page 18. Pb-plated packages are no

longer offered and there are no separa te ordering codes for commercial operation

range, the only available option now is industrial. Also, updated some order codes to

reflect changes in leadframe composition an d added VQFN package option.

3. Updated data sheet template.

4. Removed all references to 8K device.

5. Updated characteristic plots of section “Typical Characteristics”, starting on page 182.

6. Added characteristic plots:

–“Internal Bandgap Voltage vs. Supply Voltage” on page 202

–“Internal Bandgap Voltage vs. Temperature” on page 202

7. Updated sections:

–“Features” on page 1

–“Power Reduction Register” on page 34

–“Analog Comparator” on page 128

–“Features” on page 132

–“Operation” on page 133

–“Starting a Conversion” on page 134

–“ADC Voltage Reference” on page 139

–“Speed Grades” on page 174

8. Updated Figures:

–“Program Memory Map” on page 15

–“Data Memory Map” on page 16

9. Update Tables:

–“Device Signature Bytes” on page 161

–“DC Characteristics. TA = -40°C to +85°C” on page 173

–“Additional Current Consumption for the different I/O modules (absolute values)” on

page 182

–“Additional Curren t Consumption (pe rcentage) in Act ive and Idle mode ” on page 183

8183AS–AVR–12/08

Headquarters International

Atmel Corporation

2325 Orchard Parkway

San Jose, CA 95131

USA

Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

Atmel Asia

Unit 1-5 & 16, 19/F

BEA Tower, Millennium City 5

418 Kwun Tong Road

Kwun Tong, Kowloon

Hong Kong

Tel: (852) 2245-6100

Fax: (852) 2722-1369

Atmel Europe

Le Krebs

8, Rue Jean-Pierre Timbaud

BP 309

78054 Saint-Quentin-en-

Yvelines Cedex

France

Tel: (33) 1-30-60-70-00

Fax: (33) 1-30-60-71-11

Atmel Japan

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

Tel: (81) 3-3523-3551

Fax: (81) 3-3523-7581

Product Contact

Web Site

www.atmel.com Technical Support

avr@atmel.com Sales Contact

www.atmel.com/contacts

Literature Requests

www.atmel.com/literature

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any

intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-

TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY

WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR

PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-

TAL DAMAGES ( INCLUDING, WITHOUT LIMITATION, D AMAGES FOR LO SS OF P R OFIT S, BU SINESS I NTERR UPTI ON, OR L OSS OF INFORMATION) ARISING OUT OF

THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no

representations or warranties with respect to the accuracy or complete ness of the contents of this document and reserves the right to make changes to specifications

and product description s at any time without no tice. Atmel does not make any commitment to update the i nformation conta ined herein. Unless specifi cally provided

otherwise, Atmel products are n ot suitable for, and shall not be used in, automotive applications. Atmel’s products are not intend ed, authorized, or warranted for use

as components in appl ications intended to support or sustain l ife.

marks of Atmel Cor poration or its subsidiaries. Other ter ms and product n ames may be trademarks of others.