© Semiconductor Components Industries, LLC, 2012
April, 2012 − Rev. 11
1Publication Order Number:
CAT93C66/D
CAT93C66, CAT93W66
4 kb Microwire Serial CMOS
EEPROM
Description
The CAT93C66 is a 4 kb CMOS Serial EEPROM device which is
organized as either 256 registers of 16 bits (ORG pin at VCC) or 512
registers of 8 bits (ORG pin at GND). The CAT93W66 features x16
memory organization only. Each register can be written (or read)
serially by using the DI (or DO) pin. The device features sequential
read and self−timed internal write with auto−clear. On−chip
Power−On Reset circuitry protects the internal logic against powering
up in the wrong state.
Features
•High Speed Operation: 4 MHz (5 V), 2 MHz (1.8 V)
•1.8 V to 5.5 V Supply Voltage Range
•Selectable x8 or x16 Memory Organization: CAT93C66
•Self−timed Write Cycle with Auto−clear
•Sequential Read
•Software Write Protection
•Power−up Inadvertent Write Protection
•Low Power CMOS Technology
•1,000,000 Program/Erase Cycles
•100 Year Data Retention
•Industrial and Extended Temperature Ranges
•8−lead PDIP, SOIC, TSSOP, 6−lead SOT−23, 8−pad TDFN and
UDFN Packages
•These Devices are Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
ORG
DO
CAT93C66
SK
GND
VCC
Figure 1. Functional Symbols
DI
CS DO
CAT93W66
SK
GND
VCC
DI
CS
CAT93C66 Selectable Organization:
When the ORG pin is connected to VCC, the x16 organization is
selected. When it is connected to ground, the x8 organization is
selected. If the ORG pin is left unconnected, then an internal pull−up
device will select the x16 organization.
CAT93W66:
The device works in x16 mode only.
http://onsemi.com
PIN CONFIGURATION
DO
DI
SK
CS
See detailed ordering and shipping information in the package
dimensions section on page 16 of this data sheet.
ORDERING INFORMATION
SOIC−8
V, W* SUFFIX
CASE 751BD
PDIP (L), SOIC (V, X),
TSSOP (Y), TDFN (VP2)*,
UDFN (HU4)
PDIP−8
L SUFFIX
CASE 646AA
TSSOP−8
Y SUFFIX
CASE 948AL
SOIC−8
X SUFFIX
CASE 751BE
* Not recommended for new designs
** CAT93C66 available in SOT−23 6−pin for x8
Organization. Contact factory for availability.
GND
ORG
NC
VCC
SK
CS
VCC
NC 1
DI
DO
GND
ORG
SOIC (W)*
SOT23−6
TB SUFFIX
CASE 527AJ
DI
GND
DO 1
SK
CS
VCC
SOT−23 (TB)**
2
3
6
5
4
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
TDFN (VP2)
CAT93W66
DO
DI
SK
CS
GND
NC
NC
VCC
1
2
3
4
8
7
6
5
UDFN−8
HU4 SUFFIX
CASE 517AZ
TDFN−8*
VP2 SUFFIX
CASE 511AK
CAT93C66, CAT93W66
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2
Table 1. PIN FUNCTION
Pin Name Function Pin Name Function
CS Chip Select VCC Power Supply
SK Clock Input GND Ground
DI Serial Data Input ORG (Note 1) Memory Organization
DO Serial Data Output NC No Connection
1. ORG Pin available for the CAT93C66 only.
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters Ratings Units
Storage Temperature −65 to +150 °C
Voltage on Any Pin with Respect to Ground (Note 2) −0.5 to +6.5 V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
Table 3. RELIABILITY CHARACTERISTICS (Note 3)
Symbol Parameter Min Units
NEND (Note 4) Endurance 1,000,000 Program / Erase Cycles
TDR Data Retention 100 Years
3. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
4. Block Mode, VCC = 5 V, 25°C.
Table 4. D.C. OPERATING CHARACTERISTICS − MATURE PRODUCT
(VCC = +1.8 V to +5.5 V, TA = −40°C to +125°C unless otherwise specified.)
Symbol Parameter Test Conditions Min Max Units
ICC1 Power Supply Current
(Write)
fSK = 1 MHz, VCC = 5.0 V 1 mA
ICC2 Power Supply Current
(Read)
fSK = 1 MHz, VCC = 5.0 V 500 mA
ISB1 Power Supply Current
(Standby) (x8 Mode)
VIN = GND or VCC,
CS = GND ORG = GND
TA = −40°C to +85°C 2 mA
TA = −40°C to +125°C 4
ISB2 Power Supply Current
(Standby) (x16 Mode)
VIN = GND or VCC, CS = GND
ORG = Float or VCC
TA = −40°C to +85°C 1 mA
TA = −40°C to +125°C 2
ILI Input Leakage Current VIN = GND to VCC TA = −40°C to +85°C 1 mA
TA = −40°C to +125°C 2
ILO Output Leakage Current VOUT = GND to VCC,
CS = GND
TA = −40°C to +85°C 1 mA
TA = −40°C to +125°C 2
VIL1 Input Low Voltage 4.5 V ≤ VCC < 5.5 V −0.1 0.8 V
VIH1 Input High Voltage 4.5 V ≤ VCC < 5.5 V 2 VCC + 1 V
VIL2 Input Low Voltage 1.8 V ≤ VCC < 4.5 V 0 VCC x 0.2 V
VIH2 Input High Voltage 1.8 V ≤ VCC < 4.5 V VCC x 0.7 VCC + 1 V
VOL1 Output Low Voltage 4.5 V ≤ VCC < 5.5 V, IOL = 2.1 mA 0.4 V
VOH1 Output High Voltage 4.5 V ≤ VCC < 5.5 V, IOH = −400 mA2.4 V
VOL2 Output Low Voltage 1.8 V ≤ VCC < 4.5 V, IOL = 1 mA 0.2 V
VOH2 Output High Voltage 1.8 V ≤ VCC < 4.5 V, IOH = −100 mAVCC − 0.2 V
CAT93C66, CAT93W66
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Table 5. D.C. OPERATING CHARACTERISTICS − NEW PRODUCT (REV H)
(VCC = +1.8 V to +5.5 V, TA=−40°C to +125°C unless otherwise specified.)
Symbol Parameter Test Conditions Min Max Units
ICC1 Supply Current (Write) Write, VCC = 5.0 V 1 mA
ICC2 Supply Current (Read) Read, DO open, fSK = 2 MHz, VCC = 5.0 V 500 mA
ISB1 Standby Current
(x8 Mode)
VIN = GND or VCC
CS = GND, ORG = GND
TA = −40°C to +85°C 2 mA
TA = −40°C to +125°C 5
ISB2 Standby Current
(x16 Mode)
VIN = GND or VCC
CS = GND,
ORG = Float or VCC
TA = −40°C to +85°C 1 mA
TA = −40°C to +125°C 3
ILI Input Leakage Current VIN = GND to VCC TA = −40°C to +85°C 1 mA
TA = −40°C to +125°C 2
ILO Output Leakage
Current
VOUT = GND to VCC
CS = GND
TA = −40°C to +85°C 1 mA
TA = −40°C to +125°C 2
VIL1 Input Low Voltage 4.5 V ≤ VCC < 5.5 V −0.1 0.8 V
VIH1 Input High Voltage 4.5 V ≤ VCC < 5.5 V 2 VCC + 1 V
VIL2 Input Low Voltage 1.8 V ≤ VCC < 4.5 V 0 VCC x 0.2 V
VIH2 Input High Voltage 1.8 V ≤ VCC < 4.5 V VCC x 0.7 VCC + 1 V
VOL1 Output Low Voltage 4.5 V ≤ VCC < 5.5 V, IOL = 3 mA 0.4 V
VOH1 Output High Voltage 4.5 V ≤ VCC < 5.5 V, IOH = −400 mA2.4 V
VOL2 Output Low Voltage 1.8 V ≤ VCC < 4.5 V, IOL = 1 mA 0.2 V
VOH2 Output High Voltage 1.8 V ≤ VCC < 4.5 V, IOH = −100 mAVCC − 0.2 V
Table 6. PIN CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = +5.0 V)
Symbol Test Conditions Min Typ Max Units
COUT (Note 5) Output Capacitance (DO) VOUT = 0 V 5 pF
CIN (Note 5) Input Capacitance (CS, SK, DI, ORG) VIN = 0 V 5 pF
5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
Table 7. POWER−UP TIMING (Notes 6, 7)
Symbol Parameter Max Units
tPUR Power−up to Read Operation 1 ms
tPUW Power−up to Write Operation 1 ms
6. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC−Q100 and JEDEC test methods.
7. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Table 8. A.C. TEST CONDITIONS
Input Rise and Fall Times ≤ 50 ns
Input Pulse Voltages 0.4 V to 2.4 V 4.5 V ≤ VCC ≤ 5.5 V
Timing Reference Voltages 0.8 V, 2.0 V 4.5 V ≤ VCC ≤ 5.5 V
Input Pulse Voltages 0.2 VCC to 0.7 VCC 1.8 V ≤ VCC ≤ 4.5 V
Timing Reference Voltages 0.5 VCC 1.8 V ≤ VCC ≤ 4.5 V
Output Load Current Source IOLmax/IOHmax; CL = 100 pF
CAT93C66, CAT93W66
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Table 9. A.C. CHARACTERISTICS − MATURE PRODUCT
(VCC = +1.8 V to +5.5 V, TA = −40°C to +125°C, unless otherwise specified.) (Note 8)
Symbol Parameter
Limits
Units
Min Max
tCSS CS Setup Time 50 ns
tCSH CS Hold Time 0 ns
tDIS DI Setup Time 100 ns
tDIH DI Hold Time 100 ns
tPD1 Output Delay to 1 0.25 ms
tPD0 Output Delay to 0 0.25 ms
tHZ (Note 9) Output Delay to High−Z 100 ns
tEW Program/Erase Pulse Width 5 ms
tCSMIN Minimum CS Low Time 0.25 ms
tSKHI Minimum SK High Time 0.25 ms
tSKLOW Minimum SK Low Time 0.25 ms
tSV Output Delay to Status Valid 0.25 ms
SKMAX Maximum Clock Frequency DC 2000 kHz
8. Test conditions according to “A.C. Test Conditions” table.
9. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC−Q100 and JEDEC test methods.
Table 10. A.C. CHARACTERISTICS − NEW PRODUCT (Rev H)
(VCC = +1.8 V to +5.5 V, TA = −40°C to +125°C, unless otherwise specified.)
Symbol Parameter
VCC = 1.8 V − 5.5 V VCC = 4.5 V − 5.5 V
Units
Min Max Min Max
tCSS CS Setup Time 50 50 ns
tCSH CS Hold Time 0 0 ns
tDIS DI Setup Time 100 50 ns
tDIH DI Hold Time 100 50 ns
tPD1 Output Delay to 1 0.25 0.1 ms
tPD0 Output Delay to 0 0.25 0.1 ms
tHZ (Note 10) Output Delay to High−Z 100 100 ns
tEW Program/Erase Pulse Width 5 5 ms
tCSMIN Minimum CS Low Time 0.25 0.1 ms
tSKHI Minimum SK High Time 0.25 0.1 ms
tSKLOW Minimum SK Low Time 0.25 0.1 ms
tSV Output Delay to Status Valid 0.25 0.1 ms
SKMAX Maximum Clock Frequency DC 2000 DC 4000 kHz
10.This parameter is tested initially and after a design or process change that affects the parameter.
CAT93C66, CAT93W66
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5
Device Operation
The CAT93C66 is a 4096−bit nonvolatile memory
intended for use with industry standard microprocessors.
The CAT93C66 can be organized as either registers of 16
bits or 8 bits. When organized as X16, seven 11−bit
instructions control the reading, writing and erase
operations of the device. When organized as X8, seven
12−bit instructions control the reading, writing and erase
operations of the device. The CAT93W66 works in x16
mode only. The device operates on a single power supply
and will generate on chip, the high voltage required during
any write operation.
Instructions, addresses, and write data are clocked into the
DI pin on the rising edge of the clock (SK). The DO pin is
normally in a high impedance state except when reading data
from the device, or when checking the ready/busy status
after a write operation. The serial communication protocol
follows the timing shown in Figure 2.
The ready/busy status can be determined after the start of
internal write cycle by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that the
device is ready for the next instruction. If necessary, the DO
pin may be placed back into a high impedance state during
chip select by shifting a dummy “1” into the DI pin. The DO
pin will enter the high impedance state on the rising edge of
the clock (SK). Placing the DO pin into the high impedance
state is recommended in applications where the DI pin and
the DO pin are to be tied together to form a common DI/O
pin.
The format for all instructions sent to the device is a
logical “1” start bit, a 2−bit (or 4−bit) opcode, 8−bit address
(an additional bit when organized X8) and for write
operations a 16−bit data field (8−bit for X8 organizations).
The instruction format is shown in Instruction Set table.
Table 11. INSTRUCTION SET
Instruction Start Bit Opcode
Address Data
Comments
x8 (Note 11) x16 x8 (Note 11) x16
READ 1 10 A8−A0 A7−A0 Read Address AN – A0
ERASE 1 11 A8−A0 A7−A0 Clear Address AN – A0
WRITE 1 01 A8−A0 A7−A0 D7−D0 D15−D0 Write Address AN – A0
EWEN 1 00 11XXXXXXX 11XXXXXX Write Enable
EWDS 1 00 00XXXXXXX 00XXXXXX Write Disable
ERAL 1 00 10XXXXXXX 10XXXXXX Clear All Addresses
WRAL 1 00 01XXXXXXX 01XXXXXX D7−D0 D15−D0 Write All Addresses
11. The x8 memory organization is available for the CAT93C66 only.
CAT93C66, CAT93W66
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Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C66,
CAT93W66 will come out of the high impedance state and,
after sending an initial dummy zero bit, will begin shifting
out the data addressed (MSB first). The output data bits will
toggle on the rising edge of the SK clock and are stable after
the specified time delay (tPD0 or tPD1).
For the CAT93C66, CAT93W66 after the initial data word
has been shifted out and CS remains asserted with the SK
clock continuing to toggle, the device will automatically
increment to the next address and shift out the next data word
in a sequential READ mode. As long as CS is continuously
asserted and SK continues to toggle, the device will keep
incrementing to the next address automatically until it
reaches to the end of the address space, then loops back to
address 0. In the sequential READ mode, only the initial data
word is preceeded by a dummy zero bit. All subsequent data
words will follow without a dummy zero bit. The READ
instruction timing is illustrated in Figure 3.
Erase/Write Enable and Disable
The device powers up in the write disable state. Any
writing after power−up or after an EWDS (erase/write
disable) instruction must first be preceded by the EWEN
(erase/write enable) instruction. Once the write instruction
is enabled, it will remain enabled until power to the device
is removed, or the EWDS instruction is sent. The EWDS
instruction can be used to disable all CAT93C66,
CAT93W66 write and erase instructions, and will prevent
any accidental writing or clearing of the device. Data can be
read normally from the device regardless of the write
enable/disable status. The EWEN and EWDS instructions
timing is shown in Figure 4.
Figure 2. Synchronous Data Timing
SK
DI
CS
DO
VALID VALID
DATA VALID
tCSS
tDIS
tSKHI tSKLOW
tDIS
tDIH
tCSH
tCSMIN
tPD0, tPD1
Figure 3. READ Instruction Timing
SK
CS
DI
DO HIGH−Z
11 0
Dummy 0
Don’t Care
ANAN−1
tPD0
A0
Address + n
D15 . . .
or
D7 . . .
Address + 2
D15 . . . D0
or
D7 . . . D0
Address + 1
D15 . . . D0
or
D7 . . . D0
D15 . . . D0
or
D7 . . . D0
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Write
After receiving a WRITE command (Figure 5), address
and the data, the CS (Chip Select) pin must be deselected for
a minimum of tCSMIN. The falling edge of CS will start the
self clocking clear and data store cycle of the memory
location specified in the instruction. The clocking of the SK
pin is not necessary after the device has entered the self
clocking mode. The ready/busy status of the CAT93C66,
CAT93W66 can be determined by selecting the device and
polling the DO pin. Since this device features Auto−Clear
before write, it is NOT necessary to erase a memory location
before it is written into.
Erase
Upon receiving an ERASE command and address, the CS
(Chip Select) pin must be deasserted for a minimum of
tCSMIN (Figure 6). The falling edge of CS will start the self
clocking clear cycle of the selected memory location. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAT93C66, CAT93W66 can be determined by selecting the
device and polling the DO pin. Once cleared, the content of
a cleared location returns to a logical “1” state.
Figure 4. EWEN/EWDS Instruction Timing
CS
DI
STANDBY
10
0*
SK
* ENABLE = 11
DISABLE = 00
Figure 5. Write Instruction Timing
SK
CS
DI
DO
STANDBY
HIGH−Z
HIGH−Z
101
BUSY
READY
STATUS
tHZ
tEW
tSV
VERIFY
AN−1
ANA0D0
DN
tCSMIN
Figure 6. Erase Instruction Timing
SK
CS
DI
DO
STANDBY
HIGH−Z
HIGH−Z
1
BUSY READY
STATUS
11
VERIFY
tHZ
ANAN−1A0tCS
tSV
tEW
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Erase All
Upon receiving an ERAL command (Figure 7), the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
clear cycle of all memory locations in the device. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
device can be determined by selecting the device and polling
the DO pin. Once cleared, the contents of all memory bits
return to a logical “1” state.
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN (Figure 8). The falling edge of CS will start the self
clocking data write to all memory locations in the device.
The clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy status of
the device can be determined by selecting the device and
polling the DO pin. It is not necessary for all memory
locations to be cleared before the WRAL command is
executed.
Figure 7. ERAL Instruction Timing
SK
CS
DI
DO
STANDBY
HIGH−Z
HIGH−Z
10 1
BUSY READY
STATUS VERIFY
00
tHZ
tCS
tSV
tEW
Figure 8. WRAL Instruction Timing
STATUS VERIFY
SK
CS
DI
DO
STANDBY
HIGH−Z
10 1
BUSY READY
00 DND0
tSV tHZ
tCSMIN
tEW
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PACKAGE DIMENSIONS
PDIP−8, 300 mils
CASE 646AA−01
ISSUE A
E1
D
A
L
eb
b2
A1
A2
E
eB
c
TOP VIEW
SIDE VIEW END VIEW
PIN # 1
IDENTIFICATION
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
SYMBOL MIN NOM MAX
A
A1
A2
b
b2
c
D
e
E1
L
0.38
2.92
0.36
6.10
1.14
0.20
9.02
2.54 BSC
3.30
5.33
4.95
0.56
7.11
1.78
0.36
10.16
eB 7.87 10.92
E 7.62 8.25
2.92 3.80
3.30
0.46
6.35
1.52
0.25
9.27
7.87
CAT93C66, CAT93W66
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PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
E1 E
A
A1
h
θ
L
c
eb
D
PIN # 1
IDENTIFICATION
TOP VIEW
SIDE VIEW END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
SYMBOL MIN NOM MAX
θ
A
A1
b
c
D
E
E1
e
h
0º 8º
0.10
0.33
0.19
0.25
4.80
5.80
3.80
1.27 BSC
1.75
0.25
0.51
0.25
0.50
5.00
6.20
4.00
L0.40 1.27
1.35
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PACKAGE DIMENSIONS
SOIC−8, 208 mils
CASE 751BE−01
ISSUE O
E1
eb
SIDE VIEW
TOP VIEW
E
D
PIN#1 IDENTIFICATION
END VIEW
A1
A
Lc
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with EIAJ EDR-7320.
q
SYMBOL MIN NOM MAX
θ
A
A1
b
c
D
E
E1
e
0º 8º
0.05
0.36
0.19
5.13
7.75
5.13
1.27 BSC
2.03
0.25
0.48
0.25
5.33
8.26
5.38
L0.51 0.76
CAT93C66, CAT93W66
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PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
E1 E
A2
A1
e
b
D
c
A
TOP VIEW
SIDE VIEW END VIEW
q1
L1 L
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
SYMBOL
θ
MIN NOM MAX
A
A1
A2
b
c
D
E
E1
e
L1
0º 8º
L
0.05
0.80
0.19
0.09
0.50
2.90
6.30
4.30
0.65 BSC
1.00 REF
1.20
0.15
1.05
0.30
0.20
0.75
3.10
6.50
4.50
0.90
0.60
3.00
6.40
4.40
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PACKAGE DIMENSIONS
TDFN8, 2x3
CASE 511AK−01
ISSUE A
PIN#1
IDENTIFICATION
E2
E
A3
ebD
A2
TOP VIEW SIDE VIEW BOTTOM VIEW
PIN#1 INDEX AREA
FRONT VIEW
A1
A
L
D2
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-229.
SYMBOL MIN NOM MAX
A 0.70 0.75 0.80
A1 0.00 0.02 0.05
A3 0.20 REF
b 0.20 0.25 0.30
D 1.90 2.00 2.10
D2 1.30 1.40 1.50
E 3.00
E2 1.20 1.30 1.40
e
2.90
0.50 TYP
3.10
L 0.20 0.30 0.40
A2 0.45 0.55 0.65
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PACKAGE DIMENSIONS
SOT−23, 6 Lead
CASE 527AJ−01
ISSUE O
TOP VIEW
SIDE VIEW END VIEW
E1 E
PIN #1 IDENTIFICATION
A2
A1
e
b
D
c
A
L1 L
L2
Notes:
(1) All dimensions in millimeters. Angles in degrees.
(2) Complies with JEDEC standard MO-178.
θ2
θ1
θ
SYMBOL MIN NOM MAX
θ2 5°15°
A
A1
A2
b
c
D
E
E1
L
L2
0.00
0.90
0.30
0.08
2.90 BSC
1.60 BSC
0.45
1.45
0.15
1.30
0.50
0.22
0.25 REF
1.15
2.80 BSC
L1 0.60 REF
e
0.30 0.60
0.95 BSC
0.90
10°
θ1 5°15°10°
θ0°8°4°
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PACKAGE DIMENSIONS
UDFN8, 2x3 EXTENDED PAD
CASE 517AZ−01
ISSUE O
0.065 REF
Copper Exposed
E2
D2
L
E
PIN #1 INDEX AREA
PIN #1
IDENTIFICATION
DAP SIZE 1.8 x 1.8
DETAIL A
D
A1
be
A
TOP VIEW SIDE VIEW
FRONT VIEW
DETAIL A
BOTTOM VIEW
A3
0.065 REF
0.0 - 0.05A3
Notes:
(1) All dimensions are in millimeters.
(2) Refer JEDEC MO-236/MO-252.
SYMBOL MIN NOM MAX
A 0.45 0.50 0.55
A1 0.00 0.02 0.05
A3 0.127 REF
b 0.20 0.25 0.30
D 1.95 2.00 2.05
D2 1.35 1.40 1.45
E 3.00
E2 1.25 1.30 1.35
e
2.95
0.50 REF
3.05
L 0.25 0.30 0.35
A
CAT93C66, CAT93W66
http://onsemi.com
16
Table 12. ORDERING INFORMATION
Device Order Number
Specific
Device
Marking* Package Type Temperature Range
Lead
Finish Shipping
CAT93C66LI−G 93C66H PDIP−8I = Industrial
(−40°C to +85°C)
NiPdAu Tube, 50 Units / Tube
CAT93C66VE−G 93C66H SOIC−8, JEDEC E = Extended
(−40°C to +125°C)
NiPdAu Tube, 100 Units / Tube
CAT93C66VE−GT3 93C66H SOIC−8, JEDEC E = Extended
(−40°C to +125°C)
NiPdAu Tape & Reel,
3,000 Units / Reel
CAT93C66VI−G 93C66H SOIC−8, JEDEC I = Industrial
(−40°C to +85°C)
NiPdAu Tube, 100 Units / Tube
CAT93C66VI−GT3 93C66H SOIC−8, JEDEC I = Industrial
(−40°C to +85°C)
NiPdAu Tape & Reel,
3,000 Units / Reel
CAT93C66VP2E−GT3 M2T TDFN−8E = Extended
(−40°C to +125°C)
NiPdAu Tape & Reel,
3,000 Units / Reel
CAT93C66VP2I−GT3 M2T TDFN−8I = Industrial
(−40°C to +85°C)
NiPdAu Tape & Reel,
3,000 Units / Reel
CAT93C66YI−G M66 TSSOP−8I = Industrial
(−40°C to +85°C)
NiPdAu Tube, 100 Units / Tube
CAT93C66YI−GT3 M66 TSSOP−8I = Industrial
(−40°C to +85°C)
NiPdAu Tape & Reel,
3,000 Units / Reel
CAT93C66YE−GT3 M66 TSSOP−8E = Extended
(−40°C to +125°C)
NiPdAu Tape & Reel,
3,000 Units / Reel
CAT93W66VP2I−GT3 M2C TDFN−8I = Industrial
(−40°C to +85°C)
NiPdAu Tape & Reel,
3,000 Units / Reel
CAT93C66XI−T2 93C66H SOIC−8, EIAJ E = Extended
(−40°C to +125°C)
Matte−Tin Tape & Reel,
2,000 Units / Reel
CAT93C66HU4I−GT3 M2U UDFN−8I = Industrial
(−40°C to +85°C)
NiPdAu Tape & Reel,
3,000 Units / Reel
CAT93C66HU4E−GT3 M2U UDFN−8E = Extended
(−40°C to +125°C)
NiPdAu Tape & Reel,
3,000 Units / Reel
* Marking for New Product (Rev H)
12.All packages are RoHS−compliant (Lead−free, Halogen−free).
13.The standard lead finish is NiPdAu.
14.For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
15.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
16.For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device
Nomenclature document, TND310/D, available at www.onsemi.com
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
CAT93C66/D
PUBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
