ICS8634-01 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER GENERAL DESCRIPTION FEATURES The ICS8634-01 is a high performance 1-to-5 Differential-to3.3V LVPECL Zero Delay Buffer. The ICS8634-01 has two selectable clock inputs. The CLKx, nCLKx pair can accept most standard differential input levels. Utilizing one of the outputs as feedback to the PLL, output frequencies up to 700MHz can be regenerated with zero delay with respect to the input. Dual reference clock inputs support redundant clock or multiple reference applications. * Five differential 3.3V LVPECL outputs * Selectable differential clock inputs * CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL * Output frequency range: 31.25MHz to 700MHz * Input frequency range: 31.25MHz to 700MHz * VCO range: 250MHz to 700MHz * External feedback for "zero delay" clock regeneration * Cycle-to-cycle jitter: 25ps (maximum) * Output skew: 25ps (maximum) * PLL reference zero delay: 50ps 100ps * 3.3V operating supply * 0C to 70C ambient operating temperature * Lead-Free package available * Industrial temperature information available upon request BLOCK DIAGRAM PIN ASSIGNMENT VCCO nQ4 1 Q3 nQ3 1 Q4 Q2 nQ2 PLL CLK_SEL 32 31 30 29 28 27 26 25 0 0 VEE CLK1 nCLK1 Q1 nQ1 VEE CLK0 nCLK0 /4, /8 VCCA VCC PLL_SEL PLL_SEL Q0 nQ0 Q4 nQ4 FB_IN nFB_IN SEL0 1 24 VCCO SEL1 2 23 Q3 CLK0 3 22 nQ3 nCLK0 4 21 Q2 CLK1 5 20 nQ2 nCLK1 6 19 Q1 CLK_SEL 7 18 nQ1 MR 8 17 VCCO ICS8634-01 9 10 11 12 13 14 15 16 VCCO Q0 nQ0 VEE VEE FB_IN SEL1 nFB_IN VCC SEL0 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View MR 32-Lead VFQFN 5mm x 5mm x 0.95 package body K Package Top View 8634BY-01 www.idt.com 1 REV. D OCTOBER 4, 2010 ICS8634-01 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1 SEL0 Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. 2 SEL1 Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. 3 CLK0 Input Pulldown Non-inver ting differential clock input. 4 nCLK0 Input Pullup Inver ting differential clock input. Pulldown Non-inver ting differential clock input. 5 CLK1 Input 6 nCLK1 Input 7 CLK_SEL Input 8 MR Input 9, 32 VCC Power 10 nFB_IN Input 11 12, 13 28, 29 14, 15 16. 17, 24, 25 18, 19 FB_IN Input VEE Power Negative supply pins. nQ0, Q0 Output Differential output pair. LVPECL interface levels. VCCO Power Output supply pins. nQ1, Q1 Output Differential output pair. LVPECL interface levels. 20, 21 nQ2, Q2 Output Differential output pair. LVPECL interface levels. 22, 23 nQ3, Q3 Output Differential output pair. LVPECL interface levels.. 26, 27 nQ4, Q4 Output Differential output pair. LVPECL interface levels. 30 VCCA Power 31 PLL_SEL Input Analog supply pin. Selects between the PLL and the reference clock as the input to the dividers. When HIGH, selects PLL. When LOW, selects reference clock. LVCMOS / LVTTL interface levels. Pullup Inver ting differential clock input. Clock select input. When LOW, selects CLK0, nCLK0. Pulldown When HIGH, selects CLK1, nCLK1. LVCMOS / LVTTL interface levels. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx to go Pulldown high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Core supply pins. Pullup Feedback input to phase detector for regenerating clocks with "zero delay". Pulldown Feedback input to phase detector for regenerating clocks with "zero delay". Pullup NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k TABLE 3A. CONTROL INPUT FUNCTION TABLE Reference Frequency Range (MHz)* 250 - 700 /1 0 0 /4 1 /4 Inputs SEL1 SEL0 0 0 TABLE 3B. PLL BYPASS FUNCTION TABLE Outputs PLL_SEL = 1 PLL Enable Mode Q0:Q4, nQ0:nQ4 Inputs SEL1 SEL0 Outputs PLL_SEL = 0 PLL Bypass Mode Q0:Q4, nQ0:nQ4 0 1 125 - 350 /1 0 1 0 62.5 - 175 /1 1 0 /4 /1 1 1 /8 1 1 31.25 - 87.5 *NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz. 8634BY-01 www.idt.com 2 REV. D OCTOBER 4, 2010 ICS8634-01 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V NOTE: Stresses beyond those listed under Absolute Inputs, VI -0.5V to VCC + 0.5V Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, JA 32 Lead LQFP 32 Lead VFQFN 47.9C/W (0 lfpm) 34.8C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Character- istics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V 3.135 3.3 VCCO Output Supply Voltage 3.465 V IEE Power Supply Current 150 mA ICCA Analog Supply Current 15 mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH IIL Input High Current Input Low Current Test Conditions Minimum Maximum Units 2 Typical VCC + 0.3 V -0.3 0.8 V SEL0, SEL1, CLK_SEL, MR VCC = VIN = 3.465V 150 A PLL_SEL VCC = VIN = 3.465V 5 A SEL0, SEL1, CLK_SEL, MR VCC = 3.465V, VIN = 0V -5 A PLL_SEL VCC = 3.465V, VIN = 0V -150 A TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C Symbol Parameter IIH Input High Current Test Conditions Minimum VCC = VIN = 3.465V CLK0, CLK1, FB_IN nCLK0, nCLK1, nFB_IN VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V -5 nCLK0, nCLK1, nFB_IN VCC = 3.465V, VIN = 0V -150 Input Low Current VPP Peak-to-Peak Input Voltage Maximum Units 150 A 5 CLK0, CLK1, FB_IN IIL Typical 0.15 A 1.3 VCMR Common Mode Input Voltage; NOTE 1, 2 VEE + 0.5 VCC - 0.85 NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is VCC + 0.3V. NOTE 2: Common mode voltage is defined as VIH. 8634BY-01 www.idt.com 3 A A V V REV. D OCTOBER 4, 2010 ICS8634-01 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions Minimum VCCO - 1.4 Typical VCCO - 0.7 V VOL Output Low Voltage; NOTE 1 VCCO - 2.0 VCCO - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50 to VCCO - 2V. TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C Symbol fIN Parameter Input Frequency CLK0, nCLK0, CLK1, nCLK1 Test Conditions Minimum PLL_SEL = 1 31.25 Typical PLL_SEL = 0 Maximum Units 700 MHz 700 MHz Maximum Units 700 MHz 4.2 ns 150 ps 25 ps 25 50 ps ps TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C Symbol Parameter fMAX Output Frequency tPD t(O) Propagation Delay; NOTE 1 PLL Reference Zero Delay; NOTE 2, 4 Output Skew; NOTE 3, 4 t sk(o) t jit(cc) t jit() Cycle-to-Cycle Jitter; NOTE 4, 6 Phase Jitter; NOTE 4, 5, 6 tL PLL Lock Time Test Conditions Minimum PLL_SEL = 0V, f 700MHz 3.2 PLL_SEL = 3.3V -50 Typical 50 1 ms 700 ps odc Output Duty Cycle 47 53 All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Phase jitter is dependent on the input source used. NOTE 6: Characterized at VCO frequency of 622MHz. % tR / tF 8634BY-01 Output Rise/Fall Time 20% to 80% @ 50MHz www.idt.com 4 300 REV. D OCTOBER 4, 2010 ICS8634-01 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER PARAMETER MEASUREMENT INFORMATION 2V VCC , VCCA, VCCO Qx V CC SCOPE nCLK0, nCLK1 LVPECL V VEE V Cross Points PP nQx CMR CLK0, CLK1 -1.3V 0.165V VEE DIFFERENTIAL INPUT LEVEL 3.3V OUTPUT LOAD AC TEST CIRCUIT nQ0:nQ4 nQx Qx Q0:Q4 tcycle n tcycle n+1 nQy Qy t jit(cc) = tcycle n -tcycle n+1 tsk(o) 1000 Cycles OUTPUT SKEW CYCLE-TO-CYCLE JITTER nQ0:nQ4 80% 80% Q0:Q4 VSW I N G Clock Outputs Pulse Width 20% 20% tR t tF odc = PERIOD t PW t PERIOD OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD nCLK0, nCLK1 VOH CLK0, CLK1 nCLK0, nCLK1 VOL VOH nFB_IN CLK0, CLK1 nQ0:nQ4 FB_IN VOL t(O) t jit(O) = t (O) -- t (O) mean = Phase Jitter Q0:Q4 tPD t (O) mean = Static Phase Offset (where t (O) is any random sample, and t (O) mean is the average of the sampled cycles measured on controlled edges) PROPAGATION DELAY 8634BY-01 PHASE JITTER & STATIC PHASE OFFSET www.idt.com 5 REV. D OCTOBER 4, 2010 ICS8634-01 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC R1 1K Single Ended Clock Input CLKx V_REF nCLKx C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT TERMINATION FOR LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 3.3V Zo = 50 125 FOUT FIN Zo = 50 Zo = 50 FOUT 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o FIN 50 Zo = 50 VCC - 2V RTT 84 FIGURE 2A. LVPECL OUTPUT TERMINATION 8634BY-01 125 84 FIGURE 2B. LVPECL OUTPUT TERMINATION www.idt.com 6 REV. D OCTOBER 4, 2010 ICS8634-01 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8634-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 3 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin. 3.3V VCC .01F 10 VCCA 10 F .01F FIGURE 3. POWER SUPPLY FILTERING DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4D show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 4A. CLK/nCLK INPUT DRIVEN BY LVHSTL DRIVER FIGURE 4B. CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input Receiv er R2 84 FIGURE 4C. CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER 8634BY-01 nCLK Zo = 50 Ohm FIGURE 4D. CLK/nCLK INPUT DRIVEN BY 3.3V LVDS DRIVER www.idt.com 7 REV. D OCTOBER 4, 2010 ICS8634-01 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER LAYOUT GUIDELINE The schematic of the ICS8634-01 layout example is shown in Figure 5A. The ICS8634-01 recommended PCB board layout for this example is shown in Figure 5B. This layout example is used as a general guideline. The layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P.C. board. VCC SP = Space (i.e. not intstalled) R7 VCC VCCA RU2 SP RU3 1K RU4 1K RU5 SP 10 C11 0.01u VCC=3.3V VCCO=3.3V CLK_SEL PLL_SEL SEL0 SEL1 RD3 SP RD4 SP Zo = 50 Ohm 155.5 MHz DIV_SEL[1:0] = 01 + PLL_SEL RD2 1K C16 10u RD5 1K VCCO - Zo = 50 Ohm LVPECL_input VCC Zo = 50 Ohm CLK_SEL 3.3V PECL Driver R8 50 R9 50 1 2 3 4 5 6 7 8 SEL0 SEL1 CLK0 nCLK0 CLK1 nCLK2 CLK_SEL MR VCC nFB_IN FB_IN VEE VEE nQ0 Q0 VCCO SEL0 SEL1 8634-01 VCCO Q3 nQ3 Q2 nQ2 Q1 nQ1 VCCO 9 10 11 12 13 14 15 16 (155.5 MHz) Zo = 50 Ohm R5 50 32 31 30 29 28 27 26 25 3.3V VCC PLL_SEL VCCA VEE VEE Q4 nQ4 VCCO U1 24 23 22 21 20 19 18 17 R4 50 R6 50 Output Termination Example Bypass capacitor located near the power pins (U1-9) VCC C1 0.1uF (U1-32) C6 0.1uF R10 50 (U1-16) R2 50 VCCO (U1-17) (U1-24) (U1-25) R1 50 C2 0.1uF C4 0.1uF C5 0.1uF C7 0.1uF R3 50 FIGURE 5A. ICS8634-01 LVPECL ZERO DELAY BUFFER SCHEMATIC EXAMPLE 8634BY-01 www.idt.com 8 REV. D OCTOBER 4, 2010 ICS8634-01 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER The following component footprints are used in this layout example: trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. All the resistors and capacitors are size 0603. POWER AND GROUNDING * The differential 50 output traces should have same length. Place the decoupling capacitors C1, C2, C4, C5, C6, and C7, as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. * Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. * Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. * To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. The RC filter consisting of R7, C11, and C16 should be placed as close to the VCCA pin as possible. CLOCK TRACES AND TERMINATION Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the * Make sure no other signal traces are routed between the clock trace pair. * The matching termination resistors should be located as close to the receiver input pins as possible. GND R7 C16 C11 VCCO C7 C6 C5 U1 VCC VCCA Pin 1 VIA 50 Ohm Traces C4 C1 C2 FIGURE 5B. PCB BOARD LAYOUT FOR ICS8634-01 8634BY-01 www.idt.com 9 REV. D OCTOBER 4, 2010 ICS8634-01 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8634-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8634-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * * Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 150mA = 520mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 5 * 30mW = 150mW Total Power_MAX (3.465V, with all outputs switching) = 520mW + 150mW = 670mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for the devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 7A below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.670W * 42.1C/W = 98.2C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 7A. THERMAL RESISTANCE JA FOR 32-PIN LQFP, FORCED CONVECTION JA by Velocity (Linear Feet per Minute) 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 67.8C/W 55.9C/W 50.1C/W Multi-Layer PCB, JEDEC Standard Test Boards 47.9C/W 42.1C/W 39.4C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 7B. JAVS. AIR FLOW TABLE FOR 32 LEAD VFQFN PACKAGE JA 0 Air Flow (Linear Feet per Minute) 0 Multi-Layer PCB, JEDEC Standard Test Boards 8634BY-01 34.8C/W www.idt.com 10 REV. D OCTOBER 4, 2010 ICS8634-01 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. VCCO Q1 VOUT RL 50 VCCO - 2V FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V. CCO * For logic high, VOUT = V OH_MAX (V CCO_MAX * -V OH_MAX OL_MAX CCO_MAX -V CCO_MAX - 0.9V ) = 0.9V For logic low, VOUT = V (V =V =V CCO_MAX - 1.7V ) = 1.7V OL_MAX Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX - (V CCO_MAX - 2V))/R ] * (V CCO_MAX L -V OH_MAX ) = [(2V - (V CCO_MAX -V OH_MAX ))/R ] * (V CCO_MAX L -V )= OH_MAX [(2V - 0.9V)/50] * 0.9V = 19.8mW Pd_L = [(V OL_MAX - (V CCO_MAX - 2V))/R ] * (V L CCO_MAX -V OL_MAX ) = [(2V - (V CCO_MAX -V OL_MAX ))/R ] * (V L CCO_MAX -V )= OL_MAX [(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 8634BY-01 www.idt.com 11 REV. D OCTOBER 4, 2010 ICS8634-01 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER RELIABILITY INFORMATION TABLE 8A. JAVS. AIR FLOW TABLE FOR 32 LQFP JA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W 200 500 55.9C/W 42.1C/W 50.1C/W 39.4C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 8B. JAVS. AIR FLOW TABLE FOR 32 LEAD VFQFN PACKAGE JA 0 Air Flow (Linear Feet per Minute) 0 Multi-Layer PCB, JEDEC Standard Test Boards 34.8C/W TRANSISTOR COUNT The transistor count for ICS8634-01 is: 2969 8634BY-01 www.idt.com 12 REV. D OCTOBER 4, 2010 ICS8634-01 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP TABLE 9. PACKAGE DIMENISIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N 1.60 A A1 0.05 0.15 A2 1.35 1.40 b 0.30 0.37 c 0.09 D 9.00 BASIC 7.00 BASIC D2 5.60 E 9.00 BASIC E1 7.00 BASIC E2 5.60 e 0.80 BASIC 0.45 0 0.45 0.20 D1 L 1.45 0.60 0.75 7 0.10 ccc Reference Document: JEDEC Publication 95, MS-026 8634BY-01 www.idt.com 13 REV. D OCTOBER 4, 2010 ICS8634-01 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER PACKAGE OUTLINE - K SUFFIX FOR 32 LEAD VFQFN TABLE 9B. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL MINIMUM MAXIMUM 32 N A 0.80 1.0 A1 0 0.05 0.25 Reference A3 b 0.18 0.30 e 0.50 BASIC ND 8 NE 8 5.0 D D2 1.25 3.25 5.0 E E2 1.25 3.25 L 0.30 0.50 Reference Document: JEDEC Publication 95, MO-220 8634BY-01 www.idt.com 14 REV. D OCTOBER 4, 2010 ICS8634-01 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 8634BY-01 ICS8634BY-01 32 Lead LQFP Tray 0C to 70C 8634BY-01T ICS8634BY-01 32 Lead LQFP 1000 Tape & Reel 0C to 70C 8634BY-01LF ICS8634BY01L 32 Lead "Lead-Free" LQFP Tray 0C to 70C 8634BY-01LFT ICS8634BY01L 32 Lead "Lead-Free" LQFP 1000 Tape & Reel 0C to 70C 8634BK-01 ICS8634BK01 32 Lead VFQFN Tray 0C to 70C 8634BK-01T ICS8634BK01 32 Lead VFQFN 2500 Tape & Reel 0C to 70C 8634BK-01LF ICS8634B01L 32 Lead "Lead-Free" VFQFN Tray 0C to 70C 8634BK-01LFT ICS8634B01L 32 Lead "Lead-Free" VFQFN 2500 Tape & Reel 0C to 70C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. 8634BY-01 www.idt.com 15 REV. D OCTOBER 4, 2010 ICS8634-01 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER REVISION HISTORY SHEET Rev Table Page T 3A T6 1 3 5 A A A 9 2 6 A T1 8 14 B C C T1 T4A T4D 2 3 4 6 T2 T6 2 3 4 T10 6 7 14 T4D 4 C 10 - 11 D D T10 15 T10 15 17 8634BY-01 Description of Change Date Updated Block Diagram. Added note at bottom of the table. Added Note 6. Added Termination for LVPECL Outputs and Power Supply Filtering Techniques sections. Pin Description table - revised MR description. 3.3V Output Load Test Circuit Diagram - revised VEE equation from 0.135 to 0.165. Updated Output Rise/Fall Time Diagram. Power Considerations/Calculations & Equations - updated power dissipation equations. Revised MR and VCC pin descriptions. VCC Parameter replaced Positive Supply Voltage with Core Supply Voltage. Changed VSWING (max) limit from 900mV to 1.0V. Updated Fig. 1, Single Ended Signal Driving Differential Input and LVPECL Output Termination Diagrams. Updated format. Pin Characteristics Table - changed CIN 4pF max. to 4pF typical. Absolute Maximum Ratings - updated Outputs. AC Characteristics Table - modified tPD limit from 3.6ns min. to 3.2ns min. and deleted 3.9ns typical. Updated LVPECL Output Termination drawings. Added Differential Clock Input Interface section. Ordering Information Table - added Lead-Free par t number. Add 32 Lead VFQFN package throughout data sheet. LVPECL DC Characteristics Table -corrected VOH max. from VCCO - 1.0V to VCCO - 0.9V. 16 11/20/01 6/3/02 8/22/02 3/5/03 8/26/04 10/15/04 11/12/04 Power Considerations - corrected power dissipation to reflect VOH max in Table 4D. Ordering Information Table - added lead-free par t/order number for ICS8634BK-01 and added lead-free note. Updated datasheet's header/footer with IDT from ICS. Ordering Information Tablle - removed ICS prefix from Par t/Order Number column. Added VFQFN LF marking Added Contact Page. www.idt.com 11/2/01 4/12/07 10/4/10 REV. D OCTOBER 4, 2010 ICS8634-01 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER We've Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 Sales Tech Support 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 netcom@idt.com (c) 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 8634BY-01 www.idt.com 17 REV. D OCTOBER 4, 2010