8634BY-01 www.idt.com REV. D OCTOBER 4, 2010
1
ICS8634-01
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY BUFFER
GENERAL DESCRIPTION
The ICS8634-01 is a high performance 1-to-5 Differential-to-
3.3V LVPECL Zero Delay Buffer. The ICS8634-01 has two
selectable clock inputs. The CLKx, nCLKx pair can accept most
standard differential input levels. Utilizing one of the outputs
as feedback to the PLL, output frequencies up to 700MHz can
be regenerated with zero delay with respect to the input. Dual
reference clock inputs support redundant clock or multiple
reference applications.
FEATURES
•Five differential 3.3V LVPECL outputs
•Selectable differential clock inputs
•CLKx, nCLKx pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
•Output frequency range: 31.25MHz to 700MHz
•Input frequency range: 31.25MHz to 700MHz
•VCO range: 250MHz to 700MHz
•External feedback for “zero delay” clock regeneration
•Cycle-to-cycle jitter: 25ps (maximum)
•Output skew: 25ps (maximum)
•PLL reference zero delay: 50ps ± 100ps
•3.3V operating supply
•0°C to 70°C ambient operating temperature
•Lead-Free package available
•Industrial temperature information available upon request
BLOCK DIAGRAM PIN ASSIGNMENT
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VCCO
Q3
nQ3
Q2
nQ2
Q1
nQ1
VCCO
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
VCCO
Q0
nQ0
VEE
VEE
FB_IN
nFB_IN
VCC
VCCO
nQ4
Q4
VEE
VEE
VCCA
PLL_SEL
VCC
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
32-Lead VFQFN
5mm x 5mm x 0.95 package body
K Package
Top View
ICS8634-01
PLL_SEL
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
FB_IN
nFB_IN
SEL0
SEL1
MR
0
1
PLL
0
1
÷4, ÷8
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
8634BY-01 www.idt.com REV. D OCTOBER 4, 2010
2
ICS8634-01
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY BUFFER
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
rebmuNemaNepyTnoitpircseD
10LEStupnInwodlluP .slevelecafretniLTTVL/SOMCVL.3elbaTniseulavredividtuptuosenimret
eD
21LEStupnInwodlluP .slevelecafretniLTTVL/SOMCVL.3elbaTniseulavredividtuptuosenimreteD
30KLCtupnInwodlluP.tup
nikcolclaitnereffidgnitrevni-noN
40KLCntupnIpulluP.tupnikcolclaitnereffidgnitrevnI
51KLCtupnInwodlluP.tupnikcol
claitnereffidgnitrevni-noN
61KLCntupnIpulluP.tupnikcolclaitnereffidgnitrevnI
7LES_KLCtupnInwodlluP .0KLCn,0KLCs
tceles,WOLnehW.tupnitceleskcolC
.slevelecafretniLTTVL/SOMCVL.1KLCn,1KLCstceles,HGIHnehW
8RMtupnInwodlluP
tesererasredividlanretnieht,HGIHcigolnehW.teseRretsaMhgiHevitcA
ogotxQnstuptuodetrevniehtdnawologotxQstu
ptuoeurtehtgnisuac
.delbaneerastuptuoehtdnasredividlanretnieht,WOLcigolnehW.hgih
.slevelecafretniLTTVL/
SOMCVL
23,9V
CC
rewoP.snipylppuseroC
01NI_BFntupnIpulluP ."yaledorez"htiwskcolcgnitarenegerrofrotcetedesahpottupnikcabdeeF
1
1NI_BFtupnInwodlluP ."yaledorez"htiwskcolcgnitarenegerrofrotcetedesahpottupnikcabdeeF
31,21
92,82 V
EE
rewoP.snipylppusevitageN
51,410Q,0QntuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
,71.61
52,42 V
OCC
rewoP.snipylppustuptuO
91,811Q,1QntuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
12,022Q,2QntuptuO.slevel
ecafretniLCEPVL.riaptuptuolaitnereffiD
32,223Q,3QntuptuO..slevelecafretniLCEPVL.riaptuptuolaitnereffiD
72,
624Q,4QntuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
03V
ACC
rewoP.nipylppusgolanA
13LES_LLPtupnIpulluP
.sredividehtottupniehtsakcolcecnereferehtdnaLLPehtneewtebstceleS
/SOMCVL.kcolcecnereferstceles,WOLnehW.LLPstceles,HGIHnehW
.slevelecafretniLTTVL
:ETON
pulluP
dna
nwodlluP
.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotrefer
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
ecnaticapaCtupnI 4Fp
R
PULLUP
rotsiseRpulluPtupnI 15kΩ
R
NWODLLUP
rotsiseRnwodlluPtupnI 15kΩ
stupnI
stuptuO
1=LES_LLP
edoMelbanELLP
1LES0LES*)zHM(egnaRycneuqerFecnerefeR4Qn:0Qn,4Q:0Q
00 007-0521÷
01 053-5211÷
10 571
-5.261÷
11 5.78-52.131÷
sievobasnoitarugifnocllarofegnarycneuqerfOCV:ETON*
.zHM007otzHM052
stupnI
stuptuO
0=LES_LLP
edoMssapyBLLP
1LES0LES4Qn:0Qn,4Q:0Q
00 4÷
01 4÷
10 4÷
11 8÷
TABLE 3A. CONTROL INPUT FUNCTION TABLE TABLE 3B. PLL BYPASS FUNCTION TABLE
8634BY-01 www.idt.com REV. D OCTOBER 4, 2010
3
ICS8634-01
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY BUFFER
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnI 2V
CC
3.0+V
V
LI
egatloVwoLtupnI 3.0-8.0V
I
HI
tnerruChgiHtupnI
,1LES,0LES
RM,LES_KLC V
CC
V=
NI
V564.3=051Aµ
LES_LLPV
CC
V=
NI
V564.3=5Aµ
I
LI
tnerruCwoLtupnI
,1LES,0LES
RM,LES_KLC V
CC
V,V564.3=
NI
V0=5-Aµ
LES_LLPV
CC
V,V564.3=
NI
V0=051-Aµ
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
I
HI
tnerruChgiHtupnI NI_BF,1KLC,0KLCV
CC
V=
NI
V564.3=051Aµ
NI_BFn,1KLCn,0KLCnV
CC
V=
NI
V564.3=5Aµ
I
LI
tnerruCwoLtupnI NI_BF,1KLC,0KLCV
CC
V,V564.3=
NI
V0=5-Aµ
NI_BFn,1KLCn,0KLCnV
CC
V,V564.3=
NI
V0=051-Aµ
V
PP
egatloVtupnIkaeP-ot-kaeP 51.03.1V
V
RMC
2,1ETON;egatloVtupnIedoMnommoCV
EE
5.0+V
CC
58.0-V
si1KLCn,1KLCdna0KLCn,0KLCrofegatlovtupnimumixameht,snoitacilppadedneelgnisroF:1ETON V
CC
.V3.0+
VsadenifedsiegatlovedomnommoC:2ETON
HI
.
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
CC
egatloVylppuSeroC 531.33.3564.3V
V
ACC
egatloVylppuSgolanA 531.33.3564.3V
V
OCC
egatloVylppuStuptuO 531.33.3564.3V
I
EE
tnerruCylppuSrewoP 051Am
I
ACC
tnerruCylppuSgolanA 51Am
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
CC 4.6V
Inputs, VI-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current 50mA
Surge Current 100mA
Package Thermal Impedance, θJA
32 Lead LQFP 47.9°C/W (0 lfpm)
32 Lead VFQFN 34.8°C/W (0 lfpm)
Storage Temperature, T
STG -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
8634BY-01 www.idt.com REV. D OCTOBER 4, 2010
4
ICS8634-01
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY BUFFER
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HO
1ETON;egatloVhgiHtuptuOV
OCC
4.1-V
OCC
7.0-V
V
LO
1ETON;egatloVwoLtuptuOV
OCC
0.2-V
OCC
7.1-V
V
GNIWS
gniwSegatloVtuptuOkaeP-ot-kaeP6.00.1V
05htiwdetanimretstuptuO:1ETON ΩVot
OCC
.V2-
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
XAM
ycneuqerFtuptuO 007zHM
t
DP
1ETON;yaleDnoitagaporP ,V0=LES_LLP
f≤zHM007 2.32.4sn
t
)Ø( ;yaleDoreZecnerefeRLLP
4,2ETON V3.3=LES_LLP05-05051sp
t
)o(ks4,3ETON;wekStuptuO 52sp
t
)cc(tij6,4ETON;rettiJelcyC-ot-elcyC 52sp
t
(tij θ)6,5,4ETON;rettiJesahP 05±sp
t
L
emiTkcoLLLP 1sm
t
R
t/
F
emiTllaF/esiRtuptuOzHM05@%08ot%02003007sp
cdoelcyCytuDtuptuO 7435%
taderusaemsretemarapllAf
XAM
.esiwrehtodetonsselnu
.tniopgnissorctuptuolaitnereffidehtottniopgnissorctupnilaitnereffidehtmorfderusa
eM:1ETON
langistupnikcabdeefegarevaehtdnakcolcecnerefertupniehtneewtebecnereffidemitehtsadenifeD:2ETON
.elbatssiycneuqerfecnerefertupniehtdnadekcolsiLLPehtnehw
.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:3ETON
.stniopssorclaitnereffidtuptuoehttaderusaeM
.56dradnatSCEDEJhtiwe
cnadroccanidenifedsiretemarapsihT:4ETON
.desuecruostupniehtnotnednepedsirettijesahP:5ETON
.zHM226foycneuqerfOCVtadeziretcarahC:6ETON
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
NI
ycneuqerFtupnI ,0KLCn,0KLC
1KLCn,1KLC
1=LES_LLP52.13007zHM
0=LES_LLP007zHM
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
8634BY-01 www.idt.com REV. D OCTOBER 4, 2010
5
ICS8634-01
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY BUFFER
PARAMETER MEASUREMENT INFORMATION
OUTPUT SKEW
DIFFERENTIAL INPUT LEVEL
3.3V OUTPUT LOAD AC TEST CIRCUIT
SCOPE
Qx
nQx
LVPECL
2V
CYCLE-TO-CYCLE JITTER
-1.3V ± 0.165V
tsk(o)
nQx
Qx
nQy
Qy
V
CMR
Cross Points
V
PP
VCC
VEE
CLK0,
CLK1
nCLK0,
nCLK1
OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
PROPAGATION DELAY PHASE JITTER & STATIC PHASE OFFSET
Clock
Outputs 20%
80% 80%
20%
t
R
t
F
V
SWIN G
Pulse Width
tPERIOD
tPW
tPERIOD
odc =
Q0:Q4
nQ0:nQ4
t
PD
CLK0,
CLK1
nCLK0,
nCLK1
Q0:Q4
nQ0:nQ4
➤
➤
➤
➤
t
jit(cc) =
t
cycle n –
t
cycle n+1
1000 Cycles
t
cycle n
t
cycle n+1
Q0:Q4
nQ0:nQ4
(where
t
(Ø) is any random sample, and
t
(Ø) mean is the average
of the sampled cycles measured on controlled edges)
t
(Ø) mean = Static Phase Offset
➤
➤
t(Ø)
V
OH
V
OL
V
OH
V
OL
nCLK0,
nCLK1
nFB_IN
FB_IN
t
jit(Ø) =
t
(Ø) —
t
(Ø) mean = Phase Jitter
CLK0,
CLK1
VCC,
VCCA,
VCCO
VEE
8634BY-01 www.idt.com REV. D OCTOBER 4, 2010
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ICS8634-01
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY BUFFER
V
CC
- 2V
50Ω50Ω
RTT
Z
o
= 50Ω
Z
o
= 50Ω
FOUT FIN
RTT = Z
o
1
((V
OH
+ V
OL
) / (V
CC
– 2)) – 2
3.3V
125Ω125Ω
84Ω84Ω
Zo = 50Ω
Zo = 50Ω
FOUT FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion.
Figures 2A and 2B
show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
TERMINATION FOR LVPECL OUTPUTS
FIGURE 2B. LVPECL OUTPUT TERMINATIONFIGURE 2A. LVPECL OUTPUT TERMINATION
APPLICATION INFORMATION
Figure 1
shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u R2
1K
Single Ended Cl ock Input CLKx
nCLKx
VCC
8634BY-01 www.idt.com REV. D OCTOBER 4, 2010
7
ICS8634-01
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY BUFFER
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8634-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCA, and VCCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 3
illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VCCA pin.
POWER SUPPLY FILTERING T ECHNIQUES
FIGURE 3. POWER SUPPLY FILTERING
10Ω
VCCA
10 μF
.01μF
3.3V
.01μF
VCC
FIGURE 4C. CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 4B. CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 4D. CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 4A to 4D show inter-
face examples for the CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
FIGURE 4A. CLK/nCLK INPUT DRIVEN BY
LVHSTL DRIVER
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example in
Figure 4A,
the input termination applies for LVHSTL
drivers. If you are using an LVHSTL driver from another
vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
Z o = 50 Ohm
R1
100
3.3V
LVDS_Driver
Z o = 50 Ohm
Receiver
CLK
nCLK
3.3V
8634BY-01 www.idt.com REV. D OCTOBER 4, 2010
8
ICS8634-01
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY BUFFER
FIGURE 5A. ICS8634-01 LVPECL ZERO DELAY BUFFER SCHEMATIC EXAMPLE
LAYOUT GUIDELINE
The schematic of the ICS8634-01 layout example is shown in
Figure 5A.
The ICS8634-01 recommended PCB board layout
for this example is shown in
Figure 5B.
This layout example is
used as a general guideline. The layout in the actual system will
(U1-32)
VCCO
SP = Space (i.e. not intstalled)
R6
50
RU3
1K
Zo = 50 Ohm
3.3V
C2
0.1uF
C1
0.1uF
VCC
C4
0.1uF C5
0.1uF
SEL0
R9
50
(U1-9)
RD5
1K
SEL0
R8
50
Bypass capacitor located near the power pins
R2
50
VCCO=3.3V
VCC
Zo = 50 Ohm
CLK_SEL
VCC=3.3V
R4
50
RU4
1K
(155.5 MHz)
3.3V PECL Driver
SEL1
R7
10
RU2
SP
R3
50
(U1-17)
Zo = 50 Ohm
SEL1
RD2
1K
CLK_SEL
VCCO
LVPECL_input
+
-
R10
50
155.5 MHz
DIV_SEL[1:0] = 01
PLL_SEL
RD3
SP
C16
10u
R5
50
Output
Termination
Example
C11
0.01u
(U1-24)
RU5
SP
(U1-25)
VCC
RD4
SP
Zo = 50 Ohm
C6
0.1uF
U1
8634-01
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK2
CLK_SEL
MR
VCC
nFB_IN
FB_IN
VEE
VEE
nQ0
Q0
VCCO
VCCO
nQ1
Q1
nQ2
Q2
nQ3
Q3
VCCO
VCC
PLL_SEL
VCCA
VEE
VEE
Q4
nQ4
VCCO
(U1-16)
VCCA
C7
0.1uF
R1
50
VCC
PLL_SEL
depend on the selected component types, the density of the
components, the density of the traces, and the stack up of the
P.C. board.
8634BY-01 www.idt.com REV. D OCTOBER 4, 2010
9
ICS8634-01
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY BUFFER
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors C1, C2, C4, C5, C6, and C7, as
close as possible to the power pins. If space allows, placement
of the decoupling capacitor on the component side is preferred.
This can reduce unwanted inductance between the decoupling
capacitor and the power pin caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the VCCA pin as possible.
CLOCK TRACES AND TERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
• The differential 50Ω output traces should have same
length.
• Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
• Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
• Make sure no other signal traces are routed between the
clock trace pair.
• The matching termination resistors should be located as
close to the receiver input pins as possible.
FIGURE 5B. PCB BOARD LAYOUT FOR ICS8634-01
C4
C1
U1
VIA
VCCA
VCCO
C7
C11C16
C5
VCC
C2
C6
GND
R7
50 Ohm
Traces
Pin 1
8634BY-01 www.idt.com REV. D OCTOBER 4, 2010
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ICS8634-01
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8634-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8634-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 150mA = 520mW
•Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 5 * 30mW = 150mW
Total Power_MAX (3.465V, with all outputs switching) = 520mW + 150mW = 670mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for the devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 7A below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.670W * 42.1°C/W = 98.2°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
θθ
θθ
θJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 7A. THERMAL RESISTANCE θθ
θθ
θJA FOR 32-PIN LQFP, FORCED CONVECTION
TABLE 7B. θJAVS. AIR FLOW TABLE FOR 32 LEAD VFQFN PACKAGE
θθ
θθ
θJA 0 Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 34.8C/W
8634BY-01 www.idt.com REV. D OCTOBER 4, 2010
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ICS8634-01
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 6.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V
CCO
- 2V.
• For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(VCCO_MAX - VOH_MAX
) = 0.9V
• For logic low, VOUT = VOL_MAX = VCCO_MAX
– 1.7V
(VCCO_MAX - VOL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX
– (VCCO_MAX
- 2V))/R
L
] * (VCCO_MAX
- VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX
))/R
L
] * (VCCO_MAX
- VOH_MAX) =
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX
– (VCCO_MAX
- 2V))/R
L
] * (VCCO_MAX
- VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX
))/R
L
] * (VCCO_MAX
- VOL_MAX) =
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
Q1
VOUT
VCCO
RL
50
VCCO - 2V
8634BY-01 www.idt.com REV. D OCTOBER 4, 2010
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ICS8634-01
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RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS8634-01 is: 2969
TABLE 8A. θJAVS. AIR FLOW TABLE FOR 32 LQFP
θθ
θθ
θJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 8B. θJAVS. AIR FLOW TABLE FOR 32 LEAD VFQFN PACKAGE
θθ
θθ
θJA 0 Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 34.8C/W
8634BY-01 www.idt.com REV. D OCTOBER 4, 2010
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ICS8634-01
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ZERO DELAY BUFFER
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 9. PACKAGE DIMENISIONS
NOITAIRAVCEDEJ
SRETEMILLIMNISNOISNEMIDLLA
LOBMYS
ABB
MUMINIMLANIMONMUMIXAM
N23
A06.1
1A 50.051.0
2A 53.104.154.1
b03.
073.054.0
c90.002.0
DCISAB00.9
1D CISAB00.7
2D 06.5
ECISAB00.9
1E CISAB00.7
2E 06.5
eCISAB08.0
L54.006.057.0
θθ
θ
θθ 0
°
7
°
ccc 01.0
Reference Document: JEDEC Publication 95, MS-026
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ICS8634-01
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY BUFFER
PACKAGE OUTLINE - K SUFFIX FOR 32 LEAD VFQFN
TABLE 9B. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MO-220
NOITAIRAVCEDEJ
SRETEMILLIMNISNOISNEMIDLLA
LOBMYSMUMINIMMUMIXAM
N23
A08.00.1
1A 050.0
3A ecnerefeR52.0
b81.003.0
eCIS
AB05.0
N
D
8
N
E
8
D0.5
2D 52.152.3
E0.5
2E 52.152.3
L03.005.0
8634BY-01 www.idt.com REV. D OCTOBER 4, 2010
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TABLE 10. ORDERING INFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement of
any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial
applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves
the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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8634BY-01 www.idt.com REV. D OCTOBER 4, 2010
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ICS8634-01
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