LTC3789
1
3789fc
For more information www.linear.com/LTC3789
Typical applicaTion
FeaTures
applicaTions
DescripTion
High Efficiency, Synchronous,
4-Switch Buck-Boost Controller
The LTC
®
3789 is a high performance buck-boost switch-
ing regulator controller that operates from input volt-
ages above, below or equal to the output voltage. The
constant-frequency, current mode architecture allows
a phase-lockable frequency of up to 600kHz, while an
output current feedback loop provides support for battery
charging. With a wide 4V to 38V (40V maximum) input and
output range and seamless, low noise transitions between
operating regions, the LTC3789 is ideal for automotive,
telecom and battery-powered systems.
The operating mode of the controller is determined through
the MODE/PLLIN pin. The MODE/PLLIN pin can select
between pulse-skipping mode and forced continuous
mode operation and allows the IC to be synchronized to an
external clock. Pulse-skipping mode offers high efficiency
and low ripple at light loads, while forced continuous
mode operates at a constant frequency for noise-sensitive
applications.
A PGOOD pin indicates when the output is within 10% of
its designed set point. The LTC3789 is available in low pro-
file 28-pin 4mm × 5mm QFN and narrow SSOP packages.
Efficiency and Power Loss
n Single Inductor Architecture Allows VIN Above,
Below or Equal to the Regulated VOUT
n Programmable Input or Output Current
n Wide VIN Range: 4V to 38V
n 1% Output Voltage Accuracy: 0.8V < VOUT < 38V
n Synchronous Rectification: Up to 98% Efficiency
n Current Mode Control
n Phase-Lockable Fixed Frequency: 200kHz to 600kHz
n No Reverse Current During Start-Up
n Power Good Output Voltage Monitor
n Internal 5.5V LDO
n Quad N-Channel MOSFET Synchronous Drive
n VOUT Disconnected from VIN During Shutdown
n True Soft-Start and VOUT Short Protection, Even in
Boost Mode
n Available in 28-Lead QFN (4mm × 5mm) and
28-Lead SSOP Packages
n Automotive Systems
n Distributed DC Power Systems
n High Power Battery-Operated Devices
n Industrial Control
+
VIN
VINSNS VOUTSNS
ILIM
PGOOD
0.1µF 0.1µF
121k
BOOST1
TG1
SW1
BG1
TG2
BOOST2
SW2
BG2
MODE/PLLIN
RUN
VFB
ITH
SS
0.010Ω
4.7µF
A
B
D
C
2200pF
1000pF
1µF
CER
10µF
16V
CER
2.2µF
330µF
16V
ON/OFF
0.01µF
4.7µH
8k
LTC3789
INTVCC
EXTVCC
SENSE+
IOSENSE–
IOSENSE+
FREQ
SGND
SENSE–PGND
7.5k
1%
3789 TA01
105k, 1%
VIN
4V TO
38V
VOUT
12V
5A
+
0.010Ω
100Ω
100Ω
22µF
50V
CER
L, LT, LT C, LTM , Linear Technology, the Linear logo, µModule and Burst Mode are registered
trademarks and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks
are the property of their respective owners. Protected by U.S. Patents, including 5408150,
5481178, 5929620, 6580258, 7365525, 7394231.
VIN (V)
0
EFFICIENCY (%)
POWER LOSS (W)
90
95
85
80
10 15 25
520 30 35 40
75
70
100
4
2
8
10
6
0
12
3789 TA01b
VOUT = 12V
ILOAD = 5A
LTC3789
2
3789fc
For more information www.linear.com/LTC3789
absoluTe MaxiMuM raTings
Input Supply Voltage (VIN) ......................... 40V to –0.3V
Topside Driver Voltages
(BOOST1, BOOST2)................................... 46V to –0.3V
Switch Voltage (SW1, SW2) .......................... 40V to –5V
Current Sense Voltages (IOSENSE+, IOSENSE–).. 40V to –0.3V
BOOST1, BOOST2 – SW1, SW2 ................... 6V to –0.3V
TG1, TG2 – SW1, SW2 ................................. 6V to –0.3V
EXTVCC Voltage ......................................... 14V to –0.3V
INTVCC Voltage ............................................ 6V to –0.3V
SENSE+, SENSE– Voltages ....................INTVCC to –0.3V
MODE/PLLIN, SS Voltages ...................INTVCC to –0.3V
(Note 1)
VINSNS, VOUTSNS ........................................ 40V to –0.3V
TG1, TG2, BG1, BG2 Voltages ........................... (Note 6)
ITH, FREQ, ILIM Voltages .......................INTVCC to –0.3V
VFB Voltage ............................................... 2.7V to –0.3V
RUN, PGOOD Voltage .................................. 6V to –0.3V
Operating Junction Temperature Range
(Notes 2, 3) ............................................ –40°C to 125°C
Storage Temperature Range .................. –65°C to 125°C
INTVCC Peak Output Current ................................100mA
Lead Temperature (Soldering, 10 sec.)
GN Package ......................................................300°C
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3789EGN#PBF LTC3789EGN#TRPBF LTC3789 28-Lead Narrow Plastic SSOP –40°C to 125°C
LTC3789IGN#PBF LTC3789IGN#TRPBF LTC3789 28-Lead Narrow Plastic SSOP –40°C to 125°C
LTC3789EUFD#PBF LTC3789EUFD#TRPBF 3789 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C
LTC3789IUFD#PBF LTC3789IUFD#TRPBF 3789 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
GN PACKAGE
28-LEAD NARROW PLASTIC SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VFB
SS
SENSE+
SENSE–
ITH
SGND
MODE/PLLIN
FREQ
RUN
VINSNS
VOUTSNS
ILIM
IOSENSE+
IOSENSE–
PGOOD
SW1
TG1
BOOST1
PGND
BG1
VIN
INTVCC
EXTVCC
BG2
BOOST2
TG2
SW2
TRIM
TJMAX = 125°C, θJA = 80°C/W
9 10
TOP VIEW
UFD PACKAGE
28-LEAD (4mm × 5mm) PLASTIC QFN
11 12 13
28 27 26 25 24
14
23
6
5
4
3
2
1
SENSE–
ITH
SGND
MODE/PLLIN
FREQ
RUN
VINSNS
VOUTSNS
BOOST1
PGND
BG1
VIN
INTVCC
EXTVCC
BG2
BOOST2
SENSE+
SS
VFB
PGOOD
SW1
TG1
ILIM
IOSENSE+
IOSENSE–
TRIM
SW2
TG2
7
17
18
19
20
21
22
16
815
29
SGND
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 29) IS SGND, MUST BE SOLDERED TO PCB
pin conFiguraTion
LTC3789
3
3789fc
For more information www.linear.com/LTC3789
elecTrical characTerisTics
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Input Supply Voltage 4 38 V
VOUT Output Voltage 0.8 38 V
VFB Regulated Feedback Voltage ITH Voltage = 1.2V (Note 4), TA = –40°C to 85°C
ITH = 1.2V, TA = 125°C, TA = –40°C to 125°C
l
l
0.792
0.788 0.800
0.800 0.808
0.812 V
V
IFB Feedback Current (Note 4) –15 –50 nA
VREFLNREG Reference Voltage Line Regulation VIN = 4V to 38V (Note 4) 0.002 0.02 %/V
VLOADREG Output Voltage Load Regulation (Note 4)
Measured in Servo Loop, ∆ITH Voltage = 1.4V to 2V
Measured in Servo Loop, ∆ITH Voltage = 2V to 2.5V
l
l
0.01
–0.01
0.1
–0.1
%
%
gmTransconductance Amplifier gmITH = 1.2V, Sink/Source 5µA (Note 4) 1.5 mmho
IQInput DC Supply Current
Normal Mode
Shutdown
(Note 5)
VRUN = 0V
3
40
60
mA
µA
UVLO Undervoltage Lockout INTVCC Ramping Down 3.4 3.6 V
UVLO Hyst Undervoltage Hysteresis 0.4 V
ISENSE+
ISENSE–SENSE Pins Current VSENSE– = VSENSE+ = 0V 0.2 ±1 µA
IIOSENSE+
IIOSENSE–IOSENSE Pins Current VIOSENSE– = VIOSENSE+ = 10V 10 14 µA
ISS Soft-Start Charge Current VSS = 0V 2 3 4 µA
VRUN(ON) RUN Pin On-Threshold VRUN Rising 1.22 V
VRUN(HYS) RUN Pin On-Hysteresis 150 mV
IRUN RUN Pin Source Current 1.2 µA
IRUN(HYS) RUN Pin Hysteresis Current 5 µA
VSENSE(MAX) Maximum Current Sense Threshold
Buck Region, (IL Valley)
Boost Region, (IL Peak)
VFB = 0.7V
VFB = 0.7V
l
l
73
123
90
140
107
157
mV
mV
VSENSE(IAVG) Maximum Input/Output Average
Current Sense Threshold ILIM = 0V
ILIM Floating
ILIM = INTVCC
48
90
130
50
100
145
52.5
106
160
mV
mV
mV
RDSPFET(ON) Driver Pull-Up On-Resistance 2.6 Ω
RDSNFET(ON) Driver Pull-Down On-Resistance 1.5 Ω
TG tr
TG tf
Top Gate Rise Time
Top Gate Fall Time 25
25 ns
ns
BG tr
BG tf
Bottom Gate Rise Time
Bottom Gate Fall Time 25
25 ns
ns
TG/BG t1D Top Gate Off to Bottom Gate On
Delay Synchronous Switch-On
Delay Time
CLOAD = 3300pF Each Driver (Note 6) 60 ns
BG/TG t1D Bottom Gate Off to Top Gate On
Delay Top Switch-On Delay Time CLOAD = 3300pF Each Driver (Note 6) 60 ns
DFMAX,BOOST Maximum Duty Factor % Switch C On 90 %
DON(MIN,BOOST) Minimum Duty Factor for Main
Switch in Boost Operation % Switch C On 9 %
DON(MIN,BUCK) Minimum Duty Factor for
Synchronous Switch in Buck
Operation
% Switch B On 9 %
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 15V, VRUN = 5V, unless otherwise noted.
LTC3789
4
3789fc
For more information www.linear.com/LTC3789
elecTrical characTerisTics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 15V, VRUN = 5V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
INTVCC Linear Regulator
VINTVCCVIN Internal VCC Voltage 6.5V < VIN < 40V, VEXTVCC = 0V 5.2 5.5 5.8 V
VLDOVIN INTVCC Load Regulation ICC = 0mA to 20mA, VEXTVCC = 0V 0.2 1.0 %
VINTVCCEXT Internal VCC Voltage 6.5V < VEXTVCC < 14V 5.2 5.5 5.8 V
VLDOEXT INTVCC Load Regulation ICC = 0mA to 20mA, VEXTVCC = 12V 0.2 1.0 %
VEXTVCC EXTVCC Switchover Voltage ICC = 0mA to 20mA, EXTVCC Ramping Positive 4.7 4.8 V
VLDOHYS EXTVCC Hysteresis 0.25 V
Oscillator and Phase-Locked Loop
fNOM Nominal Frequency VFREQ = 1.2V 350 400 440 kHz
fLOW Low Fixed Frequency VFREQ = 0V 175 200 225 kHz
fHIGH High Fixed Frequency VFREQ = 2.4V 570 640 710 kHz
fSYNC Synchronizable Frequency MODE/PLLIN = External Clock l200 600 kHz
RMODE/PLLIN MODE/PLLIN Input Resistance 220 kΩ
IFREQ Frequency Setting Current 8 10 12 µA
PGOOD Output
VPGL PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 V
IPGOOD PGOOD Leakage Current VPGOOD = 5V ±1 µA
VPG PGOOD Trip Level VFB with Respect to Set Output Voltage
VFB Ramping Negative
VFB Ramping Positive
–10
10
%
%
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3789 is tested under pulse load conditions such that
TJ
≈
TA. The LTC3789E is guaranteed to meet performance specifications
from 0°C to 85°C operating junction temperature. Specifications over
the –40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LTC3789I is guaranteed to meet performance specifications over the
full –40°C to 125°C operating junction temperature range.
Note 3: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formula:
LTC3789GN: TJ = TA + (PD • 80°C/W)
LTC3789UFD: TJ = TA + (PD • 34°C/W)
Note 4: The LTC3789 is tested in a feedback loop that servos VITH to a
specified voltage and measures the resultant VFB.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See the Applications Information
section.
Note 6: Do not apply a voltage or current to these pins. They must be
connected to capacitive loads only, otherwise permanent damage may
occur.
LTC3789
5
3789fc
For more information www.linear.com/LTC3789
Typical perForMance characTerisTics
Efficiency vs Output Current
(Boost Region)
Efficiency vs Output Current
(Buck-Boost Region)
Efficiency vs Output Current
(Buck Region)
Efficiency vs VIN
Internal 5.5V LDO Line
Regulation EXTVCC LDO Line Regulation
INTVCC and EXTVCC Switch
Voltage vs Temperature Supply Current vs Input Voltage
RUN Pin Threshold
vs Temperature
TA = 25°C unless otherwise noted.
LOAD CURRENT (mA)
10
40
EFFICIENCY (%)
50
60
70
80
100 1000 10000
30
20
10
0
90
100
3789 G01
VIN = 6V
VOUT = 12V
DCM
FCM
DCM
FCM
CIRCUIT OF FIGURE 13
LOAD CURRENT (mA)
10
40
EFFICIENCY (%)
50
60
70
80
100 1000 10000
30
20
10
0
90
100
3789 G02
VIN = 12V
VOUT = 12V
DCM
FCM
CIRCUIT OF FIGURE 13
LOAD CURRENT (mA)
10
40
EFFICIENCY (%)
50
60
70
80
100 1000 10000
30
20
10
0
90
100
3789 G03
VIN = 18V
VOUT = 12V
DCM
FCM
CIRCUIT OF FIGURE 13
VIN (V)
0
91
EFFICIENCY (%)
93
95
97
10 20 4030
99
92
94
96
98
3789 G04
200kHz
300kHz
400kHz
520kHz
FREQUENCY
CIRCUIT OF FIGURE 13
INPUT VOLTAGE (V)
4
3.5
INTV
CC
VOLTAGE (V)
4.0
4.5
6.0
5.5
14 24 29
5.0
919 34
3789 G05 EXTVCC (V)
4
INTVCC (V)
4
5
11
3
2
6 8
5 13
7 9 12
10 14
1
0
6
3789 G06
TEMPERATURE (°C)
–60
INTVCC AND EXTVCC SWITCH VOLTAGE (V)
4
5
3
2
–20 0 40
–40 20 60 80 100
1
0
6
3789 G07
RISING
FALLING
INPUT VOLTAGE (V)
4
0
SUPPLY CURRENT (mA)
0.5
1.5
2.0
2.5
4.0
3.5
14 24 29
1.0
3.0
919 34
3789 G08
TEMPERATURE (°C)
–60
0.5
UNDERVOLTAGE RESET VOLTAGE AT RUN (V)
0.7
0.9
1.1
–40 –20 0 20 6040 80
1.3
1.5
0.6
0.8
1.0
1.2
1.4
100
3789 G09
RISING
FALLING
LTC3789
6
3789fc
For more information www.linear.com/LTC3789
Forced Continuous Mode Forced Continuous Mode Forced Continuous Mode
Pulse-Skipping Mode Pulse-Skipping Mode Pulse-Skipping Mode
Typical perForMance characTerisTics
TA = 25°C unless otherwise noted.
Oscillator Frequency
vs Temperature
Undervoltage Threshold at INTVCC
vs Temperature
Undervoltage Threshold at VIN
vs Temperature
4µs/DIV
SW1
10V/DIV
SW2
10V/DIV
IL
1A/DIV
3789 G10
VIN = 6V
VOUT = 12V
4µs/DIV
SW1
10V/DIV
SW2
10V/DIV
IL
1A/DIV
3789 G11
VIN = 12V
VOUT = 12V
4µs/DIV
IL
1A/DIV
SW1
10V/DIV
SW2
10V/DIV
3789 G12
VIN = 18V
VOUT = 12V
4µs/DIV
IL
1A/DIV
SW1
10V/DIV
SW2
10V/DIV
3789 G13
VIN = 6V
VOUT = 12V
2µs/DIV
IL
1A/DIV
SW1
10V/DIV
SW2
10V/DIV
3789 G14
VIN = 12V
VOUT = 12V
2µs/DIV
IL
1A/DIV
SW1
10V/DIV
SW2
10V/DIV
3789 G15
VIN = 18V
VOUT = 12V
TEMPERATURE (°C)
–60
0
UNDERVOLTAGE (V)
1.0
2.0
3.0
–40 –20 0 20 6040 80
4.0
5.0
0.5
1.5
2.5
3.5
4.5
100
3789 G17
RISING
FALLING
TEMPERATURE (°C)
–60
0
UNDERVOLTAGE (V)
1.0
2.0
3.0
–40 –20 0 20 6040 80
4.0
5.0
0.5
1.5
2.5
3.5
4.5
100
3789 G18
RISING
FALLING
TEMPERATURE (°C)
–50
0
OSCILLATOR FREQUENCY (kHz)
200
400
600
0 50 150100
700
100
300
500
VFREQ = 2.4V
VFREQ = 0V
VFREQ = 1.2V
LTC3789
7
3789fc
For more information www.linear.com/LTC3789
Maximum Current Sense
Threshold vs Duty Factor (Boost)
Maximum Current Sense
Threshold vs Duty Factor (Buck)
Maximum Current Limit
vs Temperature
Peak Current Threshold
vs VITH (Boost)
Valley Current Threshold
vs VITH (Buck) Current Foldback Limit
Typical perForMance characTerisTics
TA = 25°C unless otherwise noted.
VFB (V)
0
CURRENT LIMIT (mV)
120
140
0.7
100
80
0.2 0.4
0.1 0.3 0.5 0.8
0.6 0.9
20
0
60
160
40
3789 G24
BUCK
BOOST
DUTY FACTOR (%)
0
50
CURRENT LIMIT (mV)
70
90
110
20 40 60 80
130
150
60
80
100
120
140
100
3789 G19
DUTY FACTOR (%)
0
50
CURRENT LIMIT (mV)
70
90
110
20 40 60 80
130
150
60
80
100
120
140
100
3789 G20
VITH (V)
0
–200
CURRENT LIMIT (mV)
–100
0
100
0.5 11.5 2 2.5
200
–150
–50
50
150
3
3789 G22
VITH (V)
0
–100
CURRENT LIMIT (mV)
0
100
0.5 11.5 2
200
–50
50
150
2.5
3789 G23
TEMPERATURE (°C)
–50
MAXIMUM CURRENT LIMIT (mV)
120
130
140
90
110
100
–10 30
–30 10 50 110
70 130
70
60
90
150
80
3789 G21
BUCK
BOOST
LTC3789
8
3789fc
For more information www.linear.com/LTC3789
Line Transient Line Transient
Typical perForMance characTerisTics
TA = 25°C unless otherwise noted.
IL
2A/DIV
VITH
VIN
30V TO 5V
VOUT (AC)
500mV/DIV
3789 G28
1ms/DIV
IL
2A/DIV
VITH
VIN
5V TO 30V
VOUT (AC)
500mV/DIV
3789 G29
1ms/DIV
Load Step Load Step Load Step
400µs/DIV
IL
2A/DIV
VOUT
200mV/DIV
3789 G25
VIN = 6V
VOUT = 12V
LOAD STEP = 200mA TO 2A
400µs/DIV
IL
2A/DIV
VOUT
200mV/DIV
3789 G26
VIN = 12V
VOUT = 12V
LOAD STEP = 300mA TO 3A
400µs/DIV
IL
2A/DIV
VOUT
200mV/DIV
3789 G27
VIN = 18V
VOUT = 12V
LOAD STEP = 300mA TO 3A
LTC3789
9
3789fc
For more information www.linear.com/LTC3789
pin FuncTions
(SSOP/QFN)
VFB (Pin 1/Pin 26): Error Amplifier Feedback Pin. Receives
the feedback voltage for the controller from an external
resistive divider across the output.
SS (Pin 2/Pin 27): External Soft-Start Input. The LTC3789
regulates the VFB voltage to the smaller of 0.8V or the volt-
age on the SS pin. A internal 3µA pull-up current source
is connected to this pin. A capacitor to ground at this
pin sets the ramp time to final regulated output voltage.
SENSE+ (Pin 3/Pin 28): The (+) Input to the Current Sense
Comparator. The ITH pin voltage and controlled offsets
between the SENSE– and SENSE+ pins, in conjunction
with RSENSE, set the current trip threshold.
SENSE– (Pin 4/Pin 1): The (–) Input to the Current Sense
Comparator.
ITH (Pin 5/Pin 2): Error Amplifier Output and Switch-
ing Regulator Compensation Point. The channel’s
current comparator trip point increases with this control
voltage.
SGND (Pin 6/Pins 3, Exposed Pad Pin 29): Small
Signal Ground. Must be routed separately from high
current grounds to the common (–) terminals of the
CIN capacitors. In the QFN package, the exposed pad
is SGND. It must be soldered to PCB ground for rated
thermal performance.
MODE/PLLIN (Pin 7/Pin 4): Mode Selection or External
Synchronization Input to Phase Detector. This is a dual-
purpose pin. When external frequency synchronization
is not used, this pin selects the operating mode. The
pin can be tied to SGND or INTVCC. SGND or below
0.8V enables forced continuous mode. INTVCC enables
pulse-skipping mode. For external sync, apply a clock
signal to this pin. The internal PLL will synchronize the
internal oscillator to the clock, and forced continuous
mode will be enabled. The PLL composition network is
integrated into the IC.
FREQ (Pin 8/Pin 5): Frequency Set Pin. There is a precision
10µA current flowing out of this pin. A resistor to ground
sets a voltage which, in turn, programs the frequency.
Alternatively, this pin can be driven with a DC voltage to
vary the frequency of the internal oscillator.
RUN (Pin 9/Pin 6): Run Control Input. Forcing the pin
below 0.5V shuts down the controller, reducing quies-
cent current. There are 1.2µA pull-up currents for this
pin. Once the RUN pin rises above 1.22V, the IC is turned
on, and an additional 5µA pull-up current is added to
the pin.
VINSNS (Pin 10/Pin 7): VIN Sense Input to the Buck-Boost
Transition Comparator. Connect this pin to the drain of the
top N-channel MOSFET on the input side.
VOUTSNS (Pin 11/Pin 8): VOUT Sense Input to the Buck-
Boost Transition Comparator. Connect this pin to the VOUT.
ILIM (Pin 12/Pin 9): Input/Output Average Current
Sense Range Input. This pin tied to SGND, INTVCC or
left floating, sets the maximum average current sense
threshold.
IOSENSE+ (Pin 13/Pin 10): The (+) Input to the Input/Output
Average Current Sense Amplifier.
IOSENSE– (Pin 14/Pin 11): The (–) Input to the Input/Output
Average Current Sense Amplifier.
TRIM (Pin 15/Pin 12): Tie this pin to GND for normal
operation. Do not allow this pin to float.
EXTVCC (Pin 20/Pin 17): External Power Input to an
Internal LDO Connected to INTVCC. This LDO supplies
INTVCC power, bypassing the internal LDO powered from
VIN whenever EXTVCC is higher than 4.8V. See EXTVCC
Connection in the Applications Information section. Do
not exceed 14V on this pin.
LTC3789
10
3789fc
For more information www.linear.com/LTC3789
pin FuncTions
(SSOP/QFN)
INTVCC (Pin 21/Pin 18): Output of the Internal Linear Low
Dropout Regulator. The driver and control circuits are
powered from this voltage source. Must be bypassed to
power ground with a minimum of 4.7µF tantalum, ceramic,
or other low ESR capacitor.
VIN (Pin 22/Pin 19): Main Supply Pin. A bypass capacitor
should be tied between this pin and the power ground pin.
BG1, BG2 (Pins 23, 19/Pins 20, 16): High Current
Gate Drives for Bottom (Synchronous) N-Channel
MOSFETs. Voltage swing at these pins is from ground to
INTVCC.
PGND (Pin 24/Pin 21): Driver Power Ground. Connects
to COUT and RSENSE (–) terminal(s) of CIN.
BOOST1, BOOST2 (Pins 25, 18/Pins 22, 15): Bootstrapped
Supplies to the Top Side Floating Drivers. Capacitors
are connected between the BOOST and SW pins and
Schottky diodes are tied between the BOOST and INTVCC
pins. Voltage swing at the BOOST1 pin is from INTVCC
to (VIN + INTVCC). Voltage swing at the BOOST2 pin is
from INTVCC to (VOUT + INTVCC).
TG1, TG2 (Pins 26, 17/Pins 23, 14): High Current
Gate Drives for Top N-Channel MOSFETs. These are the
outputs of floating drivers with a voltage swing equal
to INTVCC – 0.5V superimposed on the switch node
voltage SW.
SW1, SW2 (Pins 27, 16/Pins 24, 13): Switch Node
Connections to Inductors. Voltage swing at the SW1
pin is from a Schottky diode (external) voltage drop
below ground to VIN. Voltage swing at the SW2 pin is
from a Schottky diode voltage drop below ground to
VOUT.
PGOOD (Pin 28/Pin 25): Open-Drain Logic Output.
PGOOD is pulled to ground when the voltage on the VFB
pin is not within ±10% of its regulation window, after the
internal 20µs power-bad mask timer expires.
LTC3789
11
3789fc
For more information www.linear.com/LTC3789
block DiagraM
–
+
–
–
+
+
BOOST1
INTVCC VIN
TG1
BG1
BG2 RSENSE
RSENSE2
PGND
FCB
FCB
INTVCC
INTVCC
INTVCC
IDREV SW1
SW2
TG2
BOOST2
IOSENSE+
IOSENSE–
IOS
SS
ITH
VFB
VOUT
0.80V
3789 BD
OV
EA
BUCK
LOGIC
CHARGE
PUMP BOOST1
CHARGE
PUMP BOOST2
BOOST
LOGIC
SENSE+
SENSE–
–
+IREV
–
+ICMP
VFLD
VIN
SW1
1.2µA
SHDN
RUN
–
+
4.8V
5.5V
VIN
VIN
INTERNAL
SUPPLY
EXTVCC
INTVCC
SGND
+
5.5V
LDO
REG
EXTVCC
5.5V
LDO
REG
–
+
–
+
–
+
0.86V
OV
0.74V
VFB
OSCILLATOR
PHASE DET
FREQ
MODE/
PLLIN
220k
FIN
PGOOD
3µA
–
ILIM
SLOPE
10µA
+
LTC3789
12
3789fc
For more information www.linear.com/LTC3789
operaTion
MAIN CONTROL LOOP
The LTC3789 is a current mode controller that provides
an output voltage above, equal to or below the input volt-
age. The LTC proprietary topology and control architecture
employs a current-sensing resistor. The inductor current
is controlled by the voltage on the ITH pin, which is the
output of the error amplifier EA. The VFB pin receives the
voltage feedback signal, which is compared to the internal
reference voltage by the EA. If the input/output current
regulation loop is implemented, the sensed inductor cur-
rent is controlled by either the sensed feedback voltage
or the input/output current.
INTVCC/EXTVCC Power
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTVCC pin.
When the EXTVCC is left open or tied to a voltage less
than 4.5V, an internal 5.5V low dropout (LDO) regulator
supplies INTVCC power from VIN. If EXTVCC is taken above
4.8V, the 5.5V regulator is turned off, and another LDO
regulates INTVCC from EXTVCC. The EXTVCC LDO allows
the INTVCC power to be derived from a high efficiency
external source such as the LTC3789 regulator output
to reduce IC power dissipation. The absolute maximum
voltage on EXTVCC is 14V.
Internal Charge Pump
Each top MOSFET driver is biased from the floating boot-
strap capacitors CA and CB, which are normally recharged
by INTVCC through an external diode when the top MOSFET
is turned off. When the LTC3789 operates exclusively in
the buck or boost regions, one of the top MOSFETs is
constantly on. An internal charge pump recharges the
bootstrap capacitor to compensate for the small leakage
current through the bootstrap diode so that the MOSFET
can be kept on. However, if a high leakage diode is used
such that the internal charge pump cannot provide sufficient
charges to the external bootstrap capacitor, an internal
UVLO comparator, which constantly monitors the drop
across the capacitor, will sense the (BOOST – SW) voltage
when it is below 3.6V. It will turn off the top MOSFET for
about one-twelfth of the clock period every four cycles to
allow CA or CB to recharge.
Shutdown and Start-Up
The controller can be shut down by pulling the RUN
pin low. When the RUN pin voltage is below 0.5V, the
LTC3789 goes into low quiescent current mode. Releas-
ing RUN allows an internal 1.2µA current to pull up the
pin and enable the controller. When RUN is above the
accurate threshold of 1.22V, the internal LDO will power
up the INTVCC. At the same time, a 6µA pull-up current
will kick in to provide more RUN pin hysteresis. The RUN
pin may be externally pulled up or driven directly by logic.
Be careful not to exceed the absolute maximum rating of
6V on this pin.
The start-up of the controller’s output voltage VOUT is
controlled by the voltage on the SS pin. When the voltage
on the SS pin is less than the 0.8V internal reference, the
LTC3789 regulates the VFB voltage to the SS voltage instead
of the 0.8V reference. This allows the SS pin to be used
to program soft-start by connecting an external capacitor
from the SS pin to SGND. An internal 3µA pull-up current
charges this capacitor, creating a voltage ramp on the SS
pin. As the SS voltage rises linearly from 0V to 0.8V (and
beyond), the output voltage VOUT rises smoothly from zero
to its final value. Alternatively, the SS pin can be used to
cause the start-up of VOUT to track that of another supply.
When RUN is pulled low to disable the controller, or when
INTVCC is below the undervoltage lockout threshold of
3.4V, the SS pin is pulled low by an internal MOSFET. In
undervoltage lockout, the controller is disabled and the
external MOSFETs are held off.
LTC3789
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For more information www.linear.com/LTC3789
Figure 3. Buck Region (VIN >> VOUT)
POWER SWITCH CONTROL
Figure 1 shows a simplified diagram of how the four
power switches are connected to the inductor, VIN, VOUT
and GND. Figure 2 shows the regions of operation for
the LTC3789 as a function of duty cycle, D. The power
switches are properly controlled so the transfer between
regions is continuous.
Buck Region (VIN >> VOUT)
Switch D is always on and switch C is always off in this
region. At the start of every cycle, synchronous switch
B is turned on first. Inductor current is sensed when
synchronous switch B is turned on. After the sensed
inductor valley current falls below a reference voltage,
which is proportional to VITH, synchronous switch B is
turned off and switch A is turned on for the remainder of
the cycle. Switches A and B will alternate, behaving like
a typical synchronous buck regulator. The duty cycle of
switch A increases until the maximum duty cycle of the
converter reaches DMAX_BUCK, given by:
DMAX _BUCK =1−
1
12
•100% =91.67%
Figure 3 shows typical buck region waveforms. If VIN
approaches VOUT, the buck-boost region is reached.
operaTion
Figure 1. Simplified Diagram of the Output Switches
Figure 2. Operating Region vs Duty Cycle
TG1
BG1
TG2
BG2
RSENSE
3789 F01
A
B
D
C
L
SW1 SW2
V
IN
V
OUT
A ON, B OFF
PWM C, D SWITCHES
D ON, C OFF
PWM A, B SWITCHES
FOUR SWITCH PWM
90%
DMAX
OOST
DMIN
BUCK
DMIN
BOOST
DMAX
BUCK
BOOST REGION
BUCK REGION
BUCK/BOOST REGION
3789 F02
SWITCH A
CLOCK
SWITCH B
SWITCH C
SWITCH D
IL
LOW
HIGH
3780 F03
Buck-Boost Region (VIN
≈
VOUT)
When VIN is close to VOUT, the controller enters buck-
boost region. Figure 4 shows the typical waveforms in this
region. At the beginning of a clock cycle, if the controller
starts with B and D on, the controller first operates as a
buck region. When ICMP trips, switch B is turned off, and
switch A is turned on. At 120° clock phase, switch C is
turned on. The LTC3789 starts to operate as a boost until
ICMP trips. Then, switch D is turned on for the remainder
of the clock period. If the controller starts with switches
A and C on, the controller first operates as a boost, until
ICMP trips and switch D is turned on. At 120°, switch B is
turned on, making it operate as a buck. Then, ICMP trips,
turning switch B off and switch A on for the remainder of
the clock period.
Boost Region (VIN << VOUT)
Switch A is always on and synchronous switch B is always
off in the boost region. In every cycle, switch C is turned
on first. Inductor current is sensed when synchronous
switch C is turned on. After the sensed inductor peak
current exceeds what the reference voltage demands,
which is proportional to VITH, switch C is turned off and
synchronous switch D is turned on for the remainder of
the cycle. Switches C and D will alternate, behaving like a
typical synchronous boost regulator.
LTC3789
14
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For more information www.linear.com/LTC3789
operaTion
The duty cycle of switch C decreases until the minimum
duty cycle of the converter reaches DMIN_BOOST, given by:
DMIN_BOOST =1
12
•100% =8.33%
Figure 5 shows typical boost region waveforms. If VIN
approaches VOUT, the buck-boost region is reached.
(4a) Buck-Boost Region (VIN ≥ VOUT)
(4b) Buck-Boost Region (VIN ≤ VOUT)
Figure 4. Buck-Boost Region
Light Load Current Operation
The LTC3789 can be enabled to enter pulse-skipping mode
or forced continuous conduction mode. To select forced
continuous operation, tie the MODE/PLLIN pin to a DC
voltage below 0.8V (e.g., SGND). To select pulse-skipping
mode of operation, tie the MODE/PLLIN pin to INTVCC.
When the LTC3789 enters pulse-skipping mode, in the
boost region, synchronous switch D is held off whenever
reverse current through switch A is detected. At very
light loads, the current comparator, ICMP , may remain
tripped for several cycles and force switch C to stay off
for the same number of cycles (i.e., skipping pulses). In
the buck region, the inductor current is not allowed to re-
verse. Synchronous switch B is held off whenever reverse
current on the inductor is detected. At very light loads,
the current comparator, ICMP , may remain untripped for
several cycles, holding switch A off for the same number
of cycles. Synchronous switch B also remains off for the
skipped cycles. In the buck-boost region, the controller
operates alternatively in boost and buck region in one
clock cycle, as in continuous operation. A small amount
of reverse current is allowed, to minimize ripple. For the
same reason, a narrow band of continuous buck and boost
operation is allowed on the high and low line ends of the
buck-boost region.
Output Overvoltage
If the output voltage is higher than the value commanded
by the VFB resistor divider, the LTC3789 will respond ac-
cording to the mode and region of operation. In continuous
conduction mode, the LTC3789 will sink current into the
input. If the input supply is capable of sinking current, the
LTC3789 will allow up to about 160mV/RSENSE to be sunk
into the input. In pulse-skipping mode and in the buck or
boost regions, switching will stop and the output will be
allowed to remain high. In pulse-skipping mode, and in the
buck/boost region as well as the narrow band of continu-
ous boost operation that adjoins it, current sunk into the
input through switchA is limited to approximately 40mV/
RDS(ON) of switch A. If this level is reached, switching will
stop and the output will rise. In pulse-skipping mode, and
in the narrow continuous buck region that adjoins the buck/
boost region, current sunk into the input through RSENSE
is limited to approximately 40mV/RSENSE.
Figure 5. Boost Region (VIN << VOUT)
SWITCH A
CLOCK
SWITCH B
SWITCH C
SWITCH D
IL
3789 F04a
SWITCH A
CLOCK
SWITCH B
SWITCH C
SWITCH D
IL3789 F04b
SWITCH A
CLOCK
SWITCH B
SWITCH C
SWITCH D
IL
0V
HIGH
3789 F05
LTC3789
15
3789fc
For more information www.linear.com/LTC3789
operaTion
Constant-Current Regulation
The LTC3789 provides a constant-current regulation loop
for either input or output current. A sensing resistor close
to the input or output capacitor will sense the input or
output current. When the current exceeds the programmed
current limit, the voltage on the ITH pin will be pulled down
to maintain the desired maximum input or output current.
The input current limit function prevents overloading the
DC input source, while the output current limit provides
a building block for battery charger or LED driver applica-
tions. It can also serve as an extra current limit protection
for a constant-voltage regulation application. The input/
output current limit function has an operating voltage range
of GND to the absolute maximum VOUT (VIN).
Frequency Selection and Phase-Locked Loop (FREQ
and MODE/PLLIN Pins)
The selection of switching frequency is a trade-off between
efficiency and component size. Low frequency opera-
tion increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage. The switching
frequency of the LTC3789’s controllers can be selected
using the FREQ pin. If the MODE/PLLIN pin is not being
driven by an external clock source, the FREQ pin can be
used to program the controller’s operating frequency from
200kHz to 600kHz.
Switching frequency is determined by the voltage on the
FREQ pin. Since there is a precision 10µA current flowing
out of the FREQ pin, the user can program the controller’s
switching frequency with a single resistor to SGND. A
curve is provided in the Applications Information section
to show the relationship between the voltage on the FREQ
pin and the switching frequency.
A phase-locked loop (PLL) is integrated on the LTC3789
to synchronize the internal oscillator to an external clock
source driving the MODE/PLLIN pin. The controller oper-
ates in forced continuous mode when it is synchronized.
The PLL filter network is integrated inside the LTC3789.
The PLL is capable of locking to any frequency within the
range of 200kHz to 600kHz. The frequency setting resis-
tor should always be present to set the controller’s initial
switching frequency before locking to the external clock.
Power Good (PGOOD) Pins
The PGOOD pin is connected to the open drain of an internal
N-channel MOSFET. When VFB is not within ±10% of the
0.8V reference voltage, the PGOOD pin is pulled low. The
PGOOD pin is also pulled low when RUN is below 1.22V
or when the LTC3789 is in the soft-start phase. There is
an internal 20µs power good or bad mask when VFB goes
in or out of the ±10% window. The PGOOD pin is allowed
to be pulled up by an external resistor to INTVCC or an
external source of up to 6V.
Short-Circuit Protection, Current Limit and Current
Limit Foldback
The maximum current threshold of the controller is limited
by a voltage clamp on the ITH pin. In every boost cycle,
the sensed maximum peak voltage is limited to 140mV.
In every buck cycle, the sensed maximum valley voltage
is limited to 90mV. In the buck-boost region, only peak
sensed voltage is limited by the same threshold as in
the boost region.
The LTC3789 includes current foldback to help limit load
current when the output is shorted to ground. If the out-
put falls below 50% of its nominal output level, then the
maximum sense voltage is progressively lowered from
its maximum value to one-third of the maximum value.
Foldback current limiting is disabled during the soft-start.
Under short-circuit conditions, the LTC3789 will limit the
current by operating as a buck with very low duty cycles,
and by skipping cycles. In this situation, synchronous
switch B will dissipate most of the power (but less than
in normal operation).
LTC3789
16
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For more information www.linear.com/LTC3789
applicaTions inForMaTion
The Typical Application on the first page is a basic
LTC3789 application circuit. External component selec-
tion is driven by the load requirement, and begins with
the selection of RSENSE and the inductor value. Next, the
power MOSFETs are selected. Finally, CIN and COUT are
selected. This circuit can be configured for operation up
to an input voltage of 38V.
RSENSE Selection and Maximum Output Current
RSENSE is chosen based on the required output current.
The current comparator threshold sets the peak of the
inductor current in the boost region and the maximum
inductor valley current in the buck region. In the boost
region, the maximum average load current at VIN(MIN) is:
IOUT(MAX,BOOST) =140mV
RSENSE
–∆IL
2
•VIN(MIN)
VOUT
where ∆IL is peak-to-peak inductor ripple current. In the
buck region, the maximum average load current is:
IOUT(MAX,BUCK) =90mV
R
SENSE
+
∆I
L
2
Figure 6 shows how ILOAD(MAX) • RSENSE varies with in-
put and output voltage.
The maximum current sensing RSENSE value for the boost
region is:
R
SENSE(MAX)
=
2•140mV •VIN(MIN)
2•IOUT(MAX,BOOST) •VOUT + ∆IL,BOOST •VIN(MIN)
The maximum current sensing RSENSE value for the buck
region is:
RSENSE(MAX) =
2•90mV
2•IOUT(MAX,BUCK) –∆IL,BUCK
The final RSENSE value should be lower than the calculated
RSENSE(MAX) in both the boost and buck regions. A 20%
to 30% margin is usually recommended.
Programming Input/Output Current Limit
As shown in Figures 7 and 8, input/output current sense
resistor RSENSE2 should be placed between the bulk capaci-
tor for VIN/VOUT and the decoupling capacitor. A lowpass
filter formed by RF and CF is recommended to reduce the
switching noise and stabilize the current loop. The input/
output current limit is set by the ILIM pin for 50mV, 100mV
or 140mV with ILIM pulled to the GND, floating, or tied to
INTVCC, respectively. If input/output current limit is not
desired, the IOSENSE+ and IOSENSE– pins should be shorted
to either VOUT or VIN.
Figure 6. Load Current vs VIN/VOUT
VIN/VOUT (V)
0.1
90
100
ILOAD(MAX) • RSENSE (mV)
110
120
130
140
160
1 10
3789 F06
150
Figure 7. Programming Output Current Limit
Figure 8. Programming Input Current Limit
LTC3789
FROM
CONTROLLER
VOUT
TO
SYSTEM
VOUT
IOSENSE–
RSENSE2
IOSENSE+
RF
100Ω RF
100Ω
CF
3789 F07
12
+
LTC3789
FROM DC
POWER INPUT TO DRAIN OF
SWITCH A
IOSENSE–
RSENSE2
IOSENSE+
RF
100Ω RF
100Ω
CF
3789 F08
12
+
LTC3789
17
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For more information www.linear.com/LTC3789
applicaTions inForMaTion
With the typical 100Ω resistors shown here, the value of
capacitor CF should be 1µF to 2.2µF. The current loop’s
transfer function should approximate that of the voltage
loop. Crossover frequency should be one-tenth the switch-
ing frequency, and gain should decrease by 20dB/decade.
Similar current and voltage loop transfer functions will
ensure overall system stability.
When the IOSENSE common mode voltage is above ~3.2V,
the IOSENSE– pin sources 10µA. The IOSENSE+ pin, however,
sources 18.3µA, 26.6µA and 35µA when the ILIM pin is
low, floating, and high, respectively, and when a constant
current is being regulated. The error introduced by this
mismatch can be offset to a first order by scaling the
IOSENSE+ and IOSENSE– resistors accordingly. For example,
if the IOSENSE+ branch has a 100Ω resistor, the 1.83mV
across it can be replicated in the IOSENSE– branch by using
a 182Ω resistor.
When the IOSENSE common mode voltage falls below ~3.2V
by a diode drop, the IOSENSE current decreases linearly; it
reaches approximately –300µA at zero volts. The values
of the diode drop and maximum current sinking can vary
by 20% to 30% due to process variation. Ensure that IO-
SENSE common mode voltage never exceeds its absolute
maximum of 0.3V below ground. Pay special attention to
short-circuit conditions in high power applications.
Slope Compensation
Slope compensation provides stability in constant-
frequency architectures by preventing subharmonic
oscillations at high duty cycles in boost operation and at
low duty cycles in buck operation. This is accomplished
internally by adding a compensating ramp to the inductor
current signal at duty cycles in excess of 40% in the boost
region, or subtracting a ramp from the inductor current
signal at lower than 40% duty cycles in the buck region.
Normally, this results in a reduction of maximum inductor
peak current for duty cycles >40% in the boost region, or
an increase of maximum inductor current for duty cycles
<40% in the buck region. However, the LTC3789 uses a
scheme that counteracts this compensating ramp, which
allows the maximum inductor current to remain unaffected
throughout all duty cycles.
Phase-Locked Loop and Frequency Synchronization
The LTC3789 has a phase-locked loop (PLL) comprised of
an internal voltage-controlled oscillator (VCO) and a phase
detector. This allows the turn-on of the top MOSFET of the
controller to be locked to the rising edge of an external
clock signal applied to the MODE/PLLIN pin. The phase
detector is an edge sensitive digital type that provides
zero degrees phase shift between the external and internal
oscillators. This type of phase detector does not exhibit
false locking to harmonics of the external clock.
The output of the phase detector is a pair of comple-
mentary current sources that charge or discharge the
internal filter network. There is a precision 10µA of cur-
rent flowing out of the FREQ pin. This allows a single
resistor to SGND to set the switching frequency when
no external clock is applied to the MODE/PLLIN pin. The
internal switch between FREQ and the integrated PLL filter
network is on, allowing the filter network to be at the same
voltage on the FREQ pin. Operating frequency is shown
in Figure 9 and specified in the Electrical Characteristics
table. If an external clock is detected on the MODE/PLLIN
pin, the internal switch previously mentioned will turn
off and isolate the influence of the FREQ pin. Note that
the LTC3789 can only be synchronized to an external
FREQ PIN VOLTAGE (V)
0
FREQUENCY (kHz)
0.5 1 1.5 2
3789 F09
2.5
0
100
300
400
500
700
200
600
Figure 9. Relationship Between Oscillator
Frequency and Voltage at the FREQ Pin
LTC3789
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applicaTions inForMaTion
clock whose frequency is within range of the LTC3789’s
internal VCO. This is guaranteed to be between 200kHz
and 600kHz. A simplified block diagram is shown in
Figure 10.
For a given ripple the inductance terms in continuous
mode are as follows:
LBOOST >VIN(MIN)
2
•(VOUT – VIN(MIN))•100
f•IOUT(MAX) •%Ripple •VOUT2H,
LBUCK >VOUT •VIN(MAX) – VOUT
( )
•100
f•IOUT(MAX) •%Ripple •VIN(MAX)
H
where:
f is operating frequency, Hz
% Ripple is allowable inductor current ripple
VIN(MIN) is minimum input voltage, V
VIN(MAX) is maximum input voltage, V
VOUT is output voltage, V
IOUT(MAX) is maximum output load current, A
For high efficiency, choose an inductor with low core
loss, such as ferrite. Also, the inductor should have low
DC resistance to reduce the I2R losses, and must be able
to handle the peak inductor current without saturating. To
minimize radiated noise, use a toroid, pot core or shielded
bobbin inductor.
CIN and COUT Selection
In the boost region, input current is continuous. In the
buck region, input current is discontinuous. In the buck
region, the selection of input capacitor CIN is driven by
the need to filter the input square wave current. Use a low
ESR capacitor sized to handle the maximum RMS current.
For buck operation, the input RMS current is given by:
IRMS ≈IOUT(MAX) •VOUT
VIN
•VIN
VOUT
– 1
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT(MAX)/2. This simple worst-case condition
is commonly used for design because even significant
deviations do not offer much relief. Note that ripple cur-
rent ratings from capacitor manufacturers are often based
on only 2000 hours of life which makes it advisable to
derate the capacitor.
DIGITAL
PHASE/
FREQUENCY
DETECTOR VCO
2.4V
10µA
5V
RSET
3789 F10
FREQ
SYNC
EXTERNAL
OSCILLATOR
MODE/
PLLIN
Figure 10. Phase-Locked Loop Block Diagram
If the external clock frequency is greater than the inter-
nal oscillator’s frequency, fOSC, then current is sourced
continuously from the phase detector output, pulling up
the filter network. When the external clock frequency is
less than fOSC, current is sunk continuously, pulling down
the filter network. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for the amount of time corresponding to
the phase difference. The voltage on the filter network is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the filter capacitor holds the voltage.
Typically, the external clock (on the MODE/PLLIN pin)
input high threshold is 1.6V, while the input low thresh-
old is 1V.
Inductor Selection
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. The inductor
value has a direct effect on ripple current. The inductor
current ripple ∆IL is typically set to 20% to 40% of the
maximum inductor current in the boost region at VIN(MIN).
LTC3789
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applicaTions inForMaTion
In the boost region, the discontinuous current shifts
from the input to the output, so COUT must be capable
of reducing the output voltage ripple. The effects of ESR
(equivalent series resistance) and the bulk capacitance
must be considered when choosing the right capacitor
for a given output ripple voltage. The steady ripple due to
charging and discharging the bulk capacitance is given by:
Ripple(Boost,Cap) =IOUT(MAX) •VOUT – VIN(MIN)
(
)
COUT •VOUT •fV
where COUT is the output filter capacitor.
The steady ripple due to the voltage drop across the ESR
is given by:
∆VBOOST,ESR = IOUT(MAX,BOOST) • ESR
In buck mode, VOUT ripple is given by:
∆VOUT ≤ ∆IL • (ESR + 1 / (8 • f • COUT)
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic
and ceramic capacitors are all available in surface mount
packages. Ceramic capacitors have excellent low ESR
characteristics but can have a high voltage coefficient.
Capacitors are now available with low ESR and high ripple
current ratings, such as OS-CON and POSCAP.
Power MOSFET Selection and
Efficiency Considerations
The LTC3789 requires four external N-channel power MOS-
FETs, two for the top switches (switches A and D, shown
in Figure 1) and two for the bottom switches (switches
B and C, shown in Figure 1). Important parameters for
the power MOSFETs are the breakdown voltage VBR,DSS,
threshold voltage VGS,TH, on-resistance RDS(ON), reverse
transfer capacitance CRSS and maximum current IDS(MAX).
The drive voltage is set by the 5.5V INTVCC supply. Con-
sequently, logic-level threshold MOSFETs must be used
in LTC3789 applications.
In order to select the power MOSFETs, the power dissipated
by the device must be known. For switch A, the maximum
power dissipation happens in the boost region, when it
remains on all the time. Its maximum power dissipation
at maximum output current is given by:
PA,BOOST =VOUT
VIN
•IOUT(MAX)
2
•ρt•RDS(ON)
where ρ
t
is a normalization factor (unity at 25°C) ac-
counting for the significant variation in on-resistance
with temperature, typically about 0.4%/°C, as shown in
Figure 11. For a maximum junction temperature of 125°C,
using a value ρ
t
= 1.5 is reasonable.
JUNCTION TEMPERATURE (°C)
–50
ρT NORMALIZED ON-RESISTANCE (Ω)
1.0
1.5
150
3789 F11
0.5
0050 100
2.0
Figure 11. Normalized RDS(ON) vs Temperature
Switch B operates in the buck region as the synchronous
rectifier. Its power dissipation at maximum output current
is given by:
P
B,BUCK =
V
IN
−V
OUT
V
IN
•IOUT(MAX)2•ρτ•RDS(ON)
Switch C operates in the boost region as the control switch.
Its power dissipation at maximum current is given by:
PC,BOOST =VOUT – VIN
( )
VOUT
VIN 2•IOUT(MAX)2•ρt
•RDS(ON) +k•VOUT 3•IOUT(MAX)
VIN
•CRSS •f
LTC3789
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where CRSS is usually specified by the MOSFET manufac-
turers. The constant k, which accounts for the loss caused
by reverse recovery current, is inversely proportional to
the gate drive current and has an empirical value of 1.7.
For switch D, the maximum power dissipation happens
in the boost region, when its duty cycle is higher than
50%. Its maximum power dissipation at maximum output
current is given by:
P
D,BOOST =VIN
VOUT
•VOUT
VIN
•IOUT(MAX)
2
•ρt•RDS(ON)
For the same output voltage and current, switch A has the
highest power dissipation and switch B has the lowest
power dissipation unless a short occurs at the output.
From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
formula:
TJ = TA + P • RTH(JA)
The RTH(JA) to be used in the equation normally includes
the RTH(JC) for the device plus the thermal resistance from
the case to the ambient temperature (RTH(JC)). This value
of TJ can then be compared to the original, assumed value
used in the iterative calculation process.
Schottky Diode (D1, D2) Selection
The Schottky diodes, D1 and D2, shown in Figure 13,
conduct during the dead time between the conduction
of the power MOSFET switches. They are intended to
prevent the body diode of synchronous switches B and D
from turning on and storing charge during the dead time.
In particular, D2 significantly reduces reverse recovery
current between switch D turn-off and switch C turn-on,
which improves converter efficiency and reduces switch
C voltage stress. In order for the diode to be effective, the
inductance between it and the synchronous switch must
be as small as possible, mandating that these components
be placed adjacently.
INTVCC Regulators and EXTVCC
The LTC3789 features a true PMOS LDO that supplies
power to INTVCC from the VIN supply. INTVCC powers the
gate drivers and much of the LTC3789’s internal circuitry.
The linear regulator regulates the voltage at the INTVCC pin
to 5.5V when VIN is greater than 6.5V. EXTVCC can supply
the needed power when its voltage is higher than 4.8V
through another on-chip PMOS LDO. Each of these can
supply a peak current of 100mA and must be bypassed to
ground with a minimum of 1µF ceramic capacitor or low
ESR electrolytic capacitor. No matter what type of bulk
capacitor is used, an additional 0.1µF ceramic capacitor
placed directly adjacent to the INTVCC and PGND pins is
highly recommended. Good bypassing is needed to supply
the high transient current required by the MOSFET gate
drivers and to prevent interaction between the channels.
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi-
mum junction temperature rating for the LTC3789 to be
exceeded. The INTVCC current, which is dominated by the
gate charge current, may be supplied by either the 5.5V
linear regulator from VIN or the 5.5V LDO from EXTVCC .
When the voltage on the EXTVCC pin is less than 4.5V, the
linear regulator from VIN is enabled. Power dissipation for
the IC in this case is highest and is equal to VIN • IINTVCC. The
gate charge current is dependent on operating frequency,
as discussed in the Efficiency Considerations section. The
junction temperature can be estimated by using the equa-
tions given in Note 3 of the Electrical Characteristics. For
example, the LTC3789 INTVCC current is limited to less
than 24mA from a 24V supply in the SSOP package and
not using the EXTVCC supply:
TJ = 70°C + (28mA)(24V)(80°C/W) = 125°C
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked while
operating in continuous conduction mode (MODE/PLLIN
= SGND) at maximum
VIN
. When the voltage applied to
EXTVCC
rises above 4.8V, the
INTVCC
linear regulator from
VIN
is turned off and the linear regulator from
EXTVCC
is
turned on and remains on as long as the voltage applied
to
EXTVCC
remains above 4.5V. Using
EXTVCC
allows the
MOSFET driver and control power to be derived from the
LTC3789’s switching regulator output during normal
operation and from the
VIN
when the output is out of
regulation (e.g., start-up, short-circuit). Do not apply
more than 14V to
EXTVCC
.
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Significant efficiency and thermal gains can be realized
by powering
EXTVCC
from the output, since the
VIN
cur-
rent resulting from the driver and control currents will be
scaled by a factor of (Duty Cycle)/(Switcher Efficiency).
Tying the
EXTVCC
pin to a 12V output reduces the junction
temperature in the previous example from 125°C to 97°C:
TJ = 70°C + (28mA)(12V)(80°C/W) = 97°C
Powering
EXTVCC
from the output can also provide
enough gate drive when
VIN
drops below 5V. This allows
a wider operating range for
VIN
after the controller start
into regulation.
The following list summarizes the three possible connec-
tions for EXTVCC:
1. EXTVCC left open (or grounded). This will cause INTVCC
to be powered from the internal 5.5V regulator at the
cost of a small efficiency penalty.
2. EXTVCC connected directly to VOUT (4.7V < VOUT < 14V).
This is the normal connection for the 5.5V regulator and
provides the highest efficiency.
3. EXTVCC connected to an external supply. If an external
supply is available in the 4.7V to 14V range, it may be
used to power EXTVCC provided it is compatible with
the MOSFET gate drive requirements.
Note that there is an internal body diode from INTVCC to
VIN. When INTVCC is powered from EXTVCC and VIN drops
lower than 4.5V, the diode will create a back-feeding path
from EXTVCC to VIN. To limit this back-feeding current, a
10Ω ~ 15Ω resistor is recommended between the system
VIN voltage and the chip VIN pin. To truly eliminate this
back-feeding current, a blocking Schottky diode should
be connected between the system VIN and the chip VIN.
Output Voltage
The LTC3789 output voltage is set by an external feed-
back resistive divider carefully placed across the output
capacitor. The resultant feedback signal is compared with
the internal precision 0.8V voltage reference by the error
amplifier. The output voltage is given by the equation:
VOUT =0.8V •1+
R2
R1
where R1 and R2 are defined in Figure 13.
Topside MOSFET Driver Supply (CA, DA, CB, DB)
Referring to Figure 13, the external bootstrap capacitors
CA and CB connected to the BOOST1 and BOOST2 pins
supply the gate drive voltage for the topside MOSFET
switches A and D. When the top switch A turns on, the
switch node SW1 rises to VIN and the BOOST1 pin rises
to approximately VIN + INTVCC. When the bottom switch
B turns on, the switch node SW1 drops to low and the
boost capacitor CA is charged through DA from INTVCC.
When the top switch D turns on, the switch node SW2
rises to VOUT and the BOOST2 pin rises to approximately
VOUT + INTVCC. When the bottom switch C turns on, the
switch node SW2 drops to low and the boost capacitor CB
is charged through DA from INTVCC. The boost capacitors
CA and CB need to store about 100 times the gate charge
required by the top switches A and D. In most applica-
tions, a 0.1µF to 0.47µF, X5R or X7R dielectric capacitor
is adequate.
Undervoltage Lockout
The LTC3789 has two functions that help protect the
controller in case of undervoltage conditions. A precision
UVLO comparator constantly monitors the INTVCC voltage
to ensure that an adequate gate-drive voltage is present.
It locks out the switching action when INTVCC is below
3.4V. To prevent oscillation when there is a disturbance
on the INTVCC, the UVLO comparator has 400mV of preci-
sion hysteresis.
Another way to detect an undervoltage condition is to moni-
tor the VIN supply. Because the RUN pin has a precision
turn-on reference of 1.22V, one can use a resistor divider
to VIN to turn on the IC when VIN is high enough. An extra
5µA of current flows out of the RUN pin once its voltage
passes 1.22V. One can program the hysteresis of the run
comparator by adjusting the values of the resistive divider.
LTC3789
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Soft-Start Function
When a capacitor is connected to the SS pin, a soft-start
current of 3µA starts to charge the capacitor. A soft-start
function is achieved by controlling the output ramp volt-
age according to the ramp rate on the SS pin. Current
foldback is disabled during this phase to ensure smooth
soft-start. When the chip is in the shutdown state with its
RUN pin voltage below 1.22V, the SS pin is actively pulled
to ground. The soft-start range is defined to be the voltage
range from 0V to 0.8V on the SS pin. The total soft-start
time can be calculated as:
tSOFTSTART =0.8 •
C
SS
3µA
Regardless of the mode selected by the MODE/PLLIN pin,
the regulator will always start in pulse-skipping mode up
to SS = 0.8V.
Fault Conditions: Current Limit and Current Foldback
The maximum inductor current is inherently limited in a
current mode controller by the maximum sense voltage. In
the boost region, maximum sense voltage and the sense
resistance determine the maximum allowed inductor peak
current, which is:
IL(MAX,BOOST) =
140mV
R
SENSE
In the buck region, maximum sense voltage and the sense
resistance determine the maximum allowed inductor valley
current, which is:
IL(MAX,BUCK) =
90mV
R
SENSE
To further limit current in the event of a short circuit to
ground, the LTC3789 includes foldback current limiting.
If the output falls by more than 50%, then the maximum
sense voltage is progressively lowered to about one-third
of its full value.
Efficiency Considerations
The percent efficiency of a switching regulator is equal
to the output power divided by the input power times
100%. It is often useful to analyze individual losses
to determine what is limiting the efficiency and which
change would produce the most improvement. Although
all dissipative elements in circuit produce losses, four
main sources account for most of the losses in LTC3789
circuits:
1. DC I2R losses. These arise from the resistances of the
MOSFETs, sensing resistor, inductor and PC board traces
and cause the efficiency to drop at high output currents.
2. MOSFET Transition loss. This loss arises from the
brief amount of time switch A or switch C spends in
the saturated region during switch node transitions. It
depends upon the input voltage, load current, driver
strength and MOSFET capacitance, among other factors.
3. INTVCC current. This is the sum of the MOSFET driver
and control currents. This loss can be reduced by sup-
plying INTVCC current through the EXTVCC pin from a
high efficiency source, such as the output (if 4.7V <
VOUT < 14V) or alternate supply if available.
4. CIN and COUT loss. The input capacitor has the difficult
job of filtering the large RMS input current to the regula-
tor in buck mode. The output capacitor has the more
difficult job of filtering the large RMS output current in
boost mode. Both CIN and COUT are required to have
low ESR to minimize the AC I2R loss and sufficient
capacitance to prevent the RMS current from causing
additional upstream losses in fuses or batteries.
5. Other losses. Schottky diodes D1 and D2 are responsible
for conduction losses during dead time and light load
conduction periods. Inductor core loss should also be
considered. Switch C causes reverse recovery current
loss in boost mode.
When making adjustments to improve efficiency, the input
current is the best indicator of changes in efficiency. If
one makes a change and the input current decreases, then
the efficiency has increased. If there is no change in input
current, then there is no change in efficiency.
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Design Example
VIN = 5V to 18V
VOUT = 12V
IOUT(MAX) = 5A
f = 400kHz
Maximum ambient temperature = 60°C
Set the frequency at 400kHz by applying 1.2V on the FREQ
pin (see Figure 7). The 10µA current flowing out of the
FREQ pin will give 1.2V across a 120k resistor to GND. The
inductance value is chosen first based on a 30% ripple cur-
rent assumption. In the buck region, the ripple current is:
∆IL,BUCK =VOUT
f•L•1– VOUT
VIN
IRIPPLE,BUCK =∆IL,BUCK •100
IOUT
%
The highest value of ripple current occurs at the maximum
input voltage. In the boost region, the ripple current is:
∆IL,BOOST =VIN
f•L•1– VIN
VOUT
IRIPPLE,BOOST =∆IL,BOOST •100
IIN
%
The highest value of ripple current occurs at VIN = VOUT/2.
A 6.8µH inductor will produce 11% ripple in the boost region
(VIN = 6V) and 29% ripple in the buck region (VIN = 18V).
The RSENSE resistor value can be calculated by using the
maximum current sense voltage specification with some
accommodation for tolerances.
R
SENSE =
2•140mV •V
IN(MIN)
2•IOUT(MAX,BOOST) •VOUT +∆IL,BOOST •VIN(MIN)
Select an RSENSE of 10mΩ.
Output voltage is 12V. Select R1 as 20k. R2 is:
R2 =
V
OUT
•R1
0.8
– R1
Select R2 as 280k. Both R1 and R2 should have a toler-
ance of no more than 1%.
Selecting MOSFET Switches
The MOSFETs are selected based on voltage rating and
RDS(ON) value. It is important to ensure that the part is
specified for operation with the available gate voltage am-
plitude. In this case, the amplitude is 5.5V and MOSFETs
with an RDS(ON) value specified at VGS = 4.5V can be used.
Select QA and QB.
With 18V maximum input voltage MOS-
FETs with a rating of at least 30V are used. As we do not yet
know the actual thermal resistance (circuit board design and
airflow have a major impact) we assume that the MOSFET
thermal resistance from junction to ambient is 50°C/W.
If we design for a maximum junction temperature, TJ(MAX)
= 125°C, the maximum RDS(ON) value can be calculated.
First, calculate the maximum power dissipation:
PD(MAX) =TJ(MAX) −TA(MAX)
R(j−a)
PD(MAX) =(125 −60)
50
=1.3W
The maximum dissipation in QA occurs at minimum input
voltage when the circuit operates in the boost region and
QA is on continuously. The input current is then:
V
OUT
•I
OUT(MAX)
VIN(MIN)
, OR 12A
We calculate a maximum value for RDS(ON):
RDS(ON) (125°C) <
P
D(MAX)
IIN(MAX) 2
RDS(ON) (125°C) <1.3W
(12A)2=0.009Ω
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The Vishay SiR422DP has a typical RDS(ON) of 0.010Ω at
TJ = 125°C and VGS = 4.5V.
The maximum dissipation in QB occurs at maximum input
voltage when the circuit is operating in the buck region.
The dissipation is:
P
B,BUCK =
V
IN
−V
OUT
VIN
•IOUT(MAX)2• ρt•RDS(ON)
R
DS(ON)(125°C) <1.3W
18V TO −12V
18V
•(5A)2=0.156Ω
This seems to indicate that a quite small MOSFET can be
used for QB if we only look at power loss. However, with
5A current the voltage drop across 0.156Ω is 0.78V, which
means the MOSFET body diode is conducting. To avoid
body diode current flow we should keep the maximum
voltage drop well below 0.5V, using, for example, Vishay
Si4840BDY in the SO-8 package (RDSON(MAX) = 0.012Ω).
Select QC and QD.
With 12V output voltage we need
MOSFETs with 20V or higher rating.
The highest dissipation occurs at minimum input voltage
when the inductor current is highest. For switch QC the
dissipation is:
PC,BOOST =
(V
OUT
−V
IN
)V
OUT
VIN 2
•IOUT(MAX)2• ρt•RDS(ON)
+k•VOUT 3•IOUT(MAX)
V
IN
•CRSS •f
where CRSS is usually specified by the MOSFET manufac-
turers. The constant k, which accounts for the loss caused
by reverse recovery current, is inversely proportional to
the gate drive current and has an empirical value of 1.7.
The dissipation in switch QD is:
PD,BOOST =VIN
VOUT
•VOUT
VIN
•IOUT(MAX)
2
•ρt•RDS(ON)
Vishay SiR484OY is a possible choice for QC and QD. The
calculated power loss at 5V input voltage is then 1.3W for
QC and 0.84W for QD.
CIN is chosen to filter the square current in the buck region.
In this mode, the maximum input current peak is:
IIN,PEAK(MAX,BUCK) =5A •1+
29%
2
=5.7A
A low ESR (10mΩ) capacitor is selected. Input voltage
ripple is 57mV (assuming ESR dominates the ripple).
COUT is chosen to filter the square current in the boost
region. In this mode, the maximum output current peak is:
IOUT,PEAK(MAX,BOOST) =
12
5•5•1+
11%
2
=10.6A
A low ESR (5mΩ) capacitor is suggested. This capacitor
will limit output voltage ripple to 53mV (assuming ESR
dominates the ripple).
PC Board Layout Checklist
The basic PC board layout requires a dedicated ground
plane layer. Also, for high current, a multilayer board
provides heat sinking for power components.
• The ground plane layer should not have any traces and
should be as close as possible to the layer with power
MOSFETs.
•
Place CIN, switch A, switch B and D1 in one com-
pact area. Place COUT, switch C, switch D and D2 in
one compact area. One layout example is shown in
Figure 12.
• Use immediate vias to connect the components (in-
cluding the LTC3789’s SGND and PGND pins) to the
ground plane. Use several large vias for each power
component.
LTC3789
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• Use planes for VIN and VOUT to maintain good voltage
filtering and to keep power losses low.
• Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of
power components. Connect the copper areas to any
DC net (VIN or GND). When laying out the printed circuit
board, the following checklist should be used to ensure
proper operation of the LTC3789. These items are also
illustrated in Figure 13.
• Segregate the signal and power grounds. All small-
signal components should return to the SGND pin at
one point, which is then tied to the PGND pin close to
the inductor current sense resistor RSENSE.
• Place switch B and switch C as close to the controller as
possible, keeping the PGND, BG and SW traces short.
• Keep the high dV/dT SW1, SW2, BOOST1, BOOST2,
TG1 and TG2 nodes away from sensitive small-signal
nodes.
• The path formed by switch A, switch B, D1 and the CIN
capacitor should have short leads and PC trace lengths.
The path formed by switch C, switch D, D2 and the
COUT capacitor also should have short leads and PC
trace lengths.
• The output capacitor (–) terminals should be connected
as closely as possible to the (–) terminals of the input
capacitor.
• Connect the top driver boost capacitor CA closely to the
BOOST1 and SW1 pins. Connect the top driver boost
capacitor CB closely to the BOOST2 and SW2 pins.
• Connect the input capacitors CIN and output capacitors
COUT closely to the power MOSFETs. These capacitors
carry the MOSFET AC current in the boost and buck
region.
• Connect VFB pin resistive dividers to the (+) terminals of
COUT and signal ground. A small VFB bypass capacitor
may be connected closely to the LTC3789 SGND pin.
The R2 connection should not be along the high current
or noise paths, such as the input capacitors.
• Route SENSE– and SENSE+ leads together with mini-
mum PC trace spacing. Avoid having sense lines pass
through noisy areas, such as switch nodes. The filter
capacitor between SENSE+ and SENSE– should be as
close as possible to the IC. Ensure accurate current
sensing with Kelvin connections at the sense resistor.
One layout example is shown in Figure 14.
• Connect the ITH pin compensation network closely to
the IC, between ITH and the signal ground pins. The
capacitor helps to filter the effects of PCB noise and
output voltage ripple voltage from the compensa-
tion loop.
• Connect the INTVCC bypass capacitor, CVCC, closely
to the IC, between the INTVCC and the power ground
pins. This capacitor carries the MOSFET drivers’ current
peaks. An additional 1µF ceramic capacitor placed im-
mediately next to the INTVCC and PGND pins can help
improve noise performance substantially.
applicaTions inForMaTion
GND
VOUT
COUT
L
RSENSE
3789 F12
QD
QCQB
QA
SW2 SW1
D1
D2
VIN
CIN
LTC3789
CKT
Figure 12. Switches Layout
LTC3789
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Figure 13. LTC3789 12V/5A, Buck-Boost Regulator
LTC3789
DA
DFLS160
DB
DFLS160
QA
SiR422DP
QB
SiR422DP
D1
B240A
CF 1µF
COUT
2.2µF
330µF
VOUT
12V, 5A
VOUT
VIN
VOUT
VIN
5V TO 38VMAX
CC1
3300pF
CC2
1000pF
CSS
6.8nF CIN
47µF
3789 F13
CA
0.22µF
VPULLUP
CB
0.22µF
QC
SiR422DP
L
6.8µH
QD
SiR422DP
CVCC 4.7µF
10mΩ
VFB
SS
SENSE+
SENSE–
ITH
SGND
MODE/PLLIN
FREQ
RUN
VINSNS
VOUTSNS
ILIM
VOUT
PGOOD SW1
TG1
BOOST1
PGND
BG1
VIN
INTVCC
EXTVCC
INTVCC
1
2
3
4
5
6
27
26
25
24
23
22
BG2
BOOST2
IOSENSE+
IOSENSE–
TG2
SW2
TRIM
7
8
9
10
11
12
13
14
21
20
19
18
17
16
15
1k
ON/OFF
RC
68k
121k
R1
20k R2
280k
D2
B240A
10mΩ
10Ω
1k
100Ω
100Ω
2.2µF
+
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SGND
PGND
RSENSE
C
RR
3789 F14
Figure 14. Sense Lines Layout
applicaTions inForMaTion
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GN Package
28-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.386 – .393*
(9.804 – 9.982)
GN28 (SSOP) 0204
1 2 345678 9 10 11 12
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
202122232425262728 19 18 17
13 14
1615
.016 – .050
(0.406 – 1.270)
.015 .004
(0.38 0.10) ¥ 45∞
0 – 8 TYP
.0075 – .0098
(0.19 – 0.25)
.0532 – .0688
(1.35 – 1.75)
.008 – .012
(0.203 – 0.305)
TYP
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
.033
(0.838)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 BSC.0165 .0015
.045 .005
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LTC3789
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package DescripTion
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
4.00 ± 0.10
(2 SIDES)
2.50 REF
5.00 ± 0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ±
0.10
27 28
1
2
BOTTOM VIEW—EXPOSED PAD
3.50 REF
0.75 ± 0.05 R = 0.115
TYP
R = 0.05
TYP
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UFD28) QFN 0506 REV B
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
0.25 ±0.05
0.50 BSC
2.50 REF
3.50 REF
4.10 ± 0.05
5.50 ± 0.05
2.65 ± 0.05
3.10 ± 0.05
4.50
± 0.05
PACKAGE OUTLINE
2.65 ± 0.10
3.65 ± 0.10
3.65 ± 0.05
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LTC3789
29
3789fc
For more information www.linear.com/LTC3789
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
A 9/11 Updated Features, Description and Typical Application. 1
Updated Electrical Characteristics section. 3
Updated text in MODE/PLLIN, BOOST1, BOOST2, SW1, SW2 in Pin Functions section. 9, 10
Updated text in Operation section. 12-15
Updated text in Applications Information section. 16-25
Updated Figure 13. 26
Updated Typical Application and Related Parts. 30
B 07/14 Updated Application Schematic
Updated Nominal Frequency Resistor
Updated VOUTSNS and VIN Sections
Updated LBOOST equation
1
4
9, 10
18
C 11/14 Added TG1, TG2 Absolute Maximum Ratings
Added Note 6
Replaced Figure 9
Added Text
2
4
17
21
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC3789
30
3789fc
For more information www.linear.com/LTC3789
relaTeD parTs
Typical applicaTion
PART NUMBER DESCRIPTION COMMENTS
LTC3780 High Efficiency (Up to 98%) Synchronous, 4-Switch Buck-Boost
DC/DC Controller 4V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 30V, 5mm × 5mm QFN-32 and
SSOP-24 Packages
LTC3785 High Efficiency (Up to 98%) Synchronous, 4-Switch Buck-Boost
DC/DC Controller 2.7V ≤ VIN ≤ 10V, 2.7V ≤ VOUT ≤ 10V, 4mm × 4mm
QFN-24 Package
LTM4605 High Efficiency Buck-Boost DC/DC µModule™ Regulator
Complete Power Supply 4.5V ≤ VIN ≤ 20V, 0.8V ≤ VOUT ≤ 16V, 15mm × 15mm × 2.8mm
LGA Package
LTM4607 High Efficiency Buck-Boost DC/DC µModule Regulator
Complete Power Supply 4.5V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 25V, 15mm × 15mm × 2.8mm
LGA Package
LTM4609 High Efficiency Buck-Boost DC/DC µModule Regulator
Complete Power Supply 4.5V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 34V, 15mm × 15mm × 2.8mm
LGA Package
LTC3112 2.5A Synchronous Buck-Boost DC/DC Converter 2.7V ≤ VIN ≤ 15V, 2.5V ≤ VOUT ≤ 14V, 4mm × 5mm DFN-16 and
TSSOP-20 Packages
LTC3533 2A Synchronous Buck-Boost Monolithic DC/DC Converter 1.8V ≤ VIN ≤ 5.5V, 1.8V ≤ VOUT ≤ 5.25V, IQ = 40µA,
ISD < 1µA, 3mm × 4mm DFN-14 Package
LTC3789EGN
D4
DFLS160
D7
DFLS160 3 1
D2
BAS16
Q2
SiR422DP
Q4
SiR422DP
D6
B240A
VOS+
VIN+
VOUT
VIN
D8
BZX84-
C5V1
C11, OPT
3789 TA02
INTVCC
Q5
SiR422DP
L1
5.5µH
Q3
SiR422DP
VFB
SS
SENSE1+
SENSE1–
ITH
SGND
MODE/PLLIN
FREQ
RUN
VINSNS
VOUTSNS
ILIM
PGOOD SW1
TG1
BOOST1
PGND1
BG1
VIN
INTVCC
EXTVCC
INTVCC
1
2
3
4
5
6
27
26
25
24
23
22
BG2
BOOST2
IOSENSE+
IOSENSE–
TG2
SW2
TRIM
7
8
9
10
11
12
13
14
21
20
19
18
17
16
15
R4, 100Ω
R3, 100Ω
R9, 1.24k
R10, 1.24k
RC, 15k
RFB2
8.06k
RFB1
232k R2
0.010Ω
2%
R5
10Ω, 0805
CC1, 1000pF
CC2, 0.01µF
R21
121k, 1%
R31
12.1k
0.01µF
R30
68.1k
C7, 0.1µF
C8, 0.1µF
R13, 100Ω
R14
100Ω
C10, 2.2µF
R11, 0Ω C4
0.22µF, 16V
C22
0.22µF, 16V
C18
10µF, 1206
R1, 5.6Ω
R18
8mΩ
2%
C1
2.2µF,
50V
X5R
COUT2
330µF
34V
C3
2.2µF
50V
X5R
R8
10Ω
C6
3.3µF
50V
1210
C15
1µF
50V
1210
CIN1
270µF
50V
OPT
CIN2
270µF
50V
VIN
9V TO
35V
VIN J3
D5
B240A
R7
100k
+
+
R25
0Ω
28
VOUT
VOUT
24V AT
5A
VOUT1
+
VOS+
J1
L1: WÜRTH 7443630550
24V/5A Buck-Boost Regulator
LINEAR TECHNOLOGY CORPORATION 2010
LT 1114 REV B • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC3789