© 2008 Microchip Technology Inc. DS21673G-page 1
24AA515/24LC515/24FC515
Device Selection Table
Features:
• Single Supply with Operation Down to 1.7V for
24AAXX Devices, 2.5V for 24LCXX Devices
• Low-Power CMOS Technology:
- Active current 500 uA, typical
- Standby current 100 nA, typical
• 2-Wire Serial Inte rfac e, I2C™ Compatible
• Cascadable up to Four Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slop e C o ntro l t o El im ina te Gro und Bounce
• 100 kHz and 400 kHz Clock Compatibility
• Page Write Time 5 ms max.
• Self-Timed Erase/Write Cycle
• 64-Byte Page Write Buffer
• Hardware Write Protect
• ESD Protection >4000V
• More than 1 Million Erase/Write Cycles
• Data Retention >200 years
• Factory Programming Available
• Packages Include 8-lead PDIP, SOIJ
• Pb-Free and RoHS Compliant
• Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E):-40°C to +125°C
Description:
The Microchip Technology Inc. 24AA515/24LC515/
24FC515 (24XX515*) is a 64K x 8 (512K bit) Serial
Electrically Erasable PROM, capable of operation
across a broad voltage range (1.7V to 5.5V). It has
been developed for advanced, low-power applications
such as personal communications or data acquisition.
This d evice has both byte write and pa ge w rite c ap abil-
ity of up to 64 bytes of data. This device is capable of
both random and sequential reads.
Reads may be sequential within address boundaries
0000h to 7FFFh and 8000h to FFFFh. Functional
address lines allow up to four devices on the same data
bus. This allows for up to 2 Mbits total system
EEPROM memory. This device is available in the
standard 8-pin plastic DIP and SOIJ packages.
Package Type
Block Diagram
Part
Number VCC
Range Max. Clock
Frequency Temp.
Ranges
24AA515 1.8-5.5V 400 kHz†I
24LC515 2.5-5.5V 400 kHz I
24FC515 2.5-5.5V 1 MHz I
†100 kHz for VCC < 2.5V.
A0
A1
A2
VSS
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
PDIP
SOIJ
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
HV Generator
EEPROM
Array
Page Latches
YDEC
XDEC
Sense AMP
R/W Control
Memory
Control
Logic
I/O
Control
Logic
I/O
A0A1
SDA
SCL
VCC
VSS
WP
512K I2C™ CMOS Serial EEPROM
*24XX515 is used in this document as a generic part number
for the 24AA515/24LC515/24FC515 devices.
24AA515/24LC515/24FC515
DS21673G-page 2 © 2008 Microchip Technology Inc.
1.0 ELECTRICAL CHARAC TERISTICS
Absolute Maximum Ratings(†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ............................................................................................................................... -65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins......................................................................................................................................................≥ 4kV
TABLE 1-1: DC CHARACTERISTICS
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device . This i s a stres s ratin g only and functio nal operati on of the devic e at thos e or any other co nditio ns abov e thos e
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
DC CHARACTERISTICS Industri al (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C
Param.
No. Sym. Characteristic Min. Max. Units Conditions
A0, A1, SCL, SDA and
WP pins:
D1 VIH High-level input voltage 0.7 VCC —V
D2 VIL Low-level input voltage — 0.3 VCC
0.2 VCC V
VVCC ≥ 2.5V
VCC < 2.5V
D3 VHYS Hysteresis of Schmitt
Trigger inputs
(SDA, SCL pins)
0.05 VCC —VVCC ≥ 2.5V (Note)
D4 VOL Low-level output voltage — 0.40 V IOL = 3.0 mA @ VCC = 4.5V
IOL = 2.1 mA @ VCC = 2.5V
D5 ILI Input leakage current — ±1 μAVIN = VSS or VCC, WP = VSS
VIN = VSS or VCC, WP = VCC
D6 ILO Output leaka ge curre nt — ±1 μAVOUT = VSS or VCC
D7 CIN,
COUT Pin capacitance
(all inputs/ou tpu t s) —10pFVCC = 5.0V (Note)
TA = 25°C, FCLK = 1 MHz
D8 ICC Read Operating current — 500 μAVCC = 5.5V, SCL = 400 kHz
ICC Write — 3 mA VCC = 5.5V
D9 Iccs Standby current — 5 μA SCL = SDA = VCC = 5.5V
A0, A1, WP = VSS, A2 = VCC
Note: This parameter is periodically sampled and not 100% tested.
© 2008 Microchip Technology Inc. DS21673G-page 3
24AA515/24LC515/24FC515
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C
Param.
No. Sym. Characteristic Min. Max. Units Conditions
1F
CLK Clock frequency —
—
—
100
400
1000
kHz 1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
2T
HIGH Clock high time 4000
600
500
—
—
—
ns 1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
3T
LOW Clock low time 4700
1300
500
—
—
—
ns 1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
4T
RSDA and SCL rise time
(Note 1) —
—
—
1000
300
300
ns 1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
5T
FSDA and SCL fall time
(Note 1) —
—300
100 ns All except, 24FC515
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
6T
HD:STA Start condition hold time 4000
600
250
—
—
—
ns 1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
7T
SU:STA Start condition setup time 4700
600
250
—
—
—
ns 1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
8T
HD:DAT Data input hold time 0 — ns (Note 2)
9T
SU:DAT Data input setup time 250
100
100
—
—
—
ns 1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
10 TSU:STO Stop condition setup time 4000
600
250
—
—
—
ns 1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
11 TSU:WP WP setup time 4000
600
600
—
—
—
ns 1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
12 THD:WP WP hold time 4700
1300
1300
—
—
—
ns 1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
13 TAA Output valid from clock
(Note 2) —
—
—
3500
900
400
ns 1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
14 TBUF Bus free time: Time the bus
must be free before a new
transmission can start
4700
1300
500
—
—
—
ns 1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
15 TOF Output fall ti me fr o m V IH
minimum to VIL maximum
CB ≤ 100 pF
10 + 0.1CB250
250 ns All except, 24FC515 (Note 1)
24FC515 (Note 1)
16 TSP Input filter spike suppression
(SDA and SCL pins) — 50 ns All except, 24FC515 (Notes 1 and 3)
17 TWC Write cycle time (byte or page) — 5 ms
18 Endurance 1 M — cycles 25°C (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of Start or S t op conditions.
3: The combined TSP and VHYS specifications are due to new S chmitt Trigger inputs which provide improved noise s pike
suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but established by characterization. For endurance estimates in a specific application,
please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com .
24AA515/24LC515/24FC515
DS21673G-page 4 © 2008 Microchip Technology Inc.
FIGURE 1-1: BUS TIMING DATA
(unprotected)
(protected)
SCL
SDA
IN
SDA
OUT
WP
5
7
6
16
3
2
89
13
D4 4
10
11 12
14
© 2008 Microchip Technology Inc. DS21673G-page 5
24AA515/24LC515/24FC515
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
2.1 A0, A1 Chip Address Inputs
The A0, A1 in puts are used b y the 24XX515 for multiple
device operations. The levels on these inputs are
compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
Up to four devices may be connected to the same bus
by usin g diffe rent Chip Select bit c ombinations . In most
applications, the chip address inputs A0 and A1 are
hard-wired to logic ‘0’ or logic ‘1’. For applications in
whic h t h es e pin s ar e c o nt ro ll ed b y a m ic rocont r ol l er o r
other programmable device, the chip address pins
must be driven to logic ‘0’ or logic ‘1’ before normal
device operation can proceed.
2.2 A2 Chip Address Input
The A2 input is non-configurable Chip Select. This pin
must be tied to VCC in order for this device to operate.
2.3 Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open-
drain terminal, therefore, the SDA bus requires a pull-
up resistor to VCC (typic al 10 kΩ for 100 kHz, 2 kΩ for
400kHz and 1MHz).
For norma l data trans fer SDA is all owed to change only
during SCL low. Changes during SCL high are
reserved for i ndicating the Start and Stop conditions .
2.4 Serial Clock (SCL)
This inpu t is used to sy nchronize the data tra nsfer from
and to the device.
2.5 Wr it e-Protect (WP)
This pin must be connected to either VSS or VCC. If tied
to VSS, write operations are enabled. If tied to VCC,
write operations are inhibited but read operations are
not affected.
3.0 FUNCTIONAL DESCRIP TION
The 24XX515 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data as a receiver. The bus must be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access, and
generates the Start and Stop conditions while the
24XX515 w o rks a s a s la ve. Bot h m as ter and s la ve ca n
operate as a transmitter or receiver, but the master
device determines which mode is activated.
Name PDIP SOIJ Function
A0 1 1 User Co nfi gurable Chip Select
A1 2 2 User Co nfi gurable Chip Select
A2 3 3 Non-Configurable Chip Select.
This pin must be hard wired to
logical 1 state (VCC). Device
will not operate with this pin
left floating or held to logical 0
(VSS).
VSS 4 4 Ground
SDA 5 5 Serial Data
SCL 6 6 Serial Clock
WP 7 7 Write-Protect In put
VCC 8 8 +1.7 to 5.5V (24AA515)
+2.5 to 5.5V (24LC515)
+2.5 to 5.5V (24FC515)
24AA515/24LC515/24FC515
DS21673G-page 6 © 2008 Microchip Technology Inc.
4.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stab le when ever th e clock lin e is high . Change s in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figur e 4 -1).
4.1 Bus Not Busy (A)
Both data and clock lines remain high.
4.2 Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3 S top Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must end with a Stop condition.
4.4 Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each dat a transf er is initiated w ith a S tart condition an d
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device.
4.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this Acknowledge
bit.
A device that acknowledges must pull down the SDA
line during the Acknowledge clock pulse in such a way
that the SD A line is sta ble low d uring the high pe riod of
the acknowledge related clock pulse. Of course, setup
and hold times must be taken into account. During
reads, a maste r mus t sign al an end of dat a to the sl ave
by NOT gene rating an Acknowl edge bit on the las t byte
that has been cl ocke d out o f the slave . In th is ca se , the
slave (24XX515) will leave the data line high to enable
the master to generate the Stop condition.
FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
FIGURE 4-2: ACKNOWLEDGE TIMING
Note: The 24XX515 does not generate any
Acknowledge bits if an internal program-
ming cycle is in progress, however, the
control byte that is being polled must
match the control byte used to initiate the
write cycle.
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
Start
Condition
SCL
SDA
(A) (B) (D) (D) (C) (A)
SCL 987654321123
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Receiver must release the SDA line at this
point so the Transmitter can continue
sending data.
Data from transmitter Data from transmitter
SDA
Acknowledge
Bit
© 2008 Microchip Technology Inc. DS21673G-page 7
24AA515/24LC515/24FC515
5.0 DEVICE ADDRESSING
A control byte is the first byte received following the
Start condition from the master device (Figure 5-1).
The con trol b yte c onsis ts of a 4-bit con trol c ode; fo r the
24XX515, thi s is set as ‘1010’ bina ry for read and write
operations. The next bit of the control byte is the block
select bit (B0). This bit acts as the A15 address bit for
accessing the entire array. The next two bits of the
control by te are the Chip Select bi ts (A1, A0). The Chip
Select bi ts allo w the use o f up to four 24XX5 15 device s
on the same bus and are used to select which device is
accessed. The Chip Select bits in the control byte must
corresp ond to the logi c le ve ls on the corre sp ond ing A1
and A0 p ins for th e devic e to resp ond. Thes e bits are in
effe ct the two Most Significant bits of the w ord addr ess.
The last bit of the control byte defines the operation to
be performed. When set to a ‘1’, a read operation is
selected, and when set to a ‘0’, a write operation is
selected. The next two bytes received define the
address of the first data byte (Figure 5-2). Because
only A14…A0 are used, the upper address bit is a
“don’t care.” The upper address bits are transferred
first, followed by the Less Significant bits.
Following the Start condition, the 24XX515 monitors
the SDA bus checking the device type identifier being
transmitted. Upon receiving a ‘1010’ code and appro-
priate device select bits, the slave device outputs an
Acknowledge signal on the SDA line . Depending on the
state of the R/W bit, the 24XX515 will select a read or
write operation.
This device has an internal addressing boundary
limit ation that is d ivided into tw o segments o f 256K bits.
Block select bit ‘B0’ is used in place of address bit
location ‘A15’ to control access to each segment.
FIGURE 5-1: CONTROL BYTE
FORMAT
5.1 Contiguous Addressing Across
Multiple Devices
The Chip Select b its A1, A0 can be used to exp and th e
contiguous address space for up to 2 Mbit by adding up
to four 24XX515’s on the same bus. In this case,
software can use A0 of the control byte as addr ess bi t
A16 and A1 as address bit A17. It is not possible to
sequentially read across device boundaries.
Each device has internal addressing boundary
limitations. This divides each part into two segments of
256K bits. The block select bit ‘B0’ controls access to
each “half” rather than address bit location A15.
Sequential read operations are limited to 256K blocks.
To read through four devices on the same bus, eight
random Read commands must be given.
FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS
1010B0 A1 A0SACKR/W
Control Code
Chip
Slave Address
Acknowledge Bit
Start Bit
Read/Write Bit
Select
Bits
Block
Select
Bit
1010B
0A
1A
0R/W xA
11 A
10 A
9A
7A
0
A
8••••••
A
12
Control Byte Address High Byte Address Low Byte
Control
Code Chip
Select
Bits X = “don’t care” bit
A
13
A
14
Block
Select
Bit
24AA515/24LC515/24FC515
DS21673G-page 8 © 2008 Microchip Technology Inc.
6.0 WRITE OPERATIONS
6.1 Byte Write
Following the Start condition from the master, the
control code (four bits), the block select (one bit) the
Chip Sele ct (two bit s), and the R /W bit (which is a l ogi c
low) are clocked onto the bus by the mast er transmitter .
This i n di ca tes t o th e ad d res se d s l av e re ce i ve r t ha t t he
address high byte will follow after it has generated an
Acknowledge bit during the ninth clock cycle. There-
fore, the next byte transmitted by the master is the
high-order byte of the word address and will be written
into the Add ress Pointer of the 24 XX515. The next by te
is the Least Significant Address Byte. After receiving
another Acknowledge signal from the 24XX515, the
master device will transmit the data word to be written
into the addressed memory location. The 24XX515
acknowledges again and the master generates a Stop
condition. This initiates the internal write cycle and
during this time, the 24XX515 will not generate
Acknowledge signals as long as the control byte being
polled matches the control byte th at was used to initiate
the write (Figure 6-1). If an attempt is made to write to
the array with the WP pin held high, the device will
acknowledge the command but no write cycle will
occur, no data will be written, and the device will
immed iately accept a ne w command. Af ter a byte Wri te
comma nd, the interna l addre ss co unter wil l point to the
address location followi ng the one that was jus t written.
6.2 Page Write
The writ e co ntro l by te, w ord add res s, and the first da t a
byte are transmitted to the 24XX515 in the same way
as in a byte write. But instead of generating a Stop
condition, the master transmits up to 63 additional
bytes, w hich are temporari ly stored in the on -chip pag e
buffer and will be written into memory after the master
has transmitted a Stop condition. After receipt of each
word, the six lower Address Pointer bits are internally
increm ented by o ne. If the master s hould trans mit more
than 6 4 bytes p rior to gen erating the S top cond ition, the
address counter will roll over and the previously
receive d dat a wil l be overwri tten. As with the by te writ e
operation, once the Stop condition is received, an
inter nal write cycl e will be gin (Fi gure 6-2). If a n attem pt
is mad e to wr ite to th e ar ray w ith t he W P pi n he ld hig h,
the device w ill ac kn owledge the c om m and but no wri te
cycle will occur, no data will be written, and the device
will immediately accept a new command.
6.3 Write Protection
The W P pin a llows th e user t o writ e-prote ct the entire
array (0 000-FFFF ) when the p in is tied to VCC. If tie d to
VSS the write protection is disabled. The WP pin is
sampled at the Stop bit for every Write command
(Figure 1-1) Toggling the WP pin after the Stop bit will
have no effect on the execution of the write cycle.
Note: Page write opera tions are l imited to wri ting
bytes within a single physical page,
regardless of the numb er o f by tes ac tua ll y
being written. Physical page boundaries
start at addresses that are integer
multiples of the page buffer size (or ‘page
size’) and end at addresses that are
integer multiples of [page size – 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being w ritte n to the next p a ge as mi ght be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
© 2008 Microchip Technology Inc. DS21673G-page 9
24AA515/24LC515/24FC515
FIGURE 6-1: BYTE WRITE
FIGURE 6-2: PAGE WRITE
x
Bus Activity
Master
SDA Line
Bus Activity
S
T
A
R
T
Control
Byte Address
High Byte Address
Low Byte Data
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
X = “don’t care” bit
S1010 0
B
0A
1A
0P
x
Bus Acti vity
Master
SDA Line
Bus Acti vity
S
T
A
R
T
Control
Byte Address
High Byte Address
Low Byte Data Byte 0
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
Data Byte 63
A
C
K
X = “don’t care” bit
S1010 0
B
0A
1A
0P
24AA515/24LC515/24FC515
DS21673G-page 10 © 2008 Microchip Technology Inc.
7.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete. (This feature can be used to maximize bus
throughput.) Once the Stop condition for a Write
comma nd has been is sued from the master , the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition, followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no AC K is retu rned, then the S t art b it and cont rol byte
must be resent. I f the cyc le is compl ete, then th e device
will return the ACK, and the master can then proceed
with the next Read or Write command. See Figure 7-1
for flow diagram.
FIGURE 7-1: ACKNOWLEDGE
POLLING FLOW
Note: Care must be taken when polling the
24LC515. The control byte that was used
to initiate the write needs to match the
control byte used for polling.
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
No
Yes
© 2008 Microchip Technology Inc. DS21673G-page 11
24AA515/24LC515/24FC515
8.0 READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
control byte is set to one. There are three basic types
of read operat ions: current address read , rand om rea d
and sequential read.
8.1 Current Address Read
The 24XX515 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address n (n is any legal address), the
next curren t addre ss read operati on would access da ta
from address n + 1.
Upon re ceipt of th e control b yte with R/ W bit set to on e,
the 24XX5 15 issu es an acknowle dge and transmit s the
8-bit data word. The master will not acknowledge the
transfer, but does generate a Stop condition and the
24XX515 discontinues transmission (Figure 8-1).
FIGURE 8-1: CURRENT ADDRESS
READ
8.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this typ e of re ad o peration, fi rst the w o rd ad dres s m us t
be set. This is done b y sending the word address to the
24XX515 as p art of a wr ite o peratio n (R/W bit se t to 0).
Aft er the word add res s is se nt, the master gen erates a
Start condition following the acknowledge. This termi-
nates the write operation, but not before the internal
Address Pointer is set. Then, the master issues the
control byte again, but with the R/W bit set to a one.
The 24XX515 will then issue an acknowledge and
transmit the 8-bit data word. The master will not
acknowledge the transfer, but does generate a Stop
condition which causes the 24XX515 to discontinue
transmission (Figure 8-2). After a random Read com-
mand, the internal address counter will point to the
address location following the one that was just read.
8.3 Sequentia l Read
Sequential reads are initiated in the same way as a
random read except that after the 24XX515 transmits
the first data byte, the master issues an acknowledge
as opposed to the Stop condition used in a random
read. This acknowledge directs the 24XX515 to trans-
mit the next sequentially addressed 8-bit word
(Figure 8-3). Following the final byte transmitted to the
master, the m aster w ill NOT generate an ackn owledg e,
but will generate a Stop condition. To provide sequen-
tial reads, the 24XX515 contains an internal Address
Pointer which is incremented by one at the completion
of each opera tio n. This Addr ess Poin ter allows half the
memory contents to be serially read during one opera-
tion. Sequ ential rea d a ddre ss bo und ari es are 000 0h to
7FFFh and 8000h to FFFFh. The internal Address
Pointer will automatic ally roll over from address 7FFF
to address 0000 if the master acknowledges the byte
received from the array address 7FFF. The internal
address counter will automatically roll over from
address FFFFh to address 8000h if the master
acknowledges the byte received from the array
address FFFFh.
Bus Acti vity
Master
SDA Line
Bus Acti vity
PS
S
T
O
P
Control
Byte
S
T
A
R
T
Data
A
C
K
N
O
A
C
K
1100
BAA1
Byte
010
24AA515/24LC515/24FC515
DS21673G-page 12 © 2008 Microchip Technology Inc.
FIGURE 8-2: RANDOM READ
FIGURE 8-3: SEQUENTIAL READ
x
Bus Acti vity
Master
SDA Line
Bus Acti vity A
C
K
N
O
A
C
K
A
C
K
A
C
K
A
C
K
S
T
O
P
S
T
A
R
T
Control
Byte Address
High Byte Address
Low Byte Control
Byte Data
Byte
S
T
A
R
T
X = “don’t care” bit
S1010BAA0
010 S1010BAA1
010 P
Bus Activity
Master
SDA Line
Bus Activity
Control
Byte Data n Data n + 1 Data n + 2 Data n + X
N
O
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
S
T
O
P
P
© 2008 Microchip Technology Inc. DS21673G-page 13
24AA515/24LC515/24FC515
9.0 PACKAGING INFORMATION
9.1 Package Marking Information
XXXXXXXX
T/XXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
*Standard marking consists of Microchip part number, year code, week code, traceability code (facility
code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please
check with your Microchip Sales Office.
24LC515
I/P 3L7
0517
8-Lead SOIJ (5.28 mm) Example:
XXXXXXXX
YYWWNNN
T/XXXXXX 24LC515
05173L7
I/SM
3
e
3
e
Legend: XX...X Part number or part number code
T Temperature (I, E)
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn)
Note: For very small packag es wit h no r oom for the Pb-free JED EC designator
, the marking will only appear on the outer carton or reel label.
Note: In the event the full Mi croch ip p art numb er ca nnot be mark ed on one l ine, it w ill
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
24AA515/24LC515/24FC515
DS21673G-page 14 © 2008 Microchip Technology Inc.
!"#$%&"' ()"&'"!&)&#*&&&#
+%&,&!&
- '!!#.#&"#'#%!&"!!#%!&"!!!&$#/!#
'!#&.0
1,21!'!&$& "!**&"&&!
3&'!&"&4#*!(!!&4%&&#&
&&255***''54
6&! 7,8.
'!9'&! 7 7: ;
7"')%! 7 <
& 1,
&& = =
##44!! -
1!&& = =
"#&"#>#& . - -
##4>#& . <
: 9& -< -?
&& 9 -
9#4!! <
69#>#& ) ?
9*9#>#& ) <
: *+ 1 = = -
N
E1
NOTE 1
D
123
A
A1
A2
L
b1
b
e
E
eB
c
* ,<1
© 2008 Microchip Technology Inc. DS21673G-page 15
24AA515/24LC515/24FC515
! ""#$%& !'
:@(@.5.@&##(%'#:,
+%&,&!&
- '!!#.#&"#'#%!&"!!#%!&"!!!&$#''!#
3&'!&"&4#*!(!!&4%&&#&
&&255***''54
6&! 99..
'!9'&! 7 7: ;
7"')%! 7 <
& 1,
: 8& = -
##44!! = <
&#%%+ =
: >#& . ? = <?
##4>#& . = -<
: 9& - = --
3&9& 9 = ?
3& IA = <A
9#4!! =
9#>#& ) -? =
#%& D= = A
#%&1&&' E= = A
φ
β
α
L
c
A2
A1
A
b
12
e
E
E1
N
D
* ,?1
24AA515/24LC515/24FC515
DS21673G-page 16 © 2008 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2008 Microchip Technology Inc. DS21673G-page 17
24AA515/24LC515/24FC515
APPENDIX A: REVISION HISTORY
Revision C
Corrections to Section 1.0, Electrical Characteristics.
Revision D
Removed Preli m inary status.
Revised conditions, Table 1-2, Param. 18.
Revision E
Revised Tables 1-1 and 2-1. Add Pb-free marking.
Revision F
Section 1.0 Electrical Characteristics: revised Ambient
Temperature; Revised Section 2.1 and Section 2.5
Revision G (07/2008)
Revised Features section; Revised 1.8V voltage to
1.7V; Replaced Package Drawings; Revised Product
ID System.
24AA515/24LC515/24FC515
DS21673G-page 18 © 2008 Microchip Technology Inc.
NOTES:
© 2008 Microchip Technology Inc. DS21673G-page 19
24AA515/24LC515/24FC515
THE MICROCHIP WEB SITE
Microc hip pro vides onl ine s upport v ia our W WW site at
www.microchi p.c om . Thi s web si te i s us ed as a m ean s
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
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application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
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•General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
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•Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
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Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specif ied produ ct family or develo pment tool of interes t.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.
CUSTOMER SUPP ORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Development Systems Information Line
Customers should contact their distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical s upport is a vailable through the web si te
at: http://support.microchip.com
24AA515/24LC515/24FC515
DS21673G-page 20 © 2008 Microchip Technology Inc.
READER RESP ONSE
It is ou r intentio n to provide you w it h th e b es t do cument ation po ss ib le to ensure suc c es sfu l u se of y ou r M ic roc hip prod-
uct. If you wi sh to prov ide you r comment s on org aniza tion, clar ity, subj ect matte r , and ways i n which o ur docum entatio n
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To: Technical Publications Manager
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Application (optional):
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Device: Literature Number:
Questions:
FAX: (______) _________ - _________
DS21673G24AA515/24LC515/24FC515
1. What are the best f eatures of this doc ument?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
© 2008 Microchip Technology Inc. DS21673G-page 21
24AA515/24LC515/24FC515
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX
PackageTemperature
Range
Device
Device: 24AA515: = 512K Bit 1.8V I2C CMOS Serial EEPROM
24AA515T: = 512K Bit 1.8V I2C CMOS Serial EEPROM
(Tape and Reel)
24LC515: = 512K Bit 2.5V I2C CMOS Serial EEPROM
24LC515T: = 512K Bit 2.5V I2C CMOS Serial EEPROM
(Tape and Reel)
24FC515: = 512K Bit 2.5V I2C CMOS Serial EEPROM
24FC515T: = 512K Bit 2.5V I2C CMOS Serial EEPROM
(Tape and Reel)
Temperature Range: I = -40°C to+85°C
Package: P = Plastic DIP (300 mil Bod y), 8-le ad
SM = Plastic SOIJ (5.28 mm Body), 8-lead
Examples:
a) 24AA515T-I/SM: Tape and Reel, Industrial
Temperature , SOIJ pac kage.
b) 24LC515-I/P: Industrial Temperature, PDIP
package.
c) 24LC515-I/SM: Industrial Temperature,
SOIJ package.
d) 24LC515T-I/SM: Tape and Reel, Industrial
Temperature , SOIJ pac kage.
24AA515/24LC515/24FC515
DS21673G-page 22 © 2008 Microchip Technology Inc.
NOTES:
© 2008 Microchip Technology Inc. DS21673G-page 23
Information contained in this publication regarding device
applications a nd the lik e is p ro vided on ly for yo ur con ve nien ce
and may be supers eded by updates . I t is you r r es ponsibil it y to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICST ART, PRO MA TE, rfPIC and SmartShunt are registered
trademarks of Microchip Te chnology Incorporat ed in the
U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEV AL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Prog ra m ming , IC SP, ICEPIC , Mi n d i , M iW i , MPASM , M P L A B
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
PICDEM.net, PICtail , PIC32 logo, PowerCal, PowerInfo,
PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology I ncorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2008, Microchip Technology Incorporated, Pr inted in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure famili es of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such act s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS21673G-page 24 © 2008 Microchip Technology Inc.
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