TPS43335-Q1
TPS43336-Q1
www.ti.com
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
LOW I
Q
, SINGLE BOOST, DUAL SYNCHRONOUS BUCK CONTROLLER
Check for Samples: TPS43335-Q1,TPS43336-Q1
1FEATURES
2• Qualified for Automotive Applications • Separate Enable Inputs (ENA, ENB)
• AEC-Q100 Test Guidance With the Following • Frequency Spread Spectrum (TPS43336-Q1)
Results: • Selectable Forced Continuous Mode or
– Device Temperature Grade 1: –40°C to Automatic Low-Power Mode at Light Loads
125°C Ambient Operating Temperature • Sense Resistor or Inductor DCR Sensing
– Device HBM ESD Classification Level H2 • Out-of-Phase Switching Between Buck
– Device CDM ESD Classification Level C2 Channels
• Two Synchronous Buck Controllers • Peak Gate-Drive Current 0.7 A
• One Pre-Boost Controller • Thermally Enhanced 38-Pin HTSSOP (DAP)
PowerPAD™ Package
• Input Range up to 40 V, (Transients up to 60
V), Operation Down to 2 V When Boost is APPLICATIONS
Enabled • Automotive Start-Stop, Infotainment,
• Low-Power-Mode IQ: 30 µA (One Buck On), Navigation Instrument Cluster Systems
35 µA (Two Bucks On) • Industrial and Automotive Multi-Rail DC Power
• Low Shutdown Current Ish < 4 µA Distribution Systems and Electronic Control
• Buck Output Range 0.9 V to 11 V Units
• Boost Output Selectable: 7 V, 10 V, or 11 V
• Programmable Frequency and External
Synchronization Range 150 kHz to 600 kHz
DESCRIPTION
The TPS43335-Q1 and TPS43336-Q1 include two current-mode synchronous buck controllers and a voltage-
mode boost controller. The devices are ideally suited as a pre-regulator stage with low Iq requirements and for
applications that must survive supply drops due to cranking events. The integrated boost controller allows the
devices to operate down to 2 V at the input without seeing a drop on the buck regulator output stages. At light
loads, one can enable the buck controllers to operate automatically in low-power mode, consuming just 30 µA of
quiescent current.
The buck controllers have independent soft-start capability and power-good indicators. Current foldback in the
buck controllers and cycle-by-cycle current limitation in the boost controller provide external MOSFET protection.
One can program the switching frequency over 150 kHz to 600 kHz or synchronize it to an external clock in the
same range. Additionally, the TPS43336-Q1 offers frequency-hopping spread-spectrum operation.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2011–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS43335-Q1
or
TPS43336-Q1
VBuckA
VBuckB
VBAT
2 V
VBAT
VBuckA
VBuckB
TPS43335-Q1
TPS43336-Q1
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
www.ti.com
Figure 1. Typical Application Diagram
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PACKAGE AND ORDERING INFORMATION
For the most-current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI Web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
2Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS43335-Q1 TPS43336-Q1
TPS43335-Q1
TPS43336-Q1
www.ti.com
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
space
ABSOLUTE MAXIMUM RATINGS(1)
MIN MAX UNIT
Voltage Input voltage: VIN, VBAT –0.3 60 V
Ground: PGNDA–AGND, PGNDB–AGND –0.3 0.3 V
Enable inputs: ENA, ENB –0.3 60 V
Bootstrap inputs: CBA, CBB –0.3 68 V
Bootstrap inputs: CBA–PHA, CBB–PHB –0.3 8.8 V
Phase inputs: PHA, PHB –0.7 60 V
Phase inputs: PHA, PHB (for 150 ns) –1 60 V
Feedback inputs: FBA, FBB –0.3 13 V
Voltage Error amplifier outputs: COMPA, COMPB –0.3 13 V
(buck function: High-side MOSFET driver: GA1–PHA, GB1–PHB –0.3 8.8 V
BuckA and BuckB) Low-side MOSFET drivers: GA2–PGNDA, GB2–PGNDB –0.3 8.8 V
Current-sense voltage: SA1, SA2, SB1, SB2 –0.3 13 V
Soft start: SSA, SSB –0.3 13 V
Power-good output: PGA, PGB –0.3 13 V
Power-good delay: DLYAB –0.3 13 V
Switching-frequency timing resistor: RT –0.3 13 V
SYNC, EXTSUP –0.3 13 V
Low-side MOSFET driver: GC1–PGNDA –0.3 8.8 V
Error-amplifier output: COMPC –0.3 13 V
Voltage Enable input: ENC –0.3 13 V
(boost function) Current-limit sense: DS –0.3 60 V
Output-voltage select: DIV –0.3 8.8 V
P-channel MOSFET driver: GC2 –0.3 60 V
Voltage
(PMOS driver) P-channel MOSFET driver: VIN–GC2 –0.3 8.8 V
Gate-driver supply: VREG –0.3 8.8 V
Junction temperature: TJ–40 150 °C
Temperature Operating temperature: TA–40 125 °C
Storage temperature: Tstg –55 165 °C
Human-body model (HBM) AEC-Q100 ±2 kV
Classification Level H2
FBA, FBB, RT, DLYAB ±400
Charged-device model (CDM) AEC-Q100
Electrostatic VBAT, ENC, SYNC, VIN ±750
Classification Level C2
discharge ratings All other pins ±500 V
PGA, PGB ±150
Machine model (MM) All other pins ±200
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to AGND, unless otherwise specified.
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: TPS43335-Q1 TPS43336-Q1
TPS43335-Q1
TPS43336-Q1
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
www.ti.com
THERMAL INFORMATION TPS4333x-Q1
THERMAL METRIC(1) DAP UNIT
38 PINS
θJA Junction-to-ambient thermal resistance(2) 27.3
θJCtop Junction-to-case (top) thermal resistance(3) 19.6
θJB Junction-to-board thermal resistance(4) 15.9 °C/W
ψJT Junction-to-top characterization parameter(5) 0.24
ψJB Junction-to-board characterization parameter(6) 6.6
θJCbot Junction-to-case (bottom) thermal resistance(7) 1.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT
Input voltage: VIN, VBAT 4 40
Enable inputs: ENA, ENB 0 40
Boot inputs: CBA, CBB 4 48
Buck function:
BuckA and BuckB Phase inputs: PHA, PHB –0.6 40 V
voltage Current-sense voltage: SA1, SA2, SB1, SB2 0 11
Power-good output: PGA, PGB 0 11
SYNC, EXTSUP 0 9
Enable input: ENC 0 9
Boost function Voltage sense: DS 40 V
DIV 0 VREG
Operating temperature: TA–40 125 °C
4Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS43335-Q1 TPS43336-Q1
TPS43335-Q1
TPS43336-Q1
www.ti.com
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
DC ELECTRICAL CHARACTERISTICS
VIN = 8 V to 18 V, TJ= –40°C to 150°C (unless otherwise noted)
NO. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
1.0 Input Supply
Boost controller enabled, after satisfying initial
1.1 VBAT Supply voltage 2 40 V
start-up condition
Input voltage required for device 6.5 40
on initial start-up
1.2 VIN V
Buck regulator operating range 4 40
after initial start-up
VIN falling. After a reset, initial start-up conditions 3.5 3.6 3.8 V
may apply.(1)
1.3 VIN(UV) Buck undervoltage lockout VIN rising. After a reset, initial start-up conditions 3.8 4 V
may apply.(1)
VBOOST_UNLOC
1.4 Boost unlock threshold VBAT rising 8.2 8.5 8.8 V
KVIN = 13 V, BuckA: LPM, BuckB: off, TA= 25°C 30 40 µA
LPM quiescent current:
1.5 Iq_LPM_ VIN = 13 V, BuckB: LPM, BuckA: off, TA= 25°C
(2)
VIN = 13 V, BuckA, B: LPM, TA= 25°C 35 45 µA
VIN = 13 V, BuckA: LPM, BuckB: off, TA= 125°C 40 50 µA
LPM quiescent current:
1.6 Iq_LPM VIN = 13 V, BuckB: LPM, BuckA: off, TA= 125°C
(2)
VIN = 13 V, BuckA, B: LPM, TA= 125°C 45 55 µA
SYNC = HIGH, TA= 25°C
VIN = 13 V, BuckA: CCM, BuckB: off, TA= 25°C 4.85 5.3
Quiescent current:
1.7 Iq_NRM mA
normal (PWM) mode(2) VIN = 13 V, BuckB: CCM, BuckA: off, TA= 25°C
VIN = 13 V, BuckA, B: CCM, TA= 25°C 7 7.6
SYNC = HIGH, TA= 125°C
VIN = 13 V, BuckA: CCM, BuckB: off, TA= 125°C 5 5.5
Quiescent current:
1.8 Iq_NRM mA
normal (PWM) mode(2) VIN = 13 V, BuckB: CCM, BuckA: off, TA= 125°C
VIN = 13 V, BuckA, B: CCM, TA= 125°C 7.5 8
1.9 Ibat_sh Shutdown current BuckA, B: off, VBAT = 13 V , TA= 25°C 2.5 4 µA
1.10 Ibat_sh Shutdown current BuckA, B: off, VBAT = 13 V, TA= 125°C 3 5 µA
2.0 Input Voltage VBAT - Undervoltage Lockout
VBAT falling. After a reset, initial start-up conditions 1.8 1.9 2 V
may apply.(1)
2.1 VBAT(UV) Boost-input undervoltage VBAT rising. After a reset, initial start-up conditions 2.4 2.5 2.6 V
may apply.(1)
2.2 UVLOHys Hysteresis 500 600 700 mV
2.3 UVLOfilter Filter time 5 µs
3.0 Input Voltage VIN - Overvoltage Lockout
VIN rising 45 46 47
3.1 VOVLO Overvoltage shutdown V
VIN falling 43 44 45
3.2 OVLOHys Hysteresis 1 2 3 V
3.3 OVLOfilter Filter time 5 µs
(1) If VBAT and VREG remain adequate, the buck can continue to operate if VIN is > 3.8 V.
(2) Quiescent current specification is non-switching current consumption without including the current in the external-feedback resistor
divider.
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: TPS43335-Q1 TPS43336-Q1
TPS43335-Q1
TPS43336-Q1
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
www.ti.com
DC ELECTRICAL CHARACTERISTICS (continued)
VIN = 8 V to 18 V, TJ= –40°C to 150°C (unless otherwise noted)
NO. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
4.0 Boost Controller
4.1 Vboost7V Boost VOUT = 7 V DIV = low, VBAT = 2 V to 7 V 6.8 7 7.3 V
Boost-enable threshold Boost VOUT = 7 V, VBAT falling 7.5 8 8.5
4.2 Vboost7V-th Boost-disable threshold Boost VOUT = 7 V, VBAT rising 8 8.5 9 V
Boost hysteresis Boost VOUT = 7 V, VBAT rising or falling 0.4 0.5 0.6
4.3 Vboost10V Boost VOUT = 10 V DIV = open, VBAT = 2 V to 10 V 9.7 10 10.4 V
Boost-enable threshold Boost VOUT = 10 V, VBAT falling 10.5 11 11.5
4.4 Vboost10V-th Boost-disable threshold Boost VOUT = 10 V, VBAT rising 11 11.5 12 V
Boost hysteresis Boost VOUT = 10 V, VBAT rising or falling 0.4 0.5 0.6
4.5 Vboost11V Boost VOUT = 11 V DIV = VREG, VBAT = 2 V to 11 V 10.7 11 11.4 V
Boost-enable threshold Boost VOUT = 11 V, VBAT falling 11.5 12 12.5
4.6 Vboost11V-th Boost-disable threshold Boost VOUT = 11 V, VBAT rising 12 12.5 13 V
Boost hysteresis Boost VOUT = 11 V, VBAT rising or falling 0.4 0.5 0.6
Boost-Switch Current Limit
4.7 VDS Current-limit sensing DS input with respect to PGNDA 0.175 0.2 0.225 V
4.8 tDS Leading-edge blanking 200 ns
Gate Driver for Boost Controller
4.9 IGC1 Peak Gate-driver peak current 1.5 A
4.10 rDS(on) Source and sink driver VREG = 5.8 V, IGC1 current = 200 mA 2 Ω
Gate Driver for PMOS
4.11 rDS(on) PMOS OFF 10 20 Ω
4.12 IPMOS_ON Gate current VIN = 13.5 V, VGS = –5 V 10 mA
4.13 tdelay_ON Turnon delay C = 10 nF 5 10 µs
Boost-Controller Switching Frequency
4.14 fsw-Boost Boost switching frequency fSW_Buck / 2 kHz
4.15 DBoost Boost duty cycle 90%
Error Amplifier (OTA) for Boost Converters
VBAT = 12 V 0.8 1.35
4.16 GmBOOST Forward transconductance mS
VBAT = 5 V 0.35 0.65
5.0 Buck Controllers
VBuckA or
5.1 Adjustable output-voltage range 0.9 11 V
VBuckB Measure FBX pin 0.792 0.800 0.808 V
Internal reference and tolerance
5.2 Vref, NRM voltage in normal mode –1% 1%
Measure FBX pin 0.784 0.800 0.816 V
Internal reference and tolerance
5.3 Vref, LPM voltage in low-power mode –2% 2%
V sense for forward-current limit in
5.4 FBx = 0.75 V (low duty cycle) 60 75 90 mV
CCM
Vsense V sense for reverse-current limit in
5.5 FBx = 1 V –65 –37.5 –23 mV
CCM
5.6 VI-Foldback V sense for output short FBx = 0 V 17 32.5 48 mV
5.7 tdead Shoot-through delay, blanking time 20 ns
High-side minimum on-time 100 ns
5.8 DCNRM Maximum duty cycle (digitally 98.75%
controlled)
5.9 DCLPM Duty cycle, LPM 80%
LPM entry-threshold load current
ILPM_Entry as fraction of maximum set load 1% .(3)
current
5.10 LPM exit-threshold load current as
ILPM_Exit fraction of maximum set load (3) 10%
current
(3) The exit threshold specification is to be always higher than the entry threshold.
6Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS43335-Q1 TPS43336-Q1
TPS43335-Q1
TPS43336-Q1
www.ti.com
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
DC ELECTRICAL CHARACTERISTICS (continued)
VIN = 8 V to 18 V, TJ= –40°C to 150°C (unless otherwise noted)
NO. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
High-Side External NMOS Gate Drivers for Buck Controller
5.11 IGX1_peak Gate-driver peak current 0.7 A
5.12 rDS(on) Source and sink driver VREG = 5.8 V, IGX1 current = 200 mA 4 Ω
Low-Side NMOS Gate Drivers for Buck Controller
5.13 IGX2_peak Gate driver peak current 0.7 A
5.14 RDS ON Source and sink driver VREG = 5.8 V, IGX2 current = 200 mA 4 Ω
Error Amplifier (OTA) for Buck Converters
COMPA, COMPB = 0.8 V,
5.15 GmBUCK Transconductance 0.72 1 1.35 mS
source/sink = 5 µA, test in feedback loop
5.16 IPULLUP_FBx Pullup current at FBx pins FBx = 0 V 50 100 200 nA
6.0 Digital Inputs: ENA, ENB, ENC, SYNC
6.1 VIH Higher threshold VIN = 13 V 1.7 V
6.2 VIL Lower threshold VIN = 13 V 0.7 V
6.3 RIH_SYNC Pulldown resistance on SYNC VSYNC = 5 V 500 kΩ
6.4 RIL_ENC Pulldown resistance on ENC VENC = 5 V 500 kΩ
Pullup current source on ENA,
6.5 IIL_ENx VENx = 0 V, 0.5 2 µA
ENB
7.0 Boost Output Voltage: DIV
7.1 VIH_DIV Higher threshold VREG = 5.8 V VREG – 0.2 V
7.2 VIL_DIV Lower threshold 0.2 V
7.3 Voz_DIV Voltage on DIV if unconnected Voltage on DIV if unconnected VREG / 2 V
8.0 Switching Parameter – Buck DC-DC Controllers
8.1 fSW_Buck Buck switching frequency RT pin: GND 360 400 440 kHz
8.2 fSW_Buck Buck switching frequency RT pin: 60-kΩexternal resistor 360 400 440 kHz
Buck adjustable range with
8.3 fSW_adj RT pin: external resistor 150 600 kHz
external resistor
8.4 fSYNC Buck synchronization range External clock input 150 600 kHz
8.5 fSS Spread-spectrum spreading TPS43336-Q1 only 5%
9.0 Internal Gate-Driver Supply
Internal regulated supply VIN = 8 V to 18 V, VEXTSUP = 0 V, SYNC = high 5.5 5.8 6.1 V
9.1 VREG IVREG = 0 mA to 100 mA, VEXTSUP = 0 V,
Load regulation 0.2% 1%
SYNC = high
Internal regulated supply VEXTSUP = 8.5 V 7.2 7.5 7.8 V
9.2 VREG(EXTSUP) IEXTSUP = 0 mA to 125 mA, SYNC = High
Load regulation 0.2% 1%
VEXTSUP = 8.5 V to 13 V
EXTSUP switch-over voltage IVREG = 0 mA to 100 mA,
9.3 VEXTSUP-th 4.4 4.6 4.8 V
threshold VEXTSUP ramping positive
9.4 VEXTSUP-Hys EXTSUP switch-over hysteresis 150 250 mV
9.5 IVREG-Limit Current limit on VREG VEXTSUP = 0 V, normal mode as well as LPM 100 400 mA
IVREG_EXTSUP- Current limit on VREG when using IVREG = 0 mA to 100 mA,
9.6 125 400 mA
Limit EXTSUP VEXTSUP = 8.5 V, SYNC = High
10.0 Soft Start
10.1 ISSx Soft-start source current VSSA and VSSB = 0 V 0.75 1 1.25 µA
11.0 Oscillator (RT)
11.1 VRT Oscillator reference voltage 1.2 V
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: TPS43335-Q1 TPS43336-Q1
TPS43335-Q1
TPS43336-Q1
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
www.ti.com
DC ELECTRICAL CHARACTERISTICS (continued)
VIN = 8 V to 18 V, TJ= –40°C to 150°C (unless otherwise noted)
NO. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
12.0 Power Good / Delay
12.1 PGpullup Pullup for A and B to Sx2 50 kΩ
12.2 PGth1 Power-good threshold FBx falling –5% –7% –9%
12.3 PGhys Hysteresis 2%
12.4 PGdrop Voltage drop IPGA = 5 mA 450 mV
12.5 IPGA = 1 mA 100 mV
12.6 PGleak Power-good leakage VSx2 = VPGx = 13 V 1 µA
12.7 tdeglitch Power-good deglitch time 2 16 µs
External capacitor = 1 nF
12.8 tdelay Reset delay 1 ms
VBuckX < PGth1
12.9 tdelay_fix Fixed reset delay No external capacitor, pin open 20 50 µs
Activate current source (current to
12.10 IOH 30 40 50 µA
charge external capacitor)
Activate current sink (current to
12.11 IIL 30 40 50 µA
discharge external capacitor)
13.0 Overtemperature Protection
Junction-temperature shutdown
13.1 Tshutdown 150 165 °C
threshold
13.2 Thys Junction-temperature hysteresis 15 °C
8Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS43335-Q1 TPS43336-Q1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19 20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
VBAT
DS
GC1
GC2
CBA
GA1
PHA
GA2
PGNDA
SA1
SA2
FBA
COMPA
SSA
PGA
ENA
ENB
COMPC
ENC SYNC
DLYAB
RT
AGND
PGB
SSB
COMPB
FBB
SB2
SB1
PGNDB
GB2
PHB
GB1
CBB
VREG
DIV
EXTSUP
VIN
TPS43335-Q1
TPS43336-Q1
www.ti.com
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
DEVICE INFORMATION
DAP PACKAGE
(TOP VIEW)
PIN FUNCTIONS
NAME NO. I/O DESCRIPTION
AGND 23 O Analog ground reference
A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck
CBA 5 I controller BuckA. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the
high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge.
A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck
CBB 34 I controller BuckB. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the
high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge.
Error amplifier output of BuckA and compensation node for voltage-loop stability. The voltage at this node sets the
COMPA 13 O target for the peak current through the inductor of BuckA. Clamping his voltage on the upper and lower ends
provides current-limit protection for the external MOSFETs.
Error amplifier output of BuckB and compensation node for voltage-loop stability. The voltage at this node sets the
COMPB 26 O target for the peak current through the inductor of BuckB. Clamping his voltage on the upper and lower ends
provides current-limit protection for the external MOSFETs.
COMPC 18 O Error-amplifier output and loop-compensation node of the boost regulator
The status of this pin defines the output voltage of the boost regulator. A high input regulates the boost converter
DIV 36 I at 11 V, a low input sets the value at 7 V, and a floating pin sets 10 V. NOTE: DIV = high and ENC = high inhibits
low-power mode on the bucks.
The capacitor at the DLYAB pin sets the power-good delay interval used to de-glitch the outputs of the power-
DLYAB 21 O good comparators. Leaving this pin open sets the power-good delay to an internal default value of 20 µs typical.
This input monitors the voltage on the external boost-converter low-side MOSFET for overcurrent protection. An
DS 2 I alternative connection for better noise immunity is to place a sense resistor between the source of the low-side
MOSFET and ground via a filter network.
Enable input for BuckA (active-high with an internal pullup current source). An input voltage higher than 1.7 V
enables the controller, whereas an input voltage lower than 1.7 V disables the controller. When both ENA and
ENA 16 I ENB are low, the device shuts down and consumes less than 4 µA of current. NOTE: DIV = high and ENC = high
inhibits low-power mode on the bucks.
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: TPS43335-Q1 TPS43336-Q1
TPS43335-Q1
TPS43336-Q1
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
www.ti.com
PIN FUNCTIONS (continued)
NAME NO. I/O DESCRIPTION
Enable input for BuckB (active-high with an internal pullup current source). An input voltage higher than 1.7 V
enables the controller, whereas an input voltage lower than 1.7 V disables the controller. When both ENA and
ENB 17 I ENB are low, the device shuts down and consumes less than 4 µA of current. NOTE: DIV = high and ENC = high
inhibits low-power mode on the bucks.
This input enables and disables the boost regulator. An input voltage higher than 1.7 V enables the controller.
Voltages lower than 0.7 V disable the controller. Because this pin provides an internal pulldown resistor (500 kΩ),
ENC 19 I enabling the boost function requires pulling it high. When enabled, the controller starts switching as soon as VBAT
falls below the boost threshold, depending on the programmed output voltage.
One can use EXTSUP to supply the VREG regulator from one of the TPS43335-Q1 or TPS43336-Q1 buck
EXTSUP 37 I regulator rails to reduce power dissipation in cases where there is an expectation of high VIN. If EXTSUP is
unused, leave the pin open without a capacitor installed.
Feedback voltage pin for BuckA. The buck controller regulates the feedback voltage to the internal reference of
FBA 12 I 0.8 V. A suitable resistor divider network between the buck output and the feedback pin sets the desired output
voltage.
Feedback voltage pin for BuckB. The buck controller regulates the feedback voltage to the internal reference of
FBB 27 I 0.8 V. A suitable resistor-divider network between the buck output and the feedback pin sets the desired output
voltage.
This output can drive the external high-side N-channel MOSFET for buck regulator BuckA. The output provides
GA1 6 O high peak currents to drive capacitive loads. The gate drive reference is to a floating ground provided by PHA that
has a voltage swing provided by CBA.
This output can drive the external low-side N-channel MOSFET for buck regulator BuckA. The output provides
GA2 8 O high peak currents to drive capacitive loads. VREG provides the voltage swing on this pin.
This output can drive the external high-side N-channel MOSFET for buck regulator BuckB. The output provides
GB1 33 O high peak currents to drive capacitive loads. The gate drive reference is to a floating ground provided by PHB that
has a voltage swing provided by CBB.
This output can drive the external low-side N-channel MOSFET for buck regulator BuckB. The output provides
GB2 31 O high peak currents to drive capacitive loads. VREG provides the voltage swing on this pin.
This output can drive an external low-side N-channel MOSFET for the boost regulator. This output provides high
GC1 3 O peak currents to drive capacitive loads. VREG provides the voltage swing on this pin.
This pin makes a floating output drive available to control the external P-channel MOSFET. This MOSFET can
GC2 4 O bypass the boost rectifier diode or a reverse-protection diode when the boost is not switching or if boost is
disabled, and thus reduce power losses.
Open-drain power-good indicator pin for BuckA. An internal power-good comparator monitors the voltage at the
PGA 15 O feedback pin and pulls this output low when the output voltage falls below 93% of the set value, or if either VIN or
VBAT drops below its respective undervoltage threshold.
Open-drain power-good indicator pin for BuckB. An internal power-good comparator monitors the voltage at the
PGB 24 O feedback pin and pulls this output low when the output voltage falls below 93% of the set value, or if either VIN or
VBAT drops below its respective undervoltage threshold.
PGNDA 9 O Power ground connection to the source of the low-side N-channel MOSFET of BuckA
PGNDB 30 O Power ground connection to the source of the low-side N-channel MOSFET of BuckB
Switching terminal of buck regulator BuckA, providing a floating ground reference for the high-side MOSFET gate-
PHA 7 O driver circuitry and used to sense current reversal in the inductor when discontinuous-mode operation is desired.
Switching terminal of buck regulator BuckB, providing a floating ground reference for the high-side MOSFET gate-
PHB 32 O driver circuitry and used to sense current reversal in the inductor when discontinuous-mode operation is desired.
Connecting a resistor to ground on this pin sets the operational switching frequency of the buck and boost
RT 22 O controllers. A short circuit to ground on this pin defaults operation to 400 kHz for the buck controllers and 200 kHz
for the boost controller.
SA1 10 I High-impedance differential-voltage inputs from the current-sense element (sense resistor or inductor DCR) for
each buck controller. Choose the current-sense element to set the maximum current through the inductor based
on the current-limit threshold (subject to tolerances) and considering the typical characteristics across duty cycle
SA2 11 I and VIN. (SA1 positive node, SA2 negative node).
SB1 29 I High-impedance differential voltage inputs from the current-sense element (sense resistor or inductor DCR) for
each buck controller. Choose the current-sense element to set the maximum current through the inductor based
on the current-limit threshold (subject to tolerances) and considering the typical characteristics across duty cycle
SB2 28 I and VIN. (SB1 positive node, SB2 negative node).
Soft-start or tracking input for buck controller BuckA. The buck controller regulates the FBA voltage to the lower of
0.8 V or the SSA pin voltage. An internal pullup current source of 1 µA is present at the pin, and an appropriate
SSA 14 O capacitor connected here sets the soft-start ramp interval. Alternatively, a resistor divider connected to another
supply can provide a tracking input to this pin.
10 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS43335-Q1 TPS43336-Q1
TPS43335-Q1
TPS43336-Q1
www.ti.com
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
PIN FUNCTIONS (continued)
NAME NO. I/O DESCRIPTION
Soft-start or tracking input for buck controller BuckB. The buck controller regulates the FBB voltage to the lower of
0.8 V or the SSB pin voltage. An internal pullup current source of 1 µA is present at the pin, and an appropriate
SSB 25 O capacitor connected here sets the soft-start ramp interval. Alternatively, a resistor divider connected to another
supply can provide a tracking input to this pin.
If an external clock is present on this pin, the device detects it and the internal PLL locks onto the external clock,
thus overriding the internal oscillator frequency. The device can synchronize to frequencies from 150 kHz to 600
kHz. A high logic level on this pin ensures forced continuous-mode operation of the buck controllers and inhibits
SYNC 20 I transition to low-power mode. An open or low allows discontinuous-mode operation and entry into low-power
mode at light loads. On the TPS43336-Q1, a high level enables frequency-hopping spread spectrum, whereas an
open or a low level disables it.
Battery input sense for the boost controller. If, with the boost controller enabled, the voltage at VBAT falls below
VBAT 1 I the boost threshold, the device activates the boost controller and regulates the voltage at VIN to the programmed
boost output voltage.
Main input pin. This is the buck controller input pin as well as the output of the boost regulator. Additionally, VIN
VIN 38 I powers the internal control circuits of the device.
The device requires an external capacitor on this pin to provide a regulated supply for the gate drivers of the buck
VREG 35 O and boost controllers. TI recommends capacitance on the order of 4.7 µF. The regulator obtains its power from
either VIN or EXTSUP. This pin has current-limit protection; do not use it to drive any other loads.
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: TPS43335-Q1 TPS43336-Q1
VIN 38 Internal ref
(Band gap)
37
EXTSUP
Gate Driver
Supply
35
VREG 35
RT 22
SYNC 20
4
Internal
Oscillator
SYNC and
LPM
180 deg
Source
and
Sink
Logic
GC2
ENC
18
23
14
SSA
1 µA
VIN
500 nA
ENA
16
ENA
25
SSB
1 µA
ENB
17
VIN
500 nA
ENB
COMPC
1
36
VBAT
DIV
Gm
2
DS OCP
0.2 V
3
GC1
19
ENC
AGND
PWM
Logic
Duplicate for second
Buck controller channel
VREG
5CBA
6GA1
7PHA
8GA2
9PGNDA
Slope
Comp Current sense
Amp
PWM
comp
OTA
10 SA1
12
FBA
11 SA2
SSA
15
PGA
FBA
Filter timer
SA2
21
DLYAB
40 µA
40 µA
21
DLYAB
34
33
32
31
30
29
28
27
26
24
CBB
GB1
PHB
GB2
PGNDB
SB1
SB2
FBB
COMPB
PGB
Second
Buck
Controller
Channel
13
COMPA
0.8 V
OTA
VIN
VboostxV Gm
Vboost7V-th
Vboost10V-th
Vboost11V-th
MUX
VREG
PGNDA
Ramp
PWM
comp
PWM
Logic
TPS43335-Q1
TPS43336-Q1
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
www.ti.com
Figure 2. Functional Block Diagram
12 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS43335-Q1 TPS43336-Q1
50 µs/DIV
V AC-COUPLED
OUT
100 mV/DIV
IIND
2 A/DIV
V = 12 V, V = 5 V, SWITCHING FREQUENCY = 400 kHz
INDUCTOR = 4.7 µH, R = 10 m
IN OUT
SENSE W
V = 12 V, V = 5 V, SWITCHING FREQUENCY = 400 kHz
INDUCTOR = 4.7 µH, R = 10 m
IN OUT
SENSE W
50 µs/DIV
V AC-COUPLED
OUT
100 mV/DIV
IIND
2 A/DIV
50 µs/DIV
V AC-COUPLED
OUT
IIND
2 A/DIV
100 mV/DIV
V = 12 V, V = 5 V, SWITCHING FREQUENCY = 400 kHz
INDUCTOR = 4.7 µH, R = 10 m
IN OUT
SENSE W
2 ms/DIV
VOUTA
VOUTB
1 V/DIV
OUTPUT CURRENT (A)
EFFICIENCY (%)
POWER LOSS (mW)
EFFICIENCY,
SYNC = LOW
POWER LOSS,
SYNC = HIGH
POWER LOSS,
SYNC = LOW
EFFICIENCY,
SYNC = HIGH
V = 12 V, V = 5 V, SWITCHING FREQUENCY = 400 kHz
INDUCTOR = 4.7 µH, R = 10 m
IN OUT
SENSE W
0.0001 0.001 0.01 0.1 110
0
10
20
30
40
50
60
70
80
90
100
0.1
1
10
100
1000
10000
2 µs/DIV
FORCED CONTINUOUS MODE (SYNC = 1), 200-mA LOAD
DISCONTINUOUS MODE (SYNC = 0), 200-mA LOAD
LOW-POWER MODE (SYNC = 0), 20-mA LOAD
V = 12 V, V = 5 V, SWITCHING FREQUENCY = 400 kHz
INDUCTOR = 4.7 µH, R = 10 m
IN OUT
SENSE W
1 A/DIV
1 A/DIV
1 A/DIV
TPS43335-Q1
TPS43336-Q1
www.ti.com
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
TYPICAL CHARACTERISTICS
EFFICIENCY ACROSS OUTPUT CURRENTS (BUCKS) INDUCTOR CURRENTS (BUCK)
Figure 3. Figure 4.
BUCK LOAD STEP: FORCED CONTINUOUS MODE
(0 TO 4 A AT 2.5 A/µs) SOFT-START OUTPUTS (BUCK)
Figure 5. Figure 6.
BUCK LOAD STEP: LOW-POWER-MODE ENTRY BUCK LOAD STEP: LOW-POWER-MODE EXIT
(4 A TO 90 mA AT 2.5 A/µs) (90 mA TO 4 A AT 2.5 A/µs)
Figure 7. Figure 8.
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: TPS43335-Q1 TPS43336-Q1
V (BOOST INPUT) = 5 V, V (BOOST OUTPUT) = 10 V,
SWITCHING FREQUENCY = 200 kHz, INDUCTOR = 1 µH,
R = 7.5 m , C = 440 µF, C = 660 µF
BAT IN
SENSE IN OUT
W
2 µs/DIV
3-A LOAD
5 A/DIV
100-mA LOAD
5 A/DIV
0 A
0 V
20 ms/DIV
V (BOOST INPUT)
BAT
5 V/DIV
V (BOOST OUTPUT)
IN
5 V/DIV
IIND
10 A/DIV
V (BOOST OUTPUT) = 10 V, BuckA = 5 V AT 1.5 A,
BuckB = 3.3V AT 3.5A, SWITCHING FREQUENCY = 200 kHz,
INDUCTOR = 1 µH, R = 7.5 m , C = 440 µF, C = 660 µF
IN
SENSE IN
WOUT
0V
0 A
0 V
20 ms/DIV
V (BOOST INPUT)
BAT
5 V/DIV
V BuckA AC-COUPLED
OUT
200 mV/DIV
V BuckB AC-COUPLED
OUT
200 mV/DIV
IIND
10 A/DIV
V (BOOST OUTPUT) = 10 V, BuckA = 5 V AT 1.5 A,
BuckB = 3.3 V AT 3.5 A, SWITCHING FREQUENCY = 200 kHz,
INDUCTOR = 1 µH, R = 7.5 m , C = 440 µF, C = 660 µF
IN
SENSE IN OUT
W
Output Current (A)
Efficiency (%)
V (BOOST OUTPUT) = 10 V, SWITCHING FREQUENCY = 200 kHz,
INDUCTOR = 1 µH, R = 7.5 m
IN
SENSE W
0.01 110
0
10
20
30
40
50
60
70
80
90
100
V = 8 V
BAT
V = 5 V
BAT
V = 3 V
BAT
VBAT (BOOST INPUT) = 5 V, VIN (BOOST OUTPUT) = 10 V,
SWITCHING FREQUENCY = 200 KHz, INDUCTOR = 680 nH,
RSENSE = 10 m, CIN = 440 F, COUT = 660 F
TPS43335-Q1
TPS43336-Q1
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
www.ti.com
TYPICAL CHARACTERISTICS (continued)
LOAD STEP RESPONSE (BOOST)
EFFICIENCY ACROSS OUTPUT CURRENTS (BOOST) (0 TO 5 A AT 10 A/µs)
Figure 9. Figure 10.
CRANKING PULSE BOOST RESPONSE CRANKING PULSE BOOST RESPONSE
(12 V TO 3 V IN 1 ms AT BUCK OUTPUTS 7.5 W / 11.5 W) (12 V TO 4 V IN 1 ms AT BOOST DIRECT OUTPUT 25 W)
Figure 11. Figure 12.
INDUCTOR CURRENTS (BOOST)
Figure 13.
14 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS43335-Q1 TPS43336-Q1
Temperature (°C)
Regulated FBx Voltage (mV)
–40 –15 10 35 60 85 110 135 160
795
796
797
798
799
800
801
802
803
804
805
Duty Cycle (%)
Peak Current Sense Voltage (mV)
0
10
20
30
40
50
60
70
80
0 10 20 30 40 50 60 70 80 90 100
V = 8 V
IN
V = 12 V
IN
FBx Voltage (V)
Peak Current Sense Voltage (mV)
0 0.2 0.4 0.6 0.8
0
10
20
30
40
50
60
70
80
Output Voltage (V)
Sense Current (µA)
01 2 34567 8 9 10 11 12
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
150°C
25°C
COMPx Voltage (V)
Peak Current Sense Voltage (mV)
SYNC = LOW
SYNC = HIGH
0.65 0.8 0.95 1.1 1.25 1.4 1.55
–37.5
–25
–12.5
0
12.5
25
37.5
50
62.5
75
BOTH BUCKS ON
ONE BUCK ON
NEITHER BUCK ON
Quiescent Current (µA)
Temperature (°C)
0
10
20
30
40
50
60
-40 -15 10 35 60 85 110 135 160
TPS43335-Q1
TPS43336-Q1
www.ti.com
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
TYPICAL CHARACTERISTICS (continued)
NO-LOAD QUIESCENT CURRENT BUCKx PEAK CURRENT LIMIT
versus versus
TEMPERATURE COMPx VOLTAGE
Figure 14. Figure 15.
CURRENT-SENSE PINS INPUT CURRENT (BUCK) FOLDBACK CURRENT LIMIT (BUCK)
Figure 16. Figure 17.
REGULATED FBx VOLTAGE CURRENT LIMIT
versus versus
TEMPERATURE (BUCK) DUTY CYCLE (BUCK)
Figure 18. Figure 19.
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: TPS43335-Q1 TPS43336-Q1
SS
SS
I t
C (Farads)
V
´ D
=
D
SW
9
SW
X
f (X 24 k MHz)
RT
10
f 24 RT
= = W ´
= ´
TPS43335-Q1
TPS43336-Q1
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
www.ti.com
DETAILED DESCRIPTION
BUCK CONTROLLERS: NORMAL MODE PWM OPERATION
Frequency Selection and External Synchronization
The buck controllers operate using constant-frequency peak-current-mode control for optimal transient behavior
and ease of component choices. The switching frequency is programmable between 150 kHz and 600 kHz,
depending upon the resistor value at the RT pin. A short circuit to ground at this pin sets the default switching
frequency to 400 kHz. Using a resistor at RT, one can set another frequency according to the formula:
For example,
600 kHz requires 40 kΩ
150 kHz requires 160 kΩ
It is also possible to synchronize to an external clock at the SYNC pin in the same frequency range of 150 kHz to
600 kHz. The device detects clock pulses at this pin, and an internal PLL locks on to the external clock within the
specified range. The device can also detect a loss of clock at this pin, and when this condition is detected, the
device sets the switching frequency to the internal oscillator. The two buck controllers operate at identical
switching frequencies, 180 degrees out-of-phase.
Enable Inputs
Independent enable inputs from the ENA and ENB pins enable the buck controllers. These are high-voltage pins,
with a threshold of 1.7 V for the high level, and with direct connection to the battery permissible for self-bias. The
low threshold is 0.7 V. Both these pins have internal pullup currents of 0.5 µA (typical). As a result, an open
circuit on these pins enables the respective buck controllers. When both buck controllers are disabled, the device
shuts down and consumes a current of less than 4 µA.
Feedback Inputs
The right resistor feedback divider network connected to the FBx (feedback) pins sets the output voltage. Choose
this network such that the regulated voltage at the FBx pin equals 0.8 V. The FBx pins have a 100-nA pullup
current source as a protection feature in case the pins open up as a result of physical damage.
Soft-Start Inputs
In order to avoid large inrush currents, each buck controller has an independent programmable soft-start timer.
The voltage at the SSx pin acts as the soft-start reference voltage. The 1-µA pullup current available at the SSx
pins, in combination with a suitably chosen capacitor, generates a ramp of the desired soft-start speed. After
start-up, the pullup current ensures that SSx is higher than the internal reference of 0.8 V; 0.8 V then becomes
the reference for the buck controllers. The following equation calculates the soft-start ramp time:
where,
ISS = 1 µA (typical)
∆V = 0.8 V
CSS is the required capacitor for ∆t, the desired soft-start time.
An alternative use of the soft-start pins is as tracking inputs. In this case, connect them to the supply to be
tracked via a suitable resistor-divider network.
16 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS43335-Q1 TPS43336-Q1
DCR
Inductor L
R11
C11
VBuckX
Sx2
2
Sx11
VC
TPS43335-Q1
or
TPS43336-Q1
TPS43335-Q1
TPS43336-Q1
www.ti.com
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
Current-Mode Operation
Peak-current-mode control regulates the peak current through the inductor to maintain the output voltage at its
set value. The error between the feedback voltage at FBx and the internal reference produces a signal at the
output of the error amplifier (COMPx) which serves as the target for the peak inductor current. The device
senses the current through the inductor as a differential voltage at Sx1–Sx2 and compares voltage with this
target during each cycle. A fall or rise in load current produces a rise or fall in voltage at FBx, causing VCOMPx to
fall or rise respectively, thus increasing or decreasing the current through the inductor until the average current
matches the load. This process maintains the output voltage in regulation.
The top N-channel MOSFET turns on at the beginning of each clock cycle and stays on until the inductor current
reaches its peak value. Once this MOSFET turns off, and after a small delay (shoot-through delay) the lower N-
channel MOSFET turns on until the start of the next clock cycle. In dropout operation, the high-side MOSFET
stays on continuously. In every fourth clock cycle, there is a limit on the duty cycle of 95% in order to charge the
bootstrap capacitor at CBx. This allows a maximum duty cycle of 98.75% for the buck regulators. During dropout,
the buck regulator switches at one-fourth of its normal frequency.
Current Sensing and Current Limit With Foldback
Clamping of the maximum value of COMPx is such as to limit the maximum current through the inductor to a
specified value. When the output of the buck regulator (and hence the feedback value at FBx) falls to a low value
due to a short circuit or overcurrent condition, the clamped voltage at COMPx successively decreases, thus
providing current foldback protection, which protects the high-side external MOSFET from excess current
(forward-direction current limit).
Similarly, if a fault condition shorts the output to a high voltage and the low-side MOSFET turns fully on, the
COMPx node drops low. A clamp is on its lower end as well, in order to limit the maximum current in the low-side
MOSFET (reverse-direction current limit).
An external resistor senses the current through the inductor. Choose the sense resistor such that the maximum
forward peak current in the inductor generates a voltage of 75 mV across the sense pins. This specified value is
for low duty cycles only. At typical duty-cycle conditions around 40% (assuming 5 V output and 12 V input), 50
mV is a more reasonable value, considering tolerances and mismatches. The typical characteristics provide a
guide for using the correct current-limit sense voltage.
The current-sense pins Sx1 and Sx2 are high-impedance pins with low leakage across the entire output range,
thus allowing DCR current sensing using the dc resistance of the inductor for higher efficiency. Figure 20 shows
DCR sensing. Here, the series resistance (DCR) of the inductor is the sense element. Place the filter
components close to the device for noise immunity. Remember that while the DCR sensing gives high efficiency,
it is inaccurate due to the temperature sensitivity and a wide variation of the parasitic inductor series resistance.
Hence, it may often be advantageous to use the more-accurate sense resistor for current sensing.
Figure 20. DCR Sensing Configuration
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: TPS43335-Q1 TPS43336-Q1
DELAY
DLYAB
t1 m s
C 1 nF
=
SW
S
L f
200
R
´
=
TPS43335-Q1
TPS43336-Q1
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
www.ti.com
Slope Compensation
Optimal slope compensation which is adaptive to changes in input voltage and duty cycle allows stable operation
under all conditions. For optimal performance of this circuit, choose the inductor and sense resistor according to
the following:
where
L is the buck regulator inductor in henries.
RSis the sense resistor in ohms.
fsw is the buck-regulator switching frequency in hertz.
Power-Good Outputs and Filter Delays
Each buck controller has an independent power-good comparator monitoring the feedback voltage at the FBx
pins and indicating whether the output voltage has fallen below a specified power-good threshold. This threshold
has a typical value of 93% of the regulated output voltage. The power-good indicator is available as an open-
drain output at the PGx pins. An internal 50-kΩpullup resistor to Sx2 is available, or use of an external resistor is
possible. Shutdown of a buck controller causes an internal pulldown of the power-good indicator. Connecting the
pullup resistor to a rail other than the output of that particular buck channel causes a constant current flow
through the resistor when the buck controller is powered down.
In order to avoid triggering the power-good indicators due to noise or fast transients on the output voltage, the
device uses an internal delay circuit for de-glitching. Similarly, when the output voltage returns to its set value
after a long negative transient, assertion of the power-good indicator (release of the open-drain pin) occurs after
the same delay. Use of this delay can pause the reset of circuits powered from the buck regulator rail. Program
the duration of the delay of by using a suitable capacitor at the DLYAB pin according to the equation:
When the DLYAB pin is open, the delay setting is for a default value of 20 µs typical. The power-good delay
timing is common to both the buck rails, but the power-good comparators and indicators function independently.
Light-Load PFM Mode
An external clock or a high level on the SYNC pin results in forced continuous-mode operation of the bucks. An
open or low on the SYNC pin allows the buck controllers to operate in discontinuous mode at light loads by
turning off the low-side MOSFET on detection of a zero-crossing in the inductor current.
In discontinuous mode, as the load decreases, the duration when both the high-side and low-side MOSFETs turn
off increases (deep discontinuous mode). In case the duration exceeds 60% of the clock period and VBAT > 8 V,
the buck controller switches to a low-power operation mode. The design ensures that this typically occurs at 1%
of the set full-load current if the choice of the inductor and sense resistor is as recommended in the slope
compensation section.
In low-power PFM mode, the buck monitors the FBx voltage and compares it with the 0.8-V internal reference.
Whenever the FBx value falls below the reference, the high-side MOSFET turns on for a pulse duration inversely
proportional to the difference VIN – Sx2. At the end of this on-time, the high-side MOSFET turns off and the
current in the inductor decays until it becomes zero. The low-side MOSFET does not turn on. The next pulse
occurs the next time FBx falls below the reference value. This results in a constant volt-second ton hysteretic
operation with a total device quiescent current consumption of 30 µA when a single buck channel is active and
35 µA when both channels are active.
As the load increases, the pulses become more and more frequent and move closer to each other until the
current in the inductor becomes continuous. At this point, the buck controller returns to normal fixed-frequency
current-mode control. Another criterion to exit the low-power mode is when VIN falls low enough to require higher
than 80% duty cycle of the high-side MOSFET.
18 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS43335-Q1 TPS43336-Q1
DS
GC1
TPS43335-Q1
or
TPS43336-Q1
VIN
VBAT
TPS43335-Q1
TPS43336-Q1
www.ti.com
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
The TPS43335-Q1 and TPS43336-Q1 can support the full-current load during low-power mode until the
transition to normal mode takes place. The design ensures that exit of the low-power mode occurs at 10%
(typical) of full-load current if the selection of inductor and sense resistor is as recommended. Moreover, there is
always a hysteresis between the entry and exit thresholds to avoid oscillating between the two modes.
In the event that both buck controllers are active, low-power mode is only possible when both buck controllers
have light loads that are low enough for low-power mode entry. With the boost controller enabled, low-power
mode is possible only if VBAT is high enough to prevent the boost from switching and if DIV is open or set to
GND. A high (VREG) level on DIV inhibits low-power mode, unless ENC is set to low.
Boost Controller
The boost controller has a fixed-frequency voltage-mode architecture and includes cycle-by-cycle current-limit
protection for the external N-channel MOSFET. The boost-controller switching-frequency setting is one-half of the
buck-controller switching frequency. An internal resistor-divider network programmable to 7 V, 10 V, or 11 V sets
the output voltage of the boost controller at the VIN pin, based on the low, open, or high status, respectively, of
the DIV pin. The device does not recognize a change of the DIV setting while the in the low-power mode.
The active-high ENC pin enables the boost controller, which is active when the input voltage at the VBAT pin has
crossed the unlock threshold of 8.5 V at least once. A single threshold crossing arms the boost controller, which
starts switching as soon as VIN falls below the value set by the DIV pin, regulating the VIN voltage. Thus, the
boost regulator maintains a stable input voltage for the buck regulators during transient events such as a
cranking pulse at VBAT.
The voltage at the DS pin exceeding 200 mV pulls the CG1 pin low, turning off the boost external MOSFET.
Connecting the DS pin to the drain of the MOSFET or to a sense resistor between the MOSFET source and
ground achieves cycle-by-cycle overcurrent protection for the MOSFET. Choose the on-resistance of the
MOSFET or the value of the sense resistor in such a way that the on-state voltage at the DS does not exceed
200 mV at the maximum-load and minimum-input-voltage conditions. When using a sense resistor, TI
recommends connecting a filter network between the DS pin and the sense resistor for better noise immunity.
One can use the boost output (VIN) to supply other circuits in the system. However, they should be high-voltage
tolerant. The device regulates the boost output to the programmed value only when VIN is low, and so VIN can
reach battery levels.
Figure 21. External Drain-Source Voltage Sensing
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: TPS43335-Q1 TPS43336-Q1
DS
GC1
TPS43335-Q1
or
TPS43336-Q1
VIN
VBAT
RISEN
RIFLT
CIFLT
TPS43335-Q1
TPS43336-Q1
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
www.ti.com
Figure 22. External Current Shunt Resistor
Frequency-Hopping Spread Spectrum (TPS43336-Q1 Only)
The TPS43336-Q1 features a frequency-hopping pseudo-random spectrum-spreading architecture. On this
device, whenever the SYNC pin is high, the internal oscillator frequency varies from one cycle to the next within
a band of ±5% around the value programmed by the resistor at the RT pin. The implementation uses a linear-
feedback shift register that changes the frequency of the internal oscillator based on a digital code. The shift
register is long enough to make the hops pseudo-random in nature and has a design such that the frequency
shifts only by one step at each cycle to avoid large jumps in the buck and boost switching frequencies.
Table 1. Frequency-Hopping Control
Sync Frequency Spread Spectrum (FSS) Comments
Terminal
Device in forced continuous mode, internal PLL locks into external clock
External clock Not active between 150 kHz and 600 kHz.
Device can enter discontinuous mode. Automatic LPM entry and exit,
Low or open Not active depending on load conditions
TPS43335-Q1: FSS not active
High Device in forced continuous mode
TPS43336-Q1: FSS active
Table 2. Mode of Operation
ENABLE AND INHIBIT PINS DRIVER STATUS DEVICE STATUS QUIESCENT CURRENT
ENA ENB ENC SYNC BUCK CONTROLLERS BOOST CONTROLLER
Low Low Low X Shutdown Disabled Shutdown Approximately 4 µA
Low BuckB: LPM enabled Approximately 30 µA (light loads)
Low High Low BuckB running Disabled
High BuckB: LPM inhibited mA range
Low BuckA: LPM enabled Approximately 30 µA (light loads)
High Low Low BuckA running Disabled
High BuckA: LPM inhibited mA range
BuckA and BuckB: LPM
Low Approximately 35 µA (light loads)
enabled
BuckA and BuckB
High High Low Disabled
running BuckA and BuckB: LPM
High mA range
inhibited
Low Low Low X Shutdown Disabled Shutdown Approximately 4 µA
Approximately 50 µA (no boost,
Low BuckB: LPM enabled
Boost running for VIN < set light loads)
Low High High BuckB running boost output
High BuckB: LPM inhibited mA range
Approximately 50 µA (no boost,
Low BuckA: LPM enabled
Boost running for VIN < set light loads)
High Low High BuckA running boost output
High BuckA: LPM inhibited mA range
20 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS43335-Q1 TPS43336-Q1
LDO
EXTSUP
LDO
VIN
VIN EXTSUP
VREG
typ 5.8 V typ 7.5 V
typ 4.6 V
TPS43335-Q1
TPS43336-Q1
www.ti.com
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
Table 2. Mode of Operation (continued)
ENABLE AND INHIBIT PINS DRIVER STATUS DEVICE STATUS QUIESCENT CURRENT
ENA ENB ENC SYNC BUCK CONTROLLERS BOOST CONTROLLER
BuckA and BuckB: LPM Approximately 60 µA (no boost,
Low enabled light loads)
BuckA and BuckB Boost running for VIN < set
High High High running boost output BuckA and BuckB: LPM
High mA range
inhibited
Gate-Driver Supply (VREG, EXTSUP)
The gate-driver supplies of the buck and boost controllers are from an internal linear regulator whose output (5.8
V typical) is on the VREG pin and requires decoupling with a ceramic capacitor in the range of 3.3 µF to 10 µF.
This pin has internal current-limit protection; do not use it to power any other circuits.
VIN powers the VREG linear regulator by default when the EXTSUP voltage is lower than 4.6 V (typical). If there
is an expectation of VIN going to high levels, there can be excessive power dissipation in this regulator, especially
at high switching frequencies and when using large external MOSFETs. In this case, it is advantageous to power
this regulator from the EXTSUP pin, which can have a connection to a supply lower than VIN but high enough to
provide the gate drive. When the voltage on EXTSUP is greater than 4.6 V, the linear regulator automatically
switches to EXTSUP as its input, to provide this advantage. Efficiency improvements are possible when using
one of the switching regulator rails from the TPS43335-Q1 or TPS43336-Q1 or any other voltage available in the
system to power EXTSUP. The maximum voltage for application to EXTSUP is 9 V.
Figure 23. Internal Gate-Driver Supply
Using a voltage above 5.8 V (sourced by VIN) for EXTSUP is advantageous, as it provides a large gate drive
and hence better on-resistance of the external MOSFETs.
When using EXTSUP, always keep the buck rail supplying EXTSUP enabled. Alternatively, if it is necessary to
switch off the buck rail supplying EXTSUP, place a diode between the buck rail and EXTSUP.
During low-power mode, the EXTSUP functionality is not available. The internal regulator operates as a shunt
regulator powered from VIN and has a typical value of 7.5 V. Current-limit protection for VREG is available in
low-power mode as well. If EXTSUP is unused, leave the pin open without a capacitor installed.
External P-Channel Drive (GC2) and Reverse Battery Protection
The TPS43335-Q1 and TPS43336-Q1 include a gate driver for an external P-channel MOSFET which can
connect across the rectifier diode of the boost regulator. Such connection is useful to reduce power losses when
the boost controller is not switching. The gate driver provides a swing of 6 V typical below the VIN voltage in
order to drive a P-channel MOSFET. When VBAT falls below the boost-enable threshold, the gate driver turns off
the P-channel MOSFET, eliminating the diode bypass.
Another use for the gate driver is to bypass any additional protection diodes connected in series, as shown in
Figure 24.Figure 25 also shows a different scheme of reverse battery protection, which may require only a
smaller-sized diode to protect the N-channel MOSFET, as the diode conducts only for a part of the switching
cycle. Because the diode is not always in the series path, the system efficiency can be improved.
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: TPS43335-Q1 TPS43336-Q1
TPS43335-Q1
or
TPS43336-Q1
GC2
VBAT
Fuse
VIN
DS
GC1
COMPC
VBAT
C14
Fuse (S1)
Q6
C13
C15C17
C16
D2
R10
Q7
D3
D1
GC2
VIN
DS
GC1
COMPC
VBAT
R9
VBAT
L3
TPS43335-Q1
or
TPS43336-Q1
TPS43335-Q1
TPS43336-Q1
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
www.ti.com
Figure 24. Reverse Battery Protection Option 1 for Buck Boost Configuration
Figure 25. Reverse Battery Protection Option 2 for Buck Boost Configuration
Undervoltage Lockout and Overvoltage Protection
The TPS43335-Q1 and TPS43336-Q1 start up at a VIN voltage of 6.5 V (minimum), required for the internal
supply (VREG). Once it has started up, the device operates down to a VIN voltage of 3.6 V; below this voltage
level, the undervoltage lockout disables the device. Note: if VIN drops, VREG drops as well; hence, the gate-drive
voltage is reduced, whereas the digital logic is fully functional. Note as well, even if ENC is high, there is a
requirement to exceed the boost-unlock voltage of typically 8.5 V once, before boost activation can take place
(see the Boost Controller section herein). A voltage of 46 V at VIN triggers the overvoltage comparator, which
shuts down the device. In order to prevent transient spikes from shutting down the device, the under- and
overvoltage protection have filter times of 5 µs (typical).
When the voltages return to the normal operating region, the enabled switching regulators start including a new
soft-start ramp for the buck regulators.
With the boost controller enabled, a voltage less than 1.9 V (typical) on VBAT triggers an undervoltage lockout
and pulls the boost gate driver (GC1) low (this action has a filter delay of 5 µs, typical). As a result, VIN falls at a
rate dependent on its capacitor and load, eventually triggering VIN undervoltage. A short falling transient at
VBAT even lower than 2 V can thus be survived, if VBAT returns above 2.5 V before VIN is discharged to the
undervoltage threshold.
Thermal Protection
The TPS43335-Q1 or TPS43336-Q1 protects itself from overheating using an internal thermal shutdown circuit. If
the die temperature exceeds the thermal shutdown threshold of 165ºC due to excessive power dissipation (for
example, due to fault conditions such as a short circuit at the gate drivers or VREG), the controllers turn off and
then restart when the temperature has fallen by 15ºC.
22 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS43335-Q1 TPS43336-Q1
COMPx
+
-
VIN
VREF
7V
10 V
12 V
C 1
C 2
R3
CO
RESR
OTA-gmEA
TPS43335-Q1
TPS43336-Q1
www.ti.com
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
APPLICATION INFORMATION
The following example illustrates the design process and component selection for the TPS43335-Q1. Table 3
lists the design-goal parameters.
Table 3. Application Example
PARAMETER VBuckA VBuckB BOOST
VIN = 6 V to 30 V VIN = 6 V to 30 V VBAT = 5 V (cranking
Input voltage 12 V - typical 12 V - typical pulse input) to 30 V
Output voltage, VOUTx 5 V 3.3 V 10 V
Maximum output current, IOUTx 3 A 2 A 2.5 A
Load-step output tolerance, ∆VOUT + ±0.5 V
±0.2 V ±0.12 V
∆VOUT(Ripple)
Current output load step, ∆IOUTx 0.1 A to 3 A 0.1 A to 2 A 0.1 A to 2.5 A
Converter switching frequency, fSW 400 kHz 400 kHz 200 kHz
This is a starting point and theoretical representation of the values for use in the application; improving the
performance of the device may require further optimization of the derived components.
Boost Component Selection
A boost converter operating in continuous-conduction mode (CCM) has a right-half-plane (RHP) zero in its
transfer function. The RHP zero relates inversely to the load current and inductor value and directly to the input
voltage. The RHP zero limits the maximum bandwidth achievable for the boost regulator. If the bandwidth is too
close to the RHP zero frequency, the regulator may become unstable.
Thus, for high-power systems with low input voltages, choose a low inductor value. A low value increases the
amplitude of the ripple currents in the N-channel MOSFET, the inductor, and the capacitors for the boost
regulator. Select these components with the ripple-to-RHP zero trade-off in mind and considering the power
dissipation effects in the components due to parasitic series resistance.
A boost converter that operates always in the discontinuous mode does not contain the RHP zero in its transfer
function. However, designing for the discontinuous mode demands an even lower inductor value that has high
ripple currents. Also, ensure that the regulator never enters the continuous-conduction mode; otherwise, it may
become unstable.
Figure 26. Boost Compensation Components
This design assumes operation in continuous-conduction mode. During light load conditions, the boost converter
operates in discontinuous mode without affecting stability. Hence, the assumptions here cover the worst case for
stability.
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: TPS43335-Q1 TPS43336-Q1
BAT min
RHP
INmax
V
f 32 kHz
2 I L
= =
p ´ ´
SENSE
0.2 V
R 25 m
7.85 A
= = W
RIPPLE
PEAK INmax
I3.1 A
I I 6.3 A + 7.85 A
2 2
= + = =
BAT ON BAT
INripplemax INripple max SW
V t V5 V
L 4.9 H
I I 2 f 2.52 A 2 200 kHz
´
= = = = m
´ ´ ´ ´
BAT
31.3 W
I (at V = 5 V) 6.3 A
INmax 5 V
= =
OUT
INmax
P25 W
P 31.3 W
Efficiency 0.8
= = =
TPS43335-Q1
TPS43336-Q1
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
www.ti.com
Boost Maximum Input Current IIN_MAX
The maximum input current flows at the minimum input voltage and maximum load. The efficiency for VBAT =5V
at 2.5 A is 80%, based on the typical characteristics plot.
Hence,
Boost Inductor Selection, L
Allow input ripple current of 40% of IIN max at VBAT = 5 V.
Choose a lower value of 4 µH in order to ensure a high RHP-zero frequency while making a compromise that
expects a high current ripple. This inductor selection also makes the boost converter operate in discontinuous
conduction mode, where it is easier to compensate.
The inductor saturation current must be higher than the peak inductor current and some percentage higher than
the maximum current-limit value set by the external resistive sensing element.
Determine the saturation rating at the minimum input voltage, maximum output current, and maximum core
temperature for the application.
Inductor Ripple Current, IRIPPLE
Based on an inductor value of 4 µH, the ripple current is approximately 3.1 A.
Peak Current in Low-Side FET, IPEAK
Based on this peak current value, calculate the external current-sense resistor RSENSE.
Select 20 mΩ, allowing for tolerance.
The filter component values RIFLT and CIFLT for current sense are 1.5 kΩand 1 nF, respectively, which allows for
good noise immunity.
Right Half-Plane Zero RHP Frequency, fRHP
24 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS43335-Q1 TPS43336-Q1
ESR ESR
OUTx ESR
ESR
LC
OUTx
1
f Hz, assume R = 40 m
2 C R
1
f 6 kHz
2 660 F 0.04
1 1
f 3.1 kHz
2 L C 2 4 H 660 F
=
= =
= W
p ´ ´
=
p ´ m ´ W
=
p ´ ´ p ´ m ´ m
RHP
LC
BAT min
INmax
OUTx
22
INmax
OUTx
BAT min
OUTx min
4 H
f
f
10
V
10
2 I L
2 L C
10 I 10 6.3 A
C L
V 5 V
C 635 F
³ ´ m
£
£p´ ´
p´ ´
æ ö
´æ ö
´
ç ÷ ´ = ç ÷
ç ÷ è ø
è ø
³ m
TPS43335-Q1
TPS43336-Q1
www.ti.com
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
Output Capacitor, COUTx
To ensure stability, choose output capacitor COUTx such that
Select COUTx = 680 µF.
This capacitor is usually aluminum electrolytic with ESR in the tens of milliohms. ESR in this range is good for
loop stability, because it provides a phase boost. The output filter components, L and C, create a double pole
(180-degree phase shift) at a frequency fLC and the ESR of the output capacitor RESR creates a zero for the
modulator at frequency fESR. These frequencies can be determined by the following:
This satisfies fLC ≤0.1 fRHP.
Bandwidth of Boost Converter, fC
Use the following guidelines to set the frequency poles, zeroes, and crossover values for the trade-off between
stability and transient response:
fLC < fESR< fC< fRHP Zero
fC< fRHP Zero / 3
fC< fSW / 6
fLC < fC/ 3
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: TPS43335-Q1 TPS43336-Q1
RIPPLE
C1
SW IN
RIPPLE
IN
SW C1
ESR RIPPLE ESR
I
V 10 mV
8 f C
I
C 194-μF
8 f V
V I R 40 mV
D = =
´ ´
= =
´ ´ D
D = ´ =
G/20
6 2
OUTx
C
SW
10
R3 7.2 k
85 10 A / V V
10 10
C1 22 nF
2 f R3 2 10 kHz 7.2 k
C1 22 nF
C2 223 pF
f 200 kHz
2 7.2 k 22 nF 1
2 R3 C1 1 2
2
-
= = W
´ ´
= = =
p ´ ´ p ´ ´ W
= = =
æ ö æ ö
p ´ W ´ ´ -
p ´ ´ ´ - ç ÷
ç ÷ è ø
è ø
C C
LC ESR
10 kHz 10 kHz
G 40 log 20 log
3.1 kHz 6 kHz
f f
G 40 log 20 log
f f
15.9 dB= -
æ ö æ ö
= ç ÷ - ç ÷
ç ÷
ç ÷ è ø
è ø
æ ö æ ö =
ç ÷ ç ÷
è ø è ø
OUTx
OUTx ESR OUTx
OUTx C
I
V R I
4 C f
2.5 A
0.04 2.5 A 0.19 V
4 660 F 10 kHz
D
+D = ´ D ´ ´
= W ´ + =
´ m ´
TPS43335-Q1
TPS43336-Q1
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
www.ti.com
Output Ripple Voltage Due to Load Transients, ∆VOUTx
Assume a bandwidth of fC= 10 kHz.
Because the boost converter is active only during brief events such as a cranking pulse, and the buck converters
are high-voltage tolerant, a higher excursion on the boost output may be tolerable in some cases. In such cases,
one can choose smaller components for the boost output.
Selection of Components for Type II Compensation
The required loop gain for unity-gain bandwidth (UGB) is
The boost-converter error amplifier (OTA) has a Gm that is proportional to the VBAT voltage. This allows a
constant loop response across the input-voltage range and makes it easier to compensate by removing the
dependency on VBAT.
Input Capacitor, CIN
The input ripple required is lower than 50 mV.
Therefore, TI recommends 220 µF with 10-mΩESR.
26 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS43335-Q1 TPS43336-Q1
OUTA
ON min
IN max SW
V3.3 V
t 275 ns
V f 30 V 400 kHz
= = =
´ ´
I Pk
I Pk
2
BOOSTFET Pk DS(on) r f SW
2
BOOSTFET
V I
2
V I
P (I ) r (1 TC) D (t t ) f
2
P (7.85 A) 0.02 (1 0.4) 0.53 (20 ns 20 ns) 200 kHz 1.07 W
´
´ ´ ´ ´ ´
´
æ ö
= ´ + ´ + ´ + ´
ç ÷
ç ÷
è ø
æ ö
= W + + + =
ç ÷
è ø
D D(PEAK) F
INMIN
OUT F
D
P I V (1 D)
V5 V
D 1 1 0.53
V V 10 V 0.6 V
P 7.85 A 0.6 V (1 0.53) 2.2 W
= ´ ´ -
= - = - =
+ +
= ´ ´ - =
TPS43335-Q1
TPS43336-Q1
www.ti.com
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
Output Schottky Diode D1 Selection
Maximizing efficiency requires a Schottky diode with low forward-conducting voltage VFover temperature and
fast switching characteristics. The reverse breakdown voltage should be higher than the maximum input voltage,
and the component should have low reverse leakage current. Additionally, the peak forward current should be
higher than the peak inductor current. The power dissipation in the Schottky diode is given by:
Low-Side MOSFET (BOT_SW3)
The times trand tfdenote the rising and falling times of the switching node and relate to the gate-driver strength
of the TPS43335-Q1 and TPS43336-Q1 and the gate Miller capacitance of the MOSFET. The first term denotes
the conduction losses, which the low on-resistance of the MOSFET minimizes. The second term denotes the
transition losses which arise due to the full application of the input voltage across the drain-source of the
MOSFET as it turns on or off. Transition losses are higher at high output currents and low input voltages (due to
the large input peak current) and when the switching time is low.
Note: The on-resistance, rDS(on), has a positive temperature coefficient, which produces the (TC = d × ΔT) term
that signifies the temperature dependence. (Temperature coefficient d is available as a normalized value from
MOSFET data sheets and can have an assumed starting value of 0.005 / °C.)
BuckA Component Selection
BuckA Component Selection
tON min is higher than the minimum duty cycle specified (100 ns typical). Hence, the minimum duty cycle is
achievable at this frequency.
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Links: TPS43335-Q1 TPS43336-Q1
OUTA
OUTA OUTA
C OUTA
I2.9 A
V I ESR 2.9 A 10 m 174 mV
4 f C 4 50 kHz 100 F
D
D = + D ´ = + ´ W =
´ ´ ´ ´ m
OUTA(Ripple)
OUTA(Ripple) OUTA(Ripple)
SW OUTA
I1 A
V I ESR 1 A 10 m 13.1 mV
8 f C 8 400 kHz 100 F
= + ´ = + ´ W =
´ ´ ´ ´ m
OUTA
OUTA
SW OUTA
2 I 2 2.9 A
C 72.5 F
f V 400 kHz 0.2 V
´ D ´
» = = m
´ D ´
SENSE
FLR
SW
R15 m
L K 200 7.5 H
f 400 kHz
W
= ´ = ´ = m
SENSE
50 mV
R 17 m
3 A
= = W
TPS43335-Q1
TPS43336-Q1
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
www.ti.com
Current-Sense Resistor RSENSE
Based on the typical characteristics for the VSENSE limit with VIN versus duty cycle, the sense limit is
approximately 65 mV (at VIN = 12 V and duty cycle of 5 V / 12 V = 0.416). Allowing for tolerances and ripple
currents, choose a VSENSE maximum of 50 mV.
Select 15 mΩ.
Inductor Selection L
As explained in the description of the buck controllers, for optimal slope compensation and loop response,
choose the inductor such that:
KFLR = coil-selection constant = 200
Choose a standard value of 8.2 µH. For the buck converter, choose the inductor saturation currents and core to
sustain the maximum currents.
Inductor Ripple Current IRIPPLE
At the nominal input voltage of 12 V, this inductor value causes a ripple current of 30% of IOUT max ≈1 A.
Output Capacitor COUTA
Select an output capacitance COUTA of 100 µF with low ESR in the range of 10 mΩ, giving ∆VOUT(Ripple) ≈15 mV
and a ∆V drop of ≈180 mV during a load step, which does not trigger the power-good comparator and is within
the required limits.
Bandwidth of Buck Converter fC
Use the following guidelines to set frequency poles, zeroes, and crossover values for the trade-off between
stability and transient response.
• Crossover frequency fCbetween fSW / 6 and fSW / 10. Assume fC= 50 kHz.
• Select the zero fz≈fC/ 10
• Make the second pole fP2 ≈fSW / 2
28 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS43335-Q1 TPS43336-Q1
P2
1 1
f 201kHz
2 R3 C2 2 24 k 33 pF
= = =
p ´ ´ p ´ W ´
Z1
1 1
f 4.42 kHz
2 R3 C1 2 24 k 1.5 nF
= = =
p ´ ´ p ´ W ´
BUCK CFB REF
C
OUTx OUT
C
Gm R3 K V
f2 C V
1mS 24 k 8.33 S 0.8 V
f 50.9 kHz
2 100 μF 5 V
´ ´
= ´
p ´
´ W ´ ´
= =
p ´ ´
SW
C1 1.5 nF
C2 33 pF
f 400 kHz
2 24k 1.5 nF 1
2 R3 C1 1 2
2
= = =
æ ö æ ö
p ´ W ´ -
p ´ ´ - ç ÷
ç ÷ è ø
è ø
C
10 10
C1 1.33 nF
2 R3 f 2 24 k 50 kHz
= = =
p ´ ´ p ´ W ´
C OUT OUTx
BUCK CFB REF BUCK CFB REF
2 f V C 2 50 kHz 5 V 100μF
R3 23.57 k
Gm K V Gm K V
p ´ ´ ´ p ´ ´ ´
= = = W
´ ´ ´ ´
VREF
RLCOMP
VSENSE
Type 2A
GmBUCK
RESR
C2
C1
R3
R1
R2
VOUT
R0
COUT
TPS43335-Q1
TPS43336-Q1
www.ti.com
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
Selection of Components for Type II Compensation
Figure 27. Buck Compensation Components
where VOUT =5V,COUT = 100 µF, GmBUCK = 1 mS, VREF = 0.8 V, KCFB = 0.125 / RSENSE = 8.33 S (0.125 is an
internal constant)
Use the standard value of R3 = 24 kΩ.
Use the standard value of 1.5 nF.
The resulting bandwidth of buck converter fC
fCis close to the target bandwidth of 50 kHz.
The resulting zero frequency fZ1
fZ1 is close to the fC/ 10 guideline of 5 kHz.
The second pole frequency fP2
fP2 is close to the fSW / 2 guideline of 200 kHz. Hence, the design satisfies all requirements for a good loop.
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Links: TPS43335-Q1 TPS43336-Q1
C
10 10
C1 1.1 nF
2 R3 f 2 30 k 50 kHz
= = =
p ´ ´ p ´ W ´
C OUTB OUTB
BUCK CFB REF
2 f V C
R3
Gm K V
2 50 kHz 3.3 V 100 F
1 mS 4.16 S 0.8 V
31k
p ´ ´ ´
=´ ´
p ´ ´ ´ m
´ ´
= = W
OUTB
OUTB OUTB
C OUTB
I1.9 A
V I ESR 1.9 A 10 m 114 mV
4 f C 4 50 kHz 100 F
D
D = + D ´ = + ´ W =
´ ´ ´ ´ m
OUTB(Ripple)
OUTB(Ripple) OUTB(Ripple)
SW OUTB
I0.4 A
V I ESR 0.4 A 10 m 5.3 mV
8 f C 8 400 kHz 100 F
= + ´ = + ´ W =
´ ´ ´ ´ m
OUTB
OUTB
SW OUTB
2 I 2 1.9 A
C 46 F
f V 400 kHz 0.12 V
´ D ´
» = = m
´ D ´
SENSE
60 mV
R 30 m
2 A
30 m
L 200 15 H
400 kHz
= = W
W
= ´ = m
OUTB
ON min
IN max SW
V3.3 V
t 275 ns
V f 30 V 400 kHz
= = =
´ ´
R2
R1 R2
0.16
+
=
5 V
R1 R2
50 A
66 k+ = m= W
REF
OUTA
V0.8 V 0.16
V 5 V
b = = =
TPS43335-Q1
TPS43336-Q1
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
www.ti.com
Resistor Divider Selection for Setting VOUTA Voltage
Choose the divider current through R1 and R2 to be 50 µA. Then
and
Therefore, R2 = 16 kΩand R1 = 84 kΩ.
BuckB Component Selection
Using the same method as for VBuckA produces the following parameters and components.
This is higher than the minimum duty cycle specified (100 ns typical).
∆Iripple current ≈0.4 A (approximately 20% of IOUT max)
Select an output capacitance COUTB of 100 µF with low ESR in the range of 10 mΩ.
Assume fC= 50 kHz.
Use the standard value of R3 = 30 kΩ.
30 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS43335-Q1 TPS43336-Q1
R2
R1 R2
0.242
+
=
3.3 V
R1 R2
50 A
66 k+ = m= W
REF
OUT
V0.8 V
V 3.3 V
0.242b = = =
P2
1 1
f2 R3 C2 2 30 k 27 pF 196 kHz=
p ´ ´ p ´ W ´
= =
Z1
1 1
f 4.8 kHz
2 R3 C1 2 30 k 1.1 nF
= = =
p ´ ´ p ´ W ´
BUCK CFB REF
C
OUTB OUTB
Gm R3 K V
f2 C V
1mS 30 k 4.16 S 0.8 V 48 kHz
2 100 μF 3.3 V
´ ´
=
p ´
´ W ´ ´
= =
p ´ ´
´
SW
C1
C2
2 R3 C1
1.1nF 27 pF
2 30 k 1.1 nF
f1
2
400 kHz 1
2
=
p ´ ´ ´
= =
p ´ W ´ ´
æ ö -
ç ÷
è ø
æ ö -
ç ÷
è ø
TPS43335-Q1
TPS43336-Q1
www.ti.com
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
fCis close to the target bandwidth of 50 kHz.
The resulting zero frequency fZ1
fZ1 is close to the fCguideline of 5 kHz.
The second pole frequency fP2
fP2 is close to the fSW / 2 guideline of 200 kHz.
Hence, the design satisfies all requirements for a good loop.
Resistor Divider Selection for Setting VOUT Voltage
Choose the divider current through R1 and R2 to be 50 µA. Then
and
Therefore, R2 = 16 kΩand R1 = 50 kΩ.
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 31
Product Folder Links: TPS43335-Q1 TPS43336-Q1
2
BuckLOWERFET OUT DS(on) F OUT d SW
P (I ) r (1 TC) (1 D) V I (2 t ) f= ´ + ´ - + ´ ´ ´ ´
2IN OUT
BuckTOPFET OUT DS(on) r f SW
2
V I
P (I ) r (1 TC) D (t t ) f
´
æ ö
= ´ + ´ + ´ + ´
ç ÷
è ø
TPS43335-Q1
TPS43336-Q1
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
www.ti.com
BuckX High-Side and Low-Side N-Channel MOSFETs
An internal supply, which is 5.8 V typical under normal operating conditions, provides the gate-drive supply for
these MOSFETs. The output is a totem pole, allowing full-voltage drive of VREG to the gate with peak output
current of 0.7 A. The reference for the high-side MOSFET is a floating node at the phase terminal (PHx), and the
reference for the low-side MOSFET is the power-ground (PGx) terminal. For a particular application, select these
MOSFETs with consideration for the following parameters: rDS(on), gate charge Qg, drain-to-source breakdown
voltage BVDSS, maximum dc current IDC(max), and thermal resistance for the package.
The times trand tfdenote the rising and falling times of the switching node and have a relationship to the gate-
driver strength of the TPS43335-Q1 and TPS43336-Q1 and to the gate Miller capacitance of the MOSFET. The
first term denotes the conduction losses, which are minimimal when the on-resistance of the MOSFET is low.
The second term denotes the transition losses, which arise due to the full application of the input voltage across
the drain-source of the MOSFET as it turns on or off. Transition losses are lower at low currents and when the
switching time is low.
In addition, during the dead time tdwhen both the MOSFETs are off, the body diode of the low-side MOSFET
conducts, increasing the losses. The second term in the preceding equation denotes this. Using external
Schottky diodes in parallel with the low-side MOSFETs of the buck converters helps to reduce this loss.
Note: rDS(on) has a positive temperature coefficient, and TC term for rDS(on) accounts for that fact. TC = d ×
ΔT[°C]. The temperature coefficient d is available as a normalized value from MOSFET data sheets and can
have an assumed starting value of 0.005 / ºC.
32 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS43335-Q1 TPS43336-Q1
VBAT
TPS43335-Q1
or
TPS43336-Q1
2.5V to 40V
VBAT
DS
GC1
GC2
CBA
GA1
PHA
GA2
PGNDA
SA1
SA2
FBA
COMPA
SSA
PGA
ENA
ENB
COMPC
ENC SYNC
DLYAB
RT
AGND
PGB
SSB
COMPB
FBB
SB2
SB1
PGNDB
GB2
PHB
GB1
CBB
VREG
DIV
EXTSUP
VIN
3.9µH
0.1µF
0.1µF
4.7µF
10nF
10nF
1nF
5kΩ5kΩ
100µF
COUTB
15µH
0.03Ω V—3.3V, 6.6W
BuckB
8.2µH
10µF 680µF
COUT1
100µF
COUTA
V—5V, 15W
BuckA 0.015Ω
7.2kΩ
22nF
220pF
24kΩ
1.5nF
33pF 30kΩ 1.1nF 27pF
16kΩ
50kΩ
16kΩ
84kΩ
TOP-SW1
BOT-SW1 BOT-SW2
TOP-SW2
TOP-SW3
BOT-SW3
C
220µF
IN
1kΩ
L1
L2 L3
D1
0.02Ω
BOOST —10V, 25W
1.5kΩ
1nF
TPS43335-Q1
TPS43336-Q1
www.ti.com
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
Schematics
The following section summarizes the previously calculated example and gives schematic and component
proposals.
Table 4. Application Example 1
PARAMETER VBuckA VBuckB BOOST
VIN = 6 V to 30 V VIN = 6 V to 30 V VBAT = 5 V (cranking pulse
Input voltage 12 V - typical 12 V - typical input) to 30 V
Output voltage, VOUTx 5 V 3.3 V 10 V
Maximum output current, IOUTx 3 A 2 A 2.5 A
Load-step output tolerance, ∆VOUT +∆VOUT(Ripple) ±0.2 V ±0.12 V ±0.5 V
Current output load step, ∆IOUTx 0.1 A to 3 A 0.1 A to 2 A 0.1 A to 2.5 A
Converter switching frequency, fSW 400 kHz 400 kHz 200 kHz
Figure 28. Simplified Application Schematic, Example 1
Table 5. Application Example 1 – Component Proposals
Name Component Proposal Value
L1 MSS1278T-392NL (Coilcraft) 4 µH
L2 MSS1278T-822ML (Coilcraft) 8.2 µH
L3 MSS1278T-153ML (Coilcraft) 15 µH
D1 SK103 (Micro Commercial Components)
TOP_SW3 IRF7416 (International Rectifier)
TOP_SW1, TOP_SW2 Si4840DY-T1-E3 (Vishay)
BOT_SW1, BOT_SW2 Si4840DY-T1-E3 (Vishay)
BOT_SW3 IRFR3504ZTRPBF (International Rectifier)
COUT1 EEVFK1J681M (Panasonic) 680 µF
COUTA, COUTB ECASD91A107M010K00 (Murata) 100 µF
CIN EEEFK1V331P (Panasonic) 220 µF
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 33
Product Folder Links: TPS43335-Q1 TPS43336-Q1
VBAT
TPS43335-Q1
or
TPS43336-Q1
5V to 30V
VBAT
DS
GC1
GC2
CBA
GA1
PHA
GA2
PGNDA
SA1
SA2
FBA
COMPA
SSA
PGA
ENA
ENB
COMPC
ENC SYNC
DLYAB
RT
AGND
PGB
SSB
COMPB
FBB
SB2
SB1
PGNDB
GB2
PHB
GB1
CBB
VREG
DIV
EXTSUP
VIN
3.9µH
0.1µF
0.1µF
4.7µF
10nF
10nF
1nF
5kΩ5kΩ
100µF
COUTB
22µH
0.045Ω V—3.3V, 16.5W
BuckB
10µH
10µF 470µF
COUT1
150µF
COUTA
V—5V, 15W
BuckA 0.015Ω
8.2kΩ
18nF
220pF
39kΩ
1nF
20pF 36kΩ 1nF 47pF
16kΩ
34kΩ
16kΩ
84kΩ
TOP-SW1
BOT-SW1 BOT-SW2
TOP-SW2
TOP-SW3
BOT-SW3
C
330µF
IN
1kΩ
L1
L2 L3
D1
0.03Ω
BOOST —10V, 20W
1.5kΩ
470pF
TPS43335-Q1
TPS43336-Q1
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
www.ti.com
Table 6. Application Example 2
PARAMETER VBuckA VBuckB BOOST
VIN = 5 V to 30 V VIN = 6 V to 30 V VBAT = 5 V (cranking pulse
Input voltage 12 V - typical 12 V - typical input) to 30 V
Output voltage, VOUTx 5 V 2.5 V 10 V
Maximum output current, IOUTx 3 A 1 A 2 A
Load-step output tolerance, ∆VOUT +∆VOUT(Ripple) ±0.2 V ±0.12 V ±0.5 V
Current output load step, ∆IOUTx 0.1 A to 3 A 0.1 A to 1 A 0.1 A to 2 A
Converter switching frequency, fSW 400 kHz 400 kHz 200 kHz
Figure 29. Simplified Application Schematic, Example 2
Table 7. Application Example 2 – Component Proposals
Name Component Proposal Value
L1 MSS1278T-392NL (Coilcraft) 3.9 µH
L2 MSS1278T-822ML (Coilcraft) 8.2 µH
L3 MSS1278T-223ML (Coilcraft) 22 µH
D1 SK103 (Micro Commercial Components)
TOP_SW3 IRF7416 (International Rectifier)
TOP_SW1, TOP_SW2 Si4840DY-T1-E3 (Vishay)
BOT_SW1, BOT_SW2 Si4840DY-T1-E3 (Vishay)
BOT_SW3 IRFR3504ZTRPBF (International Rectifier)
COUT1 EEVFK1V471Q (Panasonic) 470 µF
COUTA ECASD91A157M010K00 (Murata) 150 µF
COUTB ECASD40J107M015K00 (Murata) 100 µF
CIN EEEFK1V331P (Panasonic) 330 µF
34 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS43335-Q1 TPS43336-Q1
TPS43335-Q1
TPS43336-Q1
www.ti.com
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
Power Dissipation Derating Profile, 38-Pin HTTSOP PowerPAD Package
Figure 30. Derating Profile for Power Dissipation Based on High-K JEDEC PCB
PCB Layout Guidelines
Grounding and PCB Circuit Layout Considerations
Boost converter
1. The path formed from the input capacitor to the inductor and BOT_SW3 with the low-side current-sense
resistor should have short leads and PC trace lengths. The same applies for the trace from the inductor to
Schottky diode D1 to the COUT1 capacitor. Connect the negative terminal of the input capacitor and the
negative terminal of the sense resistor together with short trace lengths.
2. The overcurrent-sensing shunt resistor may require noise filtering, and the filter capacitor should be close to
the IC pin.
Buck Converter
1. Connect the drain of TOP_SW1 and TOP_SW2 together with the positive terminal of input capacitor COUT1.
The trace length between these terminals should be short.
2. Connect a local decoupling capacitor between the drain of TOP_SWx and the source of BOT_SWx.
3. The Kelvin-current sensing for the shunt resistor should have traces with minimum spacing, routed in parallel
with each other. Place any filtering capacitors for noise near the IC pins.
4. The resistor divider for sensing the output voltage connects between the positive terminal of its respective
output capacitor and COUTA or COUTB and the IC signal ground. Do not locate these components and their
traces near any switching nodes or high-current traces.
Other Considerations
1. Short PGNDx and AGND to the thermal pad. Use a star ground configuration if connecting to a non-ground
plane system. Use tie-ins for the EXTSUP capacitor, compensation-network ground, and voltage-sense
feedback ground networks to this star ground.
2. Connect a compensation network between the compensation pins and IC signal ground. Connect the
oscillator resistor (frequency setting) between the RT pin and IC signal ground. Do not locate these sensitive
circuits near the dv/dt nodes; these include the gate-drive outputs, phase pins, and boost circuits (bootstrap).
3. Reduce the surface area of the high-current-carrying loops to a minimum by ensuring optimal component
placement. Locate the bypass capacitors as close as possible to their respective power and ground pins.
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 35
Product Folder Links: TPS43335-Q1 TPS43336-Q1
VBAT
DS
GC1
GC2
CBA
GA1
PHA
GA2
PGNDA
SA1
SA2
FBA
COMPA
SSA
PGA
ENA
ENB
COMPC
ENC
V IN
EXTSUP
D IV
VREG
CBB
GB1
PHB
GB2
PGNDB
SB1
SB2
FBB
COMPB
SSB
PGB
AGND
RT
DLYAB
SYNC
VBUCKA
VBUCKB
POW ER
INPUT
VBOOST
Exposed Pad
connec ted to G ND
P lane
M ic rocon tro lle r
Power L ines
Connec tion to GND P lane o fPCB th rough v ias
Connec tion to top /bo ttom o fPCB th rough v ias
Vo ltage R a ilO u tpu ts
TPS43335-Q1
TPS43336-Q1
SLVSAV6D –JUNE 2011–REVISED APRIL 2013
www.ti.com
PCB Layout
Space
Space
Space REVISION HISTORY
Changes from Revision B (July 2012) to Revision C Page
• Corrected AEC specification in ESD maximum ratings ........................................................................................................ 3
• Corrected TYP value for Vsense in Electrical Characteristics ................................................................................................. 6
• Corrected capacitor value ................................................................................................................................................... 21
• Added a paragraph to the Gate-Driver Supply section ....................................................................................................... 21
36 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS43335-Q1 TPS43336-Q1
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
TPS43335QDAPRQ1 ACTIVE HTSSOP DAP 38 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 TPS43335Q1
TPS43336QDAPRQ1 ACTIVE HTSSOP DAP 38 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 105 TPS43336Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS43335QDAPRQ1 HTSSOP DAP 38 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1
TPS43336QDAPRQ1 HTSSOP DAP 38 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Sep-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS43335QDAPRQ1 HTSSOP DAP 38 2000 367.0 367.0 45.0
TPS43336QDAPRQ1 HTSSOP DAP 38 2000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Sep-2013
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated
