Application Note, Revision 1
August 28, 2003 Frequently Asked Questions About TSWC0x622/TSYN0x622 Devices
Agere Systems Inc. 3
Question 6. Are there any suggested considerations for board design and layout?
Answer: Yes, please see application note: Helpful Hints for a Successful TSYN TSWC0x622 Schematic.
6 Jitter, Phase Noise, and MTIE Performance
Question 1. Do the TSWC0x622 devices meet the ITU and the Telcordia ® standard MTIE requirements?
Answer: Yes, the TSWC0x622 devices meet transient and nontransient MTIE (maximum time interval error) require-
ments for all input and output clock rate combinations.
Question 2. What is the jitter/phase noise performance of the TSWC01622 and the TSYN01622 devices?
Answer: Typical measurements for the 155 MHz and 622 MHz outputs show about 1.7 ps of phase noise. This perfor-
mance is good for most OC-48 applications. Recommendations are available for using the TSWC01622/
TSYN01622 in an OC-192 application, please contact the FAE.
7 Holdover
Question 1. Do the TSWC0x622/TSYN0x622 devices support holdover?
Answer: Standalone, the TSWC/TSYN devices do not implement holdover. The devices can support limited holdover
(tens to hundreds of milliseconds) for typical applications. (An application note is available with more detailed
information.) True standards compatible holdover can be implemented externally. This external solution is un-
der consideration, please contact the FAE for more information.
Question 2. Do the TSWC0x622/TSYN0x622 devices support stratum 3 or stratum 3E?
Answer: Stratum 2/3/3E/4 compliancy is a system spec, therefore designers are free to do as they may. Historically, the
major component costs for system timing card switching solutions are at least several hundred dollars, and
major component costs for a line card solution are less than half of that cost. One reason why customers gen-
erally just put the stratum compliancy guarantee on the system timing card is cost. There are some systems
with 1500 line cards, but even with ordinary systems consisting of 20—30 line cards, it makes a lot more fiscal
sense to put all the stringent requirements just on the 2 system timing cards and put as little as possible on the
line card. (Smaller systems with just a few cards tend to do a hybrid mix of requirements, if they choose to meet
them at all.) When using a TSWC0x622/TSYN0x622, as long as the TSWC0x622/TSYN0x622 has a stratum
reference clock valid on its A or B input, the clock on the output will still be stratum traceable and have exactly
the same accuracy as the clock on its input. One of the major features that is required for stratum 3/3E support
is holdover. Standalone, the TSWC0x622/TSYN0x622 devices do not implement holdover. Holdover can be
implemented externally. This external solution is under consideration, please contact the FAE for more infor-
mation.
8 Serial Interface
Question 1. What can be accomplished through the serial interface vs. external pins?
Answer: The serial interface has all control of the external pins and adds more flexibility. Some of the added flexibility
include:
■Ability to program each individual CKPDHx output to any desired frequency (within range) through fractional synthesis.
■Ability to enable or disable each clock and sync output individually.
■Ability to program sync offset over the entire 8 kHz period.
■Ability to control exact duty cycle of sync outputs.