L I N E S C A N S E N S O R S DALSA IL-P1-4096E Image Sensors The IL-P1-4096E sets new line scan standards. Its unprecedented design and fabrication sophistication has produced superior performance: high blue response and low image lag, two taps for high line rates, low-voltage clocks--and DALSA's standard 100% fill factor. Features n n n n n n n n 2 taps @ 25MHz data rate per tap Line rates to 12kHz Low voltage clocks (<5V) 10m (H) x 10m (V) pixels, 100% fill factor 4096 pixels Antiblooming and exposure control Highly sensitive, with responsivity reaching 13.8V/(J/cm2) RoHS compliant Description Physical Characteristics IL-P1-4096E Pixel dimensions 10m x 10m Active area 10m x 41mm Active pixels per line 4096 Isolation pixels per line 14 Shielded pixels per line 32 Table 1. Pin Functional Description Pin 1 2,18 3 4 5 6, 22 7, 23 8 9 10 11, 28 12, 27 14, 15, 17, 19 16 20, 21, 26 24 13, 25, 29 30 31 32 03-036-00183-07 www.dalsa.com Symbol VLOW VDD OS1 VSET CRLAST CR1S CR2S TCK PR VPR CR1B CR2B VHIGH NC VBB VSTOR VSS OS2 VOD RST Name Low Bias Voltage Amplifier Supply Voltage Output Signal 1 Output Node Set Gate Voltage Readout Clock, Last storage phase Readout Clock, Phase 1--Storage Phase Readout Clock, Phase 2Storage Phase Transfer Clock Pixel Reset Clock Pixel Reset Drain Voltage Readout Clock, Phase 1Barrier Phase Readout Clock, Phase 2--Barrier Phase High Bias Voltage No Connection Substrate Bias Voltage Storage Well Voltage Ground Reference Output Signal 2 Output Reset Drain Voltage Output Reset Clock VLOW VDD OS1 VSET CRLAST CR1S CR2S TCK PR VPR CR1B CR2B VSS VHIGH VHIGH NC DALSA Corp.: Phone: 519-886-6000 Fax: 519-886-8023 DALSA EUROPE: Phone: +49-8142-46770 Fax: +49-8142-467746 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 RST VOD OS2 VSS CR1B CR2B VBB VSS VSTOR CR2S CR1S VBB VBB VHIGH VDD VHIGH 1 ISO 9001 IL-P1-4096E Line Scan Sensors For product information and updates visit www.dalsa.com Figure 1. Block Diagram CR1S, CR2S, CR1B, CR2B, CRLAST OS2 5I C C D ReadoutShiftRegister 4I Storage Well with Exposure Control and Reset Structure 32 S 4I N Photoelem ents(10 m x10m ) 4I TCK 32 S VSTOR PR VPR Storage Well with Exposure Control and Reset Structure VDD 5I C C D ReadoutShiftRegister 4I 32 S Light-shielded pixels 4 I Isolation pixels N = 4096 VBB OS1 RST VOD CR1S, CR2S, CR1B, CR2B, CRLAST VSET VSS Relative position of package Pin 1 1 Table 3. # of DC Biases Required Table 2. # of Clock Drivers Required Clock Drivers 2. 2 Speed PR off PR on Regulated? PR off PR on High 3 3 Yes 10 9 2 No 3 3 Low 1 Redundant clock drivers may be required to drive the CCD input capacitance. Refer to Figure 7 for details. PR = Pixel Reset (exposure control). The IL-P1-4096E sensor's superior performance makes it ideally suited for applications requiring maximum speed and high resolution, such as: n n 2 Low DALSA's IL-P1-4096E series of linear CCD image sensors use proprietary technology to provide two outputs at 25 MHz each. The series employs buried channel CCD shift registers to maximize output speed and reduce noise. The sensor has a dynamic range of >3200:1 and provides output which is linear for the operating range of light input. The IL-P1-4096E's exposure control allows integration times shorter than the readout time. Proprietary DALSA image sensor architecture provides low image lag pixels and high blue response. n # Required 1 DC Biases Voltage High 1. Min. # Required 1 High performance document scanning Inspection Optical character recognition Functional Description The IL-P1-4096E sensor is composed of three main functional groups: photodiodes in which the signal charge packets are generated, two CCD readout shift registers, and two output amplifiers where the charge packets are converted to voltage pulses. 2 ISO 9001 1. 2. Refer to Figure 7 for details. PR = Pixel Reset (exposure control). Detection The IL-P1-4096E series includes sensors with 4096 pixels with active imaging area lengths of 41mm. Photoelements are 10m square for a photosensitive area of 100m2 and a 1:1 aspect ratio. Light incident on these photoelements is converted into charge packets whose size (i.e., number of electrons) is linearly dependent on the light intensity and the integration time. The charge is collected into a separate storage well (VSTOR) adjacent to each photoelement. This helps to minimize both image lag and nonuniformities associated with the use of pixel reset. With exposure control disabled, integration time is the period between successive pulses of the transfer (TCK) clock. Integration time can be further reduced with electronic exposure control using the pixel reset (PR) clock. The pixel reset clock resets not the photoelements themselves but the storage well adjacent to each photoelement. When PR is clocked, the integration time becomes the duration between the falling edge of the PR clock and the rising edge of the TCK clock. When PR is clocked, the PR pulse must be damped to produce a smooth PR pulse. If PR switches too rapidly, the uniformity of the OSn signals will be affected by the PR clock feedthrough. Antiblooming is always present when biases fall within the specified operating conditions. By adjusting VSTOR however, the user has the added flexibility of selecting the antiblooming DALSA Corp.: Phone: 519-886-6000 Fax: 519-886-8023 DALSA EUROPE: Phone: +49-8142-46770 Fax: +49-8142-467746 03-036-00183-07 www.dalsa.com For product information and updates visit www.dalsa.com level (the signal level beyond which additional signal charges are drained away). A higher VSTOR bias results in a higher antiblooming level. Transfer The TCK clock controls the transfer of electrons from the storage well into two discrete readout registers for alternating odd/even pixel readout. Transfer is from the storage wells into the CR1 phases of the readout registers. The readout registers are then used to serially shift the charge packets to the two high-speed low-noise output amplifiers. The two readout registers are pseudo-2-phase buried-channel CCD shift registers. The CR1x and CR2x phases are complements of each other. Each of these two phases has a storage (CRxS) and a barrier (CRxB) gate. The storage and barrier gates of each phase are clocked in phase (i.e., CR1S is clocked in phase with CR1B, and CR2S is clocked in phase with CR2B). The only difference between the storage and barrier phase clocks is the bias levels applied to these clocks. AC-coupling and then DC-shifting the CRxS phases will produce the CRxB phases. The final storage electrode of each readout register is connected separately to CRLAST. CRLAST should be clocked in phase with CR1. All CR clocks operate with 50% duty cycle. Unlike CR1 and CR2, the CRLAST pin is connected to only two CCD gates, one for each of the two CCD shift registers on each side. Consequently, the CRLAST capacitance is much smaller than the CR1 or CR2 capacitance. To prevent CRLAST from switching much faster than CR1 and CR2, we recommend that a 100 resistor be connected in series with CRLAST. The CRLAST clock should preferably have a slower rise and fall time than CR1 and CR2. Additional details on driving the sensor are provided on Figure 7. 03-036-00183-07 www.dalsa.com IL-P1-4096E Line Scan Sensors Output The signal charge packets from the readout shift registers are transferred serially from the last readout gate (CRLAST), over the set gate (VSET), to a floating sense node diffusion. The set gate isolates the sense node diffusion from the last readout gate and the rest of the readout shift register. As signal charge accumulates on the floating node diffusion, the potential of this diffusion decreases. The floating node diffusion is connected to the input of a 2.5-stage low-noise amplifier, producing an output signal voltage on the amplifier output (OSn). The floating diffusion is cleared of signal charge by the reset gate (RST) in preparation for the next signal charge packet. The voltage level of the floating diffusion after each reset is determined by the output reset drain voltage (VOD). AC coupling the output is recommended to eliminate the DC offset. Each of the output signals (OSn) requires an off-chip load drawing approximately 8mA of load current. If the sensor is running at greater than 35MHz data rate, or if the load capacitance (CLOAD) is greater than 10pF, larger load current (up to the 18mA limit) may be required. As the load current increases, the amplifier bandwidth increases. The amplifier can also drive larger capacitive loads when the load current is larger. We recommend however that just enough bandwidth be used since larger bandwidth also results in increased noise. If an off-chip current load is not available, each of the amplifier outputs (OSn) can be connected to a 1.2k load resistor. The use of a passive (resistive) load reduces the amplifier gain, resulting in lower responsivity and saturation output signal. The variations in charge conversion efficiency among the various outputs of the sensor, along with component variations in the drive electronics, result in output gain mismatch. To match outputs, we recommend that the camera electronics incorporate gain correction. The isolation pixels should not be used for calibration or detection. DALSA Corp.: Phone: 519-886-6000 Fax: 519-886-8023 DALSA EUROPE: Phone: +49-8142-46770 Fax: +49-8142-467746 3 ISO 9001 IL-P1-4096E Line Scan Sensors For product information and updates visit www.dalsa.com Table 4. Absolute Maximum Ratings Parameter Unit Min. Max. Storage Temp C -20 80 Operating Temp C -20 60 Voltage on CR1x, CR2x, CRLAST, RST, VSET, VSTOR, TCK, PR with respect to VBB V -10 18 Voltage on OSn, VDD, VOD, VSS, VPR, VHIGH with respect to VBB V 0 18 V VDD-8 VDD+1 Voltage on OSn with respect to VSS Amplifier Load Current (ILOAD) mA per output 20 WARNING: Exceeding these values will void product warranty and may damage the device. Applying the VBB bias before the other biases will help ensure that the above conditions are maintained. Likewise, removing the VBB bias last is also recommended. Table 5. Input/Output Characteristics Input Characteristics: Capacitance to VBB 1 Unit Typical 4096 from CR1S, CR2S pF 400 from CR1B, CR2B2 pF 440 from CRLAST pF 12 from RST pF 10 from PR pF 200 from TCK pF 370 Output Impedance (ROUT)4 180 with ILOAD = 8mA Amplifier Supply Current (IDD) 5 mA 36mA with ILOAD = 8mA V 10V with ILOAD = 8mA 1 Output Characteristics: DC Output Offset (VOS) 6 Notes: 1. Using 1V pk-pk 1MHz signal with +5V DC offset. 2. The two CR1S pins (pins 6 and 22) are internally connected, as are the two CR2S pins (pins 7 and 23). 3. The two CR1B pins (pins 11 and 28) are not internally connected, nor are the two CR2B pins (pins 12 and 27). Capacitance values indicated refer to the total capacitance of the two CRxB pins. 4. In general, ROUT () ~ 520 * (ILOAD)-0.5, ILOAD in mA. 5. In general, IDD (mA) = 2 * (10 + ILOAD), ILOAD in mA. 6. In general, VOFFSET (V) = 0.003 * (ILOAD)2 - 0.22 * (ILOAD) + 11.5, ILOAD in mA. 4 ISO 9001 DALSA Corp.: Phone: 519-886-6000 Fax: 519-886-8023 DALSA EUROPE: Phone: +49-8142-46770 Fax: +49-8142-467746 03-036-00183-07 www.dalsa.com IL-P1-4096E Line Scan Sensors For product information and updates visit www.dalsa.com Table 6. DC Operating Conditions Symbol ILOAD Description Unit Load current to each output (OSn) Min. Rec. 1 Max. mA 7.5 8.0 18.0 VDD Amplifier supply voltage V 13.5 14.0 15.0 VOD Output reset drain voltage V 11.0 11.3 11.5 VSET Output node set gate voltage V -0.3 0 0.5 VSTOR 3 Storage well voltage V -0.5 0.5 1.0 VPR Pixel reset drain voltage V 13 14 15 VBB Substrate bias V -3 -2 -1 VLOW 4 Low bias voltage V VBB VBB VBB VHIGH High bias voltage V 13 14 15 VSS Ground Reference V 2 0 Notes: 1. When deviating from the recommended biases, ensure that the new biases meet the essential bias conditions listed in Table 8. 2. ILOAD needs to be > 10mA only if RST > 35MHz or CLOAD > 10pF. 3. VSTOR may be adjusted to affect the antiblooming level. VSAT decreases by 418mV for every 1.0V reduction in VSTOR. 4. If your implementation uses separate digital and analog grounds, connect VLOW to the digital ground. 03-036-00183-07 www.dalsa.com DALSA Corp.: Phone: 519-886-6000 Fax: 519-886-8023 DALSA EUROPE: Phone: +49-8142-46770 Fax: +49-8142-467746 5 ISO 9001 IL-P1-4096E Line Scan Sensors For product information and updates visit www.dalsa.com Table 7. AC Operating Conditions Unit Min. Rec. Max. CRx All CR Clocks swing* V 4.5 5.0 6.5 CRxS Readout Register Clocks (storage phase) Readout Register Clocks (barrier phase) Readout Register Clocks (last storage phase) Reset Clock offset* V 0 0 0.5 offset V -4.5 -4.0 -3.5 offset V -1 -0.8 -0.5 offset V 0.2 0.5 0.7 swing V 4.8 5.5 6.5 offset V VBB 0 0 swing V 6 7 8.5 offset V 0.5 1.2 1.5 swing V 6 7 10 Symbol CRxB CRLAST RST TCK PR Description Transfer Clock Pixel Reset Clock RST Data rate per output MHz 25 40 DATA Effective data rate MHz 50 80 LINE Line rate 4096 kHz 12.0 19.2 Notes: 1. When deviating from the recommended biases, ensure that the new biases meet the essential bias conditions listed in Table 8. Swing * Offset Table 8. Essential Bias Conditions Conditions 6 ISO 9001 If condition not satisfied, the sensor will exhibit... CR1S high + 3.5 > TCK high > VSTOR + 4.5 Larger lag PR high > VSTOR + 4 High PRNU when exposure control is enabled RST high + 5.5 > VOD Poor MTF DALSA Corp.: Phone: 519-886-6000 Fax: 519-886-8023 DALSA EUROPE: Phone: +49-8142-46770 Fax: +49-8142-467746 03-036-00183-07 www.dalsa.com IL-P1-4096E Line Scan Sensors For product information and updates visit www.dalsa.com Table 9. Performance Specifications Specification Saturation Output Voltage (VSAT) rms Noise Wavelength of Peak Responsivity Peak Responsivity Dynamic Range Charge Conversion Efficiency (CCE) Noise Equivalent Exposure (NEE) Saturation Equivalent Exposure (SEE) Full Well Capacity PR exposure control disabled Fixed Pattern Noise (FPN) 1,2 PR exposure control enabled Photoresponse Non-Uniformity (PRNU) 3,4 PR exposure control disabled 8 pixel local neighborhood PR exposure control enabled Unit Min. Typ. Max. mV mV nm V/(J/cm2) 700 900 0.28 700 13.8 3200:1 5.7 20 65 158 0.5 2.0 1100 0.31 V/epJ/cm2 nJ/cm2 kemV mV % OS 12.6 2250:1 5.4 18 45 115 15.5 3900:1 6.1 25 1.0 5.0 2.2 6.0 Global 3.5 8.5 8 pixel local neighborhood 2.5 6.5 Global 3.8 8.8 0.999999 11.5 0.15 0.5 Charge Transfer Efficiency (CTE) (readout register) First Field Lag 5 Dark Signal, Integration time = 84s 0.99999 mV mV Notes: 1. Maximum peak-to-peak variation of all outputs. 2. Due to its general purpose design, DALSA's camera and sensor evaluation hardware provides an output that cannot be used to directly measure low FPN. 3. The peak-to-peak variation is measured at ~50% SEE. 4. With output gain mismatch correction. 5. Lag is measured at VSAT with LINE = 10kHz. Test Conditions: n Operating temperature = 35C. n RST = data rate per output = 25MHz. n ILOAD = 8mA. n CLOAD = 10pF. n Tungsten halogen light source, black body color temperature 3200K, filtered with 750nm IR cutoff filter. n See Sensor Measurement Definitions (doc# 03-36-00149) for specification definitions. Life Support Applications These products are not designed for use in life suppor t appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. DALSA customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify DALSA for any damages resulting from such improper use or sale. 03-036-00183-07 www.dalsa.com DALSA Corp.: Phone: 519-886-6000 Fax: 519-886-8023 DALSA EUROPE: Phone: +49-8142-46770 Fax: +49-8142-467746 7 ISO 9001 IL-P1-4096E Line Scan Sensors For product information and updates visit www.dalsa.com Figure 2. Performance Measurements 340 W/cm 85 W/cm 100 (%) 12 10 8 6 4 2 0 400 500 600 700 800 900 1000 Wavelength (nm) Signal Output Saturation Output 2 Responsivity [V/( J/cm )] 14 80 60 40 20 34 W/cm 0 0.2 0.4 0.6 0.8 1.0 Integration Time (ms) Output vs. Integration Time (@700nm) Responsivity Table 10. Timing Parameters Symbol Description tCR Period of CRx clocks t1 Integration time (PR disabled) Unit Min. Rec. Max. t2 Integration time (PR enabled) t3 TCK to first valid pixel pixels 23 t4 Overclock pixels pixels 0 23 t5 CRxB falling edge to CRxS falling edge ns 0 0 0.25tCR t6 CR1B falling edge to CRLAST falling edge ns 0 0 0.25tCR t7 TCK high overlap with CR1S high ns 200 300 23 t8 TCK falling edge to CR1S falling edge ns 2 t9 CRLAST rising to RST rising edge ns 0 0.5tCR - t11 0.5tCR - t11 t10 RST falling edge to CRLAST falling edge ns 0 0 0.5tCR-t11 t11 RST pulse width (FWHM)1 ns 5 5 0.25tCR t12 CR1x and CR2x rise and fall time ns 2 5 0.25tCR t13 CRLAST rise and fall time ns t12 t12 + 1 0.25tCR Notes: 1. Full Width Half Maximum 8 ISO 9001 DALSA Corp.: Phone: 519-886-6000 Fax: 519-886-8023 DALSA EUROPE: Phone: +49-8142-46770 Fax: +49-8142-467746 03-036-00183-07 www.dalsa.com IL-P1-4096E Line Scan Sensors For product information and updates visit www.dalsa.com Figure 3. Overall Timing CR1x CR2x CRLAST t1 TCK RST t2 PR OSn Line 1 Line 2 Active Pixels t3 Line 3 t3 t4 Figure 4. Detailed Readout Register Timing t8 t5 t12 t12 CR1S tCR CR1B t5 CR2S CR2B t10 t6 CRLAST t7 t9 TCK t13 t13 t11 RST OSn Overclock Overclock Pixel Pixel Isolation Pixel Isolation Pixel Figure 5. Gate Structure Diagram VPR VDD Pixel PR OS VSTOR n+ VSS TCK n+ CR1B CR1S 03-036-00183-07 www.dalsa.com CR2B CR2S CR1B CR1S CR2B CR2S CR1B CRLAST DALSA Corp.: Phone: 519-886-6000 Fax: 519-886-8023 DALSA EUROPE: Phone: +49-8142-46770 Fax: +49-8142-467746 VSET n+ RST VOD 9 ISO 9001 10 ISO 9001 DALSA Corp.: Phone: 519-886-6000 Fax: 519-886-8023 DALSA EUROPE: Phone: +49-8142-46770 Fax: +49-8142-467746 OC OC OC OS2 OS3 OS4 OC OC OC OC I Isolation Pixel. S Light-Shielded Pixel. OC Overclock Pixel. Sample video OC OS1 RST TCK CRLAST CR2x CR1x I1 I1 I1 I1 I5 I5 I5 I5 S1 S1 S1 S1 S16 S16 S16 S16 I6 I6 I6 I6 I7 I7 I7 I7 Pixel N Pixel N-1 Pixel 2 Pixel 1 Pixel N-2 Pixel N-3 Pixel 4 Pixel 3 OC OC OC Pixel N/2 Pixel N/ 2+1 Pixel N/ 2+2 Pixel N/ 2-2 Pixel N/ 2+3 Pixel N/ 2+4 OC Pixel N/ 2-1 Pixel N/ 2-3 IL-P1-4096E Line Scan Sensors For product information and updates visit www.dalsa.com Figure 6. Readout Register Timing 03-036-00183-07 www.dalsa.com 03-036-00183-07 www.dalsa.com RST CR22=CR1 CR11 PR (with exposure control) TCK Low-speed High-voltage Clock Drivers DALSA Corp.: Phone: 519-886-6000 Fax: 519-886-8023 DALSA EUROPE: Phone: +49-8142-46770 Fax: +49-8142-467746 VSET-L, VSET-R (PIN 4,20) VSET ILOAD BIAS 7 VSTOR (PINS 3,14,19,30) (PINS 26) VBB VBB OSx (PINS 13,25,29) VSS-L, VSS-R VSS 10k (PINS 2,18) (PIN 24) (PIN 15) VDD VDD6 VSTOR (PINS 31) VOD-R VOD-L VOD-R 511 (PINS 1) VLOW VLOW (PIN 8) TCK (PIN 10) (PIN 17,32) RST-L, RST-R VPR (PINS 7,23)3,4 CR2S (PINS 11,27)4 (PINS 12,28)4 CR1B-R CR1B-L, CR2B-R CR2B-L, (PINS 6,22)3,4 (PIN 5)5 CR1S CRLAST-L, CRLAST-R VPR 1k 10k 10k 100 10k (PIN 9) OSx Buffer 100nF 100nF 100nF Possible Interface Circuitry PR Non-Critical DC Bias VOD-L PR (without exposure control) CRxBBIAS CRLAST BIAS Regulated DC Bias For product information and updates visit www.dalsa.com IL-P1-4096E Line Scan Sensors Figure 7. Sensor Operation Connections 11 ISO 9001 IL-P1-4096E Line Scan Sensors For product information and updates visit www.dalsa.com Notes to Figure 7. 1. 2. 3. 4. a. b. c. 5. 6. 7. Clock drivers are designed to drive only up to a maximum capacitance (CMAX) at a given clock frequency. If the total capacitances of CRLAST, CR1S, and CR1B (see Table 5) exceed CMAX, more than one CR1 driver is required. Clock drivers are designed to drive only up to a maximum capacitance (CMAX) at a given clock frequency. If the total capacitances of CR2S and CR2B (see Table 5) exceed CMAX, more than one CR2 driver is required. Both pins should be connected to clock drivers, though not necessarily to the same clock driver. If more than one clock driver is used, it is acceptable to drive each pin from separate drivers. Although the sensors are sufficiently robust that the rise and fall times of CRxS and CRxB do not need to be very closely matched, performance is more optimal, particularly with the 4096-pixel part, if attempts are made to match the CRxS and CRxB rise and fall times. If more than one CRx clock driver is used, time constants are more closely matched if the sensor is driven using either one of the following configurations: Drive the CRxS pins with n CRx drivers. Tie the CRxB pins together. Drive the CRxB pins with a separate set of n CRx drivers. Drive the CRxS pins with 2n CRx drivers. Drive each CRxB pin separately with separate sets of n CRx drivers. Connect a 10 resistor in series with CRxS. Drive the CRxS pins with n CRx clock drivers. Connect a 20 resistor in series with each CRxB pin. Drive each CRxB pin with separate sets of n CRx drivers. Note that the CRxS pins are internally connected together, while the CRxB pins are not. CRLAST should not have a fall time that is much faster than the fall time of CR1B. Unlike CR1B however, the CRLAST pin is connected to only two CCD gates, one for each of the CCD shift registers. Consequently, the CRLAST capacitance is much smaller than the CR2B capacitance. This is not an issue if the CRLAST clock is tapped from CR1. However, if CRLAST is being driven from a separate driver, we recommend that a 150 resistor be connected in series with CRLAST. Need to source IDD = 2 * (10 + ILOAD) mA. May have an optional antiblooming level adjustment. ISO 9001 DALSA maintains a registered quality system meeting the ISO 9001 standard. 12 ISO 9001 DALSA Corp.: Phone: 519-886-6000 Fax: 519-886-8023 DALSA EUROPE: Phone: +49-8142-46770 Fax: +49-8142-467746 03-036-00183-07 www.dalsa.com IL-P1-4096E Line Scan Sensors For product information and updates visit www.dalsa.com Figure 8. Package Dimensions 4096 57.300.56 28.70.3 TO CL OF OPTICAL AREA 1.10.3 DIE TO WINDOW SURFACE No. 25 No. 24 No. 8 No. 9 0.40.1 No. 17 2.80.3 0.3 Pixel 1 +0.05 -0.03 No. 16 12.70.3 12.450.20 6.20.3 TO CL OF OPTICAL AREA No. 32 1.7780.13 12.450.13 1.7780.13 30.230.13 12.450.13 5.00.3 0.50.1 Notes: 1. Dimensions are in mm. 2. Maximum die rotation is 0.6. 20 03-036-00183-07 www.dalsa.com DALSA Corp.: Phone: 519-886-6000 Fax: 519-886-8023 DALSA EUROPE: Phone: +49-8142-46770 Fax: +49-8142-467746 13 ISO 9001 IL-P1-4096E Line Scan Sensors For product information and updates visit www.dalsa.com Table 11: Revision History Revision Description 00 Document Release 01 Updated sensor mechanicals in Figure 8. Former diagrams were too detailed. 02 Under Features on page 1, changed "Line rates to 12kHz" to "Line rates to 23.7kHz". Was incorrect. 03 Changed Pin 13 label in figure from VLOW to VSS in Table 1 04 Changed last sentence on page 3 from "To match outputs. we recommend that the camera electronics incorporate a gain correction of up to 15%" to "To match outputs. we recommend that the camera electronics incorporate gain correction." This removes the chance that customers interpret 15% as a specification. This was only intended as a guideline or recommendation. 05 Added "The isolation pixels should not be used for calibration or detection" to the Functional DescriptionaOutput section. 06 07 14 ISO 9001 Added "RoHs compliant" to Features section on page 1. Added lead-free logo to Figure 8 Figure 8, package dimensions, some dimensions and tolerances revised. Added RoHS logo to Figure 8. DALSA Corp.: Phone: 519-886-6000 Fax: 519-886-8023 DALSA EUROPE: Phone: +49-8142-46770 Fax: +49-8142-467746 03-036-00183-07 www.dalsa.com