IL-P1-4096E - Teledyne Technologies Incorporated

LINE SCAN SENSORS

DALSA IL-P1-4096E

Image Sensors

The IL-P1-4096E sets new line scan standards. Its unprece-

dented design and fabrication sophistication has produced

superior performance: high blue response and low image lag,

two taps for high line rates, low-voltage clocks—and

DALSA’s standard 100% fill factor.

Features

n2 taps @ 25MHz data rate per tap

nLine rates to 12kHz

nLow voltage clocks (<5V)

n10µm (H) x 10µm (V) pixels, 100% fill factor

n4096 pixels

nAntiblooming and exposure control

nHighly sensitive, with responsivity reaching

13.8V/(µJ/cm2)

nRoHS compliant

Description

Physical Characteristics IL-P1-4096E

Pixel dimensions 10µm x 10µm

Active area 10µm x 41mm

Active pixels per line 4096

Isolation pixels per line 14

Shielded pixels per line 32

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32 RST

31 VOD

30 OS2

29 VSS

28 CR1B

27 CR2B

26 VBB

25 VSS

24 VSTOR

23 CR2S

22 CR1S

21 VBB

20 VBB

19 VHIGH

VDD

VHIGH

VLOW 1

VDD 2

OS1 3

VSET 4

CRLAST 5

CR1S 6

CR2S 7

TCK 8

PR 9

VPR 10

CR1B 11

CR2B 12

VSS 13

VHIGH 14

VHIGH 15

NC 16

Pin Symbol Name

1 VLOW Low Bias Voltage

2,18 VDD Amplifier Supply Voltage

3 OS1 Output Signal 1

4 VSET Output Node Set Gate Voltage

5 CRLAST Readout Clock, Last storage phase

6, 22 CR1S Readout Clock, Phase 1—Storage Phase

7, 23 CR2S Readout Clock, Phase 2⎯Storage Phase

8 TCK Transfer Clock

9 PR Pixel Reset Clock

10 VPR Pixel Reset Drain Voltage

11, 28 CR1B Readout Clock, Phase 1⎯Barrier Phase

12, 27 CR2B Readout Clock, Phase 2—Barrier Phase

14, 15, 17, 19 VHIGH High Bias Voltage

16 NC No Connection

20, 21, 26 VBB Substrate Bias Voltage

24 VSTOR Storage Well Voltage

13, 25, 29 VSS Ground Reference

30 OS2 Output Signal 2

31 VOD Output Reset Drain Voltage

32 RST Output Reset Clock

Table 1. Pin Functional Description

DALSA’s IL-P1-4096E series of linear CCD image sensors use

proprietary technology to provide two outputs at 25 MHz each.

The series employs buried channel CCD shift registers to maxi-

mize output speed and reduce noise. The sensor has a dynamic

range of >3200:1 and provides output which is linear for the op-

erating range of light input. The IL-P1-4096E’s exposure control

allows integration times shorter than the readout time. Proprie-

tary DALSA image sensor architecture provides low image lag

pixels and high blue response.

The IL-P1-4096E sensor’s superior performance makes it ide-

ally suited for applications requiring maximum speed and high

resolution, such as:

nHigh performance document scanning

nInspection

nOptical character recognition

Functional Description

The IL-P1-4096E sensor is composed of three main functional

groups: photodiodes in which the signal charge packets are

generated, two CCD readout shift registers, and two output am-

plifiers where the charge packets are converted to voltage

pulses.

Detection

The IL-P1-4096E series includes sensors with 4096 pixels with

active imaging area lengths of 41mm. Photoelements are 10µm

square for a photosensitive area of 100µm2and a 1:1 aspect ra-

tio. Light incident on these photoelements is converted into

charge packets whose size (i.e., number of electrons) is linearly

dependent on the light intensity and the integration time. The

charge is collected into a separate storage well (VSTOR) adja-

cent to each photoelement. This helps to minimize both image

lag and nonuniformities associated with the use of pixel reset.

With exposure control disabled, integration time is the period

between successive pulses of the transfer (TCK) clock. Integra-

tion time can be further reduced with electronic exposure control

using the pixel reset (PR) clock. The pixel reset clock resets not

the photoelements themselves but the storage well adjacent to

each photoelement. When PR is clocked, the integration time

becomes the duration between the falling edge of the PR clock

and the rising edge of the TCK clock.

When PR is clocked, the PR pulse must be damped to produce a

smooth PR pulse. If PR switches too rapidly, the uniformity of

the OSn signals will be affected by the PR clock feedthrough.

Antiblooming is always present when biases fall within the

specified operating conditions. By adjusting VSTOR however,

the user has the added flexibility of selecting the antiblooming

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NPhotoelem ents(10µ m x 10µ m )4I32 S 4I 32 S

CCD ReadoutShiftRegister

TCK

VPR

VSTOR

CR1S, CR2S,

CR1B, CR2B, CRLAST

CR1S, CR2S,

CR1B, CR2B, CRLAST

VSET

VBB

RST

VOD

VSS

VDD

OS1

32 S

Light-shielded pixels

N = 4096

Isolation pixels

OS2

Storage Well with Exposure Control and Reset Structure

Relative position of package Pin 1

Figure 1. Block Diagram

Clock Drivers Min. # Required 1

Voltage Speed PR 2off PR on

Low High 3 3

High Low 1 2

1. Redundant clock drivers may be required to drive the

CCD input capacitance. Refer to Figure 7 for details.

2. PR = Pixel Reset (exposure control).

Table 2. # of Clock Drivers Required

DC Biases # Required 1

Regulated? PR 2off PR on

Yes 10 9

No 3 3

1. Refer to Figure 7 for details.

2. PR = Pixel Reset (exposure control).

Table 3. # of DC Biases Required

level (the signal level beyond which additional signal charges are

drained away). A higher VSTOR bias results in a higher anti-

blooming level.

Transfer

The TCK clock controls the transfer of electrons from the stor-

age well into two discrete readout registers for alternating

odd/even pixel readout. Transfer is from the storage wells into

the CR1 phases of the readout registers. The readout registers

are then used to serially shift the charge packets to the two

high-speed low-noise output amplifiers.

The two readout registers are pseudo-2-phase buried-channel

CCD shift registers. The CR1x and CR2x phases are comple-

ments of each other. Each of these two phases has a storage

(CRxS) and a barrier (CRxB) gate. The storage and barrier gates

of each phase are clocked in phase (i.e., CR1S is clocked in

phase with CR1B, and CR2S is clocked in phase with CR2B).

The only difference between the storage and barrier phase

clocks is the bias levels applied to these clocks. AC-coupling

and then DC-shifting the CRxS phases will produce the CRxB

phases.

The final storage electrode of each readout register is connected

separately to CRLAST. CRLAST should be clocked in phase with

CR1.

All CR clocks operate with 50% duty cycle.

Unlike CR1 and CR2, the CRLAST pin is connected to only two

CCD gates, one for each of the two CCD shift registers on each

side. Consequently, the CRLAST capacitance is much smaller

than the CR1 or CR2 capacitance. To prevent CRLAST from

switching much faster than CR1 and CR2, we recommend that a

100Ωresistor be connected in series with CRLAST. The

CRLAST clock should preferably have a slower rise and fall time

than CR1 and CR2.

Additional details on driving the sensor are provided on Figure 7.

Output

The signal charge packets from the readout shift registers are

transferred serially from the last readout gate (CRLAST), over

the set gate (VSET), to a floating sense node diffusion. The set

gate isolates the sense node diffusion from the last readout gate

and the rest of the readout shift register. As signal charge accu-

mulates on the floating node diffusion, the potential of this diffu-

sion decreases. The floating node diffusion is connected to the

input of a 2.5-stage low-noise amplifier, producing an output

signal voltage on the amplifier output (OSn). The floating diffu-

sion is cleared of signal charge by the reset gate (RST) in prepa-

ration for the next signal charge packet. The voltage level of the

floating diffusion after each reset is determined by the output re-

set drain voltage (VOD). AC coupling the output is recom-

mended to eliminate the DC offset.

Each of the output signals (OSn) requires an off-chip load draw-

ing approximately 8mA of load current. If the sensor is running at

greater than 35MHz data rate, or if the load capacitance (CLOAD)

is greater than 10pF, larger load current (up to the 18mA limit)

may be required. As the load current increases, the amplifier

bandwidth increases. The amplifier can also drive larger capaci-

tive loads when the load current is larger. We recommend how-

ever that just enough bandwidth be used since larger bandwidth

also results in increased noise.

If an off-chip current load is not available, each of the amplifier

outputs (OSn) can be connected to a 1.2kΩload resistor. The

use of a passive (resistive) load reduces the amplifier gain, re-

sulting in lower responsivity and saturation output signal.

The variations in charge conversion efficiency among the vari-

ous outputs of the sensor, along with component variations in

the drive electronics, result in output gain mismatch. To match

outputs, we recommend that the camera electronics incorpo-

rate gain correction.

The isolation pixels should not be used for calibration or

detection.

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Parameter Unit Min. Max.

Storage Temp °C -20 80

Operating Temp °C -20 60

Voltage on CR1x, CR2x, CRLAST, RST, VSET, VSTOR,

TCK, PR with respect to VBB

V -10 18

Voltage on OSn, VDD, VOD, VSS, VPR, VHIGH with

respect to VBB

V018

Voltage on OSn with respect to VSS V VDD-8 VDD+1

Amplifier Load Current (ILOAD) mA per output 20

WARNING: Exceeding these values will void product warranty and may damage the device. Applying the VBB bias before the other

biases will help ensure that the above conditions are maintained. Likewise, removing the VBB bias last is also recommended.

Table 4. Absolute Maximum Ratings

Input Characteristics: Capacitance to VBB 1Unit Typical

4096

from CR1S, CR2S1pF 400

from CR1B, CR2B2pF 440

from CRLAST pF 12

from RST pF 10

from PR pF 200

from TCK pF 370

Output Characteristics:

Output Impedance (ROUT)4Ω180Ωwith ILOAD = 8mA

Amplifier Supply Current (IDD)5mA 36mA with ILOAD = 8mA

DC Output Offset (VOS) 6V 10V with ILOAD = 8mA

Notes:

1. Using 1V pk-pk 1MHz signal with +5V DC offset.

2. The two CR1S pins (pins 6 and 22) are internally connected, as are the two CR2S pins (pins 7 and 23).

3. The two CR1B pins (pins 11 and 28) are not internally connected, nor are the two CR2B pins (pins 12 and 27). Capacitance

values indicated refer to the total capacitance of the two CRxB pins.

4. In general, ROUT (Ω) ~520*(I

LOAD)-0.5,I

LOAD in mA.

5. In general, IDD (mA)=2*(10+I

LOAD), ILOAD in mA.

6. In general, VOFFSET (V) = 0.003 * (ILOAD)2-0.22*(I

LOAD) + 11.5, ILOAD in mA.

Table 5. Input/Output Characteristics

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Symbol Description Unit Min. Rec. 1Max.

ILOAD 2Load current to each output (OSn) mA 7.5 8.0 18.0

VDD Amplifier supply voltage V 13.5 14.0 15.0

VOD Output reset drain voltage V 11.0 11.3 11.5

VSET Output node set gate voltage V -0.3 0 0.5

VSTOR 3Storage well voltage V -0.5 0.5 1.0

VPR Pixel reset drain voltage V 13 14 15

VBB Substrate bias V -3 -2 -1

VLOW 4Low bias voltage V VBB VBB VBB

VHIGH High bias voltage V 13 14 15

VSS Ground Reference V 0

Notes:

1. When deviating from the recommended biases, ensure that the new biases meet the essential bias conditions listed in Table

2. ILOAD needs to be > 10mA only if ƒRST > 35MHz or CLOAD > 10pF.

3. VSTOR may be adjusted to affect the antiblooming level. VSAT decreases by ∼418mV for every 1.0V reduction in VSTOR.

4. If your implementation uses separate digital and analog grounds, connect VLOW to the digital ground.

Table 6. DC Operating Conditions

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Symbol Description Unit Min. Rec. Max.

CRx All CR Clocks swing* V 4.5 5.0 6.5

CRxS Readout Register Clocks (storage

phase)

offset* V 0 0 0.5

CRxB Readout Register Clocks (barrier

phase)

offset V -4.5 -4.0 -3.5

CRLAST Readout Register Clocks

(last storage phase)

offset V -1 -0.8 -0.5

RST Reset Clock offset V 0.2 0.5 0.7

swing V 4.8 5.5 6.5

TCK Transfer Clock offset V VBB 0 0

swing V 6 7 8.5

PR Pixel Reset Clock offset V 0.5 1.2 1.5

swing V 6 7 10

ƒRST Data rate per output MHz 25 40

ƒDATA Effective data rate MHz 50 80

ƒLINE Line rate 4096 kHz 12.0 19.2

Notes:

1. When deviating from the recommended biases, ensure that the new biases meet the essential bias conditions listed in Table

Table 7. AC Operating Conditions

set

Swing

Conditions If condition not satisfied, the sensor will exhibit…

CR1S high + 3.5 > TCK high > VSTOR + 4.5 Larger lag

PR high > VSTOR + 4 High PRNU when exposure control is enabled

RST high + 5.5 > VOD Poor MTF

Table 8. Essential Bias Conditions

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Life Support Applications

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products

can reasonably be expected to result in personal injury. DALSA customers using or selling these products for use in such

applications do so at their own risk and agree to fully indemnify DALSA for any damages resulting from such improper use or

sale.

Specification Unit Min. Typ. Max.

Saturation Output Voltage (VSAT) mV 700 900 1100

rms Noise mV 0.28 0.31

Wavelength of Peak Responsivity nm 700

Peak Responsivity V/(µJ/cm2) 12.6 13.8 15.5

Dynamic Range 2250:1 3200:1 3900:1

Charge Conversion Efficiency (CCE) µV/e-5.4 5.7 6.1

Noise Equivalent Exposure (NEE) pJ/cm218 20 25

Saturation Equivalent Exposure (SEE) nJ/cm245 65

Full Well Capacity ke-115 158

Fixed Pattern Noise (FPN) 1,2 PR exposure control disabled

PR exposure control enabled

0.5

2.0

1.0

5.0

Photoresponse Non-Uniformity (PRNU) 3,4 %OS

PR exposure control disabled 8 pixel local neighborhood 2.2 6.0

Global 3.5 8.5

PR exposure control enabled 8 pixel local neighborhood 2.5 6.5

Global 3.8 8.8

Charge Transfer Efficiency (CTE) (readout register) 0.99999 0.999999

First Field Lag 5mV 11.5

Dark Signal, Integration time = 84µs mV 0.15 0.5

Notes:

1. Maximum peak-to-peak variation of all outputs.

2. Due to its general purpose design, DALSA's camera and sensor evaluation hardware provides an output that cannot be used

to directly measure low FPN.

3. The peak-to-peak variation is measured at ~50% SEE.

4. With output gain mismatch correction.

5. Lag is measured at VSAT with ƒLINE = 10kHz.

Test Conditions:

nOperating temperature = 35°C.

nƒRST = data rate per output = 25MHz.

nILOAD = 8mA.

nCLOAD = 10pF.

nTungsten halogen light source, black body color temperature 3200K, filtered with 750nm IR cutoff filter.

nSee Sensor Measurement Definitions (doc# 03-36-00149) for specification definitions.

Table 9. Performance Specifications

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Responsivity [V/( J/cm)]

Wavelength (nm)

1000800600400 500 700 900

Responsivity

34 W/cm

340 W/cm

85 W/cm

100

(%)

SignalOutput

SaturationOutput

Integration Time (ms)

1.00.80.60.40.2

Output vs. Integration Time

(@700nm)

Figure 2. Performance Measurements

Symbol Description Unit Min. Rec. Max.

tCR Period of CRx clocks

t1Integration time (PR disabled)

t2Integration time (PR enabled)

t3TCK to first valid pixel pixels 23 23

t4Overclock pixels pixels 0 23

t5CRxB falling edge to CRxS falling edge ns 0 0 0.25tCR

t6CR1B falling edge to CRLAST falling edge ns 0 0 0.25tCR

t7TCK high overlap with CR1S high ns 200 300

t8TCK falling edge to CR1S falling edge ns 2

t9CRLAST rising to RST rising edge ns 0 0.5tCR -t

11 0.5tCR -t

t10 RST falling edge to CRLAST falling edge ns 0 0 0.5tCR-t11

t11 RST pulse width (FWHM)1ns 5 5 0.25tCR

t12 CR1x and CR2x rise and fall time ns 2 5 0.25tCR

t13 CRLAST rise and fall time ns t12 t12 + 1 0.25tCR

Notes:

1. Full Width Half Maximum

Table 10. Timing Parameters

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TCK

RST

OSn

CR2x

CRLAST

CR1x

Line 1 Line 2

Active Pixels

Line 3

Figure 3. Overall Timing

TCK

RST

CR2S

CR2B

CRLAST

CR1S

CR1B

OSn Overclock

Pixel

Overclock

Pixel

Isolation

Pixel

Isolation

Pixel

Figure 4. Detailed Readout Register Timing

n+ n+

VDD

VODRST

VSETCRLASTCR1BCR2SCR2S CR2BCR2B

TCK

PRVPR Pixel

VSTOR

CR1SCR1S CR1BCR1B

VSS

Figure 5. Gate Structure Diagram

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RST

TCK

OS1

OS3

OS2

OS4

CR2x

CRLAST

CR1x

Isolation Pixel.

Light-Shielded Pixel.

Overclock Pixel.

Sample video

Pixel

N-1

Pixel

N-3

Pixel

N-2

Pixel

2-3

Pixel

2+3

Pixel

2-2

Pixel

2+4

2-1

Pixel

2+1

Pixel

N/2

Pixel

2+2

S16

Figure 6. Readout Register Timing

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Low-speed

High-voltage

Clock Drivers

Regulated

DC Bias

Non-Critical

DC Bias

Possible

Interface

Circuitry

CRLAST-L,

CRLAST-R

CR1S

CR1B-R

CR1B-L,

CR2B-R

CR2B-L,

CR2S

RST-L, RST-R

TCK

VPR

VLOW

VOD-L

VOD-R

VDD

VSS-L, VSS-R

VBB

VSET-L, VSET-R

VSTOR

OSx

(PIN 5)5

(PINS 6,22)3,4

(PINS 12,28)4

(PINS 11,27)4

(PINS 7,23)3,4

(PIN 17,32)

(PIN 8)

(PIN 9)

(PINS 31)

(PIN 15)

(PINS 2,18)

(PINS 13,25,29)

(PINS 26)

(PIN 4,20)

(PIN 24)

(PINS 3,14,19,30)

(PINS 1)

(PIN 10)VPR

VLOW

VOD-L

VDD6

VSS

VBB

VSET

ILOAD

BIAS

OSx Buffer

VOD-R

CR2 =

2CR1

CR11

RST

TCK

(with

exposure

control)

(without

exposure

control)

CRLAST

BIAS

CRxB-

BIAS

VSTOR7

10k

100nF

10k

511

100

Figure 7. Sensor Operation Connections

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1. Clock drivers are designed to drive only up to a maximum capacitance (CMAX) at a given clock frequency. If the total

capacitances of CRLAST, CR1S, and CR1B (see Table 5) exceed CMAX, more than one CR1 driver is required.

2. Clock drivers are designed to drive only up to a maximum capacitance (CMAX) at a given clock frequency. If the total

capacitances of CR2S and CR2B (see Table 5) exceed CMAX, more than one CR2 driver is required.

3. Both pins should be connected to clock drivers, though not necessarily to the same clock driver. If more than one clock

driver is used, it is acceptable to drive each pin from separate drivers.

4. Although the sensors are sufficiently robust that the rise and fall times of CRxS and CRxB do not need to be very closely

matched, performance is more optimal, particularly with the 4096-pixel part, if attempts are made to match the CRxS and

CRxB rise and fall times. If more than one CRx clock driver is used, time constants are more closely matched if the sensor is

driven using either one of the following configurations:

a. Drive the CRxS pins with n CRx drivers. Tie the CRxB pins together. Drive the CRxB pins with a separate set of n CRx drivers.

b. Drive the CRxS pins with 2n CRx drivers. Drive each CRxB pin separately with separate sets of n CRx drivers.

c. Connect a 10Ωresistor in series with CRxS. Drive the CRxS pins with n CRx clock drivers. Connect a 20Ωresistor in series

with each CRxB pin. Drive each CRxB pin with separate sets of n CRx drivers.

Note that the CRxS pins are internally connected together, while the CRxB pins are not.

5. CRLAST should not have a fall time that is much faster than the fall time of CR1B. Unlike CR1B however, the CRLAST pin is

connected to only two CCD gates, one for each of the CCD shift registers. Consequently, the CRLAST capacitance is much

smaller than the CR2B capacitance. This is not an issue if the CRLAST clock is tapped from CR1. However, if CRLAST is

being driven from a separate driver, we recommend that a 150Ωresistor be connected in series with CRLAST.

6. Need to source IDD =2*(10+I

LOAD) mA.

7. May have an optional antiblooming level adjustment.

Notes to Figure 7.

ISO 9001 DALSA maintains a registered quality system meeting the ISO 9001 standard.

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57.30±0.56

12.45±0.20

1.778±0.13

12.45±0.13 12.45±0.13

30.23±0.13

1.778±0.13

5.0±0.3

Notes:

1. Dimensions are in mm.

2. Maximum die rotation is 0.6°.

1.1±0.3 DIE TO

WINDOW SURFACE

0.4±0.1

2.8±0.3

12.7±0.3

0.3 +0.05

-0.03

28.7±0.3 TO CL

OF OPTICAL AREA

No. 32 No. 25 No. 24 No. 17

6.2±0.3 TO CL

OF OPTICAL AREA

No. 8 No. 9 No. 16

Pixel 1

0.5±0.1

Figure 8. Package Dimensions

4096

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Revision Description

00 Document Release

01 Updated sensor mechanicals in Figure 8. Former diagrams were too detailed.

02 Under Features on page 1, changed "Line rates to 12kHz" to "Line rates to 23.7kHz". Was incorrect.

03 Changed Pin 13 label in figure from VLOW to VSS in Table 1

Changed last sentence on page 3 from "To match outputs. we recommend that the camera electronics incorporate a

gain correction of up to 15%" to "To match outputs. we recommend that the camera electronics incorporate gain cor-

rection." This removes the chance that customers interpret 15% as a specification. This was only intended as a guide-

line or recommendation.

05 Added "The isolation pixels should not be used for calibration or detection" to the Functional DescriptionàOutput

section.

06 Added “RoHs compliant” to Features section on page 1.

Added lead-free logo to Figure 8

07 Figure 8, package dimensions, some dimensions and tolerances revised.

Added RoHS logo to Figure 8.

Table 11: Revision History