MT28S2M32B1LLFG-8 - Micron - Datasheet.Directory

MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02

ADVANCE‡

‡PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY

MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.

64Mb: x16, x32

SYNCFLASH MEMORY

SYNCFLASH®

MEMORY

FEATURES

• 125 MHz SDRAM-compatible read timing

• Fully synchronous; all signals registered on

positive edge of system clock

• Internal pipelined operation; column address can

be changed every clock cycle

• Internal banks for hiding row access

• Programmable burst lengths:

1, 2 , 4, 8, or full page (read)

1, 2, 4, or 8 (write)

• LVTTL-compatible inputs and outputs

• 3.0V–3.6V VCC, 1.65V–1.95V VCCQ

Additional VHH hardware protect mode (RP#)

• Supports CAS latency of 1, 2, and 3

• Four-bank architecture supports true concurrent

operation with zero latency

Read any bank while programming or erasing

any other bank

• Deep power-down mode: 50µA (MAX)

• Cross-compatible Flash memory command set

• Operating temperature range of -40oC to +85oC

OPTIONS MARKING

• Configuration

4 Meg x 16 (1 Meg x 16 x 4 banks) 4M16

2 Meg x 32 (512K x 32 x 4 banks) 2M32

• Read Timing (Cycle Time)

10ns (100 MHz) @ CL2 -8

8ns (125 MHz) @ CL3 -8

10ns (100 MHz) @ CL3 -10

• Package

90-ball FBGA FG

Part Number Example:

MT28S4M16B1LLFG-8

MT28S4M16B1LL – 1 Meg x 16 x 4 banks

MT28S2M32B1LL – 512K x 32 x 4 banks

NOTE: 1. The # symbol indicates signal is active LOW.

KEY TIMING PARAMETERS

ACCESS

SPEED CLOCK TIME SETUP HOLD

GRADE FREQUENCY CL = 1* CL = 2* CL = 3* TIME TIME

-8 125 MHz - - 7ns 2ns 1ns

-10 100 MHz - - 7ns 2ns 1ns

-8 100 MHz - 8ns - 2ns 1ns

* CL = CAS (READ) Latency

PIN ASSIGNMENT (Top View)

123 789

DNU

VccQ

CLK

DQM1

VccQ

DQ11

DQ13

DNU

VccQ

DNU

MCL

CKE

RP#

DQ8

DQ10

DQ12

VccQ

DQ15

DNU

VccP

A11

Vss

DQ9

DQ14

Vss

DNU

VccQ

VssQ

Vcc

RAS#

DQM0

VccQ

DQ4

DQ2

DNU

MCL

BA1

CS#

WE#

DQ7

DQ5

DQ3

DQ0

Vcc

VccQ

DNU

A10

BA0

CAS#

Vcc

DQ6

DQ1

VccQ

Vcc

90-Ball FBGA – 2 Meg x 32

123 789

DQ26

DQ28

VccQ

CLK

DQM1

VccQ

DQ11

DQ13

DQ24

VccQ

DQ27

DQ29

DQ31

DQM3

CKE

RP#

DQ8

DQ10

DQ12

VccQ

DQ15

DQ25

DQ30

VccP

DNU

Vss

DQ9

DQ14

Vss

DQ21

DQ19

VccQ

VssQ

Vcc

RAS#

DQM0

VccQ

DQ4

DQ2

DQ23

DQ20

DQ18

DQ16

DQM2

BA1

CS#

WE#

DQ7

DQ5

DQ3

DQ0

Vcc

VccQ

DQ22

DQ17

A10

BA0

CAS#

Vcc

DQ6

DQ1

VccQ

Vcc

90-Ball FBGA – 4 Meg x 16

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x16, x32

SYNCFLASH MEMORY

ADVANCE

GENERAL DESCRIPTION

This 64Mb SyncFlash® data sheet is divided into

two major sections. The SDRAM Interface Functional

Description details compatibility with the SDRAM

memory, and the Flash Memory Functional Descrip-

tion specifies the symmetrical-sectored Flash architec-

ture and functional commands.

The 64Mb SyncFlash devices are nonvolatile, elec-

trically sector-erasable (Flash), programmable read-

only memory containing 67,108,864 bits. Each of the

x16’s 16,777,216-bit banks is organized as 4,096 rows

by 256 columns by 16 bits. Each of the x32’s 16,777,216-

bit banks is organized as 2,048 rows by 256 columns by

32 bits.

The 64Mb devices are organized into 16 indepen-

dently erasable blocks. To ensure that critical firmware

is protected from accidental erasure or overwrite, this

device features sixteen (x32: 128K-Dword; x16: 256K-

word) hardware and software-lockable blocks.

A four-bank architecture supports true concurrent

operations. A read access to any bank can occur simul-

taneously with a background PROGRAM or ERASE op-

eration to any other bank.

SyncFlash memory has a synchronous interface (all

signals are registered on the positive edge of the clock

signal, CLK). Read accesses to the memory are burst

oriented; accesses start at a selected location and con-

tinue for a programmed number of locations in a pro-

grammed sequence. Accesses begin with the registra-

tion of an ACTIVE command, followed by a READ com-

mand. The address bits registered coincident with the

ACTIVE command are used to select the bank and row

to be accessed. The address bits registered coincident

with the READ command are used to select the starting

column location for the burst access.

The 64Mb devices provide for programmable read

burst lengths of 1, 2, 4, or 8 locations, or the full page,

with a burst terminate option. The x16 device features

an 8-word internal write buffer and the x32 features an

8-Dword internal write buffer that support mode regis-

ter programmed burst write compatibility of 1, 2, 4, or 8

locations.

SyncFlash memory uses an internal pipelined archi-

tecture to achieve high-speed operation.

The 64Mb devices are designed to operate in 3.3V

VCC and 1.8V VCCQ, low-power memory systems. A deep

power-down mode is provided, along with a power-

saving standby mode. All inputs and outputs are

LVTTL-compatible.

SyncFlash memory offers substantial advances in

Flash operating performance, including the ability to

synchronously burst data at a high data rate with auto-

matic column-address generation and the capability

to randomly change column addresses on each clock

cycle during a burst access.

All Flash operations are performed using either a

hardware command sequence (HCS) or a software com-

mand sequence (SCS). The HCS operations are used

by memory controllers with native SyncFlash support.

Standard SDRAM controllers can use SCS operation to

perform Flash operations.

Please refer to Micron’s Web site (www.micron.com/

syncflash) for the latest data sheet.

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x16, x32

SYNCFLASH MEMORY

ADVANCE

TABLE OF CONTENTS

Functional Block Diagram – 4 Meg x 16 ............... 4

– 2 Meg x 32 ............... 5

Pin and Ball Descriptions ....................................... 6

SDRAM Interface Functional Description ....... 9

Initialization ...................................................... 9

Mode Register .............................................. 9

Burst Length ............................................ 9

Burst Type ............................................... 11

CAS Latency ............................................ 11

Operating Mode ..................................... 11

Write Burst Mode ................................... 11

Commands ........................................................ 12

Truth Table 1 (Commands and DQM Operation) ........ 12

Truth Table 2a (Harware Command

Sequences [HCS]) ................................................. 13

Truth Table 2b (Software Command

Sequences [SCS]) .................................................. 14

Command Inhibit ........................................ 17

No Operation (NOP) ................................... 17

Load Mode Register ..................................... 17

Active ............................................................ 17

Read ............................................................. 17

Write ............................................................ 17

Active Terminate .......................................... 17

Burst Terminate ............................................ 17

Load Command Register ............................. 17

Operation .......................................................... 18

Bank/Row Activation .................................. 18

Reads ............................................................ 19

Write Bursts .................................................. 24

Active Terminate .......................................... 24

Power-Down ................................................ 24

Clock Suspend ............................................. 24

Burst Read/Single Write ............................... 25

Truth Table 3 (CKE) .................................................. 26

Truth Table 4 (Current State, Same Bank) .................. 27

Truth Table 5 (Current State, Different Bank) ............. 28

Flash Memory Functional Description ............ 29

Flash Command Sequence ............................... 29

Hardware Command Sequence (HCS) ....... 29

Software Command Sequence (SCS) .......... 29

Memory Architecture ........................................ 30

Protected Blocks ........................................... 30

Command Execution Logic (CEL) ............... 30

Internal State Machine (ISM) ...................... 30

ISM Status Register ...................................... 30

Output (READ) Operations .............................. 31

Memory Array ............................................. 32

Status Register .............................................. 32

Device Configuration Registers ................... 32

Input Operations .............................................. 32

Memory Array ............................................. 32

Command Execution ........................................ 32

Status Register .............................................. 32

Device Configuration .................................. 33

Program Sequence ....................................... 33

Erase Sequence ............................................. 33

Program and Erase NVMode Register ......... 34

Block Protect/Unprotect Sequence ................... 34

Device Protect Sequence .............................. 34

Chip Initialize Sequence .............................. 34

Disable LCR Sequence .................................. 35

Reset/Deep Power-Down Mode ....................... 35

Error Handling .................................................. 35

Program/Erase Cycle Endurance ....................... 35

Absolute Maximum Ratings ............................. 44

DC Electrical Characteristics

and Operating Conditions .......................... 44

ICC Specifications and Conditions .................... 45

Capacitance ....................................................... 45

Electrical Characteristics and Recommended

AC Operating Conditions (Timing Table) .. 46

AC Functional Characteristics .......................... 47

Timing Waveforms

Initialize and Load Mode Register

RP# .............................................................. 48

FCS .............................................................. 49

Clock Suspend Mode ........................................ 50

Reads

Read ............................................................. 51

Alternating Bank Read Accesses .................. 52

Full-Page Burst ............................................. 53

DQM Operation .......................................... 54

Program/Erase

Bank a followed by READ to bank a .......... 55

Bank a followed by READ to bank b .......... 56

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x16, x32

SYNCFLASH MEMORY

ADVANCE

FUNCTIONAL BLOCK DIAGRAM

4 Meg x 16

RAS#

CAS#

CLK

CS#

WE#

CKE

COLUMN-

ADDRESS

COUNTER/

LATCH

A0–A11,

BA0, BA1

DQM0–

DQM1

ADDRESS

256

4,096

I/O GATING

DQM MASK LOGIC

READ DATA LATCH

WRITE DRIVERS

COLUMN

DECODER

BANK 0

MEMORY

ARRAY

(4,096 x 256 x 16)

BANK 0

ROW-

ADDRESS

LATCH

DECODER

High Voltage

Switch/Pump

4,096

SENSE AMPLIFIERS

BANK

CONTROL

LOGIC

DQ0–

DQ15

BANK 1BANK 2BANK 3

2 2

COMMAND

EXECUTION

LOGIC

MODE REGISTER

COMMAND

DECODE

STATE MACHINE

STATUS REG.

NVMODE

DATA

INPUT

DATA

OUTPUT

RP#

ID REG.

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x16, x32

SYNCFLASH MEMORY

ADVANCE

RAS#

CAS#

CLK

CS#

WE#

CKE

COLUMN-

ADDRESS

COUNTER/

LATCH

A0–A10,

BA0, BA1

DQM0–

DQM3

ADDRESS

256

8,192

I/O GATING

DQM MASK LOGIC

READ DATA LATCH

WRITE DRIVERS

COLUMN

DECODER

BANK 0

MEMORY

ARRAY

(2,048 x 256 x 32)

BANK 0

ROW-

ADDRESS

LATCH

DECODER

High Voltage

Switch/Pump

2,048

SENSE AMPLIFIERS

BANK

CONTROL

LOGIC

DQ0–

DQ31

BANK 1BANK 2BANK 3

4 4

COMMAND

EXECUTION

LOGIC

MODE REGISTER

COMMAND

DECODE

STATE MACHINE

STATUS REG.

NVMODE

DATA

INPUT

DATA

OUTPUT

RP#

ID REG.

FUNCTIONAL BLOCK DIAGRAM

2 Meg x 32

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x16, x32

SYNCFLASH MEMORY

ADVANCE

(continued on next page)

PIN AND BALL DESCRIPTIONS

TSOP PIN FBGA BALL

NUMBERS NUMBERS SYMBOL TYPE DESCRIPTION

68 J1 CLK Input Clock: CLK is driven by the system clock. All SyncFlash memory

input signals are sampled on the positive edge of CLK. CLK also

increments the internal burst counter and controls the output

registers.

67 J2 CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the

CLK signal. Deactivating the clock provides STANDBY opera-

tion or CLOCK SUSPEND operation (burst/access in progress).

CKE is synchronous except after the device enters power-down

modes, where CKE becomes asynchronous until after exiting

the same mode. The input buffers, including CLK, are disabled

during power-down modes, providing low standby power.

CKE may be tied HIGH in systems where power-down modes

(other than RP# deep power-down) are not required.

20 J8 CS# Input Chip Select: CS# enables (registered LOW) and disables

(registered HIGH) the command decoder. All commands are

masked when CS# is registered HIGH. CS# provides for external

bank selection on systems with multiple banks. CS# is consid-

ered part of the command code.

19, 18, 17 J9, K7, K8 RAS#, Input Command Inputs: RAS#, CAS#, and WE# (along with CS#)

CAS#, WE# define the command being entered.

16, 71 K9, K1 x16: DQM0, Input Input/Output Mask: DQM is an input mask signal for write

DQM1 accesses and an output enable signal for read accesses. Input

data is masked when DQM is sampled HIGH during a WRITE

16, 71, 28, K9, K1, F8, x32: DQM0 cycle. The output buffers are placed in a High-Z state (after a

59 F2 –DQM3 two-clock latency) when DQM is sampled HIGH during a READ

cycle. For x16, DQM0 corresponds to DQ0–DQ7, DQM1

corresponds to DQ8–DQ15. For x32, DQM0 corresponds to

DQ0–DQ7, DQM1 corresponds to DQ8–DQ15, DQM2 corre-

sponds to DQ16–DQ23, DQM3 corresonds to DQ24–DQ31.

DQM0–DQM3 are in the same state when referenced as DQM.

25–27, G8, G9, F7, A0–A11 Input Address Inputs: A0–A11 are sampled during the ACTIVE

60–66, 24, F3, G1, G2, command (row address A0–A11 [x16]; A0–A10 [x32]) and

70 G3, H1, H2, READ/WRITE command (column-address A0–A7) to select one

J3, K3, G7 location in the respective bank. The address inputs provide the

op-code during a LOAD MODE REGISTER command and the

com-code during an LCR command. For x16: A11 is pin 66 (J3),

and A9 is pin 70 (K3).

22, 23 J7, H8 BA0, BA1 Input Bank Address Input(s): BA0, BA1 define to which bank the

ACTIVE, READ, or WRITE command is being applied.

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x16, x32

SYNCFLASH MEMORY

ADVANCE

PIN AND BALL DESCRIPTIONS (continued)

TSOP PIN FBGA BALL

NUMBERS NUMBERS SYMBOL TYPE DESCRIPTION

30 K2 RP# Input Initialize/Power-Down: Upon initial device power-up, a 100µs

delay after RP# has transitioned from LOW to HIGH is required

for internal device initialization, prior to issuing an executable

command. RP# clears the status register, sets the internal state

machine (ISM) to the array read mode, and places the device in

the deep power-down mode when LOW. All inputs, including

CS#, are “Don’t Care” and all outputs are High-Z. When RP# =

VHH, all protection modes are ignored during PROGRAM and

ERASE. This input also allows the device protect bit to be set to

“1” (protected) and allows the block protect bits at locations 0

and 15 to be set to “0” (unprotected). RP# must be held HIGH

during all other modes of operation.

2, 4, 5, 7, R8, N7, R9, x16: DQ0– I/O Data I/O: Data bus.

8, 10, 11, N8, P9, M8, DQ15

13, 74, 76, M7, L8, L2,

77, 79, 80, M3, M2, P1,

82, 83, 85, N2, R1, N3,

2, 4, 5, 7, R8, N7, R9, x32: DQ0–

8, 10, 11, N8, P9, M8, DQ31

13, 74, 76, M7, L8, L2,

77, 79, 80, M3, M2, P1,

82, 83, 85, N2, R1, N3,

31, 33, 34, R2, E8, D7,

36, 37, 39, D8, B9, C8,

40, 42, 45, A9, C7, A8,

47, 48, 50, A2, C3, A1,

51, 53, 54, C2, B1, D2,

56 D3, E2

3, 9, 35, B2, B7, C9, VCCQ Supply DQ Power: 1.65V–1.95V; provide isolated power to DQs for

41, 49, D9, E1, L1, improved noise immunity.

55, 75, 81 M9, P2, P7,

6, 12, 32, B3, B8, C1, VSSQ Supply DQ Ground: Provide isolated ground to DQs for improved

38, 46, 52, D1, E9, L9, noise immunity.

78, 84 M1, N1, P3,

1, 15, 29, A7, F9, L7, VCC Supply Power Supply: 3.0V–3.6V.

43 R7

44, 58, 72, A3, F1, L3, VSS Supply Ground.

86 R3

(continued on next page)

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x16, x32

SYNCFLASH MEMORY

ADVANCE

PIN AND BALL DESCRIPTIONS (continued)

TSOP PIN FBGA BALL

NUMBERS NUMBERS SYMBOL TYPE DESCRIPTION

57 H3 VCCP Supply Program/Erase Supply Voltage: VCCP must be tied externally to

VCC. The VCCP pin sources current during device initialization,

PROGRAM, and ERASE operations.

14, 21, 69, E3, E7, H7, NC – No Connect: These pins may be driven or left unconnected.

73 H9

31, 33, 34, E8, D7, D8, x16: DNU – Do Not Use.

36, 37, 39, B9, C8, A9,

40, 42, 45, C7, A8, A2,

47, 48, 50, C3, A1, C2,

51, 53, 54, B1, D2, D3,

56 E2

70 K3 x32: DNU

28, 59 F8, F2 x16: MCL – Must connect to Vss.

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

SDRAM

SDRAM INTERFACE

FUNCTIONAL DESCRIPTION

In general, the 64Mb SyncFlash memory devices

(1 Meg x 16 x 4 banks, 512K x 32 x 4 banks) are config-

ured as a quad-bank, nonvolatile SDRAM that operate

at 3.0V–3.6V and include a synchronous interface (all

signals are registered on the positive edge of the clock

signal, CLK). Each of the x16’s 16,777,216-bit banks is

organized as 4,096 rows by 256 columns by 16 bits.

Each of the x32’s 16,777,216-bit banks is organized as

2,048 rows by 256 columns by 32 bits.

Read accesses to the SyncFlash memory are identi-

cal to SDR SDRAM operation. Burst accesses start at a

selected location and continue for a programmed num-

ber of locations in a programmed sequence. Accesses

begin with the registration of an ACTIVE command,

followed by a READ command. The address bits regis-

tered coincident with the ACTIVE command are used

to select the bank and row to be accessed (BA0 and BA1

select the bank; x32: A0–A10, x16: A0–A11 select the

row). The address bits (A0–A7) registered coincident

with the READ command are used to select the starting

column location for the burst access.

All non-READ operations are controlled with either

a Hardware Command Sequence (HCS) or a Software

Command Sequence (SCS). Both the HCS and SCS

interface can be used to initiate any of the internal

program, erase, initialization, or status operations. The

term Flash command sequence (FCS) refers to either

HCS or SCS operation.

Prior to normal operation, the SyncFlash memory

must be initialized. The following sections provide

detailed information covering device initialization, reg-

ister definition, command descriptions, and device op-

eration.

Initialization

The device power-up procedure can be defined two

ways. The first is a hardware initiated power-up, where

power is applied to VCC, VCCQ, and VCCP (simulta-

neously). Then, with the clock stable, RP# must be

brought from LOW to HIGH. After RP# transitions HIGH,

the power-up initialization process will complete within

100µs. The second procedure is defined as a software

initiated power-up. In this case the initialization is

performed using the INITIALIZE DEVICE FCS opera-

tion. When the INITIALIZE DEVICE command is used,

the RP# pin does not require the LOW-to-HIGH transi-

tion typically required for initialization. After the INI-

TIALIZE DEVICE command has been issued, the

power-up initialization process will complete within

100µs.

Early completion of either initialization procedure

can be detected by polling SR7 in the status register.

After initialization, the SyncFlash device is in standby

mode and ready for mode register programming or an

executable command. After initial programming of the

nvmode register, the contents are automatically loaded

into the mode register during initialization and the

device will power-up in the programmed state.

Note that when VCC is greater than 2.7V, either of the

initialization procedures can be issued.

MODE REGISTER

The mode register is used to define the specific mode

of operation of the SyncFlash memory. This definition

includes the selection of a burst length, a burst type, a

CAS latency, and an operating mode, as shown in Fig-

ure 1. The mode register is programmed via the LOAD

MODE REGISTER command and will retain the stored

information until it is reprogrammed. The nvmode reg-

ister settings are transferred into the mode register

during initialization. The contents of the mode register

may be copied into the nvmode register with a PRO-

GRAM NVMODE REGISTER command. Details on erase

nvmode register and program nvmode register

command sequences are found in the Command Ex-

ecution section of the Flash Memory Functional

Description.

Mode register bits M0–M2 specify the burst length,

M3 specifies the burst type (sequential or interleaved),

M4–M6 specify the CAS latency, M7 and M8 specify the

operating mode, M9 specifies the WRITE burst mode,

and M10 and M11 are reserved for future use.

The mode register must be loaded when all banks

are idle, and the controller must wait the specified time

before initiating the subsequent operation. Violating

either of these requirements will result in unspecified

operation.

BURST LENGTH

Read and write accesses to the SyncFlash memory

are burst oriented, with the burst length being pro-

grammable, as shown in Figure 1. The burst length

determines the maximum number of column locations

that can be accessed for a given READ or WRITE com-

mand. Burst lengths of 1, 2, 4, or 8 locations are avail-

able for both the sequential and the interleaved burst

types (read or write), and a full-page burst is available

for the sequential type (read only). The full-page burst

can be used in conjunction with the BURST TERMI-

NATE command to generate arbitrary burst lengths.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may

result.

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

SDRAM

Figure 1

Mode Register Definition

Table 1

Burst Definition

Burst Starting Column Order of Accesses Within a Burst

Length Address Type = Sequential Type = Interleaved

20 0-1 0-1

1 1-0 1-0

A1 A0

0 0 0-1-2-3 0-1-2-3

40 1 1-2-3-0 1-0-3-2

1 0 2-3-0-1 2-3-0-1

1 1 3-0-1-2 3-2-1-0

A2 A1 A0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

80 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2

1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1

1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Full n = A0–A7 Cn, Cn+1, Cn+2

Page Cn+3, Cn+4... Not supported

256 (location 0-255) …Cn-1,

Cn...

NOTE: 1. For a burst length of two, A1–A7 select the block-

of-two burst; A0 selects the starting column

within the block.

2. For a burst length of four, A2–A7 select the block-

of-four burst; A0–A1 select the starting column

within the block.

3. For a burst length of eight, A3–A7 select the

block-of-eight burst; A0–A2 select the starting

column within the block.

4. For a full-page burst, the full row is selected and

A0–A7 select the starting column.

5. Whenever a boundary of the block is reached

within a given sequence above, the following

access wraps within the block.

6. For a burst length of one, A0–A7 select the unique

column to be accessed, and mode register bit M3

is ignored.

7. Burst write (x32: 1, 2, 4, or 8 Dwords, x16: 1, 2, 4,

or 8 words) is supported (not full page).

8. The contents of the mode register can be read

using the READ DEVICE CONFIGURATION command

(004h).

M3 = 0

Reserved

Full Page

M3 = 1

Reserved

Operating Mode

Standard Operation

All other states reserved

Defined

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Burst Length

Burst LengthCAS Latency BT

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Mode Register (Mx)

Address Bus

976543

8210

M6-M0

M8 M7

Op Mode

A10

Reserved*

Write Burst Mode

Programmed Burst Length

Single Location Access

*Program M11,

M10 = “0, 0” to

ensure compatibility

with future devices.

A11

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively se-

lected. All accesses for that burst take place within this

block, meaning that the burst will wrap within the block

if a boundary is reached. The block is uniquely se-

lected by A1–A7 when the burst length is set to two, by

A2–A7 when the burst length is set to four, and by A3–

A7 when the burst length is set to eight. The remaining

(least significant) address bit(s) are used to select the

starting location within the block. Full-page bursts wrap

within the page if the boundary is reached.

NOTE: 1. A11 and M11 are supported only by 4 Meg x 16 configuration.

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

SDRAM

Figure 2

CAS Latency

CLK

T2T1 T3T0

CAS Latency = 3

OUT

tOH

COMMAND NOPREAD

tAC

NOP

DON’T CARE

UNDEFINED

CLK

T2T1T0

CAS Latency = 1

OUT

tOH

COMMAND NOPREAD

tAC

CLK

T2T1 T3T0

CAS Latency = 2

OUT

tOH

COMMAND NOPREAD

tAC

NOP

BURST TYPE

Accesses within a given burst may be programmed

to be either sequential or interleaved; this is referred to

as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the burst length, the burst type, and the

starting column address, as shown in Table 1.

CAS LATENCY

The CAS latency is the delay, in clock cycles, be-

tween the registration of a READ command and the

availability of the first piece of output data. The la-

tency can be set to one, two, or three clocks.

If a READ command is registered at clock edge n,

and the latency is m clocks, the data will be available by

clock edge n + m. The DQs will start driving as a result of

the clock edge one cycle earlier (n + m - 1), and provided

that the relevant access times are met, the data will be

valid by clock edge n + m. For example, assuming that

the clock cycle time is such that all relevant access times

are met, if a READ command is registered at T0 and the

latency is programmed to two clocks, the DQs will start

driving after T1 and the data will be valid by T2, as

shown in Figure 2. Table 2 indicates the operating fre-

quencies at which each CAS latency setting can be used.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may

result.

OPERATING MODE

The normal operating mode is selected by setting M7

and M8 to zero; the other combinations of values for M7

and M8 are reserved for future use and/or test modes.

The programmed burst length applies to READ and

WRITE bursts (full-page burst WRITE not supported).

Test modes and reserved states should not be used

because unknown operation or incompatibility with

future versions may result.

WRITE BURST MODE

When M9 = 0, the burst length programmed via

M0–M2 applies to both read and write bursts; however,

if full-page burst length is selected in conjunction with

M9 = 0, the burst write length is 8 words for the x16 and

8-Dwords for the x32 (not full page). When M9 = 1, the

programmed burst length applies to READ bursts, but

write accesses are single-location (nonburst) accesses.

Table 2

CAS Latency

ALLOWABLE OPERATING

FREQUENCY (MHz)

CAS CAS CAS

SPEED LATENCY = 1 LATENCY = 2 LATENCY = 3

-8

50 MHz

100 MHz

125MHz

-10

40 MHz

83 MHz

100 MHz

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

SDRAM

COMMANDS

Truth Table 1 provides a quick reference of avail-

able commands for SDRAM-compatible operation. This

is followed by a written description of each command.

Additional truth tables appear later.

TRUTH TABLE 1

SDRAM-COMPATIBLE INTERFACE COMMANDS AND DQM OPERATION

(Notes: 1)

NAME (FUNCTION) CS# RAS# CAS# WE# DQM ADDR DQs NOTES

COMMAND INHIBIT (NOP) H XXXX X X

NO OPERATION (NOP) L H H H X X X

ACTIVE (Select bank and activate row) L L H H X Bank/Row X 2

READ (Select bank, column and start READ burst) L H L H X Bank/Col X 3

WRITE (Select bank, column and start WRITE) L H L L X Bank/Col Valid 3, 4

BURST TERMINATE L H H L X X Active

ACTIVE TERMINATE L L H L X X X 5

LOAD COMMAND REGISTER L L L H X Com-Code X 6, 7

LOAD MODE REGISTER LLLLXOp-Code X 8

Write Enable/Output Enable ––––L – Active 9

Write Inhibit/Output High-Z ––––H – High-Z 9

NOTE: 1. CKE is HIGH for all commands shown.

2. x32: A0–A10, x16: A0–A11 provide row address, and BA0 and BA1 determine which bank is made active.

3. A0–A7 provide column address, and BA0 and BA1 determine which bank is being read from or written to.

4. A PROGRAM SETUP command sequence (see Truth Table 2a) must be completed prior to executing a WRITE.

5. ACTIVE TERMINATE is functionally equivalent to the SDRAM PRECHARGE command; however, PRECHARGE (deactivate row

in bank or banks) is not required for SyncFlash memory.

A10 LOW: BA0 and BA1 determine the bank to be active terminated.

A10 HIGH: All banks are active terminated and BA0 and BA1 are “Don’t Care.”

6. A0–A7 define the com-code, and A8–A11 are “Don’t Care” for this operation. See Truth Table 2a.

7. LOAD COMMAND REGISTER (LCR) replaces the SDRAM auto refresh or self refresh mode, which is not required for

SyncFlash memory. LCR is the first cycle for Flash memory hardware command sequences (HCS). See Truth Table 2a.

After the hardware LCR function is disabled, SyncFlash will treat SDRAM REFRESH or AUTO REFRESH commands as NOPs.

A software command sequence (SCS) is available to perform all operations described in Truth Table 2b.

8. A0–A10 define the op-code written to the mode register. The mode register can be dynamically loaded each cycle,

provided tMRD is satisfied. The default mode register value is stored in the nvmode register. The contents of the

nvmode register are automatically loaded into the mode register during device initialization.

9. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

SDRAM

COMMANDS

The following Truth Tables provide a quick reference of available

commands for Flash memory interface operation. A written descrip-

tion of each command is found in the Flash Memory Functional

Description section.

TRUTH TABLE 2a – Hardware Command Sequences

(Notes: 1–5; see notes on page 14.)

FIRST CYCLE SECOND CYCLE THIRD CYCLE

BANK BANK BANK

OPERATION CMD ADDR

ADDR DQ RP# CMD

ADDR ADDR DQ RP# CMD ADDR ADDR DQ

RP#

NOTES

READ DEVICE CONFIGURATION LCR 90h Bank X H ACTIVE CA

ROW

Bank X H READ CA

COL

Bank X H 11, 12

READ STATUS REGISTER LCR 70h X X H ACTIVE X X X H READ X X X H

CLEAR STATUS REGISTER LCR 50h X X H

ERASE SETUP/CONFIRM LCR 20h Bank X H ACTIVE Row Bank X H WRITE X Bank D0h H/V

12, 13, 14

PROGRAM SETUP/PROGRAM LCR 40h Bank X H ACTIVE Row Bank X H WRITE Col Bank D

H/V

12, 13,

14, 15

PROTECT BLOCK/CONFIRM LCR 60h Bank X H ACTIVE Row

Bank X H WRITE X Bank LBDa(

)H/V

12, 13,

15, 16

PROTECT DEVICE/CONFIRM LCR 60h Bank X H ACTIVE X Bank X H WRITE X Bank LBDa(

12, 13, 16

UNPROTECT BLOCKS/CONFIRM LCR 60h Bank X H ACTIVE X Bank X H WRITE X Bank LBDb(

)H/V

12, 13,

14, 15, 16

UNPROTECT DEVICE/CONFIRM LCR 60h Bank X H ACTIVE X Bank X H WRITE X Bank LBDb(

12, 13, 16

ERASE NVMODE REGISTER LCR 30h Bank X H ACTIVE X Bank X H WRITE X Bank C0h H 12, 13

PROGRAM NVMODE REGISTER LCR A0h Bank L X H ACTIVE X Bank L X H WRITE X Bank L X H 12, 13,

17, 18

CHIP INITIALIZE LCR 68h Bank X H ACTIVE X Bank X H WRITE X Bank C0h H 12, 13

DISABLE HARDWARE LCR LCR A0h Bank U X H ACTIVE X Bank U X H WRITE X Bank U XH 12, 13,

17, 18, 19

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

SDRAM

TRUTH TABLE 2b – SOFTWARE COMMAND SEQUENCES (SCS)

(Notes: 1, 2, 4, 5; see notes on page 16)

(continued on next page)

OPERATION FIRST SECOND THIRD FOURTH FIFTH SIXTH SEVENTH EIGHTH

CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE

READ DEVICE CONFIGURATION10

Command Active Write Active Read

ADDR = 88h 90h CAROW CACOL

Bank Address = X X Bank12 Bank12

DQ = XXXX

RP# = H H H H

READ STATUS REGISTER

Command Active Write Active Read

ADDR = 88h 70h X X

Bank Address = X X X X

DQ = X X X X

RP# = H H H H

CLEAR STATUS REGISTER

Command Active Write

ADDR = 88h 50h

Bank Address = X X

DQ = X X

RP# = H H

ERASE SETUP/CONFIRM

Command Active Write Active Write Active Write Active Write

ADDR = X 55h 55h 2Ah 80h 20h Row X

Bank Address = X Bank12 Bank12 Bank12 Bank12 Bank12 Bank12 Bank12

DQ = X X X 55h X A0h X D0h

RP# = H H H H H H H H/VHH

PROGRAM SETUP/CONFIRM

Command Active Write Active Write Active Write Active Write

ADDR = X 55h 55h 2Ah 80h 40h Row Col

Bank Address = X Bank12 Bank12 Bank12 Bank12 Bank12 Bank12 Bank12

DQ = X X X 55h X A0h X DIN

RP#9 = HHHHHHHH/VHH15

PROTECT BLOCK/CONFIRM

Command Active Write Active Write Active Write Active Write

ADDR = X 55h 55h 2Ah 80h 60h Row11 X

Bank Address = X Bank12 Bank12 Bank12 Bank12 Bank12 Bank12 Bank12

DQ = X X X 55 X A0h X LBDa(IN)16

RP#9 = HHHHHHHH/VHH15

PROTECT DEVICE CONFIRM

Command Active Write Active Write Active Write Active Write

ADDR = X 55h 55h 2Ah 80h 60h X10 X

Bank Address = X Bank12 Bank12 Bank12 Bank12 Bank12 Bank12 Bank12

DQ = X X X 55h X A0h X LBDa(IN)16

RP#9 = HHHHHHHVHH

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

SDRAM

TRUTH TABLE 2b – SOFTWARE COMMAND SEQUENCES (SCS) (continued)

(Notes: 1, 2, 4, 5; see notes on page 16)

OPERATION FIRST SECOND THIRD FOURTH FIFTH SIXTH SEVENTH EIGHTH

CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE

UNPROTECT BLOCK/CONFIRM10, 16

Command Active Write Active Write Active Write Active Write

ADDR = X 55h 55h 2Ah 80h 60h X11 X

Bank Address = X Bank12 Bank12 Bank12 Bank12 Bank12 Bank12 Bank12

DQ = X X X 55h X A0h X LBDb(IN)16

RP#5 = HHHHHHHVHH

UNPROTECT DEVICE/CONFIRM

Command Active Write Active Write Active Write Active Write

ADDR = X 55h 55h 2Ah 80h 60h X X

Bank Address = X Bank12 Bank12 Bank12 Bank12 Bank12 Bank12 Bank12

DQ = X X X 55h X A0h X LBDb(IN)16

RP#5 = HHHHHHHH/VHH

ERASE NVMODE REGISTER

Command Active Write Active Write Active Write Active Write

ADDR = X 55h 55h 2Ah 80h 30h X X

Bank Address = X Bank12 Bank12 Bank12 Bank12 Bank12 Bank12 Bank12

DQ = X X X 55h X A0h X C0h

RP# = H H H H H H H H

PROGRAM NVMODE REGISTER18

Command Active Write Active Write Active Write Active Write

ADDR = X 55h 55h 2Ah 80h A0h X X

Bank Address = X Bank L12 Bank L12 Bank L12 Bank L12 Bank L12 Bank L12 Bank L12

DQ = X X X 55h X A0h X X

RP# = H H H H H H H H

DISABLE HARDWARE LCR19

Command Active Write Active Write Active Write Active Write

ADDR = X 55 55h 2Ah 80h A0h X X

Bank Address = X Bank U12 Bank U12 Bank U12 Bank U12 Bank U12,18 Bank U12,18 Bank U12,18

DQ = X X X 55h X A0h X X

RP# = H H H H H H H H

CHIP INITIALIZE

Command Active Write Active Write Active Write Active Write

ADDR = X 55h 55h 2Ah 80h 68h X X

Bank Address = X Bank12 Bank12 Bank12 Bank12 Bank12 Bank12 Bank12

DQ = X X X 55h X A0h X C0h

RP# = H H H H H H H H

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

SDRAM

NOTE: 1. CMD = Command: decoded from CS#, RAS#, CAS#, and WE# inputs.

2. NOP/COMMAND INHIBIT/BURST TERMINATE/ACTIVE TERMINATE commands may be issued throughout the HCS or SCS.

Addtitionally, LOAD COMMAND REGISTER may be issued throughout the SCS.

3. After a PROGRAM or ERASE operation is registered to the ISM and prior to completion of the ISM operation, a READ to any

location in the bank under ISM control will output the contents of the row activated prior to the LCR/active/write sequence

(see Note 14).

4. To meet the tRCD specification, the appropriate number of NOP/COMMAND INHIBIT commands must be issued between

ACTIVE and READ/WRITE commands.

5. The ERASE, PROGRAM, PROTECT, and UNPROTECT operations are self-timed. The status register may be polled to monitor

these operations.

6. x32: A8–A10, x16: A8–A11 are “Don’t Care.”

7. A row will not be opened when ACTIVE is preceded by LCR. ACTIVE is considered a NOP.

8. x32 Data Inputs, DQ8–DQ31 are “Don’t Care” except for DIN, where all DQ31–DQ0 are driven.

x16 Data Inputs, DQ8–DQ15 are "Don’t Care" except for DIN, where all DQ15–DQ0 are driven.

Data Outputs: All unused bits are driven LOW.

9. VHH = 7.0V–8.5V

10. Address must be any row address in the Block desired to be protected.

11. CAROW, CACOL = Configuration address

This value changes depending on the bit location being accessed

CAROW = X02h for block protect bit, which corresponds to the block row address: x32: X = 0, 2, 4, or 6h

x16: X = 0, 4, 8, or Ch

For all other bits CAROW = XXXh (“Don’t Care”)

CACOL = Values shown below

00h = Manufacturer compatibility ID = 2Ch

01h = Device ID MT28S4M16B1 = D5h

Device ID MT28S2M32B1 = D4h

02h = Block protect bit (BPB)

03h = Device protect bit (DPB)

04h = Mode register

05h = Hardware load command register (LCR) bit

06h/07h = Reserved for future use

12. BA = Bank address must match for all the cycles, except for manufacturer ID/device ID/device protect where it is xxh.

13. The proper command sequence (LCR/active/write) is needed to initiate an ERASE, PROGRAM, PROTECT, or UNPROTECT

operation.

14. If the device protect bit is not set, RP# = VIH unprotects all sixteen ( x32: 128K-Dword, x16: 256K-word ) erasable blocks,

except for blocks 0 and 15. When RP# = VHH, all sixteen ( x32: 128K-Dword, x16: 256K-word) erasable blocks (including

blocks 0 and 15) will be unprotected, and the device protect bit will be ignored. If the device protect bit is set and RP# =

VIH, the block protect bits cannot be modified.

15. If the device protect bit is set, then an ERASE, PROGRAM, PROTECT, or UNPROTECT operation can still be initiated by

bringing RP# to VHH prior to the WRITE command cycle and holding it at VHH until the operation is completed.

16. LBDa = Lock bit data

01h = Set block protect bit

F1h = Set device protect bit

If the DPB is not set, RP# = VIH; all blocks can be set

If the DPB is set, RP# = VIH; BPBs cannot be modified

RP# = VHH; all BPBs can be modified

To set DPB, RP# = VHH is a must

RP# = VHH; all blocks including 0 and 15 are unprotected (reset); DPB does not matter

LBDb = Lock bit data

D0h = Clear block and device protect bit

If the DPB is not set, RP# = VIH; all blocks except 0 and 15 are unprotected (reset)

If the DPB is set, RP# = VIH; block protect bits cannot be modified

RP# = VHH; all blocks including 0, 15, and DPB are unprotected (reset)

17. Bank L: [BA1,BA0] = [0,0] or [0,1]

Bank U: [BA1 BA0] = [1,0] or [1,1]

18. If [BA1, BA0] = [0,0] or [0,1], then WRITE NVMODE REGISTER operation is performed. If [BA1, BA0] = [1,0] or [1,1], then

DISABLE HARDWARE LCR operation is performed.

19. Hardware LCR is preset to “1.” Hardware LCR bit is a one time programmable bit and cannot be reset to “1” after

programmed to “0.”

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

SDRAM

COMMAND INHIBIT

The COMMAND INHIBIT function prevents new

commands from being executed by the SyncFlash

memory, regardless of whether the CLK signal is en-

abled. The SyncFlash memory is effectively deselected.

Operations already in progress are not affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to

perform a NOP to a SyncFlash memory that is selected

(CS# is LOW). This prevents unwanted commands from

being registered during idle or wait states. Operations

already in progress are not affected.

LOAD MODE REGISTER

The mode register is loaded via inputs A0–A10. See

the mode register heading in the Register Definition

section. The LOAD MODE REGISTER command can

only be issued when all banks are idle, and a subse-

quent executable command cannot be issued until

tMRD is met. The data in the nvmode register is auto-

matically loaded into the mode register upon power-

up initialization and is the default mode setting unless

dynamically changed with the LOAD MODE REGIS-

TER command.

ACTIVE

The ACTIVE command is used to open (or activate)

a row in a particular bank for a subsequent access. The

value on the BA0, BA1 inputs selects the bank, and the

address provided on inputs (x32: A0–A10, x16: A0–A11)

selects the row. This row remains active for accesses

until the next ACTIVE command, power-down or reset.

READ

The READ command is used to initiate a burst read

access to an active row. The value on the BA0, BA1

inputs selects the bank, and the address provided on

inputs A0–A7 selects the starting column location. Read

data appears on the DQs subject to the logic level on

the DQM input two clocks earlier. If a given DQM signal

was registered HIGH, the corresponding DQs will be

High-Z two clocks later; if the DQM signal was regis-

tered LOW, the DQs will provide valid data.

WRITE

The WRITE command is used to initiate a burst write

access. A WRITE command must be preceded by LCR/

ACTIVE. The value on the BA0, BA1 inputs selects the

bank, and the address provided on inputs A0–A7 se-

lects the column location.

Input data appearing on the DQs is written to the

memory array, subject to the DQM input logic level

appearing coincident with the data. If a given DQM

signal is registered LOW, the corresponding data will

be written to memory; if the DQM signal is registered

HIGH, the corresponding data inputs will be ignored,

and a WRITE will not be executed to that word/column

location. A WRITE command with DQM HIGH is con-

sidered a NOP.

ACTIVE TERMINATE

ACTIVE TERMINATE, which replaces the SDRAM

PRECHARGE command, is not required for SyncFlash

memory, but is functionally equivalent to the SDRAM

PRECHARGE command. ACTIVE TERMINATE can be

issued to terminate a BURST READ in progress and

may or may not be bank specific.

BURST TERMINATE

The BURST TERMINATE command is used to trun-

cate either fixed-length or full-page bursts. The most

recently registered READ or WRITE command prior to

the BURST TERMINATE command will be truncated as

shown in the Operation section of this data sheet.

BURST TERMINATE is not bank specific.

LOAD COMMAND REGISTER (HCS ONLY)

The LOAD COMMAND REGISTER command in the

HCS is used to initiate Flash memory control commands

to the command execution logic (CEL). The CEL re-

ceives and interprets commands to the device. These

commands control the operation of the internal state

machine and the read path (i.e., memory array, ID reg-

ister or status register). However, there are restrictions

on what commands are allowed in this condition. See

the Command Execution section of Flash Memory Func-

tional Description for more details.

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

SDRAM

Figure 3

Activating a Specific Row in a

Specific Bank

Operation

BANK/ROW ACTIVATION

Before any READ or WRITE commands can be is-

sued to a bank within the SyncFlash memory, a row in

that bank must be “opened.” (Note: A row will not be

activated for LCR/active/read or LCR/active/write com-

mand sequences. See Flash Memory Architecture sec-

tion for additional information). This is accomplished

via the ACTIVE command, which selects both the bank

and the row to be activated.

After opening a row (issuing an ACTIVE command),

a READ or WRITE command may be issued to that row,

subject to the tRCD specification. tRCD (MIN) should

be divided by the clock period and rounded up to the

next whole number to determine the earliest clock edge

after the ACTIVE command on which a READ or WRITE

command can be entered. For example, a tRCD specifi-

cation of 20ns with a 125 MHz clock (8ns period) results

in 2.5 clocks rounded to 3. This is reflected in Figure 4,

which covers any case where 2 < tRCD (MIN)/tCK £ 3.

(The same procedure is used to convert other specifi-

cation limits from time units to clock cycles).

A subsequent ACTIVE command to a different row

in the same bank can be issued without having t o close

a previous active row, provided the minimum time in-

terval between successive ACTIVE commands to the

same bank is defined by tRC.

A subsequent ACTIVE command to another bank

can be issued while the first bank is being accessed,

which results in a reduction of total row access over-

head. The minimum time interval between successive

ACTIVE commands to different banks is defined by

tRRD.

CS#

WE#

CAS#

RAS#

CKE

CLK

A0–A10

ROW

ADDRESS

HIGH

BA0,BA1

BANK

ADDRESS

A0–A11

x32:

x16:

CLK

T2T1 T3T0

COMMAND NOPACTIVE READ or WRITE

NOP

RCD

DON’T CARE

Figure 4

Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK £

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

SDRAM

READs

Read bursts are initiated with a READ command, as

shown in Figure 5.

The starting column and bank addresses are pro-

vided with the READ command.

During read bursts, the valid data-out element from

the starting column address will be available following

the CAS latency after the READ command. Each sub-

sequent data-out element will be valid by the next

positive clock edge. Figure 6 shows general timing for

one, two and three CAS latency settings.

Upon completion of a burst, assuming no other com-

mands have been initiated, the DQs will go High-Z. A

full-page burst will continue until terminated. (At the

end of the page, it will wrap to column 0 and continue.)

Data from any read burst may be truncated with a

subsequent READ command, and data from a fixed-

length read burst may be immediately followed by data

from a subsequent READ command. In either case, a

continuous flow of data can be maintained. The first

data element from the new burst follows either the last

element of a completed burst, or the last desired data

element of a longer burst that is being truncated.

Figure 5

READ Command

Figure 6

CAS Latency

The new READ command should be issued x cycles

before the clock edge at which the last desired data

element is valid, where x equals the CAS latency minus

one. This is shown in Figure 7 for CAS latencies of one,

two and three; data element n + 3 is either the last of a

burst of four, or the last desired of a longer burst. The

SyncFlash memory uses a pipelined architecture and

therefore does not require the 2n rule associated with a

prefetch architecture. A READ command can be initi-

ated on any clock cycle following a previous READ com-

mand. Full-speed, random read accesses within a page

can be performed as shown in Figure 8, or each subse-

quent READ may be performed to a different bank.

CS#

WE#

CAS#

RAS#

CKE

CLK

COLUMN

ADDRESS

A0–A7

BA0, BA1

BANK

ADDRESS

HIGH

CLK

T2T1 T3T0

CAS Latency = 3

OUT

tOH

COMMAND NOPREAD

tAC

NOP

DON’T CARE

UNDEFINED

CLK

T2T1T0

CAS Latency = 1

OUT

tOH

COMMAND NOPREAD

tAC

CLK

T2T1 T3T0

CAS Latency = 2

OUT

tOH

COMMAND NOPREAD

tAC

NOP

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

SDRAM

Figure 7

Consecutive Read Bursts

CLK

OUT

T2T1 T4T3 T5T0

COMMAND

ADDRESS

READ NOP NOP NOP

BANK,

COL n

DON’T CARE

NOP

BANK,

COL b

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3 D

OUT

READ

X = 0 cycles

NOTE: Each READ command may be to either bank. DQM is LOW.

CAS Latency = 1

CLK

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK,

COL n

NOP

BANK,

COL b

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3 D

OUT

READ

X = 1 cycle

CAS Latency = 2

CLK

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK,

COL n

NOP

BANK,

COL b

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3 D

OUT

READ NOP

X = 2 cycles

CAS Latency = 3

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

SDRAM

Figure 8

Random Read Accesses Within a Page

CLK

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP

BANK,

COL n

DON’T CARE

DOUT

nDOUT

aDOUT

xDOUT

READ

NOTE: Each READ command may be to either bank. DQM is LOW.

READ READ NOP

BANK,

COL a BANK,

COL x BANK,

COL m

CLK

DOUT

T2T1 T4T3 T5T0

COMMAND

ADDRESS

READ NOP

BANK,

COL n

DOUT

aDOUT

xDOUT

READ READ READ NOP

BANK,

COL a BANK,

COL x BANK,

COL m

CLK

DOUT

T2T1 T4T3T0

COMMAND

ADDRESS

READ NOP

BANK,

COL n

DOUT

aDOUT

xDOUT

READ READ READ

BANK,

COL a BANK,

COL x BANK,

COL m

CAS Latency = 1

CAS Latency = 2

CAS Latency = 3

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

SDRAM

Figure 9

HCS READ to WRITE

Data from any read burst may be truncated with a

subsequent WRITE command and data from a fixed-

length read burst may be immediately followed by data

from a subsequent WRITE command (subject to bus

turnaround limitations). The WRITE may be initiated

on the clock edge immediately following the last (or last

desired) data element from the read burst, provided

that I/O contention can be avoided. In a given system

design, there may be the possibility that the device

driving the input data would go Low-Z before the

SyncFlash memory DQs go High-Z. In this case, at least

a single-cycle delay should occur between the last read

data and the WRITE command.

The DQM input is used to avoid I/O contention as

shown in Figure 9. The DQM signal must be asserted

(HIGH) at least two clocks prior to the WRITE command

(DQM latency is two clocks for output buffers) to sup-

press data-out from the READ. Once the WRITE com-

mand is registered, the DQs will go High-Z (or remain

High-Z) regardless of the state of the DQM signal. The

DQM signal must be de-asserted prior to the WRITE

command (DQM latency is zero clocks for input buff-

ers) to ensure that the written data is not masked. Fig-

ure 9 shows the case where the clock frequency allows

for bus contention to be avoided without adding a NOP

cycle.

A fixed-length or full-page read burst can be trun-

cated with ACTIVE TERMINATE (which may or may

not be bank specific) or BURST TERMINATE (which is

not bank specific). The ACTIVE TERMINATE or BURST

TERMINATE command should be issued x cycles be-

fore the clock edge at which the last desired data ele-

ment is valid, where x equals the CAS latency minus

one. This is shown in Figure 11 for each possible CAS

latency; data element n + 3 is the last desired data

element of a burst of four or the last desired of a longer

burst.

READ LCR ACTIVE WRITE

NOP

CLK

T2T1 T4T3T0

DQM, H

OUT

COMMAND

ADDRESS

BANK,

COL n BANK,

COL b

NOTE: A CAS latency of three is used for illustration. The

READ command may be to any bank, and the WRITE

command may be to any bank. If a CAS

latency

of one is

used, then DQM is not required.

40h BANK

ROW

Figure 10

HCS READ to WRITE with Extra Clock

Cycle

DON’T CARE

READ LCR NOPACTIVE NOP

DQM

CLK

OUT

T2T1 T4T3T0

COMMAND

ADDRESS

BANK,

COL n

WRITE

BANK,

COL b

NOTE: A CAS latency of three is used for illustration. The

READ command

may be to any bank, and the WRITE command may be to any bank.

BANK,

ROW

40H

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

SDRAM

Figure 11

Terminating a Read Burst

CLK

DQ D

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK,

COL n

NOP

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3

BURST

TERMINATE NOP

DON’T CARE

NOTE: DQM is LOW.

CLK

DQ D

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP

BANK,

COL n

NOP

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3

BURST

TERMINATE NOP

CLK

DQ D

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP

BANK,

COL n

NOP

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3

BURST

TERMINATE NOP

X = 0 cycles

CAS Latency = 1

X = 1 cycle

CAS Latency = 2

CAS Latency = 3

X = 2 cycles

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

SDRAM

WRITE BURSTS

Write bursts are initiated with a WRITE command as

shown in Figure 12. WRITE commands are preceded by

an FCS program command. The 2 Meg x 32 features a

32-byte internal buffer, while the 4 Meg x 16 features a

16-byte internal write buffer which supports mode reg-

ister programmed burst writes of 1, 2, 4, or 8 locations.

The starting column and bank addresses are provided

with the WRITE command. Once a WRITE command is

registered, a READ command can be executed as de-

fined by Truth Tables 4 and 5. An example is shown in

Figure 14.

During write bursts, the first valid data-in element

will be registered coincident with the WRITE command.

Subsequent data elements will be registered on each

successive positive clock edge. Upon completion of a

fixed-length burst, assuming no other commands have

been initiated, the DQs will remain High-Z and any

additional input data will be ignored (see Figure 13).

ACTIVE TERMINATE

The ACTIVE TERMINATE command is functionally

equivalent to the SDRAM PRECHARGE command. Un-

like SDRAM, SyncFlash memory does not require a

PRECHARGE command to deactivate the open row in a

particular bank or the open rows in all banks. Asserting

input A10 HIGH during an ACTIVE TERMINATE com-

mand will terminate a BURST READ in any bank. When

A10 is low during an ACTIVE TERMINATE command,

BA0 and BA1 will determine which bank will undergo a

terminate operation. ACTIVE TERMINATE is consid-

ered a NOP for banks not addresssed by A10, BA0, BA1

(see Figure 15).

POWER-DOWN

Power-down occurs if CKE is registered LOW coinci-

dent with a NOP or COMMAND INHIBIT when no ac-

cesses are in progress. Entering power-down deacti-

vates the input and output buffers (excluding CKE)

after internal state machine operations (including

WRITE operations) are completed for power savings

while in standby (see Figure 16).

The power-down state is exited by registering a NOP

or COMMAND INHIBIT and CKE HIGH at the desired

clock edge (meeting tCKS).

See the Reset/Deep Power-Down description in the

Flash Memory Functional Description for maximum

power savings mode.

CLOCK SUSPEND

The clock suspend mode occurs when a column ac-

cess/burst is in progress and CKE is registered LOW. In

the clock suspend mode, the internal clock is deacti-

vated, “freezing” the synchronous logic.

For each positive clock edge on which CKE is

sampled LOW, the next internal positive clock edge is

suspended. Any command or data present on the in-

put pins at the time of a suspended internal clock edge

is ignored, any data present on the DQ pins remains

driven, and burst counters are not incremented, as

long as the clock is suspended (see examples in Figures

17 and 18).

Figure 12

WRITE Command

CS#

WE#

CAS#

RAS#

CKE

CLK

COLUMN

ADDRESS

A0–A7

BA0, BA1

BANK

ADDRESS

HIGH

DQ DIN

T2T1 T3T0

COMMAND

ADDRESS

NOP NOP

DON’T CARE

WRITE

DIN

n + 1

NOP

BANK,

COL n

NOTE: Burst length = 2. DQM is LOW.

Figure 13

Write Burst

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

SDRAM

T2T1T0

COMMAND

ADDRESS

BANK,

COL n

WRITE BURST

TERMINATE NEXT

COMMAND

(ADDRESS)

(DATA)

NOTE: DQMs are LOW, and burst

length >1. BURST TERMINATE

command causes data on DQ to

become invalid.

Figure 14

HCS WRITE to READ

CLK

T2T1 T3T0

COMMAND

ADDRESS

WRITE

BANK,

COL n

READ NOP

BANK,

COL b

NOP

NOTE: A CAS latency of two is used for illustration.

The

WRITE command may be to any bank and

the READ command may be to any bank. DQM is

LOW. For more details, refer to Truth Tables 4

and 5.

OUT

Figure 15

Terminating a Write Burst

COMMAND

ADDRESS

WRITE

BANK,

COL n

DIN

NOPNOP

T2T1 T4T3 T5T0

CKE

INTERNAL

CLOCK

NOP

DIN

n + 1 DIN

n + 2

NOTE: For this example, burst length = 4 or greater, and DQM is LOW.

Figure 17

Clock Suspend During Write Burst

tRAS

tRCD

tRC

All banks idle Input buffers gated off

Exit power-down mode.

()()

tCKS t CKS

COMMAND

NOP ACTIVE

Enter power-down mode.

NOP

CLK

CKE

()()

Coming out of a power-down sequence (active),

CKS (CKE setup time) must be greater than or equal to 3ns.

Figure 16

Power-Down

Figure 18

Clock Suspend During Read Burst

DON’T CARE

CLK

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP

BANK,

COL n

NOP

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3

NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and

DQM is LOW.

CKE

INTERNAL

CLOCK

NOP

Clock suspend mode is exited by registering CKE

HIGH; the internal clock and related operation will re-

sume on the subsequent positive clock edge.

BURST READ/SINGLE WRITE

The burst read/single write mode is entered by pro-

gramming the write burst mode bit (M9) in the mode

access of a single column location (burst of one). READ

commands access columns according to the pro-

grammed burst length and sequence.

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

SDRAM

TRUTH TABLE 3 – CKE

(Notes: 1–4)

CKEn-1 CKEnCURRENT STATE COMMANDnACTIONnNOTES

L L Clock Standby X Maintain Clock Standby

Clock Suspend X Maintain Clock Suspend

L H Clock Standby COMMAND INHIBIT or NOP Exit Clock Standby 5

Clock Suspend X Exit Clock Suspend 6

H L No Burst in Progress COMMAND INHIBIT or NOP Clock Standby

Reading VALID Clock Suspend

H H See Truth Table 4

NOTE: 1. “CKEn” is the logic state of CKE at clock edge n; “CKEn-1” was the state of CKE at the previous clock edge.

2. “CURRENT STATE” is the state of the SyncFlash memory immediately prior to clock edge n.

3. “COMMANDn” is the command registered at clock edge n and “ACTIONn” is a result of COMMANDn.

4. All states and sequences not shown are illegal or reserved.

5. Exiting power-down at clock edge n will put the device in the idle state in time for clock edge n + 1 (provided that tCKS

is met).

6. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock

edge n + 1.

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

SDRAM

TRUTH TABLE 4 – CURRENT STATE BANK n; COMMAND TO BANK n

(Notes: 1–6)

CURRENT

STATE CS# RAS#CAS# WE# COMMAND/ACTION NOTES

Any H X X X COMMAND INHIBIT (NOP/continue previous operation)

L H H H NO OPERATION (NOP/continue previous operation)

L L H H ACTIVE (Select and activate row)

Idle L L L H LOAD COMMAND REGISTER

LLLLLOAD MODE REGISTER 7

L L H L ACTIVE TERMINATE 8

L H L H READ (Select column and start Read burst)

Row Active L H L L WRITE (Select column and start WRITE)

L L H L ACTIVE TERMINATE 8

L L L H LOAD COMMAND REGISTER

L H L H READ (Select column and start new Read burst)

Read L L H L ACTIVE TERMINATE 8

L H H L BURST TERMINATE 9

L L L H LOAD COMMAND REGISTER

Write L H L H READ (Select column and start new Read burst) 10

L L L H LOAD COMMAND REGISTER

NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 3).

2. This table is bank specific, except where noted; i.e., the Current State is for a specific bank and the commands shown

are those allowed to be issued to that bank, when in that state. Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank is not in read or write mode.

Row Active: A row in the bank has been activated and tRCD has been met. No data bursts/accesses and no

Read: A read burst has been initiated and has not yet terminated or been terminated.

Write: A WRITE operation has been initiated to the SyncFlash internal state machine (ISM) and has not

yet completed.

4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP

commands, or allowable commands to the other bank, should be issued on any clock edge occurring during these states.

Allowable commands to the other bank are determined by its current state and Truth Table 4, and according to Truth

Table 5.

Active Terminate: Starts with registration of an ACTIVE TERMINATE command and ends on the next clock cycle. The

bank will then be in the idle state.

Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the

bank will be in the row active state.

5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must

be applied on each positive clock edge during these states.

Accessing Mode

Once tMRD is met, the SyncFlash memory will be in the all banks idle state.

Initialize Mode: Starts with RP# transitioning from LOW to HIGH and ends after 100µs delay.

6. All states and sequences not shown are illegal or reserved.

7. Not bank specific; requires that all banks are idle.

8. May or may not be bank specific.

9. Not bank specific; BURST TERMINATE affects the most recent read burst, regardless of bank.

10. A READ operation to the bank under ISM control will output the contents of the row activated prior to the LCR/active/

write sequence (see Truth Table 2a).

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

SDRAM

TRUTH TABLE 5 – CURRENT STATE BANK n; COMMAND TO BANK m

(Notes: 1–6)

CURRENT

STATE CS# RAS#CAS# WE# COMMAND/ACTION

Any H X X X COMMAND INHIBIT (NOP/continue previous operation)

L H H H NO OPERATION (NOP/continue previous operation)

Idle XXXXAny command otherwise allowed to Bank m

Row L L H H ACTIVE (Select and activate row)

Activating, L H L H READ (Select column and start read burst)

Active, or L H L L WRITE (Select column and start WRITE)

Active L L H L ACTIVE TERMINATE

Terminate L L L H LOAD COMMAND REGISTER

L L H H ACTIVE (Select and activate row)

Read L H L H READ (Select column and start new read burst)

L L H L ACTIVE TERMINATE

L L L H LOAD COMMAND REGISTER

L L H H ACTIVE (Select and activate row)

L H L H READ (Select column and start read burst)

Write L L H L ACTIVE TERMINATE

L H H L BURST TERMINATE

L L L H LOAD COMMAND REGISTER (HCS)

NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 3).

2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the

commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given

command is allowable). Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank is not in initialize, read, write mode.

Row Active: A row in the bank has been activated and tRCD has been met. No data bursts/accesses and no

Read: A read burst has been initiated and has not yet terminated or been terminated.

Write: A WRITE operation has been initiated to the SyncFlash ISM and has not yet completed.

4. LOAD MODE REGISTER command may only be issued when all banks are idle.

5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state

only.

6. All states and sequences not shown are illegal or reserved.

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

FLASH

FLASH MEMORY

FUNCTIONAL DESCRIPTION

The SyncFlash memory incorporates a number of

features that make it ideally suited for code storage

and execute-in-place applications on an SDRAM bus.

The memory array is segmented into individual erase

blocks. Each block may be erased without affecting

data stored in other blocks. These memory blocks are

read, programmed, and erased by issuing commands

to the command execution logic (CEL). The CEL con-

trols the operation of the internal state machine (ISM),

which completely controls all READ DEVICE CONFIGU-

RATION, READ STATUS REGISTER, CLEAR STATUS

SETUP/CONFIRM, PROTECT BLOCKS/CONFIRM,

PROTECT DEVICE/CONFIRM, UNPROTECT DEVICE

/CONFIRM, UNPROTECT BLOCKS/CONFIRM, ERASE

NVMODE REGISTER, PROGRAM NVMODE REGISTER,

DISABLE HARDWARE LCR, ERASE SETUP CONFIRM

and CHIP INITIALIZATION operations. The ISM pro-

tects each memory location from overerasure and opti-

mizes each memory location for maximum data reten-

tion. In addition, the ISM greatly simplifies the control

necessary for programming the device in-system or in

an external programmer.

The Flash Memory Functional Description provides

detailed information on the operation of the SyncFlash

memory and is organized into these sections:

• Command Interface

• Memory Architecture

• Output (READ) Operations

• Input Operations

• Command Execution

• Reset/Power-Down Mode

• Error Handling

• PROGRAM/ERASE Cycle Endurance

FLASH COMMAND SEQUENCE

All Flash operations are performed using either a

hardware command sequence (HCS) or a software com-

mand sequence (SCS). The HCS operations are used in

systems that support the LOAD COMMAND REGIS-

TER (LCR) command. In systems that do not have the

ability to generate an LCR command, SCS operations

can be used for Flash operations. A Flash command

sequence (FCS) is used to describe Flash operations

where the actual implementation (HCS or SCS) is not

relevant.

HARDWARE COMMAND SEQUENCE (HCS)

All HCS operations are executed with LCR, LCR/

ACTIVE/READ, or LCR/ACTIVE/WRITE commands

and command sequences as defined in Truth Tables 1

and 2a. See PROGRAM/ERASE diagram for timing in-

formation. See the SDRAM Interface Functional De-

scription for information on reading the memory array.

Address pins A0–A7 are used to input 8-bit com-

mands during the LCR command cycle. This command

will identify which Flash operation is initiated.

Certain LCR/active/write command sequences re-

quire an 8-bit confirmation code on the WRITE cycle.

The confirmation code is input on DQ0–DQ7.

SOFTWARE COMMAND SEQUENCE (SCS)

Flash operations can also be performed using an

SCS. The SCS uses a series of standard CPU READ and

WRITE op-codes to perform Flash operations. This com-

mand interface is similar to the multistep sequence

common in standard Flash components. Table 3 is an

example of programming data into a particular address

using SCS. See Truth Table 2b for a description of SCS

operations.

Table 31

Software Code to Program Data Value 1234h to Address 0000h Using SCS

ASSEMBLY CODE EXECUTED SDRAM COMMANDS ISSUED

OP-CODE ADDRESS, DATA COMMAND BANK ADDRESS DATA

WRITE 00000055h, 00000000h ACTIVE 0h 000h XXXX

WRITE 0h 55h 0000h

WRITE 0000552Ah, 00000055h ACTIVE 0h 055h XXXX

WRITE 0h 2Ah 0055h

WRITE 00008040h, 000000A0h ACTIVE 0h 080h XXXX

WRITE 0h 40h 00A0h

WRITE 00000000h, 00001234h ACTIVE 0h 000h XXXX

WRITE 0h 00h 1234h

NOTE: 1. This is a programming example for the 4 Meg x 16.

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

FLASH

When a CPU executes a WRITE op-code to a memory

address configured for SDRAM, the memory controller

issues an ACTIVE command followed by a WRITE com-

mand. A similar ACTIVE/READ pair is also issued dur-

ing a READ operation. By issuing ACTIVE/WRITE and

ACTIVE/READ pairs with predefined address and data

values, any of the Flash commands can be performed.

MEMORY ARCHITECTURE

The 64Mb SyncFlash memory is a four-bank archi-

tecture with four erasable blocks per bank. By erasing

blocks rather than the entire array, the total device

endurance is enhanced, as is system flexibility. Only

the ERASE and BLOCK PROTECT functions are block

ori-ented. The four banks have simultaneous read-

while-write functionality. An ISM PROGRAM or ERASE

operation to any bank can occur simultaneously to a

READ to any other bank.

The SyncFlash memory has a single background

operation ISM to control power-up initialization,

ERASE, PROGRAM, and PROTECT operations. ISM op-

erations are initiated with an HCS or SCS. Only one ISM

operation can occur at any time; however, certain other

commands, including READ operations, can be per-

formed while an ISM operation is taking place. A new

HCS or SCS will not be permitted until the current ISM

operation is complete.

An operational command controlled by the ISM is

defined as either a bank-level operation or a device-

level operation. PROGRAM and ERASE are bank-level

ISM operations. After an ISM bank-level operation has

been initiated, a READ may be issued to any bank;

however, a READ to the bank under ISM control will

output the contents of the row activated prior to the

HCS or SCS. CHIP INITIALIZE, HARDWARE LCR DIS-

ABLE, ERASE NVMODE REGISTER, PROGRAM

NVMODE REGISTER, BLOCK PROTECT, DEVICE PRO-

TECT, and UNPROTECT ALL BLOCKS are device-level

ISM operations. Once an ISM device-level operation

has been initiated, a READ to any bank will output the

contents of the array. A READ STATUS REGISTER com-

mand sequence may be issued to determine comple-

tion of the ISM operation. When SR7 = 1, the ISM opera-

tion is complete and a new ISM operation may be initi-

ated.

PROTECTED BLOCKS

The 64Mb SyncFlash devices are organized into 16

erasable memory blocks. Each block may be software

protected by issuing the appropriate FCS for a BLOCK

PROTECT operation.

The blocks at locations 0 and 15 have additional

protection to prevent inadvertent PROGRAM or ERASE

operations in platforms where Vih is not available. Once

a PROTECT BLOCK operation has been executed to

these blocks, an UNPROTECT ALL BLOCKS operation

will unlock all blocks except the blocks at locations 0

and 15 unless RP# = VHH. This provides additional secu-

rity for critical code during in-system firmware updates

should an unintentional power disruption or system

reset occur.

A second level of block protection is possible

by completing a hardware DEVICE PROTECT opera-

tion. DEVICE PROTECT prevents block protect bit

modification.

The protection status of any block may be checked

by reading the protect bits with a read device configu-

ration command sequence.

COMMAND EXECUTION LOGIC (CEL)

SyncFlash operations are executed by issuing the

appropriate commands to the CEL. The CEL receives

and interprets commands to the device. These com-

mands control the operation of the ISM and the read

path (i.e., memory array, device configuration, or sta-

tus register). Commands may be issued to the CEL

while the ISM is active. However, there are restrictions

on what commands are allowed in this condition. See

the Command Execution section for more details.

INTERNAL STATE MACHINE (ISM)

Power-up initialization, erase, program, and pro-

tect timings are simplified by using an ISM to control all

programming algorithms in the memory array. The ISM

ensures protection against overerasure and optimizes

programming margin to each cell.

During PROGRAM operations, the ISM automati-

cally increments and monitors PROGRAM attempts,

verifies programming margin on each memory cell and

updates the ISM status register. When BLOCK ERASE is

performed, the ISM automatically overwrites the en-

tire addressed block (eliminates overerasure), incre-

ments and monitors ERASE attempts, and sets bits in

the ISM status register.

ISM STATUS REGISTER

The 16-bit ISM status register allows an external

processor to monitor the status of the ISM during de-

vice initialization, ERASE NVMODE REGISTER, PRO-

GRAM NVMODE REGISTER, PROGRAM, ERASE,

BLOCK PROTECT, DEVICE PROTECT or UNPROTECT

ALL BLOCKS, and any related errors. ISM operations

and related errors can be monitored by reading status

All of the defined bits are set by the ISM, but only

the ISM status bits (SR0, SR1, SR2, SR7) are cleared by

the ISM. The erase/unprotect block, program/protect

block, and device protection bits must be cleared by

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

FLASH

the host system using the CLEAR STATUS REGISTER

command. This allows the user to choose when to poll

and clear the status register. For example, the host

system may perform multiple PROGRAM operations

before checking the status register instead of checking

after each individual PROGRAM.

A VCC power sequence error is cleared by re-

initializing the device.

Asserting the RP# signal or powering down the de-

vice will also clear the status register.

OUTPUT (READ) OPERATIONS

SyncFlash memory features three different types of

READs. Depending on the mode, a READ operation

will produce data from the memory array, status regis-

ter, or one of the device configuration registers.

SyncFlash memory is in the array read mode unless a

status register or device register read is initiated or in

progress.

A READ to the device configuration register or the

status register must be issued as defined by the FCS.

The burst length of data-out is defined by the mode

ister or status register will not disrupt data in a previ-

ously open (or “activated”) page. When the burst is

complete, a subsequent READ will read the array. How-

ever, several differences exist and are described in the

following section. Moving between modes to perform a

specific READ will be covered in the Command Execu-

tion section.

Figure 20

4 Meg x 16 Memory Address Map

256K-word Block

Bank 0

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFF

C00

BFF

800

7FF

400

3FF

000

FFF

C00

BFF

800

7FF

400

3FF

000

FFF

C00

BFF

800

7FF

400

3FF

000

FFF

C00

BFF

800

7FF

400

3FF

000

Bank 1 Bank 2 Bank 3

Unlock Blocks

(RP# = V

)

Word-wide (x16)

Unlock Blocks

(RP# = V

)

Bank

Column

Row

ADDRESS RANGE

NOTE: See block lock and unlock flowchart sequences for

additional information.

128K-Dword Block

Bank 0

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

7FF

600

5FF

400

3FF

200

1FF

000

7FF

600

5FF

400

3FF

200

1FF

000

7FF

600

5FF

400

3FF

200

1FF

000

7FF

600

5FF

400

3FF

200

1FF

000

Bank 1 Bank 2 Bank 3

Unlock Blocks

(RP# = V

)

Dword-wide (x32)

Unlock Blocks

(RP# = V

)

Bank

Column

Row

ADDRESS RANGE

Figure 19

2 Meg x 32 Memory Address Map

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

FLASH

MEMORY ARRAY

A READ command to any bank will output the con-

tents of the memory array. While a PROGRAM or ERASE

ISM operation is in progress, a READ to any location in

the bank under ISM control will output the contents of

the row activated prior to an FCS; a READ to any other

bank will output the contents of the array. All com-

mands and their operations are covered in the SDRAM

Interface Functional Description section.

STATUS REGISTER

Reading the status register requires an FCS. The

status register contents are latched on the next posi-

tive clock edge subject to CAS latencies. The burst

length of the status register data-out is defined by the

mode register.

All commands and their operations are covered in

the Command Execution section.

DEVICE CONFIGURATION REGISTERS

To read the device ID, manufacturer compatibility

ID, device protection status, block protect status, and

the hardware LCR disable bit, the appropriate com-

mand sequence for READ DEVICE CONFIGURATION

must be issued. This is the same input sequencing

used when reading the status register, except that spe-

cific addresses must be issued.

INPUT OPERATIONS

An FCS is required to program the array, or to per-

form an ERASE, PROTECT, UNPROTECT, or HARD-

WARE LCR DISABLE operation. The first cycle of an

input operation is an FCS operation where inputs A0–

A7 determine the input command being executed to

the CEL. An input operation will not disrupt data in a

previously opened page.

The DQ pins are used either to input data to the

array or to input a command to the CEL during the

WRITE cycle.

More information describing how to program, erase,

protect, or unprotect the device is provided in the Com-

mand Execution section.

MEMORY ARRAY

Programming or erasing the memory array sets the

desired bits to logic 0s but cannot change a given bit to

a logic 1 from a logic 0. Setting any bit to a logic 1 re-

quires that the entire block be erased. Programming a

protected block requires that the RP# pin be brought to

VHH. A0–A10 (x32), A0–A11 (x16) provide the address to

be programmed, while the data to be programmed in

the array is input on the DQ pins. The data and ad-

dresses are latched on the rising edge of the clock.

Details on how to input data to the array is covered in

the Command Execution section.

COMMAND EXECUTION

Commands are issued to bring the device into dif-

ferent operational modes. Each mode has specific op-

erations that can be performed while in that mode. All

HCS modes require that an LCR/active/read or LCR/

active/write sequence be issued, except CLEAR STA-

TUS REGISTER, which is a single LCR command. In-

puts A0–A7 during the FCS determine the operation

being performed. The following section describes the

properties of each mode, and Truth Tables 1, 2a, and

2b list all commands and command sequences re-

quired to perform the desired operation. Read-while-

write functionality allows a background operation pro-

gram or erase to any bank while simultanously reading

any other bank.

The HCS operations in Truth Table 2a must be com-

pleted on consecutive clock cycles. However, in order

to reduce bus contention issues, an unlimited number

of NOPs or COMMAND INHIBITs can be issued

throughout the LCR/active/write command sequence.

For additional protection, these command sequences

must have the same bank address for the three com-

mand cycles.

The SCS operations described in Truth Table 2b

must also be completed on adjacent clock cycles. The

SCS operation will allow NOP, COMMAND INHIBIT,

REFRESH, and BURST TERMINATE commands to be

issued during the sequence without aborting the se-

quence. All steps in the SCS must access the same bank

or the operation will be aborted and the device will

return to the read array mode.

If the bank address changes during the FCS or if the

command sequences are not consecutive (other than

NOPs and COMMAND INHIBITs), the program and

erase status bits (SR4 and SR5) will be set and the de-

sired operation will be aborted.

For additional protection, these command se-

quences must have the same bank address during all

command cycles.

STATUS REGISTER

Reading and clearing the status register requires an

FCS. During status reads, the status register contents

are latched on the next positive clock edge, subject to

CAS latencies, for a burst length defined by the mode

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

FLASH

DEVICE CONFIGURATION

To read the device ID, manufacturer compatibility

ID, device protect bit, and each of the block protect

bits, the appropriate FCS operation for READ DEVICE

CONFIGURATION must be issued. Specific configura-

tion addresses must be issued to read the desired in-

formation. The manufacturer compatibility ID is read

at 000h; the device ID is read at 001h. The manufac-

turer compatibility ID and device ID are output on

DQ0–DQ7. The device protect bit is read at 003h; and

each of the block protect bits is read on the third ad-

dress location within each block (x02h). The device and

block protect bits are output on DQ0. The mode regis-

ter is read from address 004h. The hardware load com-

mand register bit is available on bit 0 of address 005h.

A LOW on bit zero means that HCS operations are

disabled and a HIGH means that HCS operations are

allowed.

The device configuration register contents are out-

put subject to CAS latencies for a burst length defined

by the mode register.

PROGRAM SEQUENCE

Using an HCS operation, three commands on con-

secutive clock edges are required to input data to the

array (NOPs and COMMAND INHIBITS are permitted

between cycles). See Table 2a. In the first cycle, LOAD

COMMAND REGISTER is issued with PROGRAM SETUP

(40h) on A0–A7, and the bank address is issued on BA0,

BA1. The next command is ACTIVE, which identifies

the row address and confirms the bank address. The

third cycle is WRITE, during which the column address,

the bank address, and data are issued.

To perform a program operation using an SCS op-

eration, the system executes a series of WRITE op-codes

using a predetermined set of address/data values (see

Truth Table 2b). The SCS operation will result in the

command register being loaded with the PROGRAM

command (40h), and the CEL being loaded with the

address and data value to be programmed.

The ISM status bit will be set on the following clock

edge (subject to CAS latencies).

While the ISM is programming the array, the ISM

status bit (SR7) will be at “0.” When the ISM status bit

(SR7) is set to a logic 1, programming is complete, and

the bank will be in the array read mode and ready for a

new ISM operation.

Programming hardware-protected blocks requires

that the RP# pin be set to VHH during the FCS, and RP#

must be held at VHH until the ISM PROGRAM operation

is complete. The program and erase status bits (SR4

and SR5) will be set and the operation aborted if the

FCS command sequence is not completed on consecu-

tive cycles or the bank address changes for any of the

three cycles. After the ISM has initiated programming,

it cannot be aborted except by a reset or by powering

down the device. Doing either while programming the

array will corrupt the data being written.

ERASE SEQUENCE

Executing an erase sequence will set all bits within a

block to logic 1. The HCS necessary to execute an ERASE

is similar to that of a PROGRAM. To provide added

security against accidental block erasure, three con-

secutive command sequences on consecutive clock

edges are required to initiate an ERASE of a block. See

Table 2a. In the first cycle, LOAD COMMAND REGIS-

TER is issued with ERASE SETUP (20h) on A0–A7, and

the bank address of the block to be erased is issued on

BA0, BA1. The next command is ACTIVE, where A10,

A11, BA0, and BA1 provide the address of the block to

be erased. The third cycle is WRITE, during which

ERASE CONFRIM (D0h) is issued on DQ0–DQ7 and the

bank address is reissued. The ISM status bit will be set

on the following clock edge (subject to CAS latencies).

After ERASE CONFIRM (D0h) is issued, the ISM will

start erasing the addressed block. When the ERASE

operation is complete, the bank will be in the array read

mode and ready for an executable command. Erasing

hardware-protected blocks also requires that the RP#

pin be set to VHH prior to the third cycle (WRITE), and

RP# must be held at VHH until the ERASE operation is

complete (SR7 = 1). If the HCS is not completed on

consecutive cycles (NOP, COMMAND INHIBIT,

PRECHARGE, and REFRESH are permitted between

cycles) or the bank address changes for one or more of

the command cycles, the program and erase status bits

(SR4 and SR5) will be set.

During the SCS operation, eight commands on con-

secutive clock edges are required to input data to the

array (NOP and COMMAND INHIBIT are permitted

between cycles). See Table 2b. After the first five setup

cycles, the next three cycles are identical to the normal

LCR command sequence except the command for the

first of last three cycles is a WRITE instead of an LCR.

The ISM status bit is set on the following clock edge

(subject to CAS latencies), indicating the ERASE op-

eration is in progress.

PROGRAM AND ERASE NVMODE REGISTER

The contents of the mode register may be copied

into the nvmode register with a PROGRAM NVMODE

nvmode register, an erase nvmode register command

sequence must be completed to set all bits in the

nvmode register to logic 1. The command sequence

necessary to execute an ERASE NVMODE REGISTER

and PROGRAM NVMODE REGISTER is similar to that

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

FLASH

of a program sequence. See Truth Tables 2a and 2b for

more information on the FCS operations necessary to

complete ERASE NVMODE REGISTER and PROGRAM

NVMODE REGISTER.

BLOCK PROTECT/UNPROTECT SEQUENCE

Executing a block protect sequence enables the first

level of software/hardware protection for a given block.

The command sequence necessary to execute a BLOCK

PROTECT is similar to that of a program sequence. To

provide added security against accidental block pro-

tection, three consecutive command cycles are re-

quired to initiate a BLOCK PROTECT during a normal

HCS. In the first cycle, LOAD COMMAND REGISTER is

issued with PROTECT SETUP (60h) on A0–A7, and the

bank address of the block to be protected is issued on

BA0, BA1. The next cycle is ACTIVE, which identifies a

row in the block to be protected and confirms the bank

address. The third cycle is WRITE, during which BLOCK

PROTECT CONFIRM (01h) is issued on DQ0–DQ7, and

the bank address is reissued. The ISM status bit is set

on the following clock edge (subject to CAS latencies),

indicating the PROTECT operation is in progress.

If the LCR/ACTIVE/WRITE is not completed on con-

secutive cycles (NOP and COMMAND INHIBIT, RE-

FRESH, and PRECHARGE are permitted between

cycles), or the bank address changes, the write and

erase status bits (SR4 and SR5) will be set and the op-

eration will be aborted. When the ISM status bit (SR7) is

set to a logic 1, the PROTECT is complete.

During the SCS operation, eight commands on con-

secutive clock edges are required to input data to the

array (NOP, COMMAND INHIBIT, REFRESH, and

PRECHARGE are permitted between cycles). After the

first six setup cycles, the last 2 cycles are identical to the

normal HCS. The ISM status bit is set on the following

clock edge (subject to CAS latencies) indicating the

PROTECT operation is in progress.

Once a block protect bit has been set to a “1” (pro-

tected), it can only be reset to a “0” if the UNPROTECT

ALL BLOCKS command is executed. The unprotect all

blocks command sequence is similar to the block pro-

tect sequence; however, in the last FCS cycle, a WRITE

is issued with UNPROTECT ALL BLOCKS CONFIRM

(D0h) and addresses are “Don’t Care.” For additional

information, refer to Truth Tables 2a and 2b.

The blocks at locations 0 and 15 have additional

security. Once the block-protect bits at locations 0 and

15 have been set to a “1” (protected), each bit can only

be reset to a “0” if RP# is brought to VHH prior to the third

cycle (WRITE) of the UNPROTECT operation and held

at VHH until the operation is complete (SR7 = 1).

If the device protect bit is set, RP# must be brought

to VHH prior to the last FCS cycle and held at VHH until

the BLOCK PROTECT or UNPROTECT ALL BLOCKS op-

eration is complete.

To check a block’s protect status, a read device con-

figuration command sequence may be issued.

DEVICE PROTECT SEQUENCE

Executing a device protect command sequence sets

the device protect bit to a “1” and prevents block pro-

tect bit modification. The command sequence neces-

sary to execute a DEVICE PROTECT is similar to that of

a PROGRAM sequence. During normal HCS operation,

LOAD COMMAND REGISTER is issued in the first cycle

with protect setup (60h) on A0–A7, and a bank address

is issued on BA0, BA1. The bank address is “Don’t Care,”

but the same bank address must be used for all three

cycles. The next cycle is ACTIVE. The third cycle is

WRITE, during which DEVICE PROTECT (F1h) is is-

sued on DQ0–DQ7. RP# must be brought to VHH prior to

registration of the WRITE command.

During the SCS, eight commands on consecutive

clock edges are required to input data to the array (NOP,

COMMAND INHIBIT, REFRESH, PRECHARGE, and

BURST TERMINATE are permitted between cycles).

After the first five setup cycles, the last three cycles are

indentical to the normal HCS, except the command for

the first of the last three cycles is a WRITE instead of an

LCR. The ISM status bit is set on the following clock

edge (subject to CAS latencies). RP# must be held at

VHH until the PROTECT operation is complete (SR7 = 1).

Once the device protect bit is set, it can be reset by

issuing an UNPROTECT BLOCK command with RP# =

VHH. With the device protect bit set to a “1,” BLOCK

PROTECT or BLOCK UNPROTECT is prevented unless

RP# is at VHH during either operation. The device pro-

tect bit does not affect PROGRAM or ERASE operations.

CHIP INITIALIZE SEQUENCE

Executing a chip initialize sequence can be accom-

plished one of two ways. The first option is a hardware

initiated power-up using the RP# transition to initiate a

reset. A successful entry into the reset mode requires

that RP# be held LOW for a minimum of 5µs before

transitioning HIGH.

The second option is called a software initiated

power-up, which requires an INITIALIZE DEVICE FCS

operation for a successful entry into reset mode.

During an HCS INITIALIZE DEVICE operation, the

LOAD COMMAND REGISTER command is issued in

the first cycle with CHIP INITIALIZE (68h) issued on

A0–A7, and a bank address issued on BA0, BA1. The

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

FLASH

bank address is “Don’t Care,” but the same bank ad-

dress must be used for all three cycles. The second

cycle is ACTIVE, and the third cycle is WRITE, during

which C0h is issued on DQ0-DQ7. Once the last com-

mand is issued, the initialization sequence will com-

mence.

During an SCS INITIALIZE DEVICE operation, eight

commands on consecutive clock edges are required to

input data to the array (NOP, COMMAND INHIBIT,

REFRESH, PRECHARGE, and BURST TERMINATE are

permitted between cycles). After the first five setup

cycles, the last three cycles are identical to a typical

HCS, except the command for the first of the last

three cycles is a WRITE instead of an LCR. Once the last

command is issued, the initialization sequence will

commence.

The initialization sequence is completed either by

allowing a time period of 100µs to elapse or by checking

for SR7 = 1.

DISABLE LCR SEQUENCE

In some systems the SDRAM controller does not

support the generation of the LCR command. These

systems will likely find that the SCS is more practical for

performing Flash operations. The DISABLE LCR com-

mand can be issued with either an HCS or SCS opera-

tion. Once issued, the DISABLE LCR bit will no longer

allow HCS operations. Note that unless DISABLE LCR

is issued, the device can function in either HCS or SCS

mode.

RESET/DEEP POWER-DOWN MODE

To allow for maximum power conservation, the de-

vice features a very low current, deep power-down

mode.

To enter this mode, RP# (reset/power-down) is taken

to VSS ±0.2V. To prevent an inadvertent reset, RP# must

be held at VSS for at least 5µs prior to the device entering

the reset/deep power-down mode. After the device

enters the reset/deep power-down mode, a transition

from LOW to HIGH on RP# results in a device power-up

initialization sequence as outlined in the Chip Initial-

ization section. When the device enters the deep power-

down mode, all buffers excluding the RP# buffer are

disabled and the current draw is a maximum of 50µA at

3.3V VCC. The input to RP# must remain at VSS during

deep power-down. Entering the reset mode clears the

status register.

ERROR HANDLING

After the ISM status bit (SR7) has been set, the de-

vice protect (SR3), write/protect block (SR4) and erase/

unprotect (SR5) status bits may be checked. If one or a

combination of SR3, SR4, SR5 status bits has been set,

an error has occurred. SR8 is set when an inadvertent

power failure occurs during device initialization. The

device should be reinitialized to ensure proper device

operation. The ISM cannot reset SR3, SR4, SR5, or SR8.

To clear these bits, CLEAR STATUS REGISTER com-

mand must be given. Table 6 lists the combination of

errors.

PROGRAM/ERASE CYCLE ENDURANCE

SyncFlash memory is designed and fabricated to

meet advanced code and data storage requirements.

Operation outside specification limits may reduce the

number of PROGRAM and ERASE cycles that can be

performed on the device. Each block is designed and

processed for a minimum of 100,000-PROGRAM/

ERASE-cycle endurance.

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

FLASH

STATUS

BIT # STATUS REGISTER BIT DESCRIPTION

SR15– RESERVED Reserved for future use.

SR9

SR8 VCC POWER SEQUENCE STATUS (VPS) VPS is set if there has been a power disruption that may result in

1 = Power-up incomplete error undefined device operation. A VPS error is only cleared by

0 = Power-up complete re-initializing the device.

SR7 ISM STATUS (ISMS) The ISMS bit displays the active status of the state machine

1 = Ready when performing PROGRAM, BLOCK ERASE or CHIP INITIALIZE.

0 = Busy The controlling logic polls this bit to determine when the erase

and program status bits are valid. This bit can be monitored to

determine the completion of power-up initialization after CHIP

INITIALIZATION sequence is issued.

SR6 RESERVED Reserved for future use.

SR5 ERASE/UNPROTECT BLOCK STATUS (ES) ES is set to “1” after the maximum number of ERASE cycles is

1 = BLOCK ERASE or BLOCK executed by the ISM without a successful verify. This bit is also set

UNPROTECT error to “1” if a BLOCK UNPROTECT operation is unsuccessful. ES is

0 = Successful BLOCK ERASE or only cleared by a CLEAR STATUS REGISTER command or by a

UNPROTECT RESET.

SR4 PROGRAM/PROTECT BLOCK STATUS (WS) WS is set to “1” after the maximum number of PROGRAM cycles

1 = PROGRAM or BLOCK PROTECT error is executed by the ISM without a successful verify. This bit is also

0 = Successful BLOCK ERASE or set to “1” if a BLOCK or DEVICE PROTECT operation is

UNPROTECT unsuccessful. WS is only cleared by a CLEAR STATUS REGISTER

command or by a RESET.

SR3 DEVICE PROTECT STATUS (DPS) DPS is set to “1” if an invalid PROGRAM, ERASE, PROTECT

1 = Device protected, invalid operation BLOCK, PROTECT DEVICE or UNPROTECT ALL BLOCKS is met.

attempted After one of these commands is issued, the condition of RP#, the

0 = Device unprotected or RP# block protect bit and the device protect bit are compared to

condition met determine if the desired operation is allowed. Must be cleared by

CLEAR STATUS REGISTER or by a RESET.

SR2 BANKA1 ISM STATUS (BISMS) When SR0 = 0, the bank under ISM control can be decoded from

SR1 BANKA0 ISM STATUS SR1, SR2: [0,0] Bank 0; [0,1] Bank 1; [1,0] Bank 2; [1,1] Bank 3.

SR1, SR2 is valid when SR7 = 0. When SR7 = 1, SR1, SR2 is reset to

“0.”

SR0 DEVICE/BANK ISM STATUS (DBS) DBS is set to “1” if the ISM operation is a device-level operation.

1 = Device-level ISM operation A valid READ to any bank can immediately follow the

0 = Bank-level ISM operation registration of an ISM PROGRAM operation. When DBS is set to

“0,” the ISM operation is a bank-level operation. A READ to the

bank under ISM control will output the contents of the row

activated prior to the FCS. SR1 and SR2 can be decoded to

determine which bank is under ISM control. SR0 is used in

conjuction with SR7, and is valid when SR7 = 0. When SR7 = 1,

SR0 is reset to “0.”

NOTE: 1. SR3–SR5 must be cleared with CLEAR STATUS REGISTER prior to initiating an ISM WRITE operation for the status bits to

be valid.

2. x32: SR32-SR16 is a copy of SR15-SR0.

Table 4

Status Register Bit Definition1

R VPS ISMS R ES WS DPS BISMS DBS

15–9 8 7 6 5 4 3 2–1 0

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

FLASH

Table 5

Device Configuration

DEVICE CONFIGURATION

CONFIGURATION ADDRESS DATA CONDITION NOTES

Manufacturer 000h xx2Ch Manufacturer compatibility ID read 1

Compatibility ID

Device ID x32: 001h xxD4h Device ID read 1

x16: 001h xxD5h Device ID read 1

Block Protect Bit x02h DQ0 = 1 Block protected 2, 3

x02h DQ0 = 0 Block unprotected

Device Protect Bit 003h DQ0 = 1 Block protect modification prevented 3

003h DQ0 = 0 Block protect modification enabled

Mode Register 004h Mode register definition data 4

Hardware LCR Disable 005h DQ0 = 1 Hardware LCR is disabled 3, 5

005h DQ0 = 0 Hardware LCR is enabled

NOTE: 1. DQ8–DQ15 are “Don’t Care.” For x32, DQ31–DQ16 are a copy of DQ15–DQ0.

2. Address to read block protect bit is always the third location within each block.

x32: X = 0, 2, 4, 6h; BA0, BA1 required.

x16: X = 0, 4, 8, Ch; BA0, BA1 required.

3. DQ1–DQ7 are reserved, DQ8–DQ15 are “Don’t Care.” For x32, DQ31–DQ16 are a copy of DQ15–DQ0.

4. See Figure 1 for more information.

5. Factory preset is “0.”

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

FLASH

Table 6

Status Register Codes1

STATUS

CODE SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 STATE MACHINE DESCRIPTION

000h 000000000Busy – ERASE or PROGRAM cycle for Bank 0

001h 000000001Busy – BLOCK PROTECT or UNPROTECT

cycle

002h 000000010Busy – ERASE or PROGRAM cycle for Bank 1

003h 000000011Busy – DEVICE PROTECT cycle

004h 000000100Busy – ERASE or PROGRAM cycle for Bank 2

005h 000000101Busy – NVMODE ERASE or PROGRAM cycle

006h 000000110Busy – ERASE or PROGRAM cycle for Bank 3

007h 000000111Busy – INITIALIZATION cycle

010h 000010000Busy – PROGRAM cycle error for Bank 0

011h 000010001Busy – BLOCK PROTECT cycle error

012h 000010010Busy – PROGRAM cycle error for Bank 1

013h 000010011Busy – DEVICE PROTECT cycle error

014h 000010100Busy – PROGRAM cycle error for Bank 2

015h 000010101Busy – NVMODE PROGRAM cycle error

016h 000010110Busy – PROGRAM cycle error for Bank 3

020h 000100000Busy – ERASE cycle error for Bank 0

021h 000100001Busy – BLOCK UNPROTECT cycle error

022h 000100010Busy – ERASE cycle error for Bank 1

023h 000100011Busy – DEVICE UNPROTECT cycle error

024h 000100100Busy – ERASE cycle error for Bank 2

025h 000100101Busy – NVMODE ERASE cycle error

026h 000100110Busy – ERASE cycle error for Bank 3

080h 010000000Ready – No errors

090h 010010000Ready – PROGRAM or PROTECT cycle error

098h 010011000Ready – Program/protect error and device/

block protection error

0A0h 010100000Ready – ERASE or UNPROTECT cycle error

0A8h 010101000Ready – Erase/unprotect error and device/

block protection error

0B0h 010110000Ready – Command sequence error

0B8h 010111000Ready – Command sequence error and

device/block protection error

1xxh 1 XXXXXXXXVCC error (power-up without initialization

error)

NOTE: 1. SR3–SR5 must be cleared using CLEAR STATUS REGISTER.

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

FLASH

COMPLETE PROGRAM STATUS-CHECK

SEQUENCE

SELF-TIMED PROGRAM SEQUENCE1

NOTE: 1. Sequence may be repeated for multiple PROGRAMs.

2. FCS includes HCS and SCS.

3. Complete status check is not required.

4. The bank will be in array read mode.

5. SR3–SR5 must be cleared using CLEAR STATUS REGISTER.

Start

FCS Command

Sequence

Read Status Register

Polling

SR7 = 1?

Complete Status

Check

PROGRAM Complete

YES

Start (PROGRAM completed)

SR4, SR5 = 1? YES Command Sequence Error

SR4 = 1?

YES

PROGRAM Successful

SR3 = 1? Invalid PROGRAM Error

PROGRAM Error

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

FLASH

SELF-TIMED BLOCK ERASE

SEQUENCE1

COMPLETE BLOCK ERASE

STATUS-CHECK SEQUENCE

NOTE: 1. Sequence may be repeated to erase multiple blocks.

2. FCS includes HCS and SCS.

3. RP# can be brought to VHH before the last command in the erase sequence is issued.

4. Complete status check is not required.

5. The bank will be in the array read mode.

6. SR3–SR5 must be cleared using CLEAR STATUS REGISTER.

FCS Command

Sequence

Start

Read Status Register

SR7 = 1

Complete Status

Check

ERASE Complete

YES

2, 3

Start (BLOCK ERASE completed)

SR4, SR5 = 1? YES Command Sequence Error

SR5 = 1?

YES

BLOCK ERASE or

UNPROTECT Error

ERASE or BLOCK UNPROTECT Successful

SR3 = 1? Invalid ERASE or

UNPROTECT Error

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

FLASH

BLOCK PROTECT SEQUENCE1

NOTE: 1. Sequence may be repeated for multiple BLOCK PROTECTs.

2. FCS includes HCS and SCS.

3. RP# can be brought to VHH before the last command in the block protect sequence is issued.

4. Complete status check is not required.

5. The bank will be in array read mode.

6. SR3–SR5 must be cleared using CLEAR STATUS REGISTER.

Start

FCS Command

Sequence

2, 3

Complete Status

Check

DEVICE PROTECT Complete

4, 5

YES

Read Status Register

SR7 = 1

COMPLETE BLOCK PROTECT

STATUS-CHECK SEQUENCE

Start (BLOCK PROTECT completed)

SR4 = 1? BLOCK or DEVICE

PROTECT Error

BLOCK PROTECT Successful

SR3 = 1? Invalid BLOCK/DEVICE

PROTECT Error

SR4, SR5 = 1? YES Command Sequence Error

YES

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

FLASH

DEVICE PROTECT SEQUENCE1COMPLETE BLOCK

STATUS-CHECK SEQUENCE

NOTE: 1. Once the device protect bit is set, it can be reset.

2. FCS includes HCS and SCS.

3. RP# can be brought to VHH before the last command in the device protect sequence is issued.

4. Complete status check is not required.

5. A subsequent WRITE command may be issued.

Start

FCS Command

Sequence2, 3

Complete Status

Check

DEVICE PROTECT Complete4, 5

YES

Read Status Register

SR7 = 1

FCS Command

Sequence

Start

Read Status Register

Complete Status

Check

ALL BLOCKS UNPROTECT Complete

4, 5

SR7 = 1

YES

RP# = V

Device

Protected?

Unprotect

Blocks 1-14?

YES

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

FLASH

COMPLETE DEVICE PROTECT

STATUS-CHECK SEQUENCE

Start (DEVICE PROTECT completed)

SR4 = 1? BLOCK or DEVICE

PROTECT Error

DEVICE PROTECT Successful

SR3 = 1? Invalid BLOCK/DEVICE

PROTECT Error

SR4, SR5 = 1? YES Command Sequence Error

YES

NOTE: 1. SR3–SR5 must be cleared using CLEAR STATUS REGISTER.

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

FLASH

ABSOLUTE MAXIMUM RATINGS*

Voltage on RP# Relative to VSS ...................... -1V to +9V

Voltage on VCC, VCCP, or VCCQ Supply, Inputs,

or I/Os Relative to VSS ........................ -1V to +2.45V

Operating Temperature,

TA (ambient)..................................... -40ºC to +85ºC

Storage Temperature (plastic) ........... -55ºC to +150ºC

Power Dissipation ........................................................ 1W

Short Circuit Output Current................................ 50mA

*Stresses greater than those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional

operation of the device at these or any other conditions

above those indicated in the operational sections of

this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may

affect reliability.

NOTE: 1. All voltages referenced to VSS.

2. An initial pause of 100µs is required after power-up. (VCC, VCCP, and VCCQ must be powered up simultaneously. VSS and

VSSQ must be at same potential.)

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS1, 2

Commercial Temperature (-40ºC £ TA £ +85ºC); VCC = 3.0V–3.6V; VCCQ = 1.65V–1.95V

PARAMETER/CONDITION SYMBOL MIN MAX UNIT

VCC SUPPLY VOLTAGE VCC 3.0 3.6 V

VCCQ SUPPLY VOLTAGE VCCQ 1.65 1.95 V

HARDWARE PROTECTION VOLTAGE VHH 7.0 8.5 V

(RP# only)

INPUT HIGH VOLTAGE: VIH 0.8 × VCCQVCCQ + 0.4 V

Logic 1; All Inputs

INPUT LOW VOLTAGE: VIL -0.3 0.3 V

Logic 0; All Inputs

INPUT LEAKAGE CURRENT:

Any input 0V £ VIN £ VCC IL-2 2 µA

(All other pins not under test = 0V)

OUPUT LEAKAGE CURRENT: IOZ -5 5 µA

DQs are disabled; 0V £ VOUT £ VCCQ

OUTPUT HIGH VOLTAGE: VOH VCCQ - 0.2 – V

IOUT = -100µA

OUTPUT LOW VOLTAGE: VOL – 0.2 V

IOUT = 100µA

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

FLASH

ICC SPECIFICATIONS AND CONDITIONS

(Notes: 1, 2, 3); Extended Temperature (-40ºC £ TA £ +85ºC); VCC = 3.0V–3.6V; VCCQ = 1.65V–1.95V

-8 -10

PARAMETER/CONDITION SYMBOL MAX TYP MAX TYP UNITS NOTES

VCC OPERATING CURRENT: ICCR 125 120 mA 4, 5, 6

READ Operation; Burst Mode

All banks active; READ; CAS latency = 3

VCC OPERATING CURRENT: ICCA 100 95 mA 4

ACTIVE Operation

All banks active

VCC STANDBY CURRENT: ICCS110 10 mA

Active Mode; CKE = HIGH; Burst in progress

VCC STANDBY CURRENT: ICCS222mA

Power-Down Mode; CKE = LOW; No burst in progress

VCC STANDBY CURRENT: ICCS3200 200 µA

Clock-Quiet Mode; CLK = CKE = LOW

VCC DEEP POWER-DOWN CURRENT: ICCDP 200 50 µA

RP# = VSS ±0.2V or DEEP POWER-DOWN Command

PROGRAM CURRENT ICCW + IPPW 55 55 mA

VCCP ERASE CURRENT IPPE 80 80 mA

VCCP CURRENT: IPPS 11µA

Standby; Power-Down; Deep Power-Down

CAPACITANCE

PARAMETER SYMBOL TYP MAX UNITS NOTES

Input Capacitance: CLK CI12.5 4.0 pF 7

Input Capacitance: All other input-only pins CI22.5 5.0 p F 7

Input/Output Capacitance: DQs CIO 4.0 6.5 pF 7

NOTE: 1. All voltages referenced to VSS.

2. An initial pause of 100µs is required after power-up. (VCC, VCCP, and VCCQ must be powered up simultaneously. VSS and

VSSQ must be at same potential.)

3. ICC specifications are tested after the device is properly initialized.

4. ICC is dependent on output loading and cycle rates. Specified values are obtained with the outputs open.

5. The ICC current will decrease as the CAS latency is reduced. This is due to the fact that the maximum cycle rate is

slower as the CAS latency is reduced.

6. Address transitions average one transition every 30ns.

7. This parameter is sampled. VCC = VCCQ; f = 1 MHz, TA = +25ºC.

8. Typical conditions: +25oC, burst length = 8, tRC = 140ns.

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

FLASH

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(Notes: 1, 2, 3, 4, 5); Extended Temperature (-40ºC £ TA £ +85ºC); VCC = 3.0V–3.6V; VCCQ = 1.65V–1.95V

AC CARACTERISTICS -8 -10

PARAMETER SYM MIN MAX MIN MAX UNITS NOTES

Access time from CLK (pos. edge) CL = 3 tAC 7 7 ns

CL = 2 tAC 8 8 ns

CL = 1 tAC 19 22 ns

Address hold time tAH 1 1 ns

Address setup time tAS 2 2 ns

CLK high level width tCH 3 3 ns

CLK low level width tCL 3 3 ns

Clock cycle time CL = 3 tCK 8 10 ns

CL = 2 tCK 10 12 ns

CL = 1 tCK 20 25 ns

CKE hold time tCKH 1 1 ns

CKE setup time tCKS 2 2 ns

CS#, RAS#, CAS#, WE#, DQM hold time tCMH 1 1 ns

CS#, RAS#, CAS#, WE#, DQM setup time tCMS 2 2 ns

Data-in hold time tDH 1 1 ns

Data-in setup time tDS 2 2 ns

Data-out high-impedance time CL = 3 tHZ 7 7 ns 6

CL = 2 tHZ 8 8 ns 6

CL = 1 tHZ 19 22 ns 6

Data-out low-impedance time tLZ 1 1 ns

Data-out hold time tOH 3 3 ns

ACTIVE command period tRC 60 60 ns

ACTIVE to READ or WRITE delay tRCD 24 30 ns

ACTIVE bank A to ACTIVE bank B command tRRD 24 30 ns

Transition time tT 0.3 1.2 0.3 1.2 ns 7

NOTE: 1. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature

range is ensured.

2. An initial pause of 100µs is required after power-up. (VCC, VCCP, and VCCQ must be powered up simultaneously. VSS and

VSSQ must be at same potential.)

3. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between

VIL and VIH) in a monotonic manner.

4. Outputs measured at 0.8V with equivalent load:

5. AC timing and ICC tests have VIL = 0V and VIH = 1.6V, with timing referenced to 0.8V crossover point.

6. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The

last valid data element will meet tOH before going High-Z.

7. AC characteristics assume tT = 1ns.

30pF

x32

50pF

x16

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

FLASH

NOTE: 1. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature

range is ensured.

2. An initial pause of 100µs is required after power-up. (VCC, VCCP, and VCCQ must be powered up simultaneously. VSS and

VSSQ must be at same potential.)

3. AC characteristics assume tT = 1ns.

4. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between

VIL and VIH) in a monotonic manner.

5. Outputs measured at 0.8V with equivalent load:

50pF

x16

30pF

x32

6. AC timing and ICC tests have VIL = 0V and VIH = 1.6V, with timing referenced to 0.8V crossover point.

7. Required clocks specified by JEDEC functionality and not dependent on any timing parameter.

8. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate.

AC FUNCTIONAL CHARACTERISTICS

(Notes: 1-6); Extended Temperature (-40ºC £ TA £ +85ºC); VCC = 3.0V–3.6V; VCCQ = 1.65V–1.95V

PARAMETER SYMBOL -8 -10 UNITS NOTES

READ/WRITE to READ/LOAD COMMAND REGISTER command tCCD 1 1 tCK 7

CKE to clock disable or power-down entry mode tCKED 1 1 tCK 8

CKE to clock enable or power-down exit setup mode tPED 1 1 tCK 8

DQM to input data delay tDQD 0 0 tCK 7

DQM to data mask during WRITEs tDQM 0 0 tCK 7

DQM to data high-impedance during READs tDQZ 2 2 tCK 7

WRITE command to input data delay tDWD 0 0 tCK 7

Data-in to ACTIVE command tDAL 5 5 tCK

Data-in to ACTIVE TERMINATE command tDPL 2 2 tCK

LOAD MODE REGISTER command to ACTIVE command tMRD 2 2 tCK 7

Data-out to High-Z from ACTIVE TERMINATE command CL = 3 tROH 3 3 tCK 7

CL = 2 tROH 2 2 tCK 7

CL = 1 tROH 1 1 tCK

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

FLASH

INITIALIZE AND LOAD MODE REGISTER (RP# CONTROL)

tCH

tCL

CKE

CLK

Tm Tn + 2 Tn + 3

COMMAND

ADDRESS

OPCODE

tMRD

Load Mode Register

3, 4, 5

tCMS

Power-up:

, V

P, V

CLK stable

T = 100µs

tAH

tAS

ROW

LOAD MODE

High-Z

DQM

, V

DON’T CARE

UNDEFINED

Tn Tn + 1

tCK

tCMH

tCKH

tCKS

()()

(

)(

)

()()

RP#

()()

(

)(

)

(

)(

)

()()

(

)(

)

()()

(

)(

)

(

)(

)

TIMING PARAMETERS

-8 -10

SYMBOL* MIN MAX MIN MAX UNITS

tAH 1 1 ns

tAS 2 2 ns

tCH 3 3 ns

tCL 3 3 ns

tCK(3) 8 10 ns

tCK(2) 10 12 ns

*CAS latency indicated in parentheses.

-8 -10

SYMBOL* MIN MAX MIN MAX UNITS

NOTE: 1. RP# = VCC or VHH

2. VCC = 3.3V, VCCP = 3.3V, VCCQ = 1.8V

3. The nvmode register contents are automatically loaded into the mode register upon power-up initialization, LOAD

MODE REGISTER cycle is required to enter new mode register values.

4. JEDEC and PC100 specify three clocks.

5. If CS is HIGH at clock time, all commands applied are NOP, with CKE a “Don’t Care.”

tCK(1) – – ns

tCKH 1 1 ns

tCKS 2 2 ns

tCMH 1 1 ns

tCMS 2 2 ns

tMRD 2 2 tCK

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x16, x32

SYNCFLASH MEMORY

ADVANCE

INITIALIZE AND LOAD MODE REGISTER (FCS CONTROL)

tCH

CKE

CLK

Tm Tn + 2 Tn + 3

COMMAND

ADDRESS

OPCODE

tMRD

Load Mode Register

3, 4, 5

CMS

Power-up:

, V

P, V

CLK stable

T = 100µs

ROW

LOAD MODE

High-Z

DQM

, V

DON’T CARE

UNDEFINED

Tn Tn + 1

CMH

CKH

CKS

(

)(

)

(

)(

)

()()

RP#

()()

(

)(

)

WRITE

C0h

()()

(

)(

)

()()

(

)(

)

(

)(

)

(

)(

)

(

)(

)

TIMING PARAMETERS

-8 -10

SYMBOL* MIN MAX MIN MAX UNITS

tAH 1 1 ns

tAS 2 2 ns

tCH 3 3 ns

tCL 3 3 ns

tCK(3) 8 10 ns

tCK(2) 10 12 ns

*CAS latency indicated in parentheses.

-8 -10

SYMBOL* MIN MAX MIN MAX UNITS

NOTE: 1. RP# = VCC or VHH

2. VCC = 3.3V, VCCP = 3.3V, VCCQ = 1.8V

3. The nvmode register contents are automatically loaded into the mode register upon power-up initialization, LOAD

MODE REGISTER cycle is required to enter new mode register values.

4. JEDEC and PC100 specify three clocks.

5. If CS is HIGH at clock time, all commands applied are NOP, with CKE a “Don’t Care.”

tCK(1) – – ns

tCKH 1 1 ns

tCKS 2 2 ns

tCMH 1 1 ns

tCMS 2 2 ns

tMRD 2 2 tCK

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x16, x32

SYNCFLASH MEMORY

ADVANCE

CLOCK SUSPEND MODE1

tCH

tCL

tCK

tAC

tLZ

DQM

CLK

tOH

OUT

tAH

tAS

tAH

tAS

tAC

tHZ

OUT

m+1

COMMAND

tCMH

tCMS

tCMH

tCMS

NOPNOP NOP NOPNOPREAD

DON’T CARE

UNDEFINED

CKE

tCKS tCKH

BANK

COLUMN m

tCKH

tCKS

T0 T1 T2 T3 T4 T5

x32: A0–A10

x16: A0–A11

NOTE: 1. For this example, the burst length = 2, CAS latency = 3.

2. A0–A7

TIMING PARAMETERS

-8 -10

SYMBOL* MIN MAX MIN MAX UNITS

tAC(3) 7 7 ns

tAC(2) 8 8 ns

tAC(1) – – ns

tAH 1 1 ns

tAS 2 2 ns

tCH 3 3 ns

tCL 3 3 ns

tCK(3) 8 10 ns

tCK(2) 10 12 ns

tCK(1) – – ns

tCKH 1 1 ns

*CAS latency indicated in parentheses.

-8 -10

SYMBOL* MIN MAX MIN MAX UNITS

tCKS 2 2 ns

tCMH 1 1 ns

tCMS 2 2 ns

tDH 1 1 ns

tDS 2 2 ns

tHZ(3) 7 7 ns

tHZ(2) 8 8 ns

tHZ(1) – – ns

tLZ 1 1 ns

tOH 3 3 ns

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x16, x32

SYNCFLASH MEMORY

ADVANCE

NOTE: 1. For this example, the burst length = 4, CAS latency = 2.

2. A0–A7.

tAC

RCD CAS Latency

DQM

CKE

CLK

OUT

COLUMN m

ROW

BANK BANK

ROW

BANK

DON’T CARE

UNDEFINED

OUT

m+3

OUT

m+2

OUT

m+1

COMMAND

CMH

CMS

CMH

CMS

NOPNOP NOPACTIVE NOP READ NOP ACTIVENOP

CKH

CKS

T0 T1 T2 T3 T4 T5 T6 T7 T8

x32: A0–A10

x16: A0–A11

TIMING PARAMETERS

-8 -10

SYMBOL* MIN MAX MIN MAX UNITS

tAC(3) 7 7 ns

tAC(2) 8 8 ns

tAC(1) – – ns

tAH 1 1 ns

tAS 2 2 ns

tCH 3 3 ns

tCL 3 3 ns

tCK(3) 8 10 ns

tCK(2) 10 12 ns

tCK(1) – – ns

*CAS latency indicated in parentheses.

-8 -10

SYMBOL* MIN MAX MIN MAX UNITS

tCKH 1 1 ns

tCKS 2 2 ns

tCMH 1 1 ns

tCMS 2 2 ns

tLZ 1 1 ns

tOH 3 3 ns

tRC 60 60 ns

tRCD 24 30 ns

tRRD 24 30 ns

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x16, x32

SYNCFLASH MEMORY

ADVANCE

READ – ALTERNATING BANK READ ACCESSES1

tCH

tCL

tCK

tAC

tLZ

DQM

CLK

tOH

OUT

tAH

tAS

tAH

tAS

COLUMN m

ROWROW

DON’T CARE

UNDEFINED

tOH

OUT

m+3

tAC

tOH

tAC

tOH

tAC

OUT

m+2D

OUT

m+1

COMMAND

tCMH

tCMS

tCMH

tCMS

NOP NOPACTIVE NOP READ NOP ACTIVE

tOH

OUT

tAC tAC

READ

COLUMN b

ACTIVE

ROW

BANK 0 BANK 0 BANK 1 BANK 1 BANK 0

CKE

tCKH

tCKS

tRCD - BANK 0 tRCD - BANK 0

CAS Latency - BANK 0

tRCD - BANK 1 CAS Latency - BANK 1

RC - BANK 0

RRD

T0 T1 T2 T3 T4 T5 T6 T7 T8

x32: A0–A10

x16: A0–A11

NOTE: 1. For this example, CAS latency = 2.

TIMING PARAMETERS

-8 -10

SYMBOL* MIN MAX MIN MAX UNITS

tAC(3) 7 7 ns

tAC(2) 8 8 ns

tAC(1) – – ns

tAH 1 1 ns

tAS 2 2 ns

tCH 3 3 ns

tCL 3 3 ns

tCK(3) 8 10 ns

tCK(2) 10 12 ns

tCK(1) – – ns

*CAS latency indicated in parentheses.

-8 -10

SYMBOL* MIN MAX MIN MAX UNITS

tCKH 1 1 ns

tCKS 2 2 ns

tCMH 1 1 ns

tCMS 2 2 ns

tLZ 1 1 ns

tOH 3 3 ns

tRC 60 60 ns

tRCD 24 30 ns

tRRD 24 30 ns

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x16, x32

SYNCFLASH MEMORY

ADVANCE

READ – FULL-PAGE BURST1

NOTE: 1. For this example, the CAS latency = 2.

2. A0–A7.

TIMING PARAMETERS

-8 -10

SYMBOL* MIN MAX MIN MAX UNITS

tAC(3) 7 7 ns

tAC(2) 8 8 ns

tAC(1) – – ns

tAH 1 1 ns

tAS 2 2 ns

tCH 3 3 ns

tCL 3 3 ns

tCK(3) 8 10 ns

tCK(2) 10 12 ns

tCK(1) – – ns

*CAS latency indicated in parentheses.

-8 -10

SYMBOL* MIN MAX MIN MAX UNITS

tCKH 1 1 ns

tCKS 2 2 ns

tCMH 1 1 ns

tCMS 2 2 ns

tHZ(3) 7 7 ns

tHZ(2) 8 8 ns

tHZ(1) – – ns

tLZ 1 1 ns

tOH 3 3 ns

tRCD 24 30 ns

tCH

tCL tCK

tAC

tLZ

tRCD CAS Latency

DQM

CKE

CLK

OUT

tAH

tAS

tAC

tOH

OUT

m+1

ROW

tHZ

tOH

OUT

m+1

tAC

tOH

OUT

m+2

tAC

tOH

OUT

m-1

tAC

tOH

OUT

Full-page burst does not self-terminate.

Can use BURST TERMINATE command.

()()

Full page completed.

256 (x16), 128 (x32) locations within

the same row.

DON’T CARE

UNDEFINED

COMMAND

tCMH

tCMS

tCMH

tCMS

NOPNOP NOPACTIVE NOP READ NOP BURST TERMNOP NOP

()()

NOP

COLUMN m

tAH

tAS

BANK

()()

BANK

tCKH

tCKS

()()

T0 T1 T2 T3 T4 T5 T6 Tn + 1 Tn + 2 Tn + 3 Tn + 4

x32: A0–A10

x16: A0–A11

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x16, x32

SYNCFLASH MEMORY

ADVANCE

READ – DQM OPERATION1

NOTE: 1. For this example, the burst length = 4, CAS latency = 2.

2. A0–A7.

tCH

tCL

tCK

tRCD CAS Latency

DQM

CKE

CLK

BANK

ROW

BANK

DON’T CARE

UNDEFINED

tAC

OUT

tOH

OUT

m+3D

OUT

m+2

ttHZ LZ

COMMAND

NOPNOP NOPACTIVE NOP READ NOPNOP NOP

tHZ

tAC tOH

tAC

tOH

tAH

tAS

tAH

tAS

tCMS tCMH

COLUMN m

tCKH

tCKS

T0 T1 T2 T3 T4 T5 T6 T7 T8

x32: A0–A10

x16: A0–A11

*CAS latency indicated in parentheses.

TIMING PARAMETERS

-8 -10

SYMBOL* MIN MAX MIN MAX UNITS

tAC(3) 7 7 ns

tAC(2) 8 8 ns

tAC(1) – – ns

tAH 1 1 ns

tAS 2 2 ns

tCH 3 3 ns

tCL 3 3 ns

tCK(3) 8 10 ns

tCK(2) 10 12 ns

tCK(1) – – ns

-8 -10

SYMBOL* MIN MAX MIN MAX UNITS

tCKH 1 1 ns

tCKS 2 2 ns

tCMH 1 1 ns

tCMS 2 2 ns

tHZ(3) 7 7 ns

tHZ(2) 8 8 ns

tHZ(1) – – ns

tLZ 1 1 ns

tOH 3 3 ns

tRCD 24 30 ns

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x16, x32

SYNCFLASH MEMORY

ADVANCE

PROGRAM/ERASE1

(Bank a followed by READ to Bank a)

tCH

tCL

tCK

DQM

CKE

CLK

ROW

BANK a

IN4

tDH

tDS

COMMAND

tCMH

tCMS

READ NOP

ACTIVE NOP WRITE

LCR NOP

BANK aBANK a

tAH

tAS

tCKH

tCKS

NOP

NOP NOP

COLUMN

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

COMCODE2

DON’T CARE

UNDEFINED

tRCD

High-Z

Dout n

BANK a

COLUMN n

tDS

Dout n+1

tCMH

tCMS

x32: A0–A10

x16: A0–A11

NOTE: 1. ACTIVE/READ or READ will output the contents of the row activated prior to the LCR/active/write command sequence. This example illustrates the

timing for activating a new row in bank a. For this example, READ burst length = 2, CAS latency = 2.

2. ComCode = 40h for PROGRAM, 20h for ERASE (see Truth Table 2).

3. LCR/ACTIVE cycles must be initiated prior to READ according to Truth Table 2 for a status register read command sequence.

4. Column address is “Don’t Care” for ERASE operation.

5. DIN = D0h (erase confirm) for ERASE operation.

*CAS latency indicated in parentheses.

TIMING PARAMETERS

-8 -10

SYMBOL* MIN MAX MIN MAX UNITS

tAH 1 1 ns

tAS 2 2 ns

tCH 3 3 ns

tCL 3 3 ns

tCK(3) 8 10 ns

tCK(2) 10 12 ns

-8 -10

SYMBOL* MIN MAX MIN MAX UNITS

tCK(1) – – ns

tCKH 1 1 ns

tCKS 2 2 ns

tCMH 1 1 ns

tCMS 2 2 ns

tMRD 2 2 tCK

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x16, x32

SYNCFLASH MEMORY

ADVANCE

tCH

tCL

tCK

DQM

CKE

CLK

x32: A0-A10

x16: A0-A11

tCMH

tCMS

BANK b

ROW

BANK a

IN4

tDH

tDS tDS

COMMAND

tCMH

tCMS

READ NOPACTIVE NOP WRITELCR NOP

BANK a

COLUMN n

BANK a

tAH

tAS

tDH

tCKH

tCKS

NOPNOP NOP

COLUMN3 m

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

COMCODE2

DON’T CARE

UNDEFINED

tRCD

OUT

n D

OUT

n + 1 High-Z

PROGRAM/ERASE1

(Bank a followed by READ to Bank b)

NOTE: 1. For this example, READ burst length = 2, CAS = 3.

2. ComCode = 40h for WRITE, 20h for ERASE (see Truth Table 2).

3. Column address is “Don’t Care” for ERASE operation.

4. DIN = D0h (erase confirm) for ERASE operation.

*CAS latency indicated in parentheses.

TIMING PARAMETERS

-8 -10

SYMBOL* MIN MAX MIN MAX UNITS

tAH 1 1 ns

tAS 2 2 ns

tCH 3 3 ns

tCL 3 3 ns

tCK(3) 8 10 ns

tCK(2) 10 12 ns

-8 -10

SYMBOL* MIN MAX MIN MAX UNITS

tCK(1) – – ns

tCKH 1 1 ns

tCKS 2 2 ns

tCMH 1 1 ns

tCMS 2 2 ns

tMRD 2 2 tCK

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x16, x32

SYNCFLASH MEMORY

ADVANCE

90-BALL FBGA

PIN A1 ID

SUBSTRATE: PLASTIC LAMINATE

ENCAPSULATION MATERIAL: EPOXY NOVOLAC

SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb.

Or 62% Sn, 36% Pb, 2% Ag

SOLDER BALL PAD: Ø .33mm

SEATING PLANE

.850 ±.075

BALL A9

SOLDER BALL DIAMETER REFERS

TO POST REFLOW CONDITION.

THE PRE-REFLOW DIAMETER IS Ø 0.40mm

.10 C

13.00 ± .10

.80

TYP

11.20

1.20 MAX

5.60 ±.05

6.50 ±.05

PIN A1 ID

BALL A1

.80

TYP

5.50 ±.05

3.20 ±.05

11.00 ±.10

6.40

0.4590X Ø

NOTE: 1. All dimensions in millimeters.

2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the M logo, and SyncFlash are registered trademarks, and the Micron logo is a trademark of Micron Technology, Inc.

DATA SHEET DESIGNATION

Advance: This data sheet contains initial descriptions of products still under development.

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x16, x32

SYNCFLASH MEMORY

ADVANCE

REVISION HISTORY

Original document, Rev. 1, Advance .................................................................................................................. 4/02