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AFE4490
SBAS602H –DECEMBER 2012–REVISED OCTOBER 2014
AFE4490 Integrated Analog Front-End for Pulse Oximeters
1 Features 2 Applications
1• Fully-Integrated Analog Front-End for • Medical Pulse Oximeter Applications
Pulse Oximeter Applications: • Industrial Photometry Applications
– Flexible Pulse Sequencing and 3 Description
Timing Control The AFE4490 is a fully-integrated analog front-end
• Transmit: (AFE) that is ideally suited for pulse-oximeter
– Integrated LED Driver (H-Bridge, Push, or Pull) applications. The device consists of a low-noise
– 110-dB Dynamic Range Across Full Range receiver channel with a 22-bit analog-to-digital
(Enables Low Noise at Low LED Current) converter (ADC), an LED transmit section, and
diagnostics for sensor and LED fault detection. The
– LED Current: device is a very configurable timing controller. This
– Programmable Ranges of 50 mA, 75 mA, flexibility enables the user to have complete control of
100 mA, 150 mA, and 200 mA, the device timing characteristics. To ease clocking
Each with 8-Bit Current Resolution requirements and provide a low-jitter clock to the
– Low Power: device, an oscillator is also integrated that functions
from an external crystal. The device communicates to
– 100 µA + Average LED Current an external microcontroller or host processor using an
– LED On-Time Programmability from SPI™ interface.
(50 µs + Settle Time) to 4 ms The device is a complete AFE solution packaged in a
– Independent LED2, LED1 Current Reference single, compact VQFN-40 package (6 mm × 6 mm)
• Receive Channel with High Dynamic Range: and is specified over the operating temperature range
of –40°C to 85°C.
– Input-Referred Noise:
50 pARMS (at 5-µA PD Current) Device Information(1)
– 13.5 Noise-Free Bits (at 5-µA PD Current) PART NUMBER PACKAGE BODY SIZE (NOM)
– Analog Ambient Cancellation Scheme with AFE4490 VQFN (40) 6.00 mm × 6.00 mm
Selectable 1-µA to 10-µA Ambient Current (1) For all available packages, see the orderable addendum at
– Low Power: < 2.3 mW at 3.0-V Supply the end of the datasheet.
– Rx Sample Time: 50 µs to 4 ms Simplified Schematic
– I-V Amplifier with Seven Separate LED2 and
LED1 Programmable Feedback R and C
Settings
– Integrated Digital Ambient Estimation and
Subtraction
• Integrated Fault Diagnostics:
– Photodiode and LED Open and
Short Detection
– Cable On or Off Detection
• Supplies:
– Rx = 2.0 V to 3.6 V
– Tx = 3.0 V or 5.25 V
• Package: Compact VQFN-40 (6 mm × 6 mm)
• Specified Temperature Range: –40°C to 85°C
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AFE4490
SBAS602H –DECEMBER 2012–REVISED OCTOBER 2014
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Table of Contents
8.2 Functional Block Diagram....................................... 27
1 Features.................................................................. 18.3 Feature Description................................................. 28
2 Applications ........................................................... 18.4 Device Functional Modes........................................ 43
3 Description............................................................. 18.5 Programming........................................................... 52
4 Revision History..................................................... 28.6 Register Maps......................................................... 56
5 Device Comparison Table..................................... 69 Applications and Implementation ...................... 85
6 Pin Configuration and Functions......................... 69.1 Application Information .......................................... 85
7 Specifications......................................................... 89.2 Typical Application.................................................. 85
7.1 Absolute Maximum Ratings ...................................... 810 Power-Supply Recommendations..................... 90
7.2 Handling Ratings....................................................... 811 Layout................................................................... 92
7.3 Recommended Operating Conditions....................... 911.1 Layout Guidelines ................................................. 92
7.4 Thermal Information.................................................. 911.2 Layout Example .................................................... 92
7.5 Electrical Characteristics......................................... 10 12 Device and Documentation Support................. 93
7.6 Timing Requirements: Serial Interface.................... 15 12.1 Documentation Support ........................................ 93
7.7 Supply Ramp and Power-Down Timing 12.2 Trademarks........................................................... 93
Requirements........................................................... 17 12.3 Electrostatic Discharge Caution............................ 93
7.8 Typical Characteristics............................................ 18 12.4 Glossary................................................................ 93
8 Detailed Description............................................ 27 13 Mechanical, Packaging, and Orderable
8.1 Overview................................................................. 27 Information........................................................... 93
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (June 2014) to Revision H Page
• Changed V(ESD) parameter specification values in Absolute Maximum Ratings table ........................................................... 8
• Updated AFE Register Description section to current standards: added legend and bit settings to each bit register ........ 59
Changes from Revision F (October 2013) to Revision G Page
• Added Applications and Implementation,Power Supply Recommendations, and Layout sections....................................... 1
• Changed sub-bullet of Transmit Features bullet .................................................................................................................... 1
• Changed second sub-bullet of Integrated Fault Diagnostics Features bullet......................................................................... 1
• Changed VCM row in Pin Functions table: changed INM to INN in VCM description........................................................... 7
• Changed Absolute Maximum Ratings table: changed first five rows and added TXP, TXN pins row................................... 8
• Added Handling Ratings table................................................................................................................................................ 8
• Changed I-V Transimpedance Amplifier, VO(shield) parameter: changed test conditions and added minimum and
maximum specifications ...................................................................................................................................................... 11
• Changed Example value for rows t, t2, t4, t5, t7, t11, t13, t15, t17, t19, t22, t24, t26, and t28 in Table 2......................................... 36
• Added footnote 2 to Table 2................................................................................................................................................. 36
• Added footnote 2 to Figure 63.............................................................................................................................................. 37
• Added footnote 2 to Figure 64.............................................................................................................................................. 38
• Changed INN pin name in Figure 76.................................................................................................................................... 49
• Changed INM to INN throughout Table 3............................................................................................................................. 51
• Added STAGE2EN1 and STG2GAIN1[2:0] in TIAGAIN register ......................................................................................... 57
• Changed STAGE2EN to STAGE2EN2 and STG2GAIN[2:0] to STG2GAIN2[2:0] in TIA_AMB_GAIN register................... 57
• Added last two sentences to NUMAV[7:0] description in CONTROL1: Control Register 1................................................. 72
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Changes from Revision E (October 2013) to Revision F Page
• Changed LED_DRV_SUP parameter in Recommended Operating Conditions table............................................................ 9
• Changed TXM to TXN in VLED footnote of Recommended Operating Conditions table......................................................... 9
• Changed VLED footnote and added VHR footnote to Recommended Operating Conditions table .......................................... 9
• Changed Figure 77 (changed TXP and TXN pin names, deleted LED 1 and LED 2 pin names) ....................................... 50
• Changed Table 6 (added VHR columns to table).................................................................................................................. 76
Changes from Revision D (May 2013) to Revision E Page
• Changed 2.3 mA to 2.3 mW in 4th sub-bullet and changed 250 µs to 4 ms in 5th sub-bullet of Receive Channel with
High Dynamic Range Features bullet..................................................................................................................................... 1
• Changed Rx, Tx supplies and deleted 5-V supply from front-page graphic........................................................................... 1
• Changed Tx Power Supply column in Family and Ordering Information table ...................................................................... 6
• Changed TX_REF description in Pin Descriptions table........................................................................................................ 7
• Changed conditions of Electrical Characteristics table ........................................................................................................ 10
• Changed Performance, PRF parameter minimum specification in Electrical Characteristics table..................................... 10
• Changed PRF = 1300 Hz to PRF = 1200 Hz in test conditions for the Performance, Total integrated noise current
and NFB parameters in Electrical Characteristics table......................................................................................................... 10
• Changed Ambient Cancellation Stage, Gain parameter in Electrical Characteristics table................................................. 11
• Added last two Low-Pass Filter parameters to Electrical Characteristics table ................................................................... 11
• Added Diagnostics, Diagnostics current parameter to Electrical Characteristics table........................................................ 12
• Changed CFto C and added TX_REF capacitor to Functional Block Diagram graphic ...................................................... 27
• Updated Figure 55................................................................................................................................................................ 28
• Changed second sentence in second paragraph of Receiver Front-End section................................................................ 28
• Changed third paragraph of Receiver Front-End section..................................................................................................... 28
• Changed second paragraph of Ambient Cancellation Scheme section............................................................................... 30
• Added last paragraph and Table 1 to Ambient Cancellation Scheme section..................................................................... 31
• Updated Figure 58................................................................................................................................................................ 32
• Updated Figure 60................................................................................................................................................................ 34
• Added footnote 1 to Table 2 and changed Example column in Table 2 .............................................................................. 36
• Changed corresponding register column description in rows t13, t15, t17, and t19 and example column values for rows
t22, t24, t26, and t28 in Table 2................................................................................................................................................. 36
• Updated Figure 63................................................................................................................................................................ 37
• Updated Figure 64................................................................................................................................................................ 38
• Deleted supply voltage range from RX_ANA_SUP and RX_DIG_SUP in Figure 65........................................................... 39
• Changed entire Transmit Section......................................................................................................................................... 39
• Deleted _5V from TX_CTRL_SUP and LED_DRV_SUP in Figure 68................................................................................. 42
• Changed second paragraph of ADC Operation and Averaging Module section.................................................................. 43
• Updated Equation 5 and Figure 71 ...................................................................................................................................... 44
• Updated Figure 72................................................................................................................................................................ 46
• Added first paragraph of AFE Output Mode (ADC Bypass Mode) section .......................................................................... 47
• Updated Figure 75................................................................................................................................................................ 48
• Added last paragraph to the Diagnostics Module section.................................................................................................... 52
• Added first and last sentence to Writing Data section.......................................................................................................... 52
• Changed second to last sentence in Writing Data section................................................................................................... 52
• Added first and last sentence to Reading Data section ....................................................................................................... 53
• Changed second to last sentence in Reading Data section................................................................................................. 53
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• Added Multiple Data Reads and Writes section................................................................................................................... 54
• Added last sentence to the AFE SPI Interface Design Considerations section................................................................... 55
• Added Register Control column to Table 4 .......................................................................................................................... 56
• Changed bits D16 and D10 in CONTROL2 row of Table 4 ................................................................................................. 57
• Changed CONTROL0 paragraph description....................................................................................................................... 59
• Added note to bit D2 description of CONTROL0 register .................................................................................................... 59
• Changed PRPCOUNT[15:0] (bits D[15:0]) description in PRPCOUNT register................................................................... 72
• Changed note within CLKALMPIN[2:0] (bits D[11:9]) description of CONTROL1 register .................................................. 72
• Changed second and third columns of Table 5.................................................................................................................... 73
• Changed 001 and 011 bit settings for the STG2GAIN[2:0] bits (bits D[10:8]) in the TIA_AMB_GAIN register................... 75
• Changed description and name of bits D16 and D10 in CONTROL2 register..................................................................... 77
Changes from Revision C (April 2013) to Revision D Page
• Changed descriptions of RX_ANA_SUP, RX_DIG_SUP, and TX_CTRL_SUP pins in Pin Descriptions table..................... 7
• Added CMRR parameter to Electrical Characteristics table................................................................................................. 10
• Added External Clock, External clock input voltage and External clock input current parameters to Electrical
Characteristics table............................................................................................................................................................. 12
• Changed TIMING, tRESET parameter unit in Electrical Characteristics table......................................................................... 12
• Added Pin Leakage Current section to Electrical Characteristics table............................................................................... 12
• Added Supply Current, ADC bypass mode parameter to Electrical Characteristics table................................................... 13
• Changed Serial Interface Timing section.............................................................................................................................. 15
• Added Figure 14................................................................................................................................................................... 18
• Added Figure 20................................................................................................................................................................... 19
• Added Figure 26................................................................................................................................................................... 20
• Added Figure 32................................................................................................................................................................... 21
• Added Figure 54................................................................................................................................................................... 25
• Updated Functional Block Diagram graphic......................................................................................................................... 27
• Changed name of register 15h............................................................................................................................................. 56
• Added note to descriptions of LED2-ALED2VAL and LED1-ALED1VAL registers.............................................................. 82
Changes from Revision B (February 2013) to Revision C Page
• Changed first two sub-bullets of Receive Channel with High Dynamic Range Features bullet............................................. 1
• Changed pin out figure........................................................................................................................................................... 6
• Changed ESD ratings specification values in Absolute Maximum Ratings table................................................................... 8
• Added Performance, PSRR parameter to Electrical Characteristics table........................................................................... 10
• Changed Performance, Total integrated noise current and NFB parameters in Electrical Characteristics table.................. 10
• Changed first row of Receiver Functional Block Level Specification, Total integrated noise current parameter in
Electrical Characteristics table ............................................................................................................................................. 10
• Changed Ambient Cancellation Stage, Gain parameter specifications in Electrical Characteristics table........................... 11
• Changed Transmitter, Transmitter noise dynamic range parameter in Electrical Characteristics table............................... 11
• Added External Clock, External clock input frequency parameter to Electrical Characteristics table.................................. 12
• Added Timing, Wake-up time from Rx power-down and Wake-up time from Tx power-down parameters to Electrical
Characteristics table............................................................................................................................................................. 12
• Changed Supply Current section of Electrical Characteristics table.................................................................................... 13
• Changed typical specification in first row and unit in second row of Power Dissipation, PD(q) parameter in Electrical
Characteristics table............................................................................................................................................................. 14
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• Changed Power Dissipation, After reset LED_DRV_SUP typical specification in Electrical Characteristics table.............. 14
• Changed Power Dissipation, With stage 2 mode enabled LED_DRV_SUP, TX_CTRL_SUP, and RX_DIG_SUP
typical specifications in Electrical Characteristics table........................................................................................................ 14
• Added Figure 13................................................................................................................................................................... 18
• Deleted Figure 11, Input-Referred Noise Current vs PLETH Current (BW = 5 Hz, PRF = 5000 Hz).................................. 18
• Deleted Figure 17, Input-Referred Noise Current vs PLETH Current (BW = 20 Hz, PRF = 5000 Hz)................................ 19
• Added Figure 24................................................................................................................................................................... 20
• Deleted Figure 23, Noise-Free Bits vs PLETH Current (BW = 5 Hz, PRF = 5000 Hz)........................................................ 20
• Added Figure 24................................................................................................................................................................... 21
• Deleted Figure 29, Noise-Free Bits vs PLETH Current (BW = 20 Hz, PRF = 5000 Hz)...................................................... 21
• Added Figure 38 through Figure 41 ..................................................................................................................................... 22
• Added Figure 49 to Figure 53............................................................................................................................................... 24
• Changed gain setting range in Receiver Front-End section................................................................................................. 28
• Changed corresponding register column description in rows t24, t26, and t28 in Table 2 ...................................................... 36
• Changed description of LED Power Reduction During Periods of Inactivity section ........................................................... 42
• Changed last paragraph of AFE Analog Output Mode (ADC Bypass Mode) section.......................................................... 49
• Updated Figure 76................................................................................................................................................................ 49
• Updated Figure 77................................................................................................................................................................ 50
• Changed LED2CONVEND register name in Table 4........................................................................................................... 56
• Changed RESERVED1 and RESERVED2 register descriptions in Table 4........................................................................ 58
• Changed description of bits D[15:0] in LED2STC register................................................................................................... 60
• Changed description of bits D[15:0] in LED2ENDC, LED2LEDSTC, and LED2LEDENDC registers.................................. 60
• Changed description of bits D[15:0] in ALED2STC, ALED2ENDC, and LED1STC registers.............................................. 61
• Changed description of bits D[15:0] in LED1ENDC, LED1LEDSTC, and LED1LEDENDC registers.................................. 63
• Changed description of bits D[15:0] in ALED1STC, ALED1ENDC, and LED2CONVST registers...................................... 64
• Changed description of bits D[15:0] in ALED2CONVST and ALED2CONVEND registers.................................................. 66
• Changed description of bits D[15:0] in LED1CONVST, LED1CONVEND, and ALED1CONVST registers......................... 67
• Changed description of bits D[15:0] in ALED1CONVEND register...................................................................................... 68
• Changed RESET to RESET in ADCRSTSTCT0 and ADCRSTENDCT0 registers.............................................................. 69
• Changed RESET to RESET in ADCRSTSTCT1, ADCRSTENDCT1, and ADCRSTSTCT2 registers ................................ 69
• Changed RESET to RESET in ADCRSTENDCT2, ADCRSTSTCT3, and ADCRSTENDCT3 registers ............................. 71
• Added footnote to Table 6.................................................................................................................................................... 76
• Changed bits D18 and D17 names in CONTROL2 bit register............................................................................................ 77
• Added note to description of bits D[18:17] in CONTROL2 register...................................................................................... 77
• Changed RESERVED1 and RESERVED2 registers............................................................................................................ 79
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INN
INP
RX_ANA_GND
VCM
DNC(1)
DNC
BG
VSS
TX_REF
DNC
CLKOUT
RESET
ADC_RDY
SPISTE
SPISIMO
SPISOMI
SCLK
PD_ALM/ADC Reset
LED_ALM
DIAG_END
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
TX_CTRL_SUP
11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31
RX_ANA_GND
LED_DRV_GND RX_ANA_SUP
LED_DRV_GND XIN
TXN XOUT
TXP RX_ANA_GND
LED_DRV_GND RXOUTP
LED_DRV_SUP RXOUTN
LED_DRV_SUP RX_ANA_SUP
RX_DIG_GND RX_DIG_GND
AFE_PDN RX_DIG_SUP
AFE4490
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5 Device Comparison Table
OPERATING
LED DRIVE LED DRIVE CURRENT Tx POWER TEMPERATURE
PRODUCT PACKAGE-LEAD CONFIGURATION (mA, max) SUPPLY (V) RANGE
AFE4490 VQFN-40 Bridge, push-pull 50, 75, 100, 150, and 200 3 to 5.25 –40°C to 85°C
AFE4400 VQFN-40 Bridge, push-pull 50 3 to 5.25 0°C to 70°C
AFE4403 WCSP-36 Bridge, push-pull 100 3 to 5.25 –20°C to 70°C
6 Pin Configuration and Functions
RHA Package
VQFN-40
(Top View)
(1) DNC = Do not connect.
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Pin Functions
PIN
NAME NO. FUNCTION DESCRIPTION
Output signal that indicates ADC conversion completion.
ADC_RDY 28 Digital Can be connected to the interrupt input pin of an external microcontroller.
AFE-only power-down input; active low.
AFE_PDN 20 Digital Can be connected to the port pin of an external microcontroller.
Decoupling capacitor for internal band-gap voltage to ground
BG 7 Reference (2.2-µF decoupling capacitor to ground, expected voltage = 1.0 V).
Buffered 4-MHz output clock output.
CLKOUT 30 Digital Can be connected to the clock input pin of an external microcontroller.
Output signal that indicates completion of diagnostics.
DIAG_END 21 Digital Can be connected to the port pin of an external microcontroller.
DNC(1) 5, 6, 10 — Do not connect these pins. Leave as open-circuit.
INN 1 Analog Receiver input pin. Connect to photodiode anode.
INP 2 Analog Receiver input pin. Connect to photodiode cathode.
LED_DRV_GND 12, 13, 16 Supply LED driver ground pin, H-bridge. Connect to common board ground.
LED driver supply pin, H-bridge. Connect to an external power supply capable of supplying the
LED_DRV_SUP 17, 18 Supply large LED current, which is drawn by this supply pin.
Output signal that indicates an LED cable fault.
LED_ALM 22 Digital Can be connected to the port pin of an external microcontroller.
Output signal that indicates a PD sensor or cable fault.
PD_ALM/ADC Reset 23 Digital Can be connected to the port pin of an external microcontroller.
In ADC bypass mode, the PD_ALM pin can be used to bring out the ADC reset signal.
AFE-only reset input, active low.
RESET 29 Digital Can be connected to the port pin of an external microcontroller.
RX_ANA_GND 3, 36, 40 Supply Rx analog ground pin. Connect to common board ground.
RX_ANA_SUP 33, 39 Supply Rx analog supply pin; 0.1-µF decoupling capacitor to ground
RX_DIG_GND 19, 32 Supply Rx digital ground pin. Connect to common board ground.
RX_DIG_SUP 31 Supply Rx digital supply pin; 0.1-µF decoupling capacitor to ground
RXOUTN 34 Analog External ADC negative input when in ADC bypass mode
RXOUTP 35 Analog External ADC positive input when in ADC bypass mode
SCLK 24 SPI SPI clock pin
SPISIMO 26 SPI SPI serial in master out
SPISOMI 25 SPI SPI serial out master in
SPISTE 27 SPI SPI serial interface enable
TX_CTRL_SUP 11 Supply Transmit control supply pin (0.1-µF decoupling capacitor to ground)
Transmitter reference voltage, 0.75 V default after reset.
TX_REF 9 Reference Connect a 2.2-μF decoupling capacitor to ground.
TXN 14 Analog LED driver out B, H-bridge output. Connect to LED.
TXP 15 Analog LED driver out B, H-bridge output. Connect to LED.
Input common-mode voltage output.
Connect a series resistor (1 kΩ) and a decoupling capacitor (10 nF) to ground.
VCM 4 Reference The voltage across the capacitor can be used to shield (guard) the INP, INN traces.
Expected voltage = 0.9 V.
VSS 8 Supply Substrate ground. Connect to common board ground.
Crystal oscillator pins.
XOUT 37 Digital Connect an external 8-MHz crystal between these pins with the correct load capacitor
(as specified by vendor) to ground.
Crystal oscillator pins.
XIN 38 Digital Connect an external 8-MHz crystal between these pins with the correct load capacitor
(as specified by vendor) to ground.
(1) Leave pins as open circuit. Do not connect.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
RX_ANA_SUP, RX_DIG_SUP to RX_ANA_GND, RX_DIG_GND –0.3 4 V
TX_CTRL_SUP, LED_DRV_SUP to LED_DRV_GND –0.3 6 V
RX_ANA_GND, RX_DIG_GND to LED_DRV_GND –0.3 0.3 V
Analog inputs RX_ANA_GND – 0.3 RX_ANA_SUP + 0.3 V
Digital inputs RX_DIG_GND – 0.3 RX_DIG_SUP + 0.3 V
Minimum [6,
TXP, TXN pins –0.3 V
(LED_DRV_SUP + 0.3)]
Input current to any pin except supply pins(2) ±7 mA
Momentary ±50 mA
Input current Continuous ±7 mA
Operating temperature range –40 85 °C
Maximum junction temperature, TJ125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that can swing beyond the supply rails must be current-limited to
10 mA or less.
7.2 Handling Ratings MIN MAX UNIT
Tstg Storage temperature range –60 150 °C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all –1000 1000
pins(1)
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification –250 250
JESD22-C101, all pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
SUPPLIES
RX_ANA_SUP AFE analog supply 2.0 3.6 V
RX_DIG_SUP AFE digital supply 2.0 3.6 V
TX_CTRL_SUP Transmit controller supply 3.0 5.25 V
Transmit LED driver supply, H-bridge or common anode [3.0 or (VHR + VLED + VCABLE)(1)(2)(3),
LED_DRV_SUP 5.25 V
configuration whichever is greater]
Difference between LED_DRV_SUP and TX_CTRL_SUP –0.3 0.3 V
TEMPERATURE
Specified temperature range –40 85 °C
(1) VHR refers to the required voltage headroom necessary to drive the LEDs. See Table 6 for the appropriate VHR value.
(2) VLED refers to the maximum voltage drop across the external LED (at maximum LED current) connected between the TXP and TXN pins
(in H-bridge mode) and from the TXP and TXN pins to LED_DRV_SUP (in the common anode configuration).
(3) VCABLE refers to voltage drop across any cable, connector, or any other component in series with the LED.
7.4 Thermal Information AFE4490
THERMAL METRIC(1) RHA (VQFN) UNIT
40 PINS
RθJA Junction-to-ambient thermal resistance 35
RθJC(top) Junction-to-case (top) thermal resistance 31
RθJB Junction-to-board thermal resistance 26 °C/W
ψJT Junction-to-top characterization parameter 0.1
ψJB Junction-to-board characterization parameter N/A
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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N = log 2
FB
IPD
6.6 I´NOISE
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7.5 Electrical Characteristics
Minimum and maximum specifications are at TA= –40°C to 85°C. Typical specifications are at 25°C.
All specifications are at RX_ANA_SUP = RX_DIG_SUP = 3 V, TX_CTRL_SUP = LED_DRV_SUP = 5 V, stage 2 amplifier
disabled, and fCLK = 8 MHz, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PERFORMANCE (Full-Signal Chain)
RF= 10 kΩ50 µA
RF= 25 kΩ20 µA
RF= 50 kΩ10 µA
IIN_FS Full-scale input current RF= 100 kΩ5 µA
RF= 250 kΩ2 µA
RF= 500 kΩ1 µA
RF= 1 MΩ0.5 µA
PRF Pulse repetition frequency 62.5 5000 SPS
DCPRF PRF duty cycle 25%
fCM = 50 Hz and 60 Hz, LED1 and LED2 with 75 dB
RSERIES = 500 kΩ, RF= 500 kΩ
CMRR Common-mode rejection ratio fCM = 50 Hz and 60 Hz, LED1-AMB and 95 dB
LED2-AMB with RSERIES = 500 kΩ, RF= 500 kΩ
fPS = 50 Hz, 60 Hz at PRF = 200 Hz 100 dB
PSRR Power-supply rejection ratio fCM = 50 Hz, 60 Hz at PRF = 600 Hz 106 dB
PSRRLED PSRR, transmit LED driver With respect to ripple on LED_DRV_SUP 75 dB
PSRRTx PSRR, transmit control With respect to ripple on TX_CTRL_SUP 60 dB
With respect to ripple on RX_ANA_SUP and
PSRRRx PSRR, receiver 60 dB
RX_DIG_SUP
RF= 100 kΩwith stage 2 gain disabled, 36 pARMS
PRF = 1200 Hz, duty cycle = 5%
Total integrated noise current, input-
referred (receiver with transmitter loop RF= 500 kΩwith ambient cancellation enabled
back, 0.1-Hz to 20-Hz bandwidth) and stage 2 gain = 4, PRF = 1200 Hz, 13 pARMS
duty cycle = 25%
RF= 100 kΩ, PRF = 1200 Hz, duty cycle = 5% 14.3 Bits
Noise-free bits (receiver with transmitter
NFB loop back, 0.1-Hz to 20-Hz bandwidth)(1) RF= 500 kΩ, PRF = 1200 Hz, duty cycle = 25% 13.5 Bits
RECEIVER FUNCTIONAL BLOCK LEVEL SPECIFICATION
RF= 500 kΩ, ambient cancellation enabled,
stage 2 gain = 4, PRF = 1300 Hz, 1.4 pARMS
Total integrated noise current, LED duty cycle = 25%
input-referred (receiver alone) over 0.1-Hz RF= 500 kΩ, ambient cancellation enabled,
to 5-Hz bandwidth stage 2 gain = 4, PRF = 1300 Hz, 5 pARMS
LED duty cycle = 5%
(1) Noise-free bits (NFB) are defined as:
where: IPD is the photodiode current, and INOISE is the input-referred RMS noise current.
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SBAS602H –DECEMBER 2012–REVISED OCTOBER 2014
Electrical Characteristics (continued)
Minimum and maximum specifications are at TA= –40°C to 85°C. Typical specifications are at 25°C.
All specifications are at RX_ANA_SUP = RX_DIG_SUP = 3 V, TX_CTRL_SUP = LED_DRV_SUP = 5 V, stage 2 amplifier
disabled, and fCLK = 8 MHz, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I-V TRANSIMPEDANCE AMPLIFIER
See the Receiver Channel section
G Gain RF= 10 kΩto RF= 1 MΩV/µA
for details
Gain accuracy ±7%
10k, 25k, 50k, 100k, 250k,
Feedback resistance RFΩ
500k, and 1M
Feedback resistor tolerance RF±7%
Feedback capacitance CF5, 10, 25, 50, 100, and 250 pF
Feedback capacitor tolerance CF±20%
VOD(fs) Full-scale differential output voltage 1 V
Common-mode voltage on input pins Set internally 0.9 V
Includes equivalent capacitance of photodiode,
External differential input capacitance 10 1000 pF
cables, EMI filter, and so forth
With a 1-kΩseries resistor and a 10-nF
VO(shield) Shield output voltage, VCM decoupling capacitor to ground, when loaded with 0.8 0.9 1.0 V
a small current (for example, of a few µA or less)
AMBIENT CANCELLATION STAGE
G Gain 0, 3.5, 6, 9.5, and 12 dB
Current DAC range 0 10 µA
Current DAC step size 1 µA
LOW-PASS FILTER
Low-pass corner frequency 3-dB attenuation 0.5 and 1 kHz
Duty cycle = 25% 0.004 dB
Pass-band attenuation, 2 Hz to 10 Hz Duty cycle = 10% 0.041 dB
After diagnostics mode with filter corner = 500 Hz 28 ms
Filter settling time After diagnostics mode with filter corner = 16 ms
1000 Hz
ADC bypass outputs output impedance RXOUTP and RXOUTN 1 kΩ
ANALOG-TO-DIGITAL CONVERTER
Resolution 22 Bits
See the ADC Operation and Averaging Module
Sample rate 4 × PRF SPS
section
ADC full-scale voltage ±1.2 V
See the ADC Operation and Averaging Module
ADC conversion time 50 PRF / 4 µs
section
ADC reset time 2 tCLK
TRANSMITTER
0, 50, 75, 100, 150, and 200
Output current range (see the LEDCNTRL: LED Control mA
Register for details)
LED current DAC error ±5%
Output current resolution 8 Bits
0.1-Hz to 20-Hz bandwidth, at 25-mA output 110 dB
current
Transmitter noise dynamic range 0.1-Hz to 20-Hz bandwidth, at 100-mA output 110 dB
current
Minimum sample time of LED1 and LED2 50 µs
pulses
LED_ON = 0 1 µA
LED current DAC leakage current LED_ON = 1 50 µA
LED current DAC linearity Percent of full-scale current 0.5%
From zero current to 150 mA 7 µs
Output current settling time
(with resistive load) From 150 mA to zero current 7 µs
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Electrical Characteristics (continued)
Minimum and maximum specifications are at TA= –40°C to 85°C. Typical specifications are at 25°C.
All specifications are at RX_ANA_SUP = RX_DIG_SUP = 3 V, TX_CTRL_SUP = LED_DRV_SUP = 5 V, stage 2 amplifier
disabled, and fCLK = 8 MHz, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIAGNOSTICS
EN_SLOW_DIAG = 0
Start of diagnostics after the DIAG_EN register
bit is set. 8 ms
End of diagnostic indicated by DIAG_END going
high.
Duration of diagnostics state machine EN_SLOW_DIAG = 1
Start of diagnostics after the DIAG_EN register
bit is set. 16 ms
End of diagnostic indicated by DIAG_END going
high.
Open fault resistance > 100 kΩ
Short fault resistance < 10 kΩ
Diagnostics current During diagnostics mode < 100 µA
INTERNAL OSCILLATOR
With an 8-MHz crystal connected to the XIN and
fCLKOUT CLKOUT frequency 4 MHz
XOUT pins
DCCLKOUT CLKOUT duty cycle 50%
With an 8-MHz crystal connected to the XIN and
Crystal oscillator start-up time 200 µs
XOUT pins
EXTERNAL CLOCK
Maximum allowable external clock jitter 50 ps
External clock input frequency ±10% 8 MHz
Voltage input high (VIH) 0.75 × RX_DIG_SUP V
External clock input voltage Voltage input low (VIL) 0.25 × RX_DIG_SUP V
External clock input current 1 µA
TIMING
Wake-up time from complete power-down 1000 ms
Wake-up time from Rx power-down 100 µs
Wake-up time from Tx power-down 1000 ms
tRESET Active low RESET pulse duration 1 ms
DIAG_END pulse duration at diagnostics CLKOUT
tDIAGEND 4
completion cycles
CLKOUT
tADCRDY ADC_RDY pulse duration 1 cycles
DIGITAL SIGNAL CHARACTERISTICS
AFE_PDN, SPI CLK, SPI SIMO, SPI STE,
VIH Logic high input voltage 0.75 × RX_DIG_SUP V
RESET
AFE_PDN, SPI CLK, SPI SIMO, SPI STE,
VIL Logic low input voltage 0.25 × RX_DIG_SUP V
RESET
IIN Logic input current Digital inputs at VIH or VIL 0.1 µA
DIAG_END, LED_ALM, PD_ALM, SPI SOMI,
VOH Logic high output voltage RX_DIG_SUP – 0.1 V
ADC_RDY, CLKOUT
DIAG_END, LED_ALM, PD_ALM, SPI SOMI,
VOL Logic low output voltage 0.1 V
ADC_RDY, CLKOUT
PIN LEAKAGE CURRENT
Pin leakage current To GND and supply 1 nA
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SBAS602H –DECEMBER 2012–REVISED OCTOBER 2014
Electrical Characteristics (continued)
Minimum and maximum specifications are at TA= –40°C to 85°C. Typical specifications are at 25°C.
All specifications are at RX_ANA_SUP = RX_DIG_SUP = 3 V, TX_CTRL_SUP = LED_DRV_SUP = 5 V, stage 2 amplifier
disabled, and fCLK = 8 MHz, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
RX_ANA_SUP = 3.0 V, with 8-MHz clock 0.6 mA
running, Rx stage 2 disabled
Receiver analog supply current RX_ANA_SUP = 3.0 V, with 8-MHz clock 0.7 mA
running, Rx stage 2 enabled
Receiver digital supply current RX_DIG_SUP = 3.0 V 0.27 mA
RX_ANA_SUP + RX_DIG_SUP
ADC bypass mode 1.8 mA
(Excluding external ADC current)
LED_DRV LED driver supply current With zero LED current setting 55 µA
_SUP
TX_CTRL Transmitter control supply current 15 µA
_SUP
Receiver current only 3 µA
(RX_ANA_SUP)
Receiver current only 3 µA
(RX_DIG_SUP)
Complete power-down
(using AFE_PDN pin) Transmitter current only 1 µA
(LED_DRV_SUP)
Transmitter current only 1 µA
(TX_CTRL_SUP)
Receiver current only 220 µA
(RX_ANA_SUP)
Power-down Rx alone Receiver current only 220 µA
(RX_DIG_SUP)
Transmitter current only 2 µA
(LED_DRV_SUP)
Power-down Tx alone Transmitter current only 2 µA
(TX_CTRL_SUP)
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Electrical Characteristics (continued)
Minimum and maximum specifications are at TA= –40°C to 85°C. Typical specifications are at 25°C.
All specifications are at RX_ANA_SUP = RX_DIG_SUP = 3 V, TX_CTRL_SUP = LED_DRV_SUP = 5 V, stage 2 amplifier
disabled, and fCLK = 8 MHz, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER DISSIPATION
Normal operation (excluding LEDs) 2.84 mW
PD(q) Quiescent power dissipation Power-down 0.1 mW
LED_DRV_SUP current value.
LED_DRV_SUP 1 µA
Does not include LED current.
Power-down with the TX_CTRL_SUP 1 µA
AFE_PDN pin RX_ANA_SUP 5 µA
RX_DIG_SUP 0.1 µA
LED_DRV_SUP current value.
LED_DRV_SUP 1 µA
Does not include LED current.
Power-down with the TX_CTRL_SUP 1 µA
PDNAFE register bit RX_ANA_SUP 15 µA
RX_DIG_SUP 20 µA
LED_DRV_SUP current value.
LED_DRV_SUP 50 µA
Does not include LED current.
TX_CTRL_SUP 15 µA
Power-down Rx RX_ANA_SUP 220 µA
RX_DIG_SUP 220 µA
LED_DRV_SUP current value.
LED_DRV_SUP 2 µA
Does not include LED current.
TX_CTRL_SUP 2 µA
Power-down Tx RX_ANA_SUP 600 µA
RX_DIG_SUP 230 µA
LED_DRV_SUP current value.
LED_DRV_SUP 55 µA
Does not include LED current.
After reset, with 8-MHz TX_CTRL_SUP 15 µA
clock running RX_ANA_SUP 600 µA
RX_DIG_SUP 230 µA
LED_DRV_SUP current value.
LED_DRV_SUP 55 µA
Does not include LED current.
With stage 2 mode TX_CTRL_SUP 15 µA
enabled and 8-MHz
clock running RX_ANA_SUP 700 µA
RX_DIG_SUP 270 µA
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}v[, can be high or low.
A7 A6 A1 A0
SPISTE
SPISIMO
SCLK
D22 D17 D16 D6 D1
SPISOMI
XIN
tCLK
tSTECLK
tSPICLK
tSOMIPD
tSOMIHD
tCLKSTEL
tCLKSTEH
tSIMOSU
tSIMOHD
31
D23
tSOMIPD
D7
07
D0
23
AFE4490
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SBAS602H –DECEMBER 2012–REVISED OCTOBER 2014
7.6 Timing Requirements: Serial Interface MIN TYP MAX UNIT
tCLK Clock frequency on XIN pin 8 MHz
tSCLK Serial shift clock period 62.5 ns
tSTECLK STE low to SCLK rising edge, setup time 10 ns
tCLKSTEH,L SCLK transition to SPI STE high or low 10 ns
tSIMOSU SIMO data to SCLK rising edge, setup time 10 ns
tSIMOHD Valid SIMO data after SCLK rising edge, hold time 10 ns
tSOMIPD SCLK falling edge to valid SOMI, setup time 17 ns
tSOMIHD SCLK rising edge to invalid data, hold time 0.5 tSCLK
(1) The SPI_READ register bit must be enabled before attempting a register read.
(2) Specify the register address whose contents must be read back on A[7:0].
(3) The AFE outputs the contents of the specified register on the SOMI pin.
Figure 1. Serial Interface Timing Diagram, Read Operation (1)(2)(3)
Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 15
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A7 A6 A1 A0
SPISTE
SPISIMO
SCLK
tSTECLK
tSIMOSU
tSIMOHD
31 0
D23 D22 D1 D0
23
AFE4490
SBAS602H –DECEMBER 2012–REVISED OCTOBER 2014
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Figure 2. Serial Interface Timing Diagram, Write Operation
16 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: AFE4490
RX Supplies
(RX_ANA_SUP, RX_DIG_SUP)
TX Supplies
(TX_CTRL_SUP, LED_DRV_SUP)
SPI Interface
ADC_RDY
AFE_PDN
~
~
~
~
t1
t2
t3t4t5
t8
t6
~
~
PDN_AFE
Bit Set PDN_AFE Bit
Reset
RESET
RX Supplies
(RX_ANA_SUP, RX_DIG_SUP)
TX Supplies
(TX_CTRL_SUP, LED_DRV_SUP)
RESET
SPI Interface
ADC_RDY
AFE_PDN
~
~
~
~
t1
t2
t3t4t5
t7t3
t4t5
t6t8
t6
AFE4490
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SBAS602H –DECEMBER 2012–REVISED OCTOBER 2014
7.7 Supply Ramp and Power-Down Timing Requirements VALUE
Keep as small as possible
t1Time between Rx and Tx supplies ramping up (for example, ±10 ms)
t2Time between both supplies stabilizing and high-going edge of RESET > 100 ms
t3RESET pulse width > 0.5 ms
t4Time between RESET and SPI commands > 1 µs
Time between SPI commands and the ADC_RESET which corresponds to valid > 3 ms of cumulative sampling time in each
t5data phase(1)(2)(3)
Time between RESET pulse and high-accuracy data coming out of the signal
t6> 1 s(3)
chain
t7Time from AFE_PDN high-going edge and RESET pulse(4) > 100 ms
Time from AFE_PDN high-going edge (or PDN_AFE bit reset) to high-accuracy
t8> 1 s(3)
data coming out of the signal chain
(1) This time is required for each of the four switched RC filters to fully settle to the new settings. The same time is applicable whenever
there is a change to any of the signal chain controls (for example, LED current setting, TIA gain, and so forth)
(2) If the SPI commands involve a change in the value of TX_REF from its default, then there is additional wait time that is approximately 1
s (for a 2.2-µF decoupling capacitor on the TX_REF pin).
(3) Dependent on the value of the capacitors on the BG and TX_REF pins. The 1-s wait time is necessary when the capacitors are 2.2 µF
and scale down proportionate to the capacitor value. A very low capacitor (for example, 0.1 µF) on these pins causes the transmitter
dynamic range to reduce to approximately 100 dB.
(4) After an active power-down from AFE_PDN, reset the device by using a low-going pulse on RESET.
Figure 3. Supply Ramp and Hardware Power-Down Timing
Figure 4. Supply Ramp and Software Power-Down Timing
Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 17
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0
100
200
300
400
500
600
0 10 20 30 40 50
Input Referred Noise Current,
pA rms in 5Hz Bandwidth
Pleth Current (A)
Duty Cycle = 1%
Duty Cycle = 5%
Duty Cycle = 10%
Duty Cycle = 15%
Duty Cycle = 20%
Duty Cycle = 25%
C005
For each setting RF adjusted for Full-Scale Output.
Amb Cancellation & stage 2 Gain = 4 used for Low
Pleth currents (0.125uA, 0.25uA & 0.5uA).
Noise is calculated in 5Hz B/W.
0
100
200
300
400
500
600
700
0 10 20 30 40 50
Input Referred Noise Current,
pA rms in 5Hz Bandwidth
Pleth Current (A)
Duty Cycle = 1%
Duty Cycle = 5%
Duty Cycle = 10%
Duty Cycle = 15%
Duty Cycle = 20%
Duty Cycle = 25%
C006
For each setting RF adjusted for Full-Scale Output.
Amb Cancellation & stage 2 Gain = 4 used for Low
Pleth currents (0.125uA, 0.25uA & 0.5uA).
Noise is calculated in 5Hz B/W.
45
46
46
47
47
48
48
49
49
50
50
2.5 3.0 3.5 4.0 4.5 5.0
TX_CTRL_SUP Current (A)
TX_CTRL_SUP Voltage (V)
C003
PRF = 600Hz
45.0
45.5
46.0
46.5
47.0
47.5
48.0
48.5
49.0
49.5
50.0
2.5 3.0 3.5 4.0 4.5 5.0
LED_DRV_SUP Current (A)
LED_DRV_SUP Voltage (V)
C004
With LED Current = 0mA
100
200
300
400
500
600
700
800
100 300 500 700 900 1100 1300
RX Current (A)
PRF (Hz)
RX_ANA_SUP_CURR (A)
RX_DIG_SUP_CURR (A)
RX_ANA_CURR_STG2EN (A)
C001
RX_ANA_SUP = RX_DIG_SUP = 3.6V
100
200
300
400
500
600
700
800
100 300 500 700 900 1100 1300
RX Current (A)
PRF (Hz)
RX_ANA_SUP_CURR (A)
RX_DIG_SUP_CURR (A)
RX_ANA_CURR_STG2EN (A)
C002
RX_ANA_SUP = RX_DIG_SUP = 2.0V
AFE4490
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7.8 Typical Characteristics
At TA= 25°C, RX_ANA_SUP = RX_DIG_SUP = 3.0 V, TX_CTRL_SUP = LED_DRV_SUP = 5 V, and fCLK = 8 MHz, unless
otherwise noted.
Figure 5. Total Rx Current vs PRF Figure 6. Total Rx Current vs PRF
Figure 7. TX_CTRL_SUP Current vs Figure 8. LED_DRV_SUP Current vs
TX_CTRL_SUP Voltage LED_DRV_SUP Voltage
Figure 9. Input-Referred Noise Current vs Figure 10. Input-Referred Noise Current vs
PLETH Current (BW = 5 Hz, PRF = 100 Hz) PLETH Current (BW = 5 Hz, PRF = 300 Hz)
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0
100
200
300
400
500
600
700
800
0 10 20 30 40 50
Input Referred Noise Current,
pA rms in 20Hz Bandwidth
Pleth Current (A)
Duty Cycle 1%
Duty Cycle 5%
Duty Cycle 10%
Duty Cycle 15%
Duty Cycle 20%
Duty Cycle 25%
C011
For each setting RF adjusted for Full-Scale Output.
Amb Cancellation & stage 2 Gain = 4 used for Low
Pleth currents (0.125uA, 0.25uA & 0.5uA).
Noise is calculated in 20Hz B/W.
0
100
200
300
400
500
600
700
800
0 10 20 30 40 50
Input Referred Noise Current,
pA rms in 20Hz Bandwidth
Pleth Current (A)
Duty Cycle 1%
Duty Cycle 5%
Duty Cycle 10%
Duty Cycle 15%
Duty Cycle 20%
Duty Cycle 25%
C012
For each setting RF adjusted for Full-Scale Output.
Amb Cancellation & stage 2 Gain = 4 used for Low
Pleth currents (0.125uA, 0.25uA & 0.5uA).
Noise is calculated in 20Hz B/W.
0
200
400
600
800
1000
1200
1400
0 10 20 30 40 50
Input Referred Noise Current,
pA rms in 5Hz Bandwidth
Pleth Current ( A)
Duty Cycle = 1%
Duty Cycle = 5%
Duty Cycle = 10%
Duty Cycle = 15%
Duty Cycle = 20%
Duty Cycle = 25%
C009
For each setting RF adjusted for Full-Scale Output.
Amb Cancellation & stage 2 Gain = 4 used for
Low Pleth currents (0.125uA, 0.25uA & 0.5uA).
Noise is calculated in 5Hz band.
0
200
400
600
800
1000
1200
1400
0 10 20 30 40 50
Input Referred Noise Current,
pA rms in 5Hz Bandwidth
Pleth Current ( A)
Duty cycle 1%
Duty cycle 5%
Duty cycle 10%
Duty cycle 15%
Duty cycle 20%
Duty cycle 25%
C010
For each setting RF adjusted for Full-Scale Output.
Amb Cancellation & stage 2 Gain = 4 used for
Low Pleth currents (0.125uA, 0.25uA & 0.5uA).
Noise is calculated in 5Hz band.
0
100
200
300
400
500
600
700
0 10 20 30 40 50
Input Referred Noise Current,
pA rms in 5Hz Bandwidth
Pleth Current (A)
Duty Cycle = 1%
Duty Cycle = 5%
Duty Cycle = 10%
Duty Cycle = 15%
Duty Cycle = 20%
Duty Cycle = 25%
C007
For each setting RF adjusted for Full-Scale Output.
Amb Cancellation & stage 2 Gain = 4 used for Low
Pleth currents (0.125uA, 0.25uA & 0.5uA.)
Noise is calculated in 5Hz band.
0
100
200
300
400
500
600
700
800
0 10 20 30 40 50
Input Referred Noise Current,
pA rms in 5Hz Bandwidth
Pleth Current ( A)
Duty Cycle = 1%
Duty Cycle = 5%
Duty Cycle = 10%
Duty Cycle = 15%
Duty Cycle = 20%
Duty Cycle = 25%
C008
For each RF adjusted for Full-Scale Output.
Amb Cancellation & stage 2 Gain = 4 used for Low
Pleth currents (0.125uA, 0.25uA & 0.5uA).
Noise is calculated in 5Hz band.
AFE4490
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SBAS602H –DECEMBER 2012–REVISED OCTOBER 2014
Typical Characteristics (continued)
At TA= 25°C, RX_ANA_SUP = RX_DIG_SUP = 3.0 V, TX_CTRL_SUP = LED_DRV_SUP = 5 V, and fCLK = 8 MHz, unless
otherwise noted.
Figure 11. Input-Referred Noise Current vs Figure 12. Input-Referred Noise Current vs
PLETH Current (BW = 5 Hz, PRF = 600 Hz) PLETH Current (BW = 5 Hz, PRF = 1200 Hz)
Figure 13. Input-Referred Noise Current vs Figure 14. Input-Referred Noise Current vs
PLETH Current (BW = 5 Hz, PRF = 2500 Hz) PLETH Current (BW = 5 Hz, PRF = 5000 Hz)
Figure 15. Input-Referred Noise Current vs Figure 16. Input-Referred Noise Current vs
PLETH Current (BW = 20 Hz, PRF = 100 Hz) PLETH Current (BW = 20 Hz, PRF = 300 Hz)
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10
11
12
13
14
15
16
0 10 20 30 40 50
Noise-Free Bits in 5Hz Bandwidth
Pleth Current (A)
Duty Cycle 1%
Duty Cycle 5%
Duty Cycle 10%
Duty Cycle 15%
Duty Cycle 20%
Duty Cycle 25%
C017
For each setting RF adjusted for Full-Scale Output.
Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA).
RMS noise is calculated in 5Hz B/W & NFB is calculated using 6.6 u RMS noise.
10
11
12
13
14
15
16
0 10 20 30 40 50
Noise-Free Bits in 5Hz Bandwidth
Pleth Current (A)
Duty Cycle 1%
Duty Cycle 5%
Duty Cycle 10%
Duty Cycle 15%
Duty Cycle 20%
Duty Cycle 25%
C018
For each setting RF adjusted for Full-Scale Output.
Amb Cancellation & stage 2 Gain = 4 used for Low pleth currents (0.125uA, 0.25uA & 0.5uA.)
RMS noise is calculated in 5Hz B/W & NFB is calculated using 6.6 u RMS noise.
0
200
400
600
800
1000
1200
1400
1600
1800
0 10 20 30 40 50
Input Referred Noise Current,
pA rms in 20Hz Bandwidth
Pleth Current (A)
Duty Cycle 1%
Duty Cycle 5%
Duty Cycle 10%
Duty Cycle 15%
Duty Cycle 20%
Duty Cycle 25%
C015
For each setting RF adjusted for Full-Scale Output.
Amb Cancellation & stage 2 Gain = 4 used for
Low Pleth currents (0.125uA, 0.25uA & 0.5uA).
Noise is calculated in 20Hz band.
0
200
400
600
800
1000
1200
1400
0 10 20 30 40 50
Input Referred Noise Current,
pA rms in 20Hz Bandwidth
Pleth Current (A)
Duty cycle 1%
Duty cycle 5%
Duty cycle 10%
Duty cycle 15%
Duty cycle 20%
Duty cycle 25%
For each setting RF adjusted for Full-Scale Output.
Amb Cancellation & stage 2 Gain = 4 used for
Low Pleth currents (0.125uA, 0.25uA & 0.5uA).
Noise is calculated in 20Hz band.
C016
0
100
200
300
400
500
600
700
800
900
0 10 20 30 40 50
Input Referred Noise Current,
pA rms in 20Hz Bandwidth
Pleth Current (A)
Duty Cycle 1%
Duty Cycle 5%
Duty Cycle 10%
Duty Cycle 15%
Duty Cycle 20%
Duty Cycle 25%
C013
For each setting RF adjusted for Full-Scale Output.
Amb Cancellation & stage 2 Gain = 4 used for Low
Pleth currents (0.125uA, 0.25uA & 0.5uA.)
Noise is calculated in 20Hz band.
0
200
400
600
800
1000
1200
0 10 20 30 40 50
Input Referred Noise Current,
pA rms in 20Hz Bandwidth
Pleth Current (A)
Duty Cycle 1%
Duty Cycle 5%
Duty Cycle 10%
Duty Cycle 15%
Duty Cycle 20%
Duty cycle 25%
C014
For each RF adjusted for Full-Scale Output.
Amb Cancellation & stage 2 Gain = 4 used for Low
Pleth currents (0.125uA, 0.25uA & 0.5uA).
Noise is calculated in 20Hz band.
AFE4490
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www.ti.com
Typical Characteristics (continued)
At TA= 25°C, RX_ANA_SUP = RX_DIG_SUP = 3.0 V, TX_CTRL_SUP = LED_DRV_SUP = 5 V, and fCLK = 8 MHz, unless
otherwise noted.
Figure 17. Input-Referred Noise Current vs Figure 18. Input-Referred Noise Current vs
PLETH Current (BW = 20 Hz, PRF = 600 Hz) PLETH Current (BW = 20 Hz, PRF = 1200 Hz)
Figure 19. Input-Referred Noise Current vs Figure 20. Input-Referred Noise Current vs
PLETH Current (BW = 20 Hz, PRF = 2500 Hz) PLETH Current (BW = 20 Hz, PRF = 5000 Hz)
Figure 21. Noise-Free Bits vs Figure 22. Noise-Free Bits vs
PLETH Current (BW = 5 Hz, PRF = 100 Hz) PLETH Current (BW = 5 Hz, PRF = 300 Hz)
20 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: AFE4490
10
11
12
13
14
15
16
0 10 20 30 40 50
Noise-Free Bits in 20Hz Bandwidth
Pleth Current (A)
Duty Cycle 1%
Duty Cycle 5%
Duty Cycle 10%
Duty Cycle 15%
Duty Cycle 20%
Duty Cycle 25%
C023
For each setting RF adjusted for Full-Scale Output.
Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA).
RMS noise is calculated in 20Hz B/W & NFB is calculated using 6.6 u RMS noise.
10
11
12
13
14
15
16
0 10 20 30 40 50
Noise-Free Bits in 20Hz Bandwidth
Pleth Current (A)
Duty Cycle 1%
Duty Cycle 5%
Duty Cycle 10%
Duty Cycle 15%
Duty Cycle 20%
Duty Cycle 25%
C024
For each setting RF adjusted for Full-Scale Output.
Amb Cancellation & stage 2 Gain = 4 used for Low pleth currents (0.125uA, 0.25uA & 0.5uA.)
RMS noise is calculated in 20Hz B/W & NFB is calculated using 6.6 u RMS noise.
10
11
12
13
14
15
0 10 20 30 40 50
Noise-Free Bits in 5Hz Bandwidth
Pleth Current (A)
Duty Cycle = 1%
Duty Cycle = 5%
Duty Cycle = 10%
Duty Cycle = 15%
Duty Cycle = 20%
Duty Cycle = 25%
C021
For each setting RF adjusted for Full-
Scale Output.
Amb Cancellation & stage 2 Gain = 4
used for Low Pleth currents (0.125uA,
0.25uA & 0.5uA).
RMS noise is calculated in 5Hz B/W &
NFB is calculated using 6.6 u RMS noise.
10
11
12
13
14
15
16
0 10 20 30 40 50
Noise-Free Bits in 5Hz Bandwidth
Pleth Current (A)
Duty cycle 1%
Duty cycle 5%
Duty cycle 10%
Duty cycle 15%
Duty cycle 20%
Duty cycle 25%
C022
For each setting RF adjusted for Full-Scale
Output.
Amb Cancellation & stage 2 Gain = 4 used
for Low Pleth currents (0.125uA, 0.25uA &
0.5uA).
RMS noise is calculated in 5Hz B/W & NFB
10
11
12
13
14
15
16
0 10 20 30 40 50
Noise-Free Bits in 5Hz Bandwidth
Pleth Current (A)
Duty Cycle 1%
Duty Cycle 5%
Duty Cycle 10%
Duty Cycle 15%
Duty Cycle 20%
Duty Cycle 25%
C019
For each setting RF adjusted for Full-Scale Output.
Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA).
RMS noise is calculated in 5Hz B/W & NFB is calculated using 6.6 u RMS noise.
10
11
12
13
14
15
16
0 10 20 30 40 50
Noise-Free Bits in 5Hz Bandwidth
Pleth Current (A)
Duty Cycle = 1%
Duty Cycle = 5%
Duty Cycle = 10%
Duty Cycle = 15%
Duty Cycle = 20%
Duty Cycle = 25%
C020
For each setting RF adjusted for Full-Scale Output.
Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA).
RMS noise is calculated in 5Hz B/W & NFB is calculated using 6.6 u RMS noise.
AFE4490
www.ti.com
SBAS602H –DECEMBER 2012–REVISED OCTOBER 2014
Typical Characteristics (continued)
At TA= 25°C, RX_ANA_SUP = RX_DIG_SUP = 3.0 V, TX_CTRL_SUP = LED_DRV_SUP = 5 V, and fCLK = 8 MHz, unless
otherwise noted.
Figure 23. Noise-Free Bits vs Figure 24. Noise-Free Bits vs
PLETH Current (BW = 5 Hz, PRF = 600 Hz) PLETH Current (BW = 5 Hz, PRF = 1200 Hz)
Figure 25. Noise-Free Bits vs Figure 26. Noise-Free Bits vs
PLETH Current (BW = 5 Hz, PRF = 2500 Hz) PLETH Current (BW = 5 Hz, PRF = 5000 Hz)
Figure 27. Noise-Free Bits vs Figure 28. Noise-Free Bits vs
PLETH Current (BW = 20 Hz, PRF = 100 Hz) PLETH Current (BW = 20 Hz, PRF = 300 Hz)
Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 21
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50
60
70
80
90
100
110
120
0 20 40 60 80 100
TX Dynamic Range (dB)
% of Full-Scale LED Current
75mA & 150mA Range
200mA Range
50mA & 100mA Range
C029
50
60
70
80
90
100
110
120
0 20 40 60 80 100
TX Dynamic Range (dB)
% of Full-Scale LED Current
75mA & 150mA Range
200mA Range
50mA & 100mA Range
C030
10
11
12
13
14
15
0 10 20 30 40 50
Noise-Free Bits in 20Hz Bandwidth
Pleth Current (A)
Duty Cycle 1%
Duty Cycle 5%
Duty Cycle 10%
Duty Cycle 15%
Duty Cycle 20%
Duty Cycle 25%
C027
For each setting RF adjusted for Full-
Scale Output.
Amb Cancellation & stage 2 Gain = 4
used for Low Pleth currents (0.125uA,
0.25uA & 0.5uA).
RMS noise is calculated in 20Hz B/W &
NFB is calculated using 6.6 u RMS noise.
10
11
12
13
14
15
16
0 10 20 30 40 50
Noise-Free Bits in 20Hz Bandwidth
Pleth Current (A)
Duty cycle 1%
Duty cycle 5%
Duty cycle 10%
Duty cycle 15%
Duty cycle 20%
Duty cycle 25%
C028
For each setting RF adjusted for Full-Scale
Output.
Amb Cancellation & stage 2 Gain = 4 used for
Low Pleth currents (0.125uA, 0.25uA &
0.5uA).
RMS noise is calculated in 20Hz B/W & NFB is
calculated using 6.6 u RMS noise.
10
11
12
13
14
15
16
0 10 20 30 40 50
Noise-Free Bits in 20Hz Bandwidth
Pleth Current (A)
Duty Cycle 1%
Duty Cycle 5%
Duty Cycle 10%
Duty Cycle 15%
Duty Cycle 20%
Duty Cycle 25%
C025
For each setting RF adjusted for Full-Scale Output.
Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA).
RMS noise is calculated in 20Hz B/W & NFB is calculated using 6.6 u RMS noise.
10
11
12
13
14
15
16
0 10 20 30 40 50
Noise-Free Bits in 20Hz Bandwidth
Pleth Current (A)
Duty Cycle 1%
Duty Cycle 5%
Duty Cycle 10%
Duty Cycle 15%
Duty Cycle 20%
Duty Cycle 25%
C026
For each setting RF adjusted for Full-Scale Output.
Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA).
RMS noise is calculated in 20Hz B/W & NFB is calculated using 6.6 u RMS noise.
AFE4490
SBAS602H –DECEMBER 2012–REVISED OCTOBER 2014
www.ti.com
Typical Characteristics (continued)
At TA= 25°C, RX_ANA_SUP = RX_DIG_SUP = 3.0 V, TX_CTRL_SUP = LED_DRV_SUP = 5 V, and fCLK = 8 MHz, unless
otherwise noted.
Figure 29. Noise-Free Bits vs Figure 30. Noise-Free Bits vs
PLETH Current (BW = 20 Hz, PRF = 600 Hz) PLETH Current (BW = 20 Hz, PRF = 1200 Hz)
Figure 31. Noise-Free Bits vs Figure 32. Noise-Free Bits vs
PLETH Current (BW = 20 Hz, PRF = 2500 Hz) PLETH Current (BW = 20 Hz, PRF = 5000 Hz)
Figure 33. Transmitter Dynamic Range Figure 34. Transmitter Dynamic Range
(5-Hz BW) (20-Hz BW)
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Product Folder Links: AFE4490
±500
±400
±300
±200
±100
0
100
200
300
400
500
0 50 100 150 200 250
DAC Step Error (A)
TX LED DAC Setting
C035
TX_REF = 0.5V
0
20
40
60
80
100
0 50 100 150 200 250
TX Current (mA)
TX LED DAC Setting
Expected + 1%
Actual DAC Current
Expected - 1%
C036
TX Reference Voltage = 0.5V
±500
±400
±300
±200
±100
0
100
200
300
400
500
0 50 100 150 200 250
DAC Step Error (A)
TX LED DAC Setting
C033
TX_REF = 0.5V
±500
±400
±300
±200
±100
0
100
200
300
400
500
0 50 100 150 200 250
DAC Step Error (A)
TX LED DAC Setting
C034
TX_REF = 0.5V
±500
±400
±300
±200
±100
0
100
200
300
400
500
0 50 100 150 200 250
DAC Step Error (A)
TX LED DAC Setting
C031
TX_REF = 0.5V
±500
±400
±300
±200
±100
0
100
200
300
400
500
0 50 100 150 200 250
DAC Step Error (A)
TX LED DAC Setting
C032
TX_REF = 0.5V
AFE4490
www.ti.com
SBAS602H –DECEMBER 2012–REVISED OCTOBER 2014
Typical Characteristics (continued)
At TA= 25°C, RX_ANA_SUP = RX_DIG_SUP = 3.0 V, TX_CTRL_SUP = LED_DRV_SUP = 5 V, and fCLK = 8 MHz, unless
otherwise noted.
Figure 35. Transmitter DAC Current Step Error Figure 36. Transmitter DAC Current Step Error
(200 mA, Max) (150 mA, Max)
Figure 37. Transmitter DAC Current Step Error Figure 38. Transmitter DAC Current Step Error
(100 mA, Max) (75 mA, Max)
Figure 39. Transmitter DAC Current Step Error Figure 40. Transmitter Current Linearity
(50 mA, Max) (50-mA Range)
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0
200
400
600
800
8.0
8.2
8.4
8.6
8.8
9.0
9.2
9.4
9.6
9.8
10.0
10.2
10.4
10.6
10.8
11.0
11.2
11.4
11.6
11.8
12.0
Number of Occurences
LED Current (mA)
C043
TX_RANGE = 150mA,
Data from 2326 devices
0
200
400
600
800
1000
1200
1400
1600
1800
2000
2200
30.0
30.5
31.0
31.5
32.0
32.5
33.0
33.5
34.0
34.5
35.0
35.5
36.0
36.5
37.0
37.5
38.0
38.5
39.0
39.5
40.0
Number of Occurences
LED Current (mA)
C044
TX_RANGE = 150mA,
Data from 7737 devices
0
20
40
60
80
100
120
140
160
0 50 100 150 200 250
TX Current (mA)
TX LED DAC Setting
Expected + 1%
Actual DAC Current
Expected - 1%
C039
TX Reference Voltage = 0.75V
0
20
40
60
80
100
120
140
160
180
200
0 50 100 150 200 250
TX Current (mA)
TX LED DAC Setting
Expected + 1%
Actual DAC Current
Expected - 1%
C040
TX Reference Voltage = 1.0V
0
20
40
60
80
100
0 50 100 150 200 250
TX Current (mA)
TX LED DAC Setting
Expected + 1%
Actual DAC Current
Expected - 1%
C037
TX Reference Voltage = 0.5V
0
20
40
60
80
100
0 50 100 150 200 250
TX Current (mA)
TX LED DAC Setting
Expected + 1%
Actual DAC Current
Expected - 1%
C038
TX Reference Voltage = 0.5V
AFE4490
SBAS602H –DECEMBER 2012–REVISED OCTOBER 2014
www.ti.com
Typical Characteristics (continued)
At TA= 25°C, RX_ANA_SUP = RX_DIG_SUP = 3.0 V, TX_CTRL_SUP = LED_DRV_SUP = 5 V, and fCLK = 8 MHz, unless
otherwise noted.
Figure 41. Transmitter Current Linearity Figure 42. Transmitter Current Linearity
(75-mA Range) (100-mA Range)
Figure 43. Transmitter Current Linearity Figure 44. Transmitter Current Linearity
(150-mA Range) (200-mA Range)
Figure 45. LED Current with Tx DAC Setting = 17 Figure 46. LED Current with Tx DAC Setting = 60
(10 mA) (35 mA)
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0
50
100
150
200
250
300
350
400
450
500
550
600
650
700
0 10 20 30 40 50 60 70
Supply Current, uA
Temperature, C
RX_ANA_SUP (STG2DIS)
RX_ANA_SUP (STG2EN)
RX_DIG_SUP
TX_CTRL_SUP
LED_DRV_SUP
C049
0
20
40
60
80
100
±40 ±30 ±20 ±10 0 10 20 30 40 50 60 70 80
Input referred noise current, pA rms
Temperature, C
STG2=DIS, 5Hz BW (Note 1)
STG2=EN, 5Hz BW (Note 2)
STG2=DIS, 20Hz BW (Note 1)
STG2=EN, 20Hz BW (Note 2)
C050
PRF = 1200 Hz, Duty cycle = 10%
1) RF = 100K, Stage 2 & ambient cancellation disabled
2) RF = 500K, Stage 2 & ambient cancellation enabled with stage 2 gain = 4
100
200
300
400
500
600
700
800
100 300 500 700 900 1100
RX Supply Current, uA
PRF, Hz
RX_ANA_SUP = 2V (STG2=DIS)
RX_ANA_SUP = 2V (STG2=EN)
RX_DIG_SUP=2V
RX_ANA_SUP = 3.3V (STG2=DIS)
RX_ANA_SUP = 3.3V (STG2=EN)
RX_DIG_SUP=3.3V
C047
0.00
20.00
40.00
60.00
80.00
100.00
0.50 0.75 1.00
TX Supply Current, uA
TX_VREF, V
TX_CTRL_SUP
LED_DRV_SUP
C048
TX_CTRL_SUP = LED_DRV_SUP = 3V TO 3.6V
0
200
400
600
800
1000
1200
63.0
63.5
64.0
64.5
65.0
65.5
66.0
66.5
67.0
67.5
68.0
68.5
69.0
69.5
70.0
70.5
71.0
71.5
72.0
72.5
73.0
73.5
74.0
74.5
75.0
75.5
76.0
76.5
77.0
Number of Occurences
LED Current (mA)
C045
TX_RANGE = 150mA,
Data from 7737 devices
0
200
400
600
800
1000
1200
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
Number of Occurences
LED Current (mA)
C046
TX_RANGE = 150mA,
Data from 7737 devices
AFE4490
www.ti.com
SBAS602H –DECEMBER 2012–REVISED OCTOBER 2014
Typical Characteristics (continued)
At TA= 25°C, RX_ANA_SUP = RX_DIG_SUP = 3.0 V, TX_CTRL_SUP = LED_DRV_SUP = 5 V, and fCLK = 8 MHz, unless
otherwise noted.
Figure 47. LED Current with Tx DAC Setting = 120 Figure 48. LED Current with Tx DAC Setting = 255
(70 mA) (150 mA)
Figure 49. Receiver Supplies vs PRF Figure 50. Transmitter Supplies vs TX_REF
Figure 51. Power Supplies vs Temperature Figure 52. Input-Referred Noise vs Temperature
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10
15
0 10 20 30 40 50 60 70
Noise Free Bits
Temperature, C
STG2=DIS, 5Hz BW (Note 1)
STG2=EN, 5Hz BW (Note 2)
STG2=DIS, 20Hz BW (Note 1)
STG2=EN, 20Hz BW (Note 2)
C051
PRF = 1200 Hz, Duty cycle = 10%
1) RF = 100K, Stage 2 & ambient cancellation disabled
2) RF = 500K, Stage 2 & ambient cancellation enabled with stage 2 gain = 4
±50
±40
±30
±20
±10
0
1 10 100
Attenuation, dB
Input signal frequency, Hz
5% Duty cycle
25% Duty cycle
C052
AFE4490
SBAS602H –DECEMBER 2012–REVISED OCTOBER 2014
www.ti.com
Typical Characteristics (continued)
At TA= 25°C, RX_ANA_SUP = RX_DIG_SUP = 3.0 V, TX_CTRL_SUP = LED_DRV_SUP = 5 V, and fCLK = 8 MHz, unless
otherwise noted.
Figure 53. Noise-Free Bits vs Temperature Figure 54. Filter Response vs Duty Cycle
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Device
Digital
Filter
SPI
+
Buffer 4GADC
+
TIA
+
Stage 2
Gain
Photodiode
CPD Filter
SPI Interface
Diagnostics
Timing
Controller
OSC
8 MHz
Diagnostic
Signals
INN
INP
RX_ANA_GND
VCM
DNC(1)
DNC(1)
BG
VSS
TX_REF
TX_CTRL_SUP
LED_DRV_GND
LED_DRV_GND
TXN
TXP
LED_DRV_GND
LED_DRV_SUP
LED_DRV_SUP
RX_DIG_GND
AFE_PDN
DIAG_END
LED_ALM
PD_ALM
SCLK
SPISOMI
SPISIMO
SPISTE
ADC_RDY
RESET
CLKOUT
RX_DIG_SUP
RX_DIG_GND
RX_ANA_SUP
DNC
DNC
RX_ANA_GND
XOUT
XIN
RX_ANA_SUP
RX_ANA_GND
DNC(1)
Control
Reference
CF
CF
RF
RF
LED
Driver
LED Current
Control DAC
LED
C
r1.2 V
C
AFE4490
www.ti.com
SBAS602H –DECEMBER 2012–REVISED OCTOBER 2014
8 Detailed Description
8.1 Overview
The AFE4490 is a complete analog front-end (AFE) solution targeted for pulse-oximeter applications. The device
consists of a low-noise receiver channel, an LED transmit section, and diagnostics for sensor and LED fault
detection. To ease clocking requirements and provide the low-jitter clock to the AFE, an oscillator is also
integrated that functions from an external crystal. The device communicates to an external microcontroller or host
processor using an SPI interface. The Functional Block Diagram section provides a detailed block diagram for
the device. The blocks are described in more detail in the following sections.
8.2 Functional Block Diagram
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Product Folder Links: AFE4490
R C
F´ £
F
Rx Sample Time
10
LED2
SLED2 CONVLED2
Amb
Amb
SLED1_amb
SLED1
SLED2_amb
CONVLED1
CONVLED2_amb
CONVLED1_amb
LED1
Rx
Ambient-cancellation current can be set digitally using SPI interface.
CF
CF
RF
RF
CPD
+TIA +
Stage 2
Gain
RG
RG
+Buffer ûADC
ADC
ADC Clock
ADC Convert
ADC Output Rate
PRF Sa/sec
I-V Amplifier Amb cancellation DAC BufferFilter ADC
Ambient
DAC
AFE4490
SBAS602H –DECEMBER 2012–REVISED OCTOBER 2014
www.ti.com
8.3 Feature Description
8.3.1 Receiver Channel
This section describes the receiver channel functionality.
8.3.1.1 Receiver Front-End
The receiver consists of a differential current-to-voltage (I-V) transimpedance amplifier that converts the input
photodiode current into an appropriate voltage, as shown in Figure 55. The feedback resistor of the amplifier (RF)
is programmable to support a wide range of photodiode currents. Available RFvalues include: 1 MΩ, 500 kΩ,
250 kΩ, 100 kΩ, 50 kΩ, 25 kΩ, and 10 kΩ.
Figure 55. Receiver Front-End
The RFamplifier and the feedback capacitor (CF) form a low-pass filter for the input signal current. Always ensure
that the low-pass filter RC time constant has sufficiently high bandwidth (as shown by Equation 1) because the
input current consists of pulses. For this reason, the feedback capacitor is also programmable. Available CF
values include: 5 pF, 10 pF, 25 pF, 50 pF, 100 pF, and 250 pF. Any combination of these capacitors can also be
used.
(1)
The output voltage of the I-V amplifier includes the pleth component (the desired signal) and a component
resulting from the ambient light leakage. The I-V amplifier is followed by the second stage, which consists of a
current digital-to-analog converter (DAC) that sources the cancellation current and an amplifier that gains up the
pleth component alone. The amplifier has five programmable gain settings: 0 dB, 3.5 dB, 6 dB, 9.5 dB, and
12 dB. The gained-up pleth signal is then low-pass filtered (500-Hz bandwidth) and buffered before driving a 22-
bit ADC. The current DAC has a cancellation current range of 10 µA with 10 steps (1 µA each). The DAC value
can be digitally specified with the SPI interface. Using ambient compensation with the ambient DAC allows the
dc-biased signal to be centered to near mid-point of the amplifier (±0.9 V). Using the gain of the second stage
allows for more of the available ADC dynamic range to be used.
The output of the ambient cancellation amplifier is separated into LED2 and LED1 channels. When LED2 is on,
the amplifier output is filtered and sampled on capacitor CR. Similarly, the LED1 signal is sampled on the CLED1
capacitor when LED1 is ON. In between the LED2 and LED1 pulses, the idle amplifier output is sampled to
estimate the ambient signal on capacitors CLED2_amb and CLED1_amb.
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Product Folder Links: AFE4490
Device
Digital Control for Ambient-Cancellation DAC
Rx
Digital
LED2 Data
ADC Output Rate
PRF Samples per Second Ambient (LED2)
Data
LED1 Data
Ambient (LED1)
Data
SPI
Block
SPI
Interface
Host Processor
Ambient Estimation Block
Ambient information is available in the host
processor.
The processor can:
* Read ambient data
* Estimate ambient value to
be cancelled
* Set the value to be used by the ambient
cancellation DAC using the SPI of AFE
Front End
(LED2 ± Ambient)
Data
(LED1 ± Ambient)
Data
ADC
AFE4490
www.ti.com
SBAS602H –DECEMBER 2012–REVISED OCTOBER 2014
Feature Description (continued)
The sampling duration is termed the Rx sample time and is programmable for each signal, independently.
Sampling can start after the I-V amplifier output is stable (to account for LED and cable settling times). The Rx
sample time is used for all dynamic range calculations; the minimum time supported is 50 µs.
A single, 22-bit ADC converts the sampled LED2, LED1, and ambient signals sequentially. Each conversion
takes a maximum of 25% of the pulse repetition period (PRP) and provides a single digital code at the ADC
output. As discussed in the Receiver Timing section, the conversions are staggered so that the LED2 conversion
starts after the end of the LED2 sample phase, and so on. This configuration also means that the Rx sample
time for each signal is no greater than 25% of the pulse repetition period.
Note that four data streams are available at the ADC output (LED2, LED1, ambient LED2, and ambient LED1) at
the same rate as the pulse repetition frequency. The ADC is followed by a digital ambient subtraction block that
additionally outputs the (LED2 – ambient LED2) and (LED1 – ambient LED1) data values.
8.3.1.2 Ambient Cancellation Scheme
The receiver provides digital samples corresponding to ambient duration. The host processor (external to the
AFE) can use these ambient values to estimate the amount of ambient light leakage. The processor must then
set the value of the ambient cancellation DAC using the SPI, as shown in Figure 56.
Figure 56. Ambient Cancellation Loop (Closed by the Host Processor)
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Product Folder Links: AFE4490
V = 2
DIFF ´IPLETH ´
RF
RI
+ IAMB ´
RF
RI
-ICANCEL ´RG
Rf
Cf
Rf
Cf
Rx
VDIFF
Ri
Ri
Rg
Rg
IPLETH + IAMB
ICANCEL
Value of ICANCEL set using
the SPI interface.
ICANCEL
AFE4490
SBAS602H –DECEMBER 2012–REVISED OCTOBER 2014
www.ti.com
Feature Description (continued)
Using the set value, the ambient cancellation stage subtracts the ambient component and gains up only the pleth
component of the received signal, as shown in Figure 57. The amplifier gain is programmable to 0 dB, 3.5 dB,
6 dB, 9.5 dB, and 12 dB.
Figure 57. Front-End (I-V Amplifier and Cancellation Stage)
The differential output of the second stage is VDIFF, as given by Equation 2:
where:
• RI= 100 kΩ,
• IPLETH = photodiode current pleth component,
• IAMB = photodiode current ambient component, and
• ICANCEL = the cancellation current DAC value (as estimated by the host processor). (2)
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AFE4490
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SBAS602H –DECEMBER 2012–REVISED OCTOBER 2014
Feature Description (continued)
RGvalues with various gain settings are listed in Table 1.
Table 1. RGValues
RG(dB) GAIN (kΩ)
0 (x1) 100
3.5 (x1.5) 150
6 (x2) 200
9.5 (x3) 300
12 (x4) 400
8.3.1.3 Receiver Control Signals
LED2 sample phase (SLED2): When this signal is high, the amplifier output corresponds to the LED2 on-time.
The amplifier output is filtered and sampled into capacitor CLED2. To avoid settling effects resulting from the LED
or cable, program SLED2 to start after the LED turns on. This settling delay is programmable.
Ambient sample phase (SLED2_amb): When this signal is high, the amplifier output corresponds to the LED2 off-
time and can be used to estimate the ambient signal (for the LED2 phase). The amplifier output is filtered and
sampled into capacitor CLED2_amb.
LED1 sample phase (SLED1): When this signal is high, the amplifier output corresponds to the LED1 on-time.
The amplifier output is filtered and sampled into capacitor CLED1. To avoid settling effects resulting from the LED
or cable, program SLED1 to start after the LED turns on. This settling delay is programmable.
Ambient sample phase (SLED1_amb): When this signal is high, the amplifier output corresponds to the LED1 off-
time and can be used to estimate the ambient signal (for the LED1 phase). The amplifier output is filtered and
sampled into capacitor CLED1_amb.
LED2 convert phase (CONVLED2): When this signal is high, the voltage sampled on CLED2 is buffered and
applied to the ADC for conversion. The conversion time duration is always 25% of the pulse repetition period. At
the end of the conversion, the ADC provides a single digital code corresponding to the LED2 sample.
Ambient convert phases (CONVLED2_amb, CONVLED1_amb): When this signal is high, the voltage sampled on
CLED2_amb (or CLED1_amb) is buffered and applied to the ADC for conversion. The conversion time duration is
always 25% of the pulse repetition period. At the end of the conversion, the ADC provides a single digital code
corresponding to the ambient sample.
LED1 convert phase (CONVLED1): When this signal is high, the voltage sampled on CLED1 is buffered and
applied to the ADC for conversion. The conversion time duration is always 25% of the pulse repetition period. At
the end of the conversion, the ADC provides a single digital code corresponding to the LED1 sample.
8.3.1.4 Receiver Timing
See Figure 58 for a timing diagram detailing the control signals related to the LED on-time, Rx sample time, and
the ADC conversion times for each channel.
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Photodiode Current
Or
I-V Output Pulses
Ambient Level
(Dark Level)
SR,
Sample RED
SR_amb,
Sample Ambient
(RED Phase)
SIR,
Sample IR
SIR_amb,
Sample Ambient
(IR Phase)
Plethysmograph Signal
N
N+2
N+1
NN+1
Convert Red
Sample N
Convert Ambient
Sample N
Convert IR
Sample N
Convert Ambient
Sample N
Convert Red
Sample N+1
Convert Ambient
Sample N+1
Convert IR
Sample N+1
Convert Ambient
Sample N+1
Convert Ambient
Sample N-1
Sample phase t input current is converted to an analog voltage.
Sample phase width is variable from 0 to 25% duty cycle.
Convert Red
Sample N-1
Convert phase t sampled analog voltage is converted to a digital code.
ADC Conversion time is fixed at 25% duty cycle of PRF.
IR LED
On Signal
RED LED
On Signal
Pulse Repetition Period T = 1 / PRF
TCONV
tLED LED On-Time
d 0.25 T
Rx Sample Time =
tLED ± Settle Time
0 T
0.25 T
0.50 T
0.75 T
1.0 T
CONVIR_amb,
Convert Ambient Sample
(IR Phase)
CONVR,
Convert RED Sample
CONVR_amb,
Convert Ambient Sample
(RED Phase)
CONVIR,
Convert IR Sample
ADC Conversion
AFE4490
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NOTE: Relationship to the AFE4490EVM is: LED1 = IR and LED2 = RED.
Figure 58. Rx Timing Diagram
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8-MHz Crystal
Timer
Module
Diagnostics
Module
ADC
Oscillator
Divide-
by-2
CLKOUT
4 MHz
XIN XOUT
AFE4490
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8.3.2 Clocking and Timing Signal Generation
The crystal oscillator generates a master clock signal using an external 8-MHz crystal. A divide-by-2 block
converts the 8-MHz clock to 4 MHz, which is used by the AFE to operate the timer modules, ADC, and
diagnostics. The 4-MHz clock is buffered and output from the AFE in order to clock an external microcontroller.
The clocking functionality is shown in Figure 59.
Figure 59. AFE Clocking
8.3.3 Timer Module
See Figure 60 for a timing diagram detailing the various timing edges that are programmable using the timer
module. The rising and falling edge positions of 11 signals can be controlled. The module uses a single 16-bit
counter (running off of the 4-MHz clock) to set the time-base.
All timing signals are set with reference to the pulse repetition period (PRP). Therefore, a dedicated compare
register compares the 16-bit counter value with the reference value specified in the PRF register. Every time that
the 16-bit counter value is equal to the reference value in the PRF register, the counter is reset to '0'.
Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 33
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LED1(IR LED)
ON signal
LED2(Red LED)
ON signal
tLED LED On-Time
d 0.25 T
Rx Sample Time = tLED ± Settling Time
0 T
0.25 T
0.50 T
0.75 T
1.0 T
ADC Conversion
Pulse Repetition Period (PRP)
T = 1 / PRF
ADC Reset
ADC_RDY Pin
CONVLED1_amb,
Convert ambient sample
(LED1(IR) phase)
CONVLED1,
Convert LED1(IR) sample
CONVLED2_amb,
Convert ambient sample
(LED2(Red) phase)
CONVLED2,
Convert LED2(Red) sample
SLED2,
Sample LED2(Red)
SLED2_amb,
Sample Ambient
(LED2(Red) phase)
SLED1,
Sample LED1(IR)
SLED1_amb,
Sample Ambient
(LED1(IR) phase)
AFE4490
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NOTE: Programmable edges are shown in blue and red.
Figure 60. AFE Control Signals
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Timer Compare
16-Bit Register 11
16-Bit Counter
Timer Compare
16-Bit Register 1
Start
Stop
Timer Compare
16-Bit Register 2
Start
Stop
Timer Compare
16-Bit Register 3
Start
Stop
Timer Compare
16-Bit Register 4
Start
Stop
Timer Compare
16-Bit Register 5
Start
Stop
Timer Compare
16-Bit Register 6
Start
Stop
Timer Compare
16-Bit PRF Register PRF
Pulse
Timer Compare
16-Bit Register 7 Start
Stop
Timer Compare
16-Bit Register 8 Start
Stop
Timer Compare
16-Bit Register 9 Start
Stop
Timer Compare
16-Bit Register 10 Start
Stop
START-A
STOP-A
START-B
STOP-B
START-C
STOP-D
START-D
STOP-D
RED LED S
R
IR LED S
R
SR
Sample RED S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
Reset
Counter
Reset
SIR
Sample IR
SR_amb,
Sample Ambient
(red phase)
SIR_amb,
Sample Ambient
(IR phase)
CONVR,
Convert RED Sample
CONVIR,
Convert IR Sample
CONVIR_amb,
Convert Ambient Sample
(IR Phase)
CONVR_amb,
Convert Ambient Sample
(RED Phase)
ADC
Conversion
Timer Module
Enable
En
En
En
En
En
En
En
En
En
En
En
En
CLKIN
Reset
Enable
START
STOP
Set
Reset Enable
Timer Compare Register
Start Reference Register
Stop Reference Register
Counter
Input
Output
Signal
AFE4490
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For the 11 signals in Figure 58, the start and stop edge positions are programmable with respect to the PRF
period. Each signal uses a separate timer compare module that compares the counter value with
preprogrammed reference values for the start and stop edges. All reference values can be set using the SPI
interface.
When the counter value equals the start reference value, the output signal is set. When the counter value equals
the stop reference value, the output signal is reset. Figure 61 shows a diagram of the timer compare register.
With a 4-MHz clock, the edge placement resolution is 0.25 µs. The ADC conversion signal requires four pulses in
each PRF clock period. The 11th timer compare register uses four sets of start and stop registers to control the
ADC conversion signal.
Figure 61. Compare Register
The ADC conversion signal requires four pulses in each PRF clock period. Timer compare register 11 uses four
sets of start and stop registers to control the ADC conversion signal, as shown in Figure 62.
Figure 62. Timer Module
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8.3.3.1 Using the Timer Module
The timer module registers can be used to program the start and end instants in units of 4-MHz clock cycles.
These timing instants and the corresponding registers are listed in Table 2.
Note that the device does not restrict the values in these registers; thus, the start and end edges can be
positioned anywhere within the pulse repetition period. Care must be taken by the user to program suitable
values in these registers to avoid overlapping the signals and to make sure none of the edges exceed the value
programmed in the PRP register. Writing the same value in the start and end registers results in a pulse duration
of one clock cycle. The following steps describe the timer sequencing configuration:
1. With respect to the start of the PRP period (indicated by timing instant t0in Figure 63 and Figure 64), the
sequence of conversions must be followed in order: convert LED2 →LED2 ambient →LED1 →LED1
ambient.
2. Also, starting from t0, the sequence of sampling instants must be staggered with respect to the respective
conversions as follows: sample LED2 ambient →LED1 →LED1 ambient →LED2.
3. Finally, align the edges for the two LED pulses with the respective sampling instants.
Table 2. Clock Edge Mapping to SPI Registers
TIME INSTANT
(See Figure 63 and EXAMPLE(1)
Figure 64) DESCRIPTION CORRESPONDING REGISTER ADDRESS AND REGISTER BITS (Decimal)
t0Start of pulse repetition period No register control —
t1Start of sample LED2 pulse Sample LED2 start count (bits 15-0 of register 01h) 6050
t2End of sample LED2 pulse Sample LED2 end count (bits 15-0 of register 02h) 7998
t3Start of LED2 pulse LED2 start count (bits 15-0 of register 03h) 6000
t4End of LED2 pulse LED2 end count (bits 15-0 of register 04h) 7999
t5Start of sample LED2 ambient pulse Sample ambient LED2 start count (bits 15-0 of register 05h) 50
t6End of sample LED2 ambient pulse Sample ambient LED2 end count (bits 15-0 of register 06h) 1998
t7Start of sample LED1 pulse Sample LED1 start count (bits 15-0 of register 07h) 2050
t8End of sample LED1 pulse Sample LED1 end count (bits 15-0 of register 08h) 3998
t9Start of LED1 pulse LED1 start count (bits 15-0 of register 09h) 2000
t10 End of LED1 pulse LED1 end count (bits 15-0 of register 0Ah) 3999
t11 Start of sample LED1 ambient pulse Sample ambient LED1 start count (bits 15-0 of register 0Bh) 4050
t12 End of sample LED1 ambient pulse Sample ambient LED1 end count (bits 15-0 of register 0Ch) 5998
LED2 convert start count (bits 15-0 of register 0Dh)
t13 Start of convert LED2 pulse 4
Must start one AFE clock cycle after the ADC reset pulse ends.
t14 End of convert LED2 pulse LED2 convert end count (bits 15-0 of register 0Eh) 1999
LED2 ambient convert start count (bits 15-0 of register 0Fh)
t15 Start of convert LED2 ambient pulse 2004
Must start one AFE clock cycle after the ADC reset pulse ends.
t16 End of convert LED2 ambient pulse LED2 ambient convert end count (bits 15-0 of register 10h) 3999
LED1 convert start count (bits 15-0 of register 11h)
t17 Start of convert LED1 pulse 4004
Must start one AFE clock cycle after the ADC reset pulse ends.
t18 End of convert LED1 pulse LED1 convert end count (bits 15-0 of register 12h) 5999
LED1 ambient convert start count (bits 15-0 of register 13h)
t19 Start of convert LED1 ambient pulse 6004
Must start one AFE clock cycle after the ADC reset pulse ends.
t20 End of convert LED1 ambient pulse LED1 ambient convert end count (bits 15-0 of register 14h) 7999
t21 Start of first ADC conversion reset pulse ADC reset 0 start count (bits 15-0 of register 15h) 0
t22 End of first ADC conversion reset pulse(2) ADC reset 0 end count (bits 15-0 of register 16h) 3
t23 Start of second ADC conversion reset pulse ADC reset 1 start count (bits 15-0 of register 17h) 2000
End of second ADC conversion reset
t24 ADC reset 1 end count (bits 15-0 of register 18h) 2003
pulse(2)
t25 Start of third ADC conversion reset pulse ADC reset 2 start count (bits 15-0 of register 19h) 4000
t26 End of third ADC conversion reset pulse(2) ADC reset 2 end count (bits 15-0 of register 1Ah) 4003
t27 Start of fourth ADC conversion reset pulse ADC reset 3 start count (bits 15-0 of register 1Bh) 6000
t28 End of fourth ADC conversion reset pulse(2) ADC reset 3 end count (bits 15-0 of register 1Ch) 6003
t29 End of pulse repetition period Pulse repetition period count (bits 15-0 of register 1Dh) 7999
(1) Values are based off of a pulse repetition frequency (PRF) = 500 Hz and duty cycle = 25%.
(2) See Figure 64, note 2 for the affect of the ADC reset time crosstalk.
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LED1 (IR LED)
On Signal
LED2 (RED LED)
On Signal
t0
ADC Conversion
Pulse Repetition Period (PRP),
One Cycle
ADC Reset
CONVLED1_amb,
Convert Ambient Sample
LED1 (IR) Phase
CONVLED1,
Convert LED1 (IR) Sample
CONVLED2_amb,
Convert Ambient Sample
LED2 (RED) Phase
CONVLED2,
Convert LED2 (RED) Sample
SLED2,
Sample LED2 (RED)
SLED2_amb,
Sample Ambient
LED2 (RED) Phase
SLED1,
Sample LED1 (IR)
SLED1_amb,
Sample Ambient
LED1 (IR) Phase
t29
t3t4
t10
t9
t5t6
t7t8
t11 t12
t2
t1
t13 t14
t15 t16
t17 t18
t19 t20
t21 t22
t23
t24
t25
t26
t27
t28
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(1) RED = LED2, IR = LED1.
(2) A low ADC reset time can result in a small component of the LED signal leaking into the ambient phase. With an ADC reset of two clock
cycles, a –60-dB leakage is expected. In many cases, this leakage does not affect system performance. However, if this crosstalk must be
completely eliminated, a longer ADC reset time of approximately six clock cycles is recommended for t22, t24, t26, and t28.
Figure 63. Programmable Clock Edges(1)(2)
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t0t29
ADC Conversion
Pulse Repetition Period (PRP),
One Cycle
t14
t15 t16
t13
t17 t18
t19 t20
t21
t22
t23
t24
t25
t26
t27
t28
ADC Reset
CONVLED1_amb,
Convert Ambient Sample
LED1 (IR) Phase
CONVLED1,
Convert LED1 (IR) Sample
CONVLED2_amb,
Convert Ambient Sample
LED2 (RED) Phase
CONVLED2,
Convert LED2 (RED) Sample
Two 4-MHz Clock Cycles
AFE4490
SBAS602H –DECEMBER 2012–REVISED OCTOBER 2014
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(1) RED = LED2, IR = LED1.
(2) A low ADC reset time can result in a small component of the LED signal leaking into the ambient phase. With an ADC reset of two clock
cycles, a –60-dB leakage is expected. In many cases, this leakage does not affect system performance. However, if this crosstalk must be
completely eliminated, a longer ADC reset time of approximately six clock cycles is recommended for t22, t24, t26, and t28.
Figure 64. Relationship Between the ADC Reset and ADC Conversion Signals(1)(2)
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RX_ANA_SUP
I/O
Pins
Device
1.8 V
1.8 V
RX_DIG_SUP
RX_ANA_SUP to
1.8-V Regulator Rx Analog Modules
RX_DIG_SUP to
1.8-V Regulator Rx Digital Rx I/O
Block
AFE4490
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SBAS602H –DECEMBER 2012–REVISED OCTOBER 2014
8.3.4 Receiver Subsystem Power Path
The block diagram in Figure 65 shows the device Rx subsystem power routing.
Figure 65. Receive Subsystem Power Routing
8.3.5 Transmit Section
The transmit section integrates the LED driver and the LED current control section with 8-bit resolution. This
integration is designed to meet a dynamic range of better than 105 dB (based on a 1-sigma LED current noise).
The RED and IR LED reference currents can be independently set. The current source (ILED) locally regulates
and ensures that the actual LED current tracks the specified reference. The transmitter section uses a reference
voltage for operation. This reference voltage is available on the REF_TX pin and must be decoupled to ground
with a 2.2-μF capacitor. The TX_REF voltage is derived from the TX_CTRL_SUP. The maximum LED current
setting depends on the transmitter reference voltage. By default, after reset, this voltage is 0.75 V and supports
up to a 150-mA LED current. For higher LED currents up to 200 mA, the reference can be programmed to 1.0 V
(using the LED_RANGE[1:0] register bits).
The minimum LED_DRV_SUP voltage required for operation depends on the:
• Voltage drop across the LED (VLED),
• Voltage drop across the external cable, connector, and any other component in series with the LED (VCABLE),
and
• Transmitter reference voltage.
Using the default reference voltage of 0.75 V, the minimum LED_DRV_SUP voltage can be as low as 3.25 V,
provided that Equation 3 is met. Refer to the Recommended Operating Conditions table.
3.25 V – (VLED + VCABLE) > 1.4 V (3)
To lower the minimum LED_DRV_SUP voltage even further, the transmitter reference voltage can be
programmed to 0.5 V. By doing so, the minimum LED_DRV_SUP voltage can be reduced to 3.0 V, provided that
Equation 4 is met. Refer to the Recommended Operating Conditions table.
3.0 V – (VLED + VCABLE) > 1.4 V (4)
Note that with the 0.5-V transmitter reference voltage, the maximum LED current supported is 100 mA.
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LED
Current
Control
8-Bit Resolution
LED2 Current
Reference
LED1 Current
Reference
H-Bridge
Driver
H-Bridge
LED2_ON
LED1_ON
LED2_ON
or
LED1_ON
Register LED2 Current Reference
Register LED1 Current Reference
TX_CTRL_SUP
Tx
ILED
CBULK
LED_DRV_SUP
External
Supply
AFE4490
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Two LED driver schemes are supported:
• An H-bridge drive for a two-pin, back-to-back LED package, as shown in Figure 66.
• A push-pull drive for a three-pin, common-anode LED package; see Figure 67.
Figure 66. Transmit: H-Bridge Drive
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LED
Current
Control
8-Bit Resolution
LED2 Current
Reference
LED1 Current
Reference
H-Bridge
Driver
LED2_ON
LED1_ON
LED2_ON
or
LED1_ON
Register RED Current Reference
Register IR Current Reference
Tx
ILED
CBULK
External
Supply
TX_CTRL_SUP
LED_DRV_SUP
AFE4490
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Figure 67. Transmit: Push-Pull LED Drive for Common Anode LED Configuration
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50uA 0 mA to 200 mA
(See the LEDRANGE bits
in the LEDCNTRL register.)
LED_ON
1 PA
TX_CTRL_SUP
LED_DRV_SUP
Device
Tx LED
Bridge
LED
Current
Control
DAC
Tx Reference
and Control
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8.3.5.1 Transmitter Power Path
The block diagram in Figure 68 shows the device Tx subsystem power routing.
Figure 68. Transmit Subsystem Power Routing
8.3.5.2 LED Power Reduction During Periods of Inactivity
The diagram in Figure 69 shows how LED bias current passes 50 µA whenever LED_ON occurs. In order to
minimize power consumption in periods of inactivity, the LED_ON control must be turned off. Furthermore,
disable the TIMEREN bit in the CONTROL1 register by setting the value to '0'.
Note that depending on the LEDs used, the LED may sometimes appear dimly lit even when the LED current is
set to 0 mA. This appearance is because of the switching leakage currents (as shown in Figure 69) inherent to
the timer function. The dimmed appearance does not effect the ambient light level measurement because during
the ambient cycle, LED_ON is turned off for the duration of the ambient measurement.
Figure 69. LED Bias Current
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ADC Clock
ADC Convert
LED2 Data
ADC Output Rate
PRF Samples per Second
ADC
Ambient
(LED2) Data
LED1 Data
Ambient
(LED1) Data
Rx Digital
Averager
22-Bits Register
42 LED2 Data
Register
43 LED2_Ambient Data
Register
44 LED1 Data
Register
45 LED1_Ambient Data
ADC Reset
ADC Reset
ADC
AFE4490
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8.4 Device Functional Modes
8.4.1 ADC Operation and Averaging Module
After the falling edge of the ADC reset signal, the ADC conversion phase starts (refer to Figure 64). Each ADC
conversion takes 50 µs.
There are two modes of operation: without averaging and with averaging. The averaging mode can average
multiple ADC samples and reduce noise to improve dynamic range because the ADC conversion time is usually
shorter than 25% of the pulse repetition period. Figure 70 shows a diagram of the averaging module. The ADC
output format is in 22-bit twos complement. The two MSB bits of the 24-bit data can be ignored.
Figure 70. Averaging Module
8.4.1.1 Operation Without Averaging
In this mode, the ADC outputs a digital sample one time for every 50 µs. At the next rising edge of the ADC reset
signal, the first 22-bit conversion value is written into the result registers sequentially as follows (see Figure 71):
• At the 25% reset signal, the first 22-bit ADC sample is written to register 2Ah.
• At the 50% reset signal, the first 22-bit ADC sample is written to register 2Bh.
• At the 75% reset signal, the first 22-bit ADC sample is written to register 2Ch.
• At the next 0% reset signal, the first 22-bit ADC sample is written to register 2Dh. The contents of registers
2Ah and 2Bh are written to register 2Eh and the contents of registers 2Ch and 2Dh are written to register
2Fh.
At the rising edge of the ADC_RDY signal, the contents of all six result registers can be read out.
8.4.1.2 Operation With Averaging
In this mode, all ADC digital samples are accumulated and averaged after every 50 µs. At the next rising edge of
the ADC reset signal, the average value (22-bit) is written into the output registers sequentially as follows (see
Figure 72):
• At the 25% reset signal, the averaged 22-bit word is written to register 2Ah.
• At the 50% reset signal, the averaged 22-bit word is written to register 2Bh.
• At the 75% reset signal, the averaged 22-bit word is written to register 2Ch.
• At the next 0% reset signal, the averaged 22-bit word is written to register 2Dh. The contents of registers 2Ah
and 2Bh are written to register 2Eh and the contents of registers 2Ch and 2Dh are written to register 2Fh.
At the rising edge of the ADC_RDY signal, the contents of all six result registers can be read out.
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NUMAV[7:0] + 1 = 0.25 Pulse Repetition Period´
50 sm
-1
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Device Functional Modes (continued)
The number of samples to be used per conversion phase is specified in the CONTROL1 register (NUMAV[7:0]).
The user must specify the correct value for the number of averages, as described in Equation 5:
(5)
When the number of averages is '0', the averaging is disabled and only one ADC sample is written to the result
registers.
Note that he number of average conversions is limited by 25% of the PRF. For example, eight samples can be
averaged with PRF = 625 Hz, and four samples can be averaged with PRF = 1250 Hz.
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ADC Conversion
Pulse Repetition Period (PRP)
T = 1 / PRF
ADC Reset
ADC_RDY Pin
12 3 4 56 7 8 910 11 12 13 14 15 16
0% 25% 50% 75%
ADC Data
ADC Data 1 are
written into
register 42.
ADC Data 5 are
written into
register 43.
ADC Data 9 are
written into
register 44. ADC Data 13 are written into
register 45.
Register 42 register 43
are written into register 46.
Register 44 register 45
are written into register 47.
0%
17 18 19 20
0 T 1.0 T
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Device Functional Modes (continued)
Figure 71. ADC Data without Averaging (when Number of Averages = 0)
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ADC Conversion
Pulse Repetition Period
T = 1 / PRF
ADC Reset
ADC_RDY Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
0% 25% 50% 75%
ADC Data
Average of
ADC data 1 to 3 are
written into
register 42.
Average of
ADC data 5 to 7
are written into
register 43.
Average of
ADC data 9 to 11 are
written into
register 44.
Average of
ADC data 13 to 15 are written
into register 45.
Register 42 register 43
are written into register 46.
Register 44 register 45
are written into register 47.
0%
17 18 19 20
0 T 1.0 T
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Device Functional Modes (continued)
NOTE: Example is with three averages. The value of the NUMAVG[7:0] register bits = 2.
Figure 72. ADC Data with Averaging Enabled
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Clocking
Internal
ûADC
+
TIA
RXOUTP
+
Stage 2
Gain
RXOUTN
INP
INN
Device
External
ûADC
PD_ALM ADC_RDY
Use the ADC_Reset
signal on the PD_ALM pin
to clock the external ADC.
Use ADC_RDY to
sync the external
ADC with the AFE.
ûADC
+
TIA
RXOUTP
+
Stage 2
Gain
RXOUTN
INP
INN
Device
AFE4490
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Device Functional Modes (continued)
8.4.2 AFE Analog Output Mode (ADC Bypass Mode)
This mode is only intended for use in system debug. Note that this function is not recommended for production
use because of the minimal device production testing performed on this function.
The ADC bypass mode brings out the analog output voltage of the receiver front-end on two pins (RXOUTP,
RXOUTN), around a common-mode voltage of approximately 0.9 V. In this mode, the internal ADC of the
AFE4490 is disabled. Figure 73 shows a block diagram of this mode.
Figure 73. Device Set to ADC Bypass Mode
In ADC bypass mode, one of the internal clocks (ADC_Reset) can be brought out on the PD_ALM pin, as shown
in Figure 74. This signal can be used to convert each of the four phases (within every pulse repetition period).
Additionally, the ADC_RDY signal can be used to synchronize the external ADC with the AFE. See Figure 75 for
the timing of this mode.
Figure 74. Device in ADC Bypass Mode with ADC_Reset to PD_ALM Pin
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LED1 (IR LED)
On Signal
LED2 (RED LED)
On Signal
t0
ADC_RDY
(Pin 28)
Pulse Repetition Period (PRP),
One Cycle
ADC Reset
(Pin 23)
SLED2,
Sample LED2 (RED)
SLED2_amb,
Sample Ambient
LED2 (RED) Phase
SLED1,
Sample LED1 (IR)
SLED1_amb,
Sample Ambient
LED1 (IR) Phase
t29
t3t4
t10
t9
t5t6
t7t8
t11 t12
t2
t1
t21
t22
t23
t24
t25
t26
t27
t28
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Device Functional Modes (continued)
NOTE: RED = LED2, IR = LED1.
Figure 75. Device Analog Output Mode (ADC Bypass) Timing Diagram
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To Rx Front-End
INN
INP
Cable
10 k10 k
Rx On/Off
Rx On/Off
Legend for Cable
Internal
TX_CTRL_SUP
1 k
100 PA
100 PA
GND Wires
PD Wires
LED Wires
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Device Functional Modes (continued)
In ADC bypass mode, the ADC reset signal can be used to start conversions with the external ADC. Use
registers 15h through 1Ch to position the ADC reset signal edges appropriately. Also, use the CLKALMPIN[2:0]
bits on the PD_ALM pin register bit to bring out the ADC reset signal to the PD_ALM pin. ADC_RDY can be used
to indicate the start of the pulse repetition period to the external ADC.
8.4.3 Diagnostics
The device includes diagnostics to detect open or short conditions of the LED and photosensor, LED current
profile feedback, and cable on or off detection.
8.4.3.1 Photodiode-Side Fault Detection
Figure 76 shows the diagnostic for the photodiode-side fault detection.
Figure 76. Photodiode Diagnostic
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C
D
SW1SW4
SW3SW2
Cable TXP
TXN
10 k10 k
Legend for Cable
Internal
TX_CTRL_SUP
LED DAC
100 PA
100 PA
GND Wires
PD Wires
LED Wires
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Device Functional Modes (continued)
8.4.3.2 Transmitter-Side Fault Detection
Figure 77 shows the diagnostic for the transmitter-side fault detection.
Figure 77. Transmitter Diagnostic
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Diagnostic State Machine
tWIDTH = Four 4-MHz
Clock Cycles
Diagnostic State
Machine
DIAG_END Pin
DIAG_EN Register Bit = 1
Diagnostic Ends
tDIAG
Diagnostic Starts
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Device Functional Modes (continued)
8.4.3.3 Diagnostics Module
The diagnostics module, when enabled, checks for nine types of faults sequentially. The results of all faults are
latched in 11 separate flags. At the end of the sequence, the state of the 11 flags are combined to generate two
interrupt signals: PD_ALM for photodiode-related faults and LED_ALM for transmit-related faults. The status of all
flags can also be read using the SPI interface. Table 3 details each fault and flag used. Note that the diagnostics
module requires all AFE blocks to be enabled in order to function reliably.
Table 3. Fault and Flag Diagnostics(1)
MODULE SEQ. FAULT FLAG1 FLAG2 FLAG3 FLAG4 FLAG5 FLAG6 FLAG7 FLAG8 FLAG9 FLAG10 FLAG11
— — No fault 0 0 0 0 0 0 0 0 0 0 0
Rx INP cable
1 1
shorted to LED cable
Rx INN cable
2 1
shorted to LED cable
Rx INP cable
PD 3 shorted to GND 1
cable
Rx INN cable
4 shorted to GND 1
cable
5 PD open or shorted 1 1
Tx OUTM line
6 shorted to GND 1
cable
Tx OUTP line
LED 7 shorted to GND 1
cable
8 LED open or shorted 1 1
9 LED open or shorted 1
(1) Resistances below 10 kΩare considered to be shorted.
Figure 78 shows the timing for the diagnostic function.
Figure 78. Diagnostic Timing Diagram
By default, the diagnostic function takes tDIAG = 8 ms to complete after the DIAG_EN register bit is enabled. By
setting the EN_SLOW_DIAG register bit (CONTROL2 register, bit D8) the diagnostic time can be increased to
16 ms.
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A7 A6 A1 A0 D23 D22 D17 D16 D15 D14 D9 D8 D7 D6 D1 D0
SPISTE
SPISIMO
SCLK
'RQ¶WFDUH, can be high or low.
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After completion of the diagnostics function, time must be allowed for the device filter to settle. See the Electrical
Characteristics for the filter settling time. The slow diagnostics feature is provided for use in systems where high-
capacitance sensors (such as photodiodes, capacitors, cables, and so forth) are connected to the INP, INN, TXP,
or TXN pins.
8.5 Programming
8.5.1 Serial Programming Interface
The SPI-compatible serial interface consists of four signals: SCLK (serial clock), SPISOMI (serial interface data
output), SPISIMO (serial interface data input), and SPISTE (serial interface enable).
The serial clock (SCLK) is the serial peripheral interface (SPI) serial clock. SCLK shifts in commands and shifts
out data from the device. SCLK features a Schmitt-triggered input and clocks data out on SPISOMI. Data are
clocked in on the SPISIMO pin. Even though the input has hysteresis, TI recommends keeping SCLK as clean
as possible to prevent glitches from accidentally shifting the data. When the serial interface is idle, hold SCLK
low.
The SPISOMI (SPI serial out master in) pin is used with SCLK to clock out device data. The SPISIMO (SPI serial
in master out) pin is used with SCLK to clock in data to the device. The SPISTE (SPI serial interface enable) pin
enables the serial interface to clock data on the SPISIMO pin in to the device.
8.5.2 Reading and Writing Data
The device has a set of internal registers that can be accessed by the serial programming interface formed by
the SPISTE, SCLK, SPISIMO, and SPISOMI pins.
8.5.2.1 Writing Data
The SPI_READ register bit must be first set to '0' before writing to a register. When SPISTE is low,
• Serially shifting bits into the device is enabled.
• Serial data (on the SPISIMO pin) are latched at every SCLK rising edge.
• The serial data are loaded into the register at every 32nd SCLK rising edge.
In case the word length exceeds a multiple of 32 bits, the excess bits are ignored. Data can be loaded in
multiples of 32-bit words within a single active SPISTE pulse. The first eight bits form the register address and
the remaining 24 bits form the register data. Figure 79 shows an SPI timing diagram for a single write operation.
For multiple read and write cycles, refer to the Multiple Data Reads and Writes section.
Figure 79. AFE SPI Write Timing Diagram
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A7 A6 A1 A0
SPISTE
SPISIMO
SCLK
'RQ¶WFDUH, can be high or low.
D23 D22 D17 D16 D15 D14 D9 D8 D7 D6 D1 D0
SPISOMI
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Programming (continued)
8.5.2.2 Reading Data
The SPI_READ register bit must be first set to '1' before reading from a register. The device includes a mode
where the contents of the internal registers can be read back on the SPISOMI pin. This mode may be useful as a
diagnostic check to verify the serial interface communication between the external controller and the AFE. To
enable this mode, first set the SPI_READ register bit using the SPI write command, as described in the Writing
Data section. In the next command, specify the SPI register address with the desired content to be read. Within
the same SPI command sequence, the AFE outputs the contents of the specified register on the SPISOMI pin.
Figure 80 shows an SPI timing diagram for a single read operation. For multiple read and write cycles, refer to
the Multiple Data Reads and Writes section.
(1) The SPI_READ register bit must be enabled before attempting a serial readout from the AFE.
(2) Specify the register address of the content that must be readback on bits A[7:0].
(3) The AFE outputs the contents of the specified register on the SPISOMI pin.
Figure 80. AFE SPI Read Timing Diagram(1)(2)(3)
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A7 A0 D23 D16 D15 D8 D7 D0
SPISTE
SPISIMO
'RQ¶WFDUH, can be high or low
A7 A0
SCLK
D23 D16 D15 D8 D7 D0
SPISOMI
Operation First Write Second Write(1, 2) Read(3, 4)
A7 A0 D23 D16 D15 D8 D7 D0
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8.5.2.3 Multiple Data Reads and Writes
The device includes functionality where multiple read and write operations can be performed during a single SPISTE event. To enable this functionality,
the first eight bits determine the register address to be written and the remaining 24 bits determine the register data. Perform two writes with the SPI read
bit enabled during the second write operation in order to prepare for the read operation, as described in the Writing Data section. In the next command,
specify the SPI register address with the desired content to be read. Within the same SPI command sequence, the AFE outputs the contents of the
specified register on the SPISOMI pin. This functionality is described in the Writing Data and Reading Data sections. Figure 81 shows a timing diagram
for the SPI multiple read and write operations.
(1) The SPI read register bit must be enabled before attempting a serial readout from the AFE.
(2) The second write operation must be configured for register 0 with data 000001h.
(3) Specify the register address whose contents must be read back on A[7:0].
(4) The AFE outputs the contents of the specified register on the SOMI pin.
Figure 81. Serial Multiple Read and Write Operations
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8.5.2.4 Register Initialization
After power-up, the internal registers must be initialized to the default values. This initialization can be done in
one of two ways:
• Through a hardware reset by applying a low-going pulse on the RESET pin, or
• By applying a software reset. Using the serial interface, set SW_RESET (bit D3 in register 00h) high. This
setting initializes the internal registers to the default values and then self-resets to '0'. In this case, the RESET
pin is kept high (inactive).
8.5.2.5 AFE SPI Interface Design Considerations
Note that when the device is deselected, the SPISOMI, CLKOUT, ADC_RDY, PD_ALM, LED_ALM, and
DIAG_END digital output pins do not enter a 3-state mode. This condition, therefore, must be taken into account
when connecting multiple devices to the SPI port and for power-management considerations. In order to avoid
loading the SPI bus when multiple devices are connected, the DIGOUT_TRISTATE register bit must be to '1'
whenever the AFE SPI is inactive.
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8.6 Register Maps
The AFE consists of a set of registers that can be used to configure it, such as receiver timings, I-V amplifier settings, transmit LED currents, and so forth.
The registers and their contents are listed in Table 4. These registers can be accessed using the AFE SPI interface.
Table 4. AFE Register Map
ADDRESS REGISTER DATA
REGISTER
NAME CONTROL(1) Hex Dec D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CONTROL0 W 00000000000000000000000
SW_RST
DIAG_EN
SPI_READ
TIM_COUNT_RST
LED2STC R/W 01 1 0 0 0 0 0 0 0 0 LED2STC[15:0]
LED2ENDC R/W 02 2 0 0 0 0 0 0 0 0 LED2ENDC[15:0]
LED2LEDSTC R/W 03 3 0 0 0 0 0 0 0 0 LED2LEDSTC[15:0]
LED2LEDENDC R/W 04 4 0 0 0 0 0 0 0 0 LED2LEDENDC[15:0]
ALED2STC R/W 05 5 0 0 0 0 0 0 0 0 ALED2STC[15:0]
ALED2ENDC R/W 06 6 0 0 0 0 0 0 0 0 ALED2ENDC[15:0]
LED1STC R/W 07 7 0 0 0 0 0 0 0 0 LED1STC[15:0]
LED1ENDC R/W 08 8 0 0 0 0 0 0 0 0 LED1ENDC[15:0]
LED1LEDSTC R/W 09 9 0 0 0 0 0 0 0 0 LED1LEDSTC[15:0]
LED1LEDENDC R/W 0A 10 0 0 0 0 0 0 0 0 LED1LEDENDC[15:0]
ALED1STC R/W 0B 11 0 0 0 0 0 0 0 0 ALED1STC[15:0]
ALED1ENDC R/W 0C 12 0 0 0 0 0 0 0 0 ALED1ENDC[15:0]
LED2CONVST R/W 0D 13 0 0 0 0 0 0 0 0 LED2CONVST[15:0]
LED2CONVEND R/W 0E 14 0 0 0 0 0 0 0 0 LED2CONVEND[15:0]
ALED2CONVST R/W 0F 15 0 0 0 0 0 0 0 0 ALED2CONVST[15:0]
ALED2CONVEND R/W 10 16 0 0 0 0 0 0 0 0 ALED2CONVEND[15:0]
LED1CONVST R/W 11 17 0 0 0 0 0 0 0 0 LED1CONVST[15:0]
LED1CONVEND R/W 12 18 0 0 0 0 0 0 0 0 LED1CONVEND[15:0]
ALED1CONVST R/W 13 19 0 0 0 0 0 0 0 0 ALED1CONVST[15:0]
ALED1CONVEND R/W 14 20 0 0 0 0 0 0 0 0 ALED1CONVEND[15:0]
ADCRSTSTCT0 R/W 15 21 0 0 0 0 0 0 0 0 ADCRSTCT0[15:0]
ADCRSTENDCT0 R/W 16 22 0 0 0 0 0 0 0 0 ADCRENDCT0[15:0]
ADCRSTSTCT1 R/W 17 23 0 0 0 0 0 0 0 0 ADCRSTCT1[15:0]
ADCRSTENDCT1 R/W 18 24 0 0 0 0 0 0 0 0 ADCRENDCT1[15:0]
ADCRSTSTCT2 R/W 19 25 0 0 0 0 0 0 0 0 ADCRSTCT2[15:0]
ADCRSTENDCT2 R/W 1A 26 0 0 0 0 0 0 0 0 ADCRENDCT2[15:0]
ADCRSTSTCT3 R/W 1B 27 0 0 0 0 0 0 0 0 ADCRSTCT3[15:0]
ADCRSTENDCT3 R/W 1C 28 0 0 0 0 0 0 0 0 ADCRENDCT3[15:0]
(1) R = read only, R/W = read or write, N/A = not available, and W = write only.
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Register Maps (continued)
Table 4. AFE Register Map (continued)
ADDRESS REGISTER DATA
REGISTER
NAME CONTROL(1) Hex Dec D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PRPCOUNT R/W 1D 29 0 0 0 0 0 0 0 0 PRPCT[15:0]
CONTROL1 R/W 1E 30 0 0 0 0 0 0 0 0 0 0 0 0 CLKALMPIN[2:0] NUMAV[7:0]
TIMEREN
SPARE1 N/A 1F3100000000000000000000000 0
TIAGAIN R/W 20 32 0 0 0 0 0 0 0 0 0 0 0 STG2GAIN1[2:0] CF_LED1[4:0] RF_LED1[2:0]
ENSEPGAN
STAGE2EN1
TIA_AMB_GAIN R/W 21 33 0 0 0 0 AMBDAC[3:0] 0 0 0 STG2GAIN2[2:0] CF_LED2[4:0] RF_LED2[2:0]
STAGE2EN2
FLTRCNRSEL
LED
LEDCNTRL R/W 22 34 0 0 0 0 0 0 LED1[7:0] LED2[7:0]
RANGE[1:0]
CONTROL2 R/W 23 35 0 0 0 0 0 0 0 0 0 0 0 0 0
PDNTX
PDNRX
PDNAFE
XTALDIS
TX_REF1
TX_REF0
TXBRGMOD
EN_ADC_BYP
EN_SLOW_DIAG
DIGOUT_TRISTATE
RST_CLK_ON_PD_ALM
SPARE2 N/A 243600000000000000000000000 0
SPARE3 N/A 253700000000000000000000000 0
SPARE4 N/A 263800000000000000000000000 0
RESERVED1 N/A 2739XXXXXXXXXXXXXXXXXXXXXXX X
RESERVED2 N/A 2840XXXXXXXXXXXXXXXXXXXXXXX X
ALARM R/W 29410000000000000000 000000 0
ALMPINCLKEN
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Register Maps (continued)
Table 4. AFE Register Map (continued)
ADDRESS REGISTER DATA
REGISTER
NAME CONTROL(1) Hex Dec D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED2VAL R 2A 42 LED2VAL[23:0]
ALED2VAL R 2B 43 ALED2VAL[23:0]
LED1VAL R 2C 44 LED1VAL[23:0]
ALED1VAL R 2D 45 ALED1VAL[23:0]
LED2-ALED2VAL R 2E 46 LED2-ALED2VAL[23:0]
LED1-ALED1VAL R 2F 47 LED1-ALED1VAL[23:0]
DIAG R 30 48 0 0 0 0 0 0 0 0 0 0 0
PDOC
PDSC
LEDSC
PD_ALM
LED_ALM
INPSCLED
INNSCLED
INPSCGND
INNSCGND
LED1OPEN
LED2OPEN
OUTPSHGN
OUTNSHGND
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8.6.1 AFE Register Description
Figure 82. CONTROL0: Control Register 0 (Address = 00h, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
000000000000
W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
TIM_ SPI_
0 0 0 0 0 0 0 0 SW_RST DIAG_EN COUNT_ READ
RST
W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h
LEGEND: W = Write only; -n = value after reset
This register is write-only. CONTROL0 is used for AFE software and count timer reset, diagnostics enable, and
SPI read functions.
Bits D[23:4] Must be '0'
Bit D3 SW_RST: Software reset
0 = No action (default after reset)
1 = Software reset applied; resets all internal registers to the default values and self-clears
to '0'
Bit D2 DIAG_EN: Diagnostic enable
0 = No Action (default after reset)
1 = Diagnostic mode is enabled and the diagnostics sequence starts when this bit is set.
At the end of the sequence, all fault statuses are stored in the DIAG: Diagnostics Flag
Register. Afterwards, the DIAG_EN register bit self-clears to '0'.
Note that the diagnostics enable bit is automatically reset after the diagnostics completes
(slow =16 ms, fast = 8 ms). During diagnostics mode, the ADC data are invalid because of
toggling diagnostics switches.
Bit D1 TIM_CNT_RST: Timer counter reset
0 = Disables timer counter reset, required for normal timer operation (default after reset)
1 = Timer counters are in reset state
Bit D0 SPI READ: SPI read
0 = SPI read is disabled (default after reset)
1 = SPI read is enabled
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Figure 83. LED2STC: Sample LED2 Start Count Register (Address = 01h, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 LED2STC[15:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED2STC[15:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register sets the start timing value for the LED2 signal sample.
Bits D[23:16] Must be '0'
Bits D[15:0] LED2STC[15:0]: Sample LED2 start count
The contents of this register can be used to position the start of the sample LED2 signal with
respect to the pulse repetition period (PRP), as specified in the PRPCOUNT register. The
count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer
Module section for details.
Figure 84. LED2ENDC: Sample LED2 End Count Register (Address = 02h, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 LED2ENDC[15:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED2ENDC[15:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register sets the end timing value for the LED2 signal sample.
Bits D[23:16] Must be '0'
Bits D[15:0] LED2ENDC[15:0]: Sample LED2 end count
The contents of this register can be used to position the end of the sample LED2 signal with
respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the
number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 85. LED2LEDSTC: LED2 LED Start Count Register (Address = 03h, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 LED2LEDSTC[15:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED2LEDSTC[15:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register sets the start timing value for when the LED2 signal turns on.
Bits D[23:16] Must be '0'
Bits D[15:0] LED2LEDSTC[15:0]: LED2 start count
The contents of this register can be used to position the start of the LED2 with respect to the
PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-
MHz clock cycles. Refer to the Using the Timer Module section for details.
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Figure 86. LED2LEDENDC: LED2 LED End Count Register (Address = 04h, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 LED2LEDENDC[15:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED2LEDENDC[15:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register sets the end timing value for when the LED2 signal turns off.
Bits D[23:16] Must be '0'
Bits D[15:0] LED2LEDENDC[15:0]: LED2 end count
The contents of this register can be used to position the end of the LED2 signal with respect
to the PRP, as specified in the PRPCOUNT register. The count is specified as the number
of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 87. ALED2STC: Sample Ambient LED2 Start Count Register (Address = 05h, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 ALED2STC[15:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ALED2STC[15:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register sets the start timing value for the ambient LED2 signal sample.
Bits D[23:16] Must be '0'
Bits D[15:0] ALED2STC[15:0]: Sample ambient LED2 start count
The contents of this register can be used to position the start of the sample ambient LED2
signal with respect to the PRP, as specified in the PRPCOUNT register. The count is
specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section
for details.
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Figure 88. ALED2ENDC: Sample Ambient LED2 End Count Register
(Address = 06h, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 ALED2ENDC[15:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ALED2ENDC[15:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register sets the end timing value for the ambient LED2 signal sample.
Bits D[23:16] Must be '0'
Bits D[15:0] ALED2ENDC[15:0]: Sample ambient LED2 end count
The contents of this register can be used to position the end of the sample ambient LED2
signal with respect to the PRP, as specified in the PRPCOUNT register. The count is
specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section
for details.
Figure 89. LED1STC: Sample LED1 Start Count Register (Address = 07h, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 LED1STC[15:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED1STC[15:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register sets the start timing value for the LED1 signal sample.
Bits D[23:17] Must be '0'
Bits D[16:0] LED1STC[15:0]: Sample LED1 start count
The contents of this register can be used to position the start of the sample LED1 signal with
respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the
number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
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Figure 90. LED1ENDC: Sample LED1 End Count (Address = 08h, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 LED1ENDC[15:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED1ENDC[15:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register sets the end timing value for the LED1 signal sample.
Bits D[23:17] Must be '0'
Bits D[16:0] LED1ENDC[15:0]: Sample LED1 end count
The contents of this register can be used to position the end of the sample LED1 signal with
respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the
number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 91. LED1LEDSTC: LED1 LED Start Count Register (Address = 09h, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 LED1LEDSTC[15:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED1LEDSTC[15:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register sets the start timing value for when the LED1 signal turns on.
Bits D[23:16] Must be '0'
Bits D[15:0] LED1LEDSTC[15:0]: LED1 start count
The contents of this register can be used to position the start of the LED1 signal with respect
to the PRP, as specified in the PRPCOUNT register. The count is specified as the number
of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 92. LED1LEDENDC: LED1 LED End Count Register (Address = 0Ah, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 LED1LEDENDC[15:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED1LEDENDC[15:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register sets the end timing value for when the LED1 signal turns off.
Bits D[23:16] Must be '0'
Bits D[15:0] LED1LEDENDC[15:0]: LED1 end count
The contents of this register can be used to position the end of the LED1 signal with respect
to the PRP, as specified in the PRPCOUNT register. The count is specified as the number
of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
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Figure 93. ALED1STC: Sample Ambient LED1 Start Count Register (Address = 0Bh, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 ALED1STC[15:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ALED1STC[15:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register sets the start timing value for the ambient LED1 signal sample.
Bits D[23:16] Must be '0'
Bits D[15:0] ALED1STC[15:0]: Sample ambient LED1 start count
The contents of this register can be used to position the start of the sample ambient LED1
signal with respect to the PRP, as specified in the PRPCOUNT register. The count is
specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section
for details.
Figure 94. ALED1ENDC: Sample Ambient LED1 End Count Register
(Address = 0Ch, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 ALED1ENDC[15:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ALED1ENDC[15:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register sets the end timing value for the ambient LED1 signal sample.
Bits D[23:16] Must be '0'
Bits D[15:0] ALED1ENDC[15:0]: Sample ambient LED1 end count
The contents of this register can be used to position the end of the sample ambient LED1
signal with respect to the PRP, as specified in the PRPCOUNT register. The count is
specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section
for details.
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Figure 95. LED2CONVST: LED2 Convert Start Count Register (Address = 0Dh, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 LED2CONVST[15:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED2CONVST[15:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register sets the start timing value for the LED2 conversion.
Bits D[23:16] Must be '0'
Bits D[15:0] LED2CONVST[15:0]: LED2 convert start count
The contents of this register can be used to position the start of the LED2 conversion signal
with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as
the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 96. LED2CONVEND: LED2 Convert End Count Register (Address = 0Eh, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 LED2CONVEND[15:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED2CONVEND[15:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register sets the end timing value for the LED2 conversion.
Bits D[23:16] Must be '0'
Bits D[15:0] LED2CONVEND[15:0]: LED2 convert end count
The contents of this register can be used to position the end of the LED2 conversion signal
with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as
the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
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Figure 97. ALED2CONVST: LED2 Ambient Convert Start Count Register
(Address = 0Fh, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 ALED2CONVST[15:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ALED2CONVST[15:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register sets the start timing value for the ambient LED2 conversion.
Bits D[23:16] Must be '0'
Bits D[15:0] ALED2CONVST[15:0]: LED2 ambient convert start count
The contents of this register can be used to position the start of the LED2 ambient
conversion signal with respect to the PRP, as specified in the PRPCOUNT register. The
count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer
Module section for details.
Figure 98. ALED2CONVEND: LED2 Ambient Convert End Count Register
(Address = 10h, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 ALED2CONVEND[15:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ALED2CONVEND[15:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register sets the end timing value for the ambient LED2 conversion.
Bits D[23:16] Must be '0'
Bits D[15:0] ALED2CONVEND[15:0]: LED2 ambient convert end count
The contents of this register can be used to position the end of the LED2 ambient
conversion signal with respect to the PRP. The count is specified as the number of 4-MHz
clock cycles. Refer to the Using the Timer Module section for details.
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Figure 99. LED1CONVST: LED1 Convert Start Count Register (Address = 11h, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 LED1CONVST[15:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED1CONVST[15:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register sets the start timing value for the LED1 conversion.
Bits D[23:16] Must be '0'
Bits D[15:0] LED1CONVST[15:0]: LED1 convert start count
The contents of this register can be used to position the start of the LED1 conversion signal
with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as
the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 100. LED1CONVEND: LED1 Convert End Count Register (Address = 12h, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 LED1CONVEND[15:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED1CONVEND[15:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register sets the end timing value for the LED1 conversion.
Bits D[23:16] Must be '0'
Bits D[15:0] LED1CONVEND[15:0]: LED1 convert end count
The contents of this register can be used to position the end of the LED1 conversion signal
with respect to the PRP. The count is specified as the number of 4-MHz clock cycles. Refer
to the Using the Timer Module section for details.
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Figure 101. ALED1CONVST: LED1 Ambient Convert Start Count Register
(Address = 13h, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 ALED1CONVST[15:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ALED1CONVST[15:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register sets the start timing value for the ambient LED1 conversion.
Bits D[23:16] Must be '0'
Bits D[15:0] ALED1CONVST[15:0]: LED1 ambient convert start count
The contents of this register can be used to position the start of the LED1 ambient
conversion signal with respect to the PRP, as specified in the PRPCOUNT register. The
count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer
Module section for details.
Figure 102. ALED1CONVEND: LED1 Ambient Convert End Count Register
(Address = 14h, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 ALED1CONVEND[15:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ALED1CONVEND[15:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register sets the end timing value for the ambient LED1 conversion.
Bits D[23:16] Must be '0'
Bits D[15:0] ALED1CONVEND[15:0]: LED1 ambient convert end count
The contents of this register can be used to position the end of the LED1 ambient
conversion signal with respect to the PRP. The count is specified as the number of 4-MHz
clock cycles. Refer to the Using the Timer Module section for details.
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Figure 103. ADCRSTSTCT0: ADC Reset 0 Start Count Register (Address = 15h, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 ADCRSTSTCT0[15:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ADCRSTSTCT0[15:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register sets the start position of the ADC0 reset conversion signal.
Bits D[23:16] Must be '0'
Bits D[15:0] ADCRSTSTCT0[15:0]: ADC RESET 0 start count
The contents of this register can be used to position the start of the ADC reset conversion
signal (default value after reset is 0000h). Refer to the Using the Timer Module section for
details.
Figure 104. ADCRSTENDCT0: ADC Reset 0 End Count Register (Address = 16h, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 ADCRSTENDCT0[15:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ADCRSTENDCT0[15:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register sets the end position of the ADC0 reset conversion signal.
Bits D[23:16] Must be '0'
Bits D[15:0] ADCRSTENDCT0[15:0]: ADC RESET 0 end count
The contents of this register can be used to position the end of the ADC reset conversion
signal (default value after reset is 0000h). Refer to the Using the Timer Module section for
details.
Figure 105. ADCRSTSTCT1: ADC Reset 1 Start Count Register (Address = 17h, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 ADCRSTSTCT1[15:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ADCRSTSTCT1[15:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register sets the start position of the ADC1 reset conversion signal.
Bits D[23:16] Must be '0'
Bits D[15:0] ADCRSTSTCT1[15:0]: ADC RESET 1 start count
The contents of this register can be used to position the start of the ADC reset conversion.
Refer to the Using the Timer Module section for details.
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Figure 106. ADCRSTENDCT1: ADC Reset 1 End Count Register (Address = 18h, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 ADCRSTENDCT1[15:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ADCRSTENDCT1[15:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register sets the end position of the ADC1 reset conversion signal.
Bits D[23:16] Must be '0'
Bits D[15:0] ADCRSTENDCT1[15:0]: ADC RESET 1 end count
The contents of this register can be used to position the end of the ADC reset conversion.
Refer to the Using the Timer Module section for details.
Figure 107. ADCRSTSTCT2: ADC Reset 2 Start Count Register (Address = 19h, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 ADCRSTSTCT2[15:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ADCRSTSTCT2[15:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register sets the start position of the ADC2 reset conversion signal.
Bits D[23:16] Must be '0'
Bits D[15:0] ADCRSTSTCT2[15:0]: ADC RESET 2 start count
The contents of this register can be used to position the start of the ADC reset conversion.
Refer to the Using the Timer Module section for details.
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Figure 108. ADCRSTENDCT2: ADC Reset 2 End Count Register (Address = 1Ah, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 ADCRSTENDCT2[15:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ADCRSTENDCT2[15:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register sets the end position of the ADC2 reset conversion signal.
Bits D[23:16] Must be '0'
Bits D[15:0] ADCRSTENDCT2[15:0]: ADC RESET 2 end count
The contents of this register can be used to position the end of the ADC reset conversion.
Refer to the Using the Timer Module section for details.
Figure 109. ADCRSTSTCT3: ADC Reset 3 Start Count Register (Address = 1Bh, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 ADCRSTSTCT3[15:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ADCRSTSTCT3[15:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register sets the start position of the ADC3 reset conversion signal.
Bits D[23:16] Must be '0'
Bits D[15:0] ADCRSTSTCT3[15:0]: ADC RESET 3 start count
The contents of this register can be used to position the start of the ADC reset conversion.
Refer to the Using the Timer Module section for details.
Figure 110. ADCRSTENDCT3: ADC Reset 3 End Count Register (Address = 1Ch, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 ADCRSTENDCT3[15:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ADCRSTENDCT3[15:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register sets the end position of the ADC3 reset conversion signal.
Bits D[23:16] Must be '0'
Bits D[15:0] ADCRSTENDCT3[15:0]: ADC RESET 3 end count
The contents of this register can be used to position the end of the ADC reset conversion
signal (default value after reset is 0000h). Refer to the Using the Timer Module section for
details.
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Figure 111. PRPCOUNT: Pulse Repetition Period Count Register (Address = 1Dh, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 PRPCOUNT[15:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PRPCOUNT[15:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register sets the device pulse repetition period count.
Bits D[23:16] Must be '0'
Bits D[15:0] PRPCOUNT[15:0]: Pulse repetition period count
The contents of this register can be used to set the pulse repetition period (in number of
clock cycles of the 4-MHz clock). The PRPCOUNT value must be set in the range of 800 to
64000. Values below 800 do not allow sufficient sample time for the four samples; see the
Electrical Characteristics table.
Figure 112. CONTROL1: Control Register 1 (Address = 1Eh, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
000000000000
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CLKALMPIN[2:0] TIMEREN NUMAV[7:0]
R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register configures the clock alarm pin, timer, and number of averages.
Bits D[23:12] Must be '0'
Bits D[11:9] CLKALMPIN[2:0]: Clocks on ALM pins
Internal clocks can be brought to the PD_ALM and LED_ALM pins for monitoring.
Note that the ALMPINCLKEN register bit must be set before using this register bit. Table 5
defines the settings for the two alarm pins.
Bit D8 TIMEREN: Timer enable
0 = Timer module is disabled and all internal clocks are off (default after reset)
1 = Timer module is enabled
Bits D[7:0] NUMAV[7:0]: Number of averages
Specify an 8-bit value corresponding to the number of ADC samples to be averaged – 1.
For example, to average four ADC samples, set NUMAV[7:0] equal to 3.
The maximum number of averages is 16. Any NUMAV[7:0] setting greater than or equal to a
decimal value of 15 results in the number of averages being set to 16.
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Table 5. PD_ALM and LED_ALM Pin Settings
CLKALMPIN[2:0] PD_ALM PIN SIGNAL LED_ALM PIN SIGNAL
000 Sample LED2 pulse Sample LED1 pulse
001 LED2 LED pulse LED1 LED pulse
010 Sample LED2 ambient pulse Sample LED1 ambient pulse
011 LED2 convert LED1 convert
100 LED2 ambient convert LED1 ambient convert
101 No output No output
110 No output No output
111 No output No output
Figure 113. SPARE1: SPARE1 Register For Future Use (Address = 1Fh, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
000000000000
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
000000000000
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register is a spare register and is reserved for future use.
Bits D[23:0] Must be '0'
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Figure 114. TIAGAIN: Transimpedance Amplifier Gain Setting Register
(Address = 20h, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
ENSEP STAGE2
00000000 00
GAIN EN1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 STG2GAIN1[2:0] CF_LED1[4:0] RF_LED1[2:0]
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register sets the device transimpedance amplifier gain mode and feedback resistor and capacitor values.
Bits D[23:16] Must be '0'
Bit D15 ENSEPGAIN: Enable separate gain mode
0 = The RF, CFvalues and stage 2 gain settings are the same for both the LED2 and LED1
signals; the values are specified by the RF_LED2, CF_LED2, STAGE2EN2, and
STG2GAIN2 bits in the TIA_AMB_GAIN register (default after reset)
1 = The RF, CFvalues and stage 2 gain settings can be independently set for the LED2 and
LED1 signals. The values for LED1 are specified using the RF_LED1, CF_LED1,
STAGE2EN1, and STG2GAIN1 bits in the TIAGAIN register, whereas the values for LED2
are specified using the corresponding bits in the TIA_AMB_GAIN register.
Bit D14 STAGE2EN1: Enable Stage 2 for LED 1
0 = Stage 2 is bypassed (default after reset)
1 = Stage 2 is enabled with the gain value specified by the STG2GAIN1[2:0] bits
Bits D[13:11] Must be '0'
Bits D[10:8] STG2GAIN1[2:0]: Program Stage 2 gain for LED1
000 = 0 dB, or linear gain of 1 (default after 100 = 12 dB, or linear gain of 4
reset) 101 = Do not use
001 = 3.5 dB, or linear gain of 1.5 110 = Do not use
010 = 6 dB, or linear gain of 2 111 = Do not use
011 = 9.5 dB, or linear gain of 3
Bits D[7:3] CF_LED1[4:0]: Program CFfor LED1
00000 = 5 pF (default after reset) 00100 = 25 pF + 5 pF
00001 = 5 pF + 5 pF 01000 = 50 pF + 5 pF
00010 = 15 pF + 5 pF 10000 = 150 pF + 5 pF
Note that any combination of these CFsettings is also supported by setting multiple bits to
'1'. For example, to obtain CF= 100 pF, set D[7:3] = 01111.
Bits D[2:0] RF_LED1[2:0]: Program RFfor LED1
000 = 500 kΩ(default after reset) 100 = 25 kΩ
001 = 250 kΩ101 = 10 kΩ
010 = 100 kΩ110 = 1 MΩ
011 = 50 kΩ111 = None
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Figure 115. TIA_AMB_GAIN: Transimpedance Amplifier and Ambient Cancellation Stage Gain Register
(Address = 21h, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
FLTR STAGE2
0 0 0 0 AMBDAC[3:0] 0 0
CNRSEL EN2
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 STG2GAIN2[2:0] CF_LED2[4:0] RF_LED2[2:0]
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register configures the ambient light cancellation amplifier gain, cancellation current, and filter corner
frequency.
Bits D[23:20] Must be '0'
Bits D[19:16] AMBDAC[3:0]: Ambient DAC value
These bits set the value of the cancellation current.
0000 = 0 µA (default after reset) 1000 = 8 µA
0001 = 1 µA 1001 = 9 µA
0010 = 2 µA 1010 = 10 µA
0011 = 3 µA 1011 = Do not use
0100 = 4 µA 1100 = Do not use
0101 = 5 µA 1101 = Do not use
0110 = 6 µA 1110 = Do not use
0111 = 7 µA 1111 = Do not use
Bit D15 FLTRCNRSEL: Filter corner selection
0 = 500-Hz filter corner (default after reset)
1 = 1000-Hz filter corner
Bit D14 STAGE2EN2: Stage 2 enable for LED 2
0 = Stage 2 is bypassed (default after reset)
1 = Stage 2 is enabled with the gain value specified by the STG2GAIN2[2:0] bits
Bits D[13:11] Must be '0'
Bits D[10:8] STG2GAIN2[2:0]: Stage 2 gain setting for LED 2
000 = 0 dB, or linear gain of 1 (default after 100 = 12 dB, or linear gain of 4
reset) 101 = Do not use
001 = 3.5 dB, or linear gain of 1.5 110 = Do not use
010 = 6 dB, or linear gain of 2 111 = Do not use
011 = 9.5 dB, or linear gain of 3
Bits D[7:3] CF_LED2[4:0]: Program CFfor LED2
00000 = 5 pF (default after reset) 00100 = 25 pF + 5 pF
00001 = 5 pF + 5 pF 01000 = 50 pF + 5 pF
00010 = 15 pF + 5 pF 10000 = 150 pF + 5 pF
Note that any combination of these CFsettings is also supported by setting multiple bits to
'1'. For example, to obtain CF= 100 pF, set D[7:3] = 01111.
Bits D[2:0] RF_LED2[2:0]: Program RFfor LED2
000 = 500 kΩ100 = 25 kΩ
001 = 250 kΩ101 = 10 kΩ
010 = 100 kΩ110 = 1 MΩ
011 = 50 kΩ111 = None
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Figure 116. LEDCNTRL: LED Control Register (Address = 22h, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 LED_RANGE[1:0] LED1[7:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED1[7:0] LED2[7:0]
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register sets the LED current range and the LED1 and LED2 drive current.
Bits D[23:18] Must be '0'
Bits D[17:16] LED_RANGE[1:0]: LED range
These bits program the full-scale LED current range for Tx. Table 6 details the settings.
Bits D[15:8] LED1[7:0]: Program LED current for LED1 signal
Use these register bits to specify the LED current setting for LED1 (default after reset is
00h).
The nominal value of the LED current is given by Equation 6,
where the full-scale LED current is either 0 mA, 50 mA, 75 mA, 100 mA, 150 mA, or 200 mA
(as specified by the LED_RANGE[1:0] register bits).
Bits D[7:0] LED2[7:0]: Program LED current for LED2 signal
Use these register bits to specify the LED current setting for LED2 (default after reset is
00h).
The nominal value of LED current is given by Equation 7,
where the full-scale LED current is either 0 mA, 50 mA, 75 mA, 100 mA, 150 mA, or 200 mA
(as specified by the LED_RANGE[1:0] register bits).
Table 6. Full-Scale LED Current across Tx Reference Voltage Settings(1)
0.75 V (TX_REF[1:0] = 00) 0.5 V (TX_REF[1:0] = 01) 1.0 V (TX_REF[1:0] = 10)
LED_RANGE[1:0] IMAX VHR IMAX VHR IMAX VHR
00 (default after reset) 150 mA 1.4 V 100 mA 1.1 V 200 mA 1.7 V
01 75 mA 1.3 V 50 mA 1.0 V 100 mA 1.6 V
10 150 mA 1.4 V 100 mA 1.1 V 200 mA 1.7 V
11 Tx is off — Tx is off — Tx is off —
(1) For a 3-V to 3.6-V supply, use TX_REF = 0.5 V. For a 4.75-V to 5.25-V supply, use TX_REF = 0.75 V or 1.0 V.
(6)
(7)
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Figure 117. CONTROL2: Control Register 2 (Address = 23h, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
RST_
CLK_ON EN_ADC
0 0 0 0 0 TX_REF1 TX_REF0 0 0 0
_PD_ _BYP
ALM
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DIGOUT_ EN_
TXBRG XTAL
TRI SLOW_ 0 0 0 0 0 PDNTX PDNRX PDNAFE
MOD DIS
STATE DIAG
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register controls the LED transmitter, crystal, and the AFE, transmitter, and receiver power modes.
Bits D[23:19] Must be '0'
Bits D[18:17] TX_REF[1:0]: Tx reference voltage
These bits set the transmitter reference voltage. This Tx reference voltage is available on
the device TX_REF pin.
00 = 0.75-V Tx reference voltage (default value after reset)
01 = 0.5-V Tx reference voltage
10 = 1.0-V Tx reference voltage
11 = 0.75-V Tx reference voltage
NOTE: For best results, use TX_REF = 0.5 V for 3-V operation. Use TX_REF = 0.75V and
TX_REF = 1.0 V for 5-V operation.
Bit D16 RST_CLK_ON_PD_ALM: Reset clock onto PD_ALM pin
0 = Normal mode; no reset clock signal is connected to the PD_ALM pin
1 = Reset clock signal is connected to the PD_ALM pin
Bit D15 EN_ADC_BYP: ADC bypass mode enable
0 = Normal mode, the internal ADC is active (default after reset)
1 = ADC bypass mode, the analog signal is output to the ADC_BYPP and ADC_BYPN pins
Bits D[14:12] Must be '0'
Bit D11 TXBRGMOD: Tx bridge mode
0 = LED driver is configured as an H-bridge (default after reset)
1 = LED driver is configured as a push-pull
Bit D10 DIGOUT_TRISTATE: Digital output 3-state mode
This bit determines the state of the device digital output pins, including the clock output pin
and SPI output pins. In order to avoid loading the SPI bus when multiple devices are
connected, this bit must be set to '1' (3-state mode) whenever the device SPI is inactive.
0 = Normal operation (default)
1 = 3-state mode
Bit D9 XTALDIS: Crystal disable mode
0 = The crystal module is enabled; the 8-MHz crystal must be connected to the XIN and
XOUT pins
1 = The crystal module is disabled; an external 8-MHz clock must be applied to the XIN pin
Bit D8 EN_SLOW_DIAG: Fast diagnostics mode enable
0 = Fast diagnostics mode, 8 ms (default value after reset)
1 = Slow diagnostics mode, 16 ms
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Bits D[7:3] Must be '0'
Bit D2 PDN_TX: Tx power-down
0 = The Tx is powered up (default after reset)
1 = Only the Tx module is powered down
Bit D1 PDN_RX: Rx power-down
0 = The Rx is powered up (default after reset)
1 = Only the Rx module is powered down
Bit D0 PDN_AFE: AFE power-down
0 = The AFE is powered up (default after reset)
1 = The entire AFE is powered down (including the Tx, Rx, and diagnostics blocks)
Figure 118. SPARE2: SPARE2 Register For Future Use (Address = 24h, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
000000000000
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
000000000000
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register is a spare register and is reserved for future use.
Bits D[23:0] Must be '0'
Figure 119. SPARE3: SPARE3 Register For Future Use (Address = 25h, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
000000000000
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
000000000000
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register is a spare register and is reserved for future use.
Bits D[23:0] Must be '0'
Figure 120. SPARE4: SPARE4 Register For Future Use (Address = 26h, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
000000000000
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
000000000000
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
This register is a spare register and is reserved for future use.
Bits D[23:0] Must be '0'
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Figure 121. RESERVED1: RESERVED1 Register For Factory Use Only
(Address = 27h, Reset Value = XXXXh)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
X(1) XXXXXXXXXXX
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
XXXXXXXXXXXX
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
LEGEND: R = Read only; -n = value after reset
(1) X = don't care.
This register is reserved for factory use. Readback values vary between devices.
Bits D[23:0] Must be '0'
Figure 122. RESERVED2: RESERVED2 Register For Factory Use Only
(Address = 28h, Reset Value = XXXXh)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
X(1) XXXXXXXXXXX
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
XXXXXXXXXXXX
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
LEGEND: R = Read only; -n = value after reset
(1) X = don't care.
This register is reserved for factory use. Readback values vary between devices.
Bits D[23:0] Must be '0'
Figure 123. ALARM: Alarm Register (Address = 29h, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
000000000000
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ALMPIN
0000 0000000
CLKEN
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
LEGEND: R = Read only; -n = value after reset
This register controls the Alarm pin functionality.
Bits D[23:8] Must be '0'
Bit D7 ALMPINCLKEN: Alarm pin clock enable
0 = Disables the monitoring of internal clocks; the PD_ALM and LED_ALM pins function as
diagnostic fault alarm output pins (default after reset)
1 = Enables the monitoring of internal clocks; these clocks can be brought out on PD_ALM
and LED_ALM selectively (depending on the value of the CLKALMPIN[2:0] register bits).
Bits D[6:0] Must be '0'
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Figure 124. LED2VAL: LED2 Digital Sample Value Register (Address = 2Ah, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
LED2VAL[23:0]
R-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED2VAL[23:0]
R-0h
LEGEND: R = Read only; -n = value after reset
This register contains the digital value of the latest LED2 sample converted by the ADC. The ADC_RDY signal
goes high each time that the contents of this register are updated. The host processor must readout this register
before the next sample is converted by the AFE.
Bits D[23:0] LED2VAL[23:0]: LED2 digital value
This register contains the digital value of the latest LED2 sample converted by the ADC. The
ADC_RDY signal goes high each time that the contents of this register are updated. The
host processor must readout this register before the next sample is converted by the AFE.
Figure 125. ALED2VAL: Ambient LED2 Digital Sample Value Register
(Address = 2Bh, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
ALED2VAL[23:0]
R-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ALED2VAL[23:0]
R-0h
LEGEND: R = Read only; -n = value after reset
This register contains the digital value of the latest LED2 ambient sample converted by the ADC. The ADC_RDY
signal goes high each time that the contents of this register are updated. The host processor must readout this
register before the next sample is converted by the AFE.
Bits D[23:0] ALED2VAL[23:0]: LED2 ambient digital value
This register contains the digital value of the latest LED2 ambient sample converted by the
ADC. The ADC_RDY signal goes high each time that the contents of this register are
updated. The host processor must readout this register before the next sample is converted
by the AFE.
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Figure 126. LED1VAL: LED1 Digital Sample Value Register (Address = 2Ch, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
LED1VAL[23:0]
R-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED1VAL[23:0]
R-0h
LEGEND: R = Read only; -n = value after reset
This register contains the digital value of the latest LED1 sample converted by the ADC. The ADC_RDY signal
goes high each time that the contents of this register are updated. The host processor must readout this register
before the next sample is converted by the AFE.
Bits D[23:0] LED1VAL[23:0]: LED1 digital value
This register contains the digital value of the latest LED1 sample converted by the ADC. The
ADC_RDY signal goes high each time that the contents of this register are updated. The
host processor must readout this register before the next sample is converted by the AFE.
Figure 127. ALED1VAL: Ambient LED1 Digital Sample Value Register
(Address = 2Dh, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
ALED1VAL[23:0]
R-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ALED1VAL[23:0]
R-0h
LEGEND: R = Read only; -n = value after reset
This register contains the digital value of the latest LED1 ambient sample converted by the ADC. The ADC_RDY
signal goes high each time that the contents of this register are updated. The host processor must readout this
register before the next sample is converted by the AFE.
Bits D[23:0] ALED1VAL[23:0]: LED1 ambient digital value
This register contains the digital value of the latest LED1 ambient sample converted by the
ADC. The ADC_RDY signal goes high each time that the contents of this register are
updated. The host processor must readout this register before the next sample is converted
by the AFE.
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Figure 128. LED2-ALED2VAL: LED2-Ambient LED2 Digital Sample Value Register
(Address = 2Eh, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
LED2-ALED2VAL[23:0]
R-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED2-ALED2VAL[23:0]
R-0h
LEGEND: R = Read only; -n = value after reset
This register contains the digital value of the LED2 sample after the LED2 ambient is subtracted. The host
processor must readout this register before the next sample is converted by the AFE.
Bits D[23:0] LED2-ALED2VAL[23:0]: (LED2 – LED2 ambient) digital value
This register contains the digital value of the LED2 sample after the LED2 ambient is
subtracted. The host processor must readout this register before the next sample is
converted by the AFE.
Note that this value is inverted when compared to waveforms shown in many publications.
Figure 129. LED1-ALED1VAL: LED1-Ambient LED1 Digital Sample Value Register
(Address = 2Fh, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
LED1-ALED1VAL[23:0]
R-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED1-ALED1VAL[23:0]
R-0h
LEGEND: R = Read only; -n = value after reset
This register contains the digital value of the LED1 sample after the LED1 ambient is subtracted. The host
processor must readout this register before the next sample is converted by the AFE.
Bits D[23:0] LED1-ALED1VAL[23:0]: (LED1 – LED1 ambient) digital value
This register contains the digital value of the LED1 sample after the LED1 ambient is
subtracted from it. The host processor must readout this register before the next sample is
converted by the AFE.
Note that this value is inverted when compared to waveforms shown in many publications.
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AFE4490
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SBAS602H –DECEMBER 2012–REVISED OCTOBER 2014
Figure 130. DIAG: Diagnostics Flag Register (Address = 30h, Reset Value = 0000h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
00000000000PD_ALM
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED_ LED1 LED2 OUTPSH OUTNSH INNSC INPSC INNSC INPSC
LEDSC PDOC PDSC
ALM OPEN OPEN GND GND GND GND LED LED
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
LEGEND: R = Read only; -n = value after reset
This register is read only. This register contains the status of all diagnostic flags at the end of the diagnostics
sequence. The end of the diagnostics sequence is indicated by the signal going high on DIAG_END pin.
Bits D[23:13] Read only
Bit D12 PD_ALM: Power-down alarm status diagnostic flag
This bit indicates the status of PD_ALM (and the PD_ALM pin).
0 = No fault (default after reset)
1 = Fault present
Bit D11 LED_ALM: LED alarm status diagnostic flag
This bit indicates the status of LED_ALM (and the LED_ALM pin).
0 = No fault (default after reset)
1 = Fault present
Bit D10 LED1OPEN: LED1 open diagnostic flag
This bit indicates that LED1 is open.
0 = No fault (default after reset)
1 = Fault present
Bit D9 LED2OPEN: LED2 open diagnostic flag
This bit indicates that LED2 is open.
0 = No fault (default after reset)
1 = Fault present
Bit D8 LEDSC: LED short diagnostic flag
This bit indicates an LED short.
0 = No fault (default after reset)
1 = Fault present
Bit D7 OUTPSHGND: OUTP to GND diagnostic flag
This bit indicates that OUTP is shorted to the GND cable.
0 = No fault (default after reset)
1 = Fault present
Bit D6 OUTNSHGND: OUTN to GND diagnostic flag
This bit indicates that OUTN is shorted to the GND cable.
0 = No fault (default after reset)
1 = Fault present
Bit D5 PDOC: PD open diagnostic flag
This bit indicates that PD is open.
0 = No fault (default after reset)
1 = Fault present
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Bit D4 PDSC: PD short diagnostic flag
This bit indicates a PD short.
0 = No fault (default after reset)
1 = Fault present
Bit D3 INNSCGND: INN to GND diagnostic flag
This bit indicates a short from the INN pin to the GND cable.
0 = No fault (default after reset)
1 = Fault present
Bit D2 INPSCGND: INP to GND diagnostic flag
This bit indicates a short from the INP pin to the GND cable.
0 = No fault (default after reset)
1 = Fault present
Bit D1 INNSCLED: INN to LED diagnostic flag
This bit indicates a short from the INN pin to the LED cable.
0 = No fault (default after reset)
1 = Fault present
Bit D0 INPSCLED: INP to LED diagnostic flag
This bit indicates a short from the INP pin to the LED cable.
0 = No fault (default after reset)
1 = Fault present
84 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: AFE4490
TP25
TP22
AFE_PDNZ AFE_PDNZ
11
12
13
14
15
16
17
18
19
20
41
LED_DRV_SUPTX_CTRL_SUP
0.1 µF
C16
1 Fµ
C15
2.2 Fµ
C41
2.2 µF
C42
TX_N
TX_P
XIN_MSP
TP30
BAV99W-7-F
75 V
D4
TX_LED_P
BAV99W-7-F
75 V
D3
1
3
2
0 Ω
Jumper
R48
TP23
TP17
TX_LED_N
1
3
2
LED_DRV_SUP
0 Ω
Jumper
R44
1
2
3
4
5
6
7
8
9
11
10
DB9-F-TP
NellCor DS-100A PulseOx Connectors
DB9-F
J2
TP14
DET_P
BAV99W-7-F
75 V
1
3
2
D2
TP13
DET_N
BAV99W-7-F
75 V
1
3
2
D1
RX_ANA_SUP
TP7
TP12
VCM_SHIELD
VCM_AFE
C12
0 Ω
R27
0 Ω
R24 IN_N
IN_P
0.01 Fµ
1.00 kΩ
R28
VBG
R32 130 Ω
R36 130 Ω
R40 130 Ω
R41 130 Ω
1
2
3
4
5
6
7
8
9
10
AFE_RESETZ
ADC_RDY
STE
SIMO
SOMI
SCLK
PD_ALM
LED_ALM
DIAG_END
AFE_CLKOUT
RX_DIG_SUP
R23 10 Ω
TP20
21
22
23
24
25
26
27
28
29
30
INM
INP
RX_ANA_GND
VCM
DNC
DNC
BG
VSS
RSVD
DNC
TX_CTRL_SUP
LED_DRV_GND
LED_DRV_GND
TXM
TXP
LED_DRV_GND
LED_DRV_SUP
LED_DRV_SUP
RX_DIG_GND
AFE_PDNZ
EP
DIAG_END
LED_ALM
PD_ALM
SPI_CLK
SPI_SOMI
SPI_SIMO
SPI_STE
ADC_RDY
RESETZ
CLK_OUT
RX_DIG_SUP
RX_DIG_GND
RX_ANA_SUP
RX_OUTN
RX_OUTP
RX_ANA_GND
XOUT
XIN
RX_ANA_SUP
RX_ANA_GND
TP8
TP6
0.1 Fµ
C10
0.1 µF
C9
RX_ANA_SUP
31
32
33
34
35
36
37
38
39
40
AFE4400
U1
RX_DIG_SUP
R22 130 Ω
R20 130 Ω
0 Ω
DNI
R15
0 ΩR16
0 Ω
R17
TP11
18 pF
C7
18 pF
C6
1 2
8 MHz
Y1
10 kΩ
R98
AFE4490
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SBAS602H –DECEMBER 2012–REVISED OCTOBER 2014
9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The AFE4490 can be used for measuring SPO2 and for monitoring heart rate. The high dynamic range of the
device enables measuring SPO2 with a high degree of accuracy even under low-perfusion (ac-to-dc ratio)
conditions. An SPO2 measurement system involves two different wavelength LEDs—usually Red and IR. By
computing the ratio of the ac to dc at the two different wavelengths, the SPO2 can be calculated. Heart rate
monitoring systems can also benefit from the high dynamic range of the device, which enables capturing a high-
fidelity pulsating signal even in cases where the signal strength is low.
For more information on application guidelines, refer to the AFE44x0SPO2EVM User's Guide (SLAU480).
9.2 Typical Application
Device connections in a typical application are shown in Figure 131. Refer to the AFE44x0SPO2EVM User's
Guide (SLAU480) for more details. The schematic in Figure 131 is a part of the AFE44x0SPO2EVM and shows a
cabled application in which the LEDs and photodiode are connected to the AFE4490 through a cable. However,
in an application without cables, the LEDs and photodiode can be directly connected to the TXP, TXN and INP,
INN pins directly, as shown in the Design Requirements section.
NOTE: The following signals must be considered as two sets of differential pains and routed as adjacent signals within each pair:
TXM, TXP and INM, INP.
INM and INP must be guarded with VCM_SHIELD the signal. Run the VCM_SHIELD signal to the DB9 connector and back to the device.
Figure 131. AFE44x0SPO2EVM: Connections to the AFE4490
Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 85
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RED
TXP TXM
LED_DRV_GND
LED1
Controls
LED2
Controls
LED1
Controls LED2
Controls
LED_DRV_SUP
IR
LED2
Controls LED1
Controls
RED IR
TXP TXM
LED_DRV_SUP
LED_DRV_GND
AFE4490
SBAS602H –DECEMBER 2012–REVISED OCTOBER 2014
www.ti.com
Typical Application (continued)
9.2.1 Design Requirements
An SPO2 application usually involves a Red LED and an IR LED. These LEDs can be connected either in the
common anode configuration or H-bridge configuration to the TXP, TXN pins. Figure 132 shows common anode
configuration and Figure 133 shows H-bridge configuration.
Figure 132. LEDs in Common Anode Configuration
Figure 133. LEDs in H-Bridge Configuration
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INP
INN
AFE4490
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SBAS602H –DECEMBER 2012–REVISED OCTOBER 2014
Typical Application (continued)
9.2.2 Detailed Design Procedure
The photodiode receives the light from both the Red and IR phases and usually has good sensitivities at both
these wavelengths.
The photodiode connected in this manner operates in zero bias because of the negative feedback from the
transimpedance amplifier. The connections of the photodiode to the AFE inputs are shown in Figure 134.
Figure 134. Photodiode Connection
The signal current generated by the photodiode is converted into a voltage by the transimpedance amplifier,
which has a programmable transimpedance gain. The rest of the signal chain then presents a voltage to the
ADC. The full-scale output of the transimpedance amplifier is ±1 V and the full-scale input to the ADC is ±1.2 V.
An automatic gain control loop can be used to set the target dc voltage at the ADC input to approximately 50% of
full scale. This type of AGC loop can control a combination of LED current and TIA gain to achieve this target
value; see Figure 135.
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Product Folder Links: AFE4490
+1.2 V
+1 V
+0.6 V
0 V
-1 V
-1.2 V
ADC max
(Differential)
TIA max
(Differential)
Ideal Operating
Point
TIA min
(Differential)
ADC min
(Differential)
AFE4490
SBAS602H –DECEMBER 2012–REVISED OCTOBER 2014
www.ti.com
Typical Application (continued)
Figure 135. AGC Loop
The ADC output is a 22-bit code that is obtained by discarding the two MSBs of the 24-bit registers (for example
the register with address 2Ah).
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
Ignore 22-Bit ADC Code, MSB to LSB
R/W-0h R/W-0h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
22-Bit ADC Code, MSB to LSB
R/W-0h (TBD register correct?)
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7 shows the mapping of the input voltage to the ADC output code.
Table 7. Input Voltage Mapping
DIFFERENTIAL INPUT VOLTAGE AT ADC INPUT 22-BIT ADC OUTPUT CODE
–1.2 V 1000000000000000000000
(–1.2 / 221) V 1111111111111111111111
0 0000000000000000000000
(1.2 / 221) V 0000000000000000000001
1.2 V 0111111111111111111111
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Product Folder Links: AFE4490
0
100
200
300
400
500
600
700
800
900
0 10 20 30 40 50
Input Referred Noise Current,
pA rms in 20Hz Bandwidth
Pleth Current (A)
Duty Cycle 1%
Duty Cycle 5%
Duty Cycle 10%
Duty Cycle 15%
Duty Cycle 20%
Duty Cycle 25%
C013
For each setting RF adjusted for Full-Scale Output.
Amb Cancellation & stage 2 Gain = 4 used for Low
Pleth currents (0.125uA, 0.25uA & 0.5uA.)
Noise is calculated in 20Hz band.
AFE4490
www.ti.com
SBAS602H –DECEMBER 2012–REVISED OCTOBER 2014
The data format is binary twos complement format, MSB first. TI recommends that the input to the ADC does not
exceed ±1 V (which is approximately 80% full-scale) because the TIA has a full-scale range of ±1 V.
9.2.3 Application Curve
The dc component of the current from the PPG signal is referred to as Pleth (short for photoplethysmography)
current. The input-referred noise current (referred differentially to the INP, INN inputs) as a function of the Pleth
current is shown in Figure 136 at a PRF of 600 Hz and for various duty cycles of LED pulsing. For example, a
duty cycle of 25% refers to a case where the LED is pulsed for 25% of the pulse repetition period and the
receiver samples the photodiode current for the same period of time. The noise shown in Figure 136 is the
integrated noise over a 20-Hz bandwidth from dc.
Figure 136. Input-Referred Noise Current vs
Pleth Current (BW = 20Hz, PRF = 600 Hz)
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Product Folder Links: AFE4490
Boost
Converter
3.6 V
(Connect to LED_DRV_SUP, TX_CTRL_SUP)
2.2-V supply
(Connect to RX_ANA, RX_DIG)
AFE4490
SBAS602H –DECEMBER 2012–REVISED OCTOBER 2014
www.ti.com
10 Power-Supply Recommendations
The AFE4490 has two sets of supplies: the receiver supplies (RX_ANA_SUP, RX_DIG_SUP) and the transmitter
supplies (TX_CTRL_SUP, LED_DRV_SUP). The receiver supplies can be between 2.0 V to 3.6 V whereas the
transmitter supplies can be between 3.0 V to 5.25 V. Another consideration that determines the minimum allowed
value of the transmitter supplies is the forward voltage of the LEDs being driven. The current source and
switches inside the AFE require voltage headroom that mandates the transmitter supply to be a few hundred
millivolts higher than the LED forward voltage. TX_REF is the voltage that governs the generation of the LED
current from the internal reference voltage. Choosing the lowest allowed TX_REF setting reduces the additional
headroom required but results in higher transmitter noise. Other than for the highest end clinical SPO2
applications, this extra noise resulting from a lower TX_REF setting might be acceptable.
The LED_DRV_SUP and TX_CTRL_SUP are recommended to be tied together to the same supply (between
3.0 V and 5.25 V). The external supply (connected to the common anode of the two LEDs) must be high enough
to account for the forward drop of the LEDs as well as the voltage headroom required by the current source and
switches inside the AFE. In most cases, this voltage is expected to fall below 5.25 V; thus the external supply
can be the same as the LED_DRV_SUP. However, there might be cases (for instance when two LEDs are
connected in series) where the voltage required on the external supply is higher than 5.25 V. Such a case must
be handled with care to ensure that the voltage on the TXP and TXN pins stays less than 5.25 V and also never
exceeds the supply voltage of LED_DRV_SUP, TX_CTRL_SUP by more than 0.3 V.
Many scenarios of power management are possible.
Case 1: LED forward voltage is such that a voltage of 3.3 V (for example) is acceptable on LED_DRV_SUP. In
that case, a single 3.3-V supply can be used to drive all four pins (RX_ANA_SUP, RX_DIG_SUP,
TX_CTRL_SUP, LED_DRV_SUP). Care must be taken to provide some isolation between the transmit and
receive supplies because the LED_DRV_SUP carries the high switching current from the LEDs.
Case 2: A low-voltage supply (2.2 V for instance) is available in the system. In this case, a boost converter can
be used to derive the voltage for the LED_DRV_SUP, as shown in Figure 137.
Figure 137. Boost Converter
The boost converter requires a clock (usually in the megahertz range) and there is usually a ripple at the boost
converter output at this switching frequency. While this frequency is much higher than the signal frequency of
interest (which is at maximum a few 10s of hertz around dc), a small fraction of this switching noise might
possibly alias to the low-frequency band. Therefore, TI strongly recommends that the switching frequency of the
boost converter be offset from every multiple of the PRF by at least 20 Hz, which can be ensured by choosing
the appropriate PRF.
90 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: AFE4490
LDO
3.6 V
(Connect to LED_DRV_SUP, TX_CTRL_SUP)
2.2-V supply
(Connect to RX_ANA, RX_DIG)
AFE4490
www.ti.com
SBAS602H –DECEMBER 2012–REVISED OCTOBER 2014
Case 3: In cases where a high voltage supply is available in the system, a buck converter or an LDO can be
used to derive the voltage levels required to drive RX_ANA and RX_DIG. Such a scenario is shown in
Figure 138.
Figure 138. Buck Converter or an LDO
For more information on power-supply recommendations, see the AFE44x0SPO2EVM User's Guide (SLAU480).
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SBAS602H –DECEMBER 2012–REVISED OCTOBER 2014
www.ti.com
11 Layout
11.1 Layout Guidelines
Some key layout guidelines are:
1. TXP, TXN are fast switching lines and must be routed away from sensitive reference lines as well as from
the INP, INN inputs.
2. If required to route long, TI recommends that the VCM be used as a shield for the INP, INN lines.
3. The device can draw high switching currents from the LED_DRV_SUP pin. Therefore, having a decoupling
capacitor electrically close to the pin is recommended.
11.2 Layout Example
Figure 139. Typical Layout of the AFE4490 Board
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AFE4490
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SBAS602H –DECEMBER 2012–REVISED OCTOBER 2014
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
AFE44x0SPO2EVM User's Guide, SLAU480
SpO Pulse Ox Wrist Oximeter Reference Design,TIDU124
12.2 Trademarks
SPI is a trademark of Motorola.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.4 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 93
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PACKAGE OPTION ADDENDUM
www.ti.com 24-Jun-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
AFE4490RHAR ACTIVE VQFN RHA 40 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AFE4490
AFE4490RHAT ACTIVE VQFN RHA 40 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AFE4490
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 24-Jun-2014
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
AFE4490RHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2
AFE4490RHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Oct-2015
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
AFE4490RHAR VQFN RHA 40 2500 367.0 367.0 38.0
AFE4490RHAT VQFN RHA 40 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Oct-2015
Pack Materials-Page 2
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