© Semiconductor Components Industries, LLC, 2016
April, 2017 − Rev. 9 1Publication Order Number:
NCV8877/D
NCV8877
Automotive Grade
Start-Stop Non-Synchronous
Boost Controller
The NCV8877 is a Non-Synchronous Boost controller designed to
supply a minimum output voltage during Start-Stop vehicle operation
battery voltage sags. The controller drives an external N-channel
MOSFET. The device uses peak current mode control with internal
slope compensation. The IC incorporates an internal regulator that
supplies charge to the gate driver.
Protection features include, cycle-by-cycle current limiting and
thermal shutdown.
Additional features include low quiescent current sleep mode
operation. The NCV8877 is enabled when the supply voltage drops
below the wake up threshold. Boost Operation is initiated when the
supply voltage drops below the regulation set point.
Features
•Automatic Enable Below Wake Up Threshold Voltage (Factory
Programmable)
•Override Disable Function
•Boost Mode Operation at Regulation Set Point
•$2% Output Accuracy Over Temperature Range
•Peak Current Mode Control with Internal Slope Compensation
•Externally Adjustable Frequency Operation
•Wide Input Voltage Range of 2 V to 40 V, 45 V Load Dump
•Low Quiescent Current in Sleep Mode (<12 mA Typical)
•Cycle−by−Cycle Current Limit Protection
•Hiccup−Mode Overcurrent Protection (OCP)
•Thermal Shutdown (TSD)
•This is a Pb−Free Device
Typical Applications
•Applications Requiring Regulated Voltage through Cranking and
Start−Stop Operation
MARKING
DIAGRAM
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SOIC−8
D SUFFIX
CASE 751
1
8
PIN CONNECTIONS
1 8
2
3
4
7
6
5
(Top View)
DISB
ISNS
GND
GDRV
ROSC
VC
VOUT
VDRV
8877xx = Specific Device Code
xx = 00, 01, 20, 40
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
8877xx
ALYW
G
1
8
Device Package Shipping†
ORDERING INFORMATION
NCV887700D1R2G
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
NCV887701D1R2G
NCV887720D1R2G SOIC−8
(Pb−Free) 2500 / Tape &
Reel
NCV887740D1R2G
NCV887711D1R2G
NCV887721D1R2G
NCV8877
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2
Figure 1. Typical Application
BATTERY
IN
DISABLE
CC
RC
ROSC
CDRV
Q
DB
LP
VDRV
GND
ISNS
ROSC
VOUT
DISB GDRV
VC
RSNS
Co
Cg
VOUT
Figure 2. Functional Waveforms
Wake Up Threshold
Wakeup
DISB
(Internal signal)
Battery In
VOUT
Regulation
Sleep Threshold
GDRV
Wake Up Delay
COMP
GDRV Switching Delay
Internal Clamp
Voltage
NRVB440MFS
NVMFS5844NL
PACKAGE PIN DESCRIPTIONS
Pin No. Pin
Symbol Function
1 DISB Disable input. This part is disabled when this pin is brought low.
2 ISNS Current sense input. Connect this pin to the source of the external N−MOSFET, through a current−sense res-
istor to ground to sense the switching current for regulation and current limiting.
3 GND Ground reference.
4 GDRV Gate driver output. Connect to gate of the external N−MOSFET. A series resistance can be added from GDRV
to the gate to tailor EMC performance.
5 VDRV Driving voltage. Internally−regulated supply for driving the external N−MOSFET, sourced from VOUT. Bypass
with a 1.0 mF ceramic capacitor to ground.
6 VOUT Monitors output voltage and provides IC input voltage.
7 VC Output of the voltage error transconductance amplifier. An external compensator network from VC to GND is
used to stabilize the converter.
8 ROSC Use a resistor to ground to set the frequency.
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ABSOLUTE MAXIMUM RATINGS (Voltages are with respect to GND, unless otherwise indicated)
Rating Value Unit
Dc Supply Voltage (VOUT) −0.3 to 40 V
Peak Transient Voltage (Load Dump on VOUT) 45 V
Dc Supply Voltage (VDRV, GDRV) 12 V
Dc Voltage (VC, ISNS, ROSC) −0.3 to 3.6 V
Dc Voltage (DISB) −0.3 to 6 V
Dc Voltage Stress (VOUT − VDRV) −0.7 to 40 V
Operating Junction Temperature −40 to 150 °C
Storage Temperature Range −65 to 150 °C
Peak Reflow Soldering Temperature: Pb−Free, 60 to 150 seconds at 217°C265 peak °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
PACKAGE CAPABILITIES
Characteristic Value Unit
ESD Capability (All Pins) Human Body Model
Machine Model ≥2.0
≥200 kV
V
Moisture Sensitivity Level 1
Package Thermal Resistance Junction−to−Ambient, RqJA (Note 1) 100 °C/W
1. 1 in2, 1 oz copper area used for heatsinking.
TYPICAL VALUES
Part No. Dmax fSSaVcl Isrc Isink VOUT SCE
NCV887700 83% 170 kHz 34 mV/ms400 mV 800 mA 600 mA 6.8 V N
NCV887701 83% 170 kHz 53 mV/ms200 mV 800 mA 600 mA 6.8 V N
NCV887711 83% 170 kHz 53 mV/ms200 mV 800 mA 600 mA 8.55 V N
NCV887720 83% 170 kHz 53 mV/ms200 mV 800 mA 600 mA 10 V N
NCV887721 83% 170 kHz 53 mV/ms200 mV 800 mA 600 mA 10.28 V N
NCV887740 83% 170 kHz 53 mV/ms200 mV 800 mA 600 mA 12 V N
NCV8877
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ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 3.6 V < VOUT < 40 V, unless otherwise specified) Min/Max values are
guaranteed by test, design or statistical correlation.
Characteristic Symbol Conditions Min Typ Max Unit
GENERAL
Quiescent Current, Sleep Mode Iq,sleep VOUT = 13.2 V, TJ = 25°C, DISB = 0 V − 12 14 mA
Quiescent Current, No switching Iq,off Into VOUT pin, VOUT,reg < VOUT <
VOUT,des, No switching − 2.2 4.0 mA
OSCILLATOR
Switching Frequency FSW 153 − 501 kHz
ROSC Voltage VROSC − 1.0 − V
Switching Frequency FSW ROSC = Open 153 170 187 kHz
Default Switching FSW ROSC = Open
ROSC = 100 kW
ROSC = 20 kW
ROSC = 10 kW
153
180
283
409
170
200
315
455
187
220
347
501
kHz
Minimum Pulse Width ton,min NCV887700
NCV887701
NCV887711
NCV887720
NCV887721
NCV887740
90
90
89
90
90
90
115
115
115
115
115
115
145
145
146
145
145
145
ns
Maximum Duty Cycle Dmax ROSC = OPEN 81 83 85 %
Slope Compensating Ramp
(Note 2) SaNCV887700
NCV887701
NCV887711
NCV887720
NCV887721
NCV887740
30
46
45
46
46
46
34
53
53
53
53
53
38
60
61
60
60
60
mV/ ms
DISABLE
DISB Pull−down Current (Note 2) IDIS VDIS = 5 V − 0.6 1.0 mA
DISB Input High Voltage Vd,ih 2.0 − 5.0 V
DISB Input High Voltage Hysteresis Vd,hys − 500 − mV
DISB Input Low Voltage Vd,il 0 − 800 mV
CURRENT SENSE AMPLIFIER
Low−Frequency Gain Acsa Input−to−output gain at dc, ISNS ≤ 1 V 0.9 1.0 1.1 V/V
Bandwidth BWcsa Gain of Acsa − 3 dB 2.5 − − MHz
ISNS Input Bias Current Isns,bias Out of ISNS pin − 30 50 mA
Current Limit Threshold Voltage Vcl Voltage on ISNS pin NCV887700
NCV887701
NCV887711
NCV887720
NCV887721
NCV887740
360
180
180
180
180
180
400
200
200
200
200
200
440
220
220
220
220
220
mV
Current Limit, Response Time (Note
2) tcl CL tripped until GDRV falling edge,
VISNS = Vcl(typ) + 60 mV − 80 125 ns
Overcurrent Protection,
Threshold Voltage %Vocp Percent of Vcl 125 150 175 %
Overcurrent Protection,
Response Time (Note 2) tocp From overcurrent event, Until switching
stops, VISNS = VOCP + 40 mV − 80 125 ns
VOLTAGE ERROR OPERATIONAL TRANSCONDUCTANCE AMPLIFIER
Transconductance gm,vea VOUT = ±100 mV 0.8 1.2 1.63 mS
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Not tested in production. Limits are guaranteed by design.
NCV8877
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ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 3.6 V < VOUT < 40 V, unless otherwise specified) Min/Max values are
guaranteed by test, design or statistical correlation.
Characteristic UnitMaxTypMinConditionsSymbol
VOLTAGE ERROR OPERATIONAL TRANSCONDUCTANCE AMPLIFIER
VEA Output Resistance (Note 2) Ro,vea 2.0 − − MΩ
VEA Maximum Output Voltage Vc,max 2.5 − − V
VEA Sourcing Current Isrc,vea VEA output current, Vc = 2.0 V 80 100 − mA
VEA Sinking Current Isnk,vea VEA output current, Vc = 1.5 V 80 100 − mA
VEA Clamp Voltage Vc,clamp VOUT < VOUT,des − 1.1 − V
GDRV Switching Delay VOUT < VOUT,des or when IC DISB goes
from low to high with Vc pin compensation
network disconnected
− 55 64 ms
GATE DRIVER
Sourcing Current Isrc VDRV ≥ Typical Driving Voltage Specifica-
tion, VDRV − VGDRV = 2 V 550 800 − mA
Sinking Current Isink VGDRV ≥ 2 V 480 600 − mA
Driving Voltage Dropout (Note 2) Vdrv,do VOUT − VDRV, IvDRV = 25 mA − 0.3 0.6 V
Driving Voltage Source Current Idrv VOUT − VDRV = 1 V 35 45 − mA
Backdrive Diode Voltage Drop Vd,bd VDRV – VOUT, Id,bd = 5 mA − − 0.7 V
Driving Voltage VDRV IVDRV = 0.1 − 25 mA NCV887700
NCV887701
NCV887711
NCV887720
NCV887721
NCV887740
5.8
5.8
5.67
5.8
5.92
5.8
6.0
6.0
5.9
6.0
6.12
6.0
6.2
6.2
6.13
6.2
6.32
6.2
V
Pull−down Resistance − 21 − kW
UVLO
Undervoltage Lock−out,
Threshold Voltage Vuvlo VOUT falling NCV887700
NCV887701
NCV887711
NCV887720
NCV887721
NCV887740
3.60
3.60
3.54
3.60
3.67
3.60
3.80
3.80
3.73
3.80
3.87
3.80
4.00
4.00
4.00
4.00
4.08
4.00
V
Undervoltage Lock−out,
Hysteresis Vuvlo,hys VOUT rising NCV887700
NCV887701
NCV887711
NCV887720
NCV887721
NCV887740
330
330
325
330
337
330
450
450
442
450
459
450
570
570
563
570
581
570
mV
THERMAL SHUTDOWN
Thermal Shutdown Threshold (Note
2) Tsd TJ rising 160 170 180 °C
Thermal Shutdown Hysteresis (Note
2) Tsd,hys TJ falling 10 15 20 °C
Thermal Shutdown Delay (Note 2) tsd,dly From TJ > Tsd to stop switching − − 100 ns
VOLTAGE REGULATION
Voltage Regulation VOUT,reg NCV887700
NCV887701
NCV887711
NCV887720
NCV887721
NCV887740
6.66
6.66
8.06
9.80
10.08
11.76
6.80
6.80
8.55
10.00
10.28
12.00
6.94
6.94
8.72
10.20
10.49
12.24
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Not tested in production. Limits are guaranteed by design.
NCV8877
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ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 3.6 V < VOUT < 40 V, unless otherwise specified) Min/Max values are
guaranteed by test, design or statistical correlation.
Characteristic UnitMaxTypMinConditionsSymbol
VOLTAGE REGULATION
Threshold IC Enable VOUT descending NCV887700
NCV887701
NCV887711
NCV887720
NCV887721
NCV887740
7.10
7.10
8.82
10.36
10.65
12.64
7.30
7.30
9.11
10.65
10.95
13.00
7.50
7.50
9.39
10.94
11.29
13.36
V
Threshold IC Disable VOUT ascending NCV887700
NCV887701
NCV887711
NCV887720
NCV887721
NCV887740
7.55
7.55
9.33
10.96
11.27
13.40
7.75
7.75
9.62
11.25
11.57
13.75
7.95
7.95
9.91
11.54
11.86
14.10
V
Threshold IC Enable – Voltage Reg-
ulation NCV887700
NCV887701
NCV887711
NCV887720
NCV887721
NCV887740
0.32
0.32
0.33
0.39
0.40
0.52
0.5
0.5
0.5
0.6
0.6
0.8
−
−
−
−
−
−
V
Threshold IC Disable – Threshold
IC Enable NCV887700
NCV887701
NCV887711
NCV887720
NCV887721
NCV887740
−
−
−
−
−
−
0.4
0.4
0.4
0.5
0.5
0.7
−
−
−
−
−
−
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Not tested in production. Limits are guaranteed by design.
NCV8877
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TYPICAL CHARACTERISTICS
15
Iq,sleep, SLEEP CURRENT (mA)
TJ, JUNCTION TEMPERATURE (°C)
Figure 3. Sleep Current vs. Temperature
2.12
−50 0 15050 100
Iq,on, QUIESCENT CURRENT (mA)
TJ, JUNCTION TEMPERATURE (°C)
Figure 4. Quiescent Current vs. Temperature
14
13
12
11
10
2.10
2.08
2.06
2.04
2.02
2.00
VOUT = VOUT,reg < VOUT < VOUT descending
fs = 170 kHz
124
ton,min, MINIMUM ON TIME (ns)
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. Minimum On Time vs. Temperature
−50 0 15050 100
123
122
121
120
119
118
117
116
115
1.020
NORMALIZED CURRENT LIMIT
TJ, JUNCTION TEMPERATURE (°C)
Figure 6. Normalized Current vs. Temperature
−50 0 15050 100
1.005
1.000
0.990
0.980
NORMALIZED VOUT REGULATION (V)
TJ, JUNCTION TEMPERATURE (°C)
Figure 7. VOUT Regulation vs. Temperature
−50 0 15050 100
1.000
0.998
0.996
169.0
SWITCHING FREQUENCY (ROSC = Open) (kHz)
TJ, JUNCTION TEMPERATURE (°C)
Figure 8. Switching Frequency vs.
Temperature
−50 0 15050 100
168.8
168.6
168.4
168.2
168.0
167.8
167.6
167.4
167.2
167.0 ROSC = Open
−50 0 15050 100
VOUT = 13.2 V
0.995
0.985
1.010
1.015
1.002
1.004
1.006
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TYPICAL CHARACTERISTICS
4.3
UVLO THRESHOLD (V)
TJ, JUNCTION TEMPERATURE (°C)
Figure 9. UVLO Threshold vs. Temperature
−50 0 15050 100
4.2
4.1
4.0
3.9
3.8
VOUT Rising
VOUT Falling
7.9
THRESHOLD IC VOLTAGE (V)
TJ, JUNCTION TEMPERATURE (°C)
Figure 10. NCV887700/01 Threshold IC Voltage
vs. Temperature
−50 0 15
0
50 100
7.8
7.7
7.6
7.5
7.4
7.3
ENABLE
DISABLE
11.1
THRESHOLD IC VOLTAGE (V)
TJ, JUNCTION TEMPERATURE (°C)
Figure 11. NCV887711 Threshold IC Voltage
vs. Temperature
−50 0 15050 100
10.9
10.8
10.7
10.5
10.4
13.8
THRESHOLD IC VOLTAGE (V)
TJ, JUNCTION TEMPERATURE (°C)
−50 0 15
0
50 100
13.6
13.5
13.3
13.1
13.0
10.6
11.0
ENABLE
13.2
13.4
13.7
DISABLE
ENABLE
DISABLE
11.3
THRESHOLD IC VOLTAGE (V)
TJ, JUNCTION TEMPERATURE (°C)
Figure 12. NCV887720 Threshold IC Voltage
vs. Temperature
−50 0 15
0
50 100
11.1
11.0
10.9
10.7
10.6
10.8
11.2
ENABLE
DISABLE
11.5
THRESHOLD IC VOLTAGE (V)
TJ, JUNCTION TEMPERATURE (°C)
−50 0 15050 100
11.3
11.2
11.1
10.9
10.8
11.0
11.4
ENABLE
DISABLE
Figure 13. NCV887721 Threshold IC Voltage
vs. Temperature Figure 14. NCV887740 Threshold IC Voltage
vs. Temperature
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THEORY OF OPERATION
+
Figure 16. Current Mode Control Schematic
Oscillator
Slope
Compensation
Q
S
R
NCV8877
Voltage
Error
VEA
CSA
PWM Comparator Gate
Drive
L
ISNS
GDRV
VOUT
WAKEUP
ROSC
DISB DISABLE
RL
CO
VOUT
VIN
RSNS
ROSC
VC
RDAMP
CDECOUPLING
GND
DISB
The DISB pin provides an IC disable function. When a DC
logic-low voltage is applied to this pin, the NCV8877 enters
a low quiescent sleep mode, permitting an external signal to
either shutdown the IC or disable the wakeup function.
Regulation
The NCV8877 is a non−synchronous boost controller
designed to supply a minimum output voltage during
Start−Stop vehicle operation battery voltage sags. The
NCV8877 is in low quiescent current sleep mode under
normal battery operation (12 V) and is enabled when the
supply voltage drops below the descending threshold (7.3 V
for the NCV887700). Boost operation is initiated when the
supply voltage is below the regulation set point (6.8 V for the
NCV887700). Once the supply voltage sag condition ends
and begins to increase, the NCV8877 boost operation will
cease when the supply voltage increases beyond the
regulation set point. The NCV8877 low quiescent current
sleep mode resumes once the supply voltage increases
beyond the ascending voltage threshold (7.6 V for the
NCV887700).
The NCV8877 VOUT pin serves the dual purpose: (1)
powering the NCV8877 and (2) providing the regulation
feedback signal. The feedback network is imbedded within
the I C t o e liminate t he c onstant c urrent b attery d rain t hat w ould
exist with the use of external voltage feedback resistors.
There i s no soft−start operating mode. The NCV8877 will
instantly respond to a voltage sag so as to maintain normal
operation of downstream loads. Once the NCV8877 is
enabled, the voltage error operational transconductance
amplifier supplies current to set VC to 1.1 V to minimize the
feedback loop response time when the battery voltage sag
goes below the regulation set point.
Current Mode Control
The NCV8877 incorporates a current mode control
scheme, in which the PWM ramp signal is derived from the
power switch current. This ramp signal is compared to the
output of the error amplifier to control the on−time of the
power switch. The oscillator is used as a fixed−frequency
clock to ensure a constant operational frequency. The
resulting control scheme features several advantages over
conventional voltage mode control. First, derived directly
from the inductor, the ramp signal responds immediately to
line voltage changes. This eliminates the delay caused by the
output filter and the error amplifier, which is commonly
found in voltage mode controllers. The second benefit
comes from inherent pulse−by−pulse current limiting by
merely clamping the peak switching current. Finally, since
current mode commands an output current rather than
voltage, the filter offers only a single pole to the feedback
loop. This allows for a simpler compensation.
The NCV8877 also includes a slope compensation
scheme in which a fixed ramp generated by the oscillator is
added to the current ramp. A proper slope rate is provided to
improve circuit stability without sacrificing the advantages
of current mode control.
Current Limit
The NCV8877 features two current limit protections,
peak current mode and over current latch off. When the
current sense amplifier detects a voltage above the peak
current limit between ISNS and GND after the current limit
leading edge blanking time, the peak current limit causes the
power switch to turn off for the remainder of the cycle. Set
the current limit with a resistor from ISNS to GND, with R
= VCL / Ilimit.
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If the voltage across the current sense resistor exceeds the
over current threshold voltage the device enters over current
hiccup mode. The device will remain of f for the hiccup time
and then go through the soft−start procedure.
UVLO
Input Undervoltage Lockout (UVLO) is provided to
ensure that unexpected behavior does not occur when VIN
is too low to support the internal rails and power the
controller. The IC will start up when enabled and VIN
surpasses the UVLO threshold plus the UVLO hysteresis
and will shut down when VIN drops below the UVLO
threshold or the part is disabled.
VDRV
An internal regulator provides the drive voltage for the
gate driver. Bypass with a ceramic capacitor to ground to
ensure fast turn on times. The capacitor should be between
0.1 mF and 1 mF, depending on switching speed and charge
requirements of the external MOSFET.
VDRV uses an internal linear regulator to charge the
VDRV bypass capacitor. VOUT must be decoupled at the IC
by a capacitor that is equal or lar ger in value than the VDRV
decoupling capacitor.
APPLICATION INFORMATION
Design Methodology
This section d etails a n o verview o f the c omponent s election
process for the NCV8877 in continuous conduction mode
boost. I t i s intended to assist with the design process but does
not remove all engineering design work. Many of the
equations make heavy use of the small ripple approximation.
This process entails the following steps:
1. Define Operational Parameters
2. Select Operating Frequency
3. Select Current Sense Resistor
4. Select Output Inductor
5. Select Output Capacitors
6. Select Input Capacitors
7. Select Compensator Components
8. Select MOSFET(s)
9. Select Diode
10. Design Notes
11. Determine Feedback Loop Compensation Network
1. Define Operational Parameters
Before beginning the design, define the operating
parameters of the application. These include:
VIN(min): minimum input voltage [V]
VIN(max): maximum input voltage [V]
VOUT: output voltage [V]
IOUT(max): maximum output current [A]
ICL: desired typical cycle-by-cycle current limit [A]
From this the ideal minimum and maximum duty cycles
can be calculated as follows:
Dmin +1*VIN(max)
VOUT
Dmax +1*VIN(min)
VOUT
Both duty cycles will actually be higher due to power loss
in the conversion. The exact duty cycles will depend on
conduction and switching losses. If the maximum input
voltage is higher than the output voltage, the minimum duty
cycle will be negative. This is because a boost converter
cannot have an output lower than the input. In situations
where the input is higher than the output, the output will
follow the input, minus the diode drop of the output diode
and the converter will not attempt to switch.
If the calculated Dmax is higher the Dmax of the NCV8877,
the conversion will not be possible. It is important for a boost
converter to have a restricted Dmax, because while the ideal
conversion ration of a boost converter goes up to infinity as
D approaches 1, a real converter’s conversion ratio starts to
decrease as losses overtake the increased power transfer. If
the converter is in this range it will not be able to regulate
properly.
If the following equation is not satisfied, the device will
skip pulses at high VIN:
Dmin
fswton(min)
Where: fs: switching frequency [Hz]
ton(min): minimum on time [s]
2. Select Operating Frequency
The default setting is an open ROSC pin, allowing the
oscillator to operate at the default frequency Fs. Adding a
resistor to GND increases the switching frequency.
The graph in Figure 17, below, shows the required
resistance to program the frequency. From 200 kHz to
500 kHz, the following formula is accurate to within 3% of
the expected
Figure 17. ROSC vs. FSW
100
90
80
70
60
50
40
30
20
10
0150 200 250 500450400350300
FSW (kHz)
ROSC (kW)
550
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12
ROSC +2859
(Fsw *170)
Where: fsw: switching frequency [kHz]
ROSC: resistor from ROSC pin to GND [k]
Note: The ROSC resistor ground return to the NCV8877 pin
3 must be independent of power grounds.
3. Select Current Sense Resistor
Current sensing for peak current mode control and current
limit relies on the MOSFET current signal, which is
measured with a ground referenced amplifier. The easiest
method of generating this signal is to use a current sense
resistor from the source of the MOSFET to device ground.
The sense resistor should be selected as follows:
RS+VCL
ICL
Where: RS: sense resistor [W]
VCL: current limit threshold voltage [V]
ICL: desire current limit [A]
4. Select Output Inductor
The output inductor controls the current ripple that occurs
over a switching period. A high current ripple will result in
excessive power loss and ripple current requirements. A low
current ripple will result in a poor control signal and a slow
current slew rate in case of load steps. A good starting point
for peak to peak ripple is around 20−40% of the inductor
current at the maximum load at the worst case VIN, but
operation should be verified empirically. The worst case VIN
is half of VOUT, or whatever VIN is closest to half of VOUT.
After choosing a peak current ripple value, calculate the
inductor value as follows:
L+VIN(WC) DWC
DIL,max fs
Where: VIN(WC): VIN value as close as possible to
half of VOUT [V]
DWC: duty cycle at VIN(WC)
DIL,max: maximum peak to peak ripple [A]
The maximum average inductor current can be calculated
as follows:
IL,AVG +VOUTIOUT(max)
VIN(min)h
The Peak Inductor current can be calculated as follows:
IL,peak +IL,avg )DIL,max
2
Where: IL,peak: Peak inductor current value [A]
5. Select Output Capacitors
The output capacitors smooth the output voltage and
reduce the overshoot and undershoot associated with line
transients. The steady state output ripple associated with the
output capacitors can be calculated as follows:
VOUT(ripple) +
DIOUT(max)
fCOUT )ǒIOUT(max)
1*D)VIN(min)D
2fLǓRESR
The capacitors need to survive an RMS ripple current as
follows:
ICout(RMS) +IOUT DWC
DȀWC )DWC
12 ǒDȀWC
L
ROUT TSWǓ2
Ǹ
The use of parallel ceramic bypass capacitors is strongly
encouraged to help with the transient response.
6. Select Input Capacitors
The input capacitor reduces voltage ripple on the input to
the module associated with the ac component of the input
current.
ICin(RMS) +VIN(WC)2DWC
LfsVOUT23
Ǹ
7. Select Compensator Components
Current Mode control method employed by the NCV8877
allows the use of a simple, T ype II compensation to optimize
the dynamic response according to system requirements.
8. Select MOSFET(s)
In order to ensure the gate drive voltage does not drop out
the MOSFET(s) chosen must not violate the following
inequality:
Qg(total) vIdrv
fs
Where: Qg(total): Total Gate Charge of MOSFET(s) [C]
Idrv: Drive voltage current [A]
fs: Switching Frequency [Hz]
The maximum RMS Current can be calculated as follows:
IQ(max) +Iout D
Ǹ
DȀ
The maximum voltage across the MOSFET will be the
maximum output voltage, which is the higher of the
maximum input voltage and the regulated output voltaged:
VQ(max) +VOUT(max)
9. Select Diode
The output diode rectifies the output current. The average
current through diode will be equal to the output current:
ID(avg) +IOUT(max)
Additionally, the diode must block voltage equal to the
higher of the output voltage and the maximum input voltage:
VD(max) +VOUT(max)
The maximum power dissipation in the diode can be
calculated as follows:
PD+Vf(max) IOUT(max)
NCV8877
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13
Where: Pd: Power dissipation in the diode [W]
Vf(max): Maximum forward voltage of the diode [V]
10. Design Notes
•VOUT serves a dual purpose (feedback and IC power).
The VDRV circuit has a current pulse power draw
resulting in current flow from the output sense location
to the IC. Trace ESL will cause voltage ripple to
develop at IC pin VOUT which could affect
performance.
♦Use a 1 mF IC VOUT pin decoupling capacitor close
to IC in addition to the VDRV decoupling capacitor.
•Classic feedback loop measurements are not possible
(VOUT pin serves a dual purpose as a feedback path
and IC power). Feedback loop computer modeling
recommended.
♦A step load test for stability verification is
recommended.
•Compensation ground must be dedicated and connected
directly to IC ground.
♦Do not use vias. Use a dedicated ground trace.
•ROSC programming resistor ground must be dedicated
and connected directly to IC ground
♦Do not use vias. Use a dedicated ground trace.
•IC ground & current sense resistor ground sense point
must be located on the same side of PCB.
♦Vias introduce sufficient ESR/ESL voltage drop
which can degrade the accuracy of the current
feedback signal amplitude (signal bounce) and
should be avoided.
•Star ground should be located at IC ground pad.
♦This is the location for connecting the compensation
and current sense grounds.
•The IC architecture has a leading edge ISNS blanking
circuit. In some instances, current pulse leading edge
current spike RC filter may be required.
♦If required, 330 pF + 250 W are a recommended
evaluation starting point.
•RDAMPING (optional)
♦The IC-VOUT pin may be located a few cm from
the output voltage sensing point. Parasitic
inductance from the feedback trace (roughly
5 nH/cm) results in the requirement for a decoupling
capacitor (Cdecoupling = 1 mF recommended) next to
the IC-VOUT pin to support the VDRV charging
pulses. The IC-VDRV energy is replenished from
current pulses by an internal linear regulator whose
charging frequency corresponds to that of the IC
oscillator (phase lag may occur; some charging
pulses may occasionally be skipped depending on
the state of the VDRV voltage). The trace’s parasitic
inductance can introduce a low amplitude damped
voltage oscillation between the IC-VOUT and the
output voltage sense location which may result in
minor frequency jitter.
♦If the measured frequency jitter is objectionable, it
may be attenuated by placing a series damping
resistor (Rdamp) in the feedback path between the
output voltage sense and IC-VOUT. The resulting
filter introduced by Rdamp introduces a high
frequency pole in the feedback loop path. The RC
filter 3 dB pole frequency must be chosen at a
minimum of 1 decade above the design’s feedback
loop cross-over frequency (at minimum power
supply input voltage where the worst case phase
margin will occur) to avoid deteriorating the
feedback loop cross-over frequency phase margin.
♦The average operating current demand from the IC
is dominated by the MOSFET gate drive power
energy consumption (IVDRV = Qg(tot)_6V x fosc).
The IVDRV x Rdamp voltage drop results in a
corresponding increase in power supply regulation
voltage. Rdamp is typically 0.68 W, so the resulting
increase in output voltage regulation will be minimal
(10-30 mV may be typical).
11. Determine Feedback Loop Compensation Network
The purpose of a compensation network is to stabilize the
dynamic response of the converter. By optimizing the
compensation network, stable regulation response is
achieved for input line and load transients.
Compensator design involves the placement of poles and
zeros in the closed loop transfer function. Losses from the
boost inductor, MOSFET, current sensing and boost diode
losses also influence the gain and compensation
expressions. The OTA has an ESD protection structure
(RESD ≈ 502 W, data not provided in the datasheet) located
on the die between the OTA output and the IC package
compensation pin (VC). The information from the OTA
PWM feedback control signal (VCTRL) may differ from the
IC−VC signal if R2 is of similar order of magnitude as RESD.
The compensation and gain expressions which follow take
influence from the OTA output impedance elements into
account.
Type−I compensation is not possible due to the presence
of RESD. The Figure 18 compensation network corresponds
to a Type−II network in series with R
ESD. The resulting
control−output transfer function is an accurate mathematical
model of the IC in a boost converter topology. The model
does have limitations and a more accurate SPICE model
should be considered for a more detailed analysis:
•The attenuating effect of large value ceramic capacitors
in parallel with output electrolytic capacitor ESR is not
considered in the equations.
•The efficiency term h should be a reasonable operating
condition estimate.
NCV8877
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14
Rds(on)
Vd
L
Ri
COUT
VOUT
C1
R2
VIN rL
rCf
C2
ROUT
GND
ISNS
VOUT
GDRV
VC
VCTRL
OTA
RESD
R1
RLOW
R0VREF
Figure 18. NCV8877 OTA and Compensation
NRVB440MFS
NVMFS5844NL
A worksheet as well as a SPICE model which may be used
for selecting compensation components R2, C1, C2 is
available at the ON Semiconductor web site
(http://onsemi.com/PowerSolutions/product.do?id=NCV8
877). The following equations may be used to analyze the
Figure 1 0 boost converter. Required input design parameters
for analysis are:
Vd = Boost diode Vf (V)
VIN = Boost supply input voltage (V)
Ri = Current sense resistor (W)
RDS(on) = MOSFET RDS(on) (W)
COUT = Bulk output capacitor value (F)
Rsw_eq = RDS(on) + Ri, for the boost continuous
conduction mode (CCM) expressions
rCF = Bulk output capacitor ESR (W)
ROUT = Equivalent resistance of output load (W)
Pout = Output Power (W)
L = Boost inductor value (H)
rL = Boost inductor ESR (W)
Ts = 1/fs, where fs = clock frequency (Hz)
VOUT = Device specific output voltage (e.g. 6.8 V
for NCV887701) (V)
Vref = OTA internal voltage reference = 1.2 V
R0 = OTA output resistance = 3 MW
Sa = IC slope compensation (e.g. 53 mV/ms for
NCV887701)
gm = OTA transconductance = 1.2 mS
D = Controller duty ratio
D’ = 1 − D
NCV8877
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15
Necessary equations for describing the modulator gain (Vctrl−to−Vout gain) Hctrl_output(f) are described in Table 1.
Table 1. BOOST CCM TRANSFER FUNCTION EXPRESSIONS
Duty ratio (D)
ȧ
ȧ
ȧ
ȧ
ȡ
Ȣ
2ROUTVdVIN*ƪRsw_eq)ROUTǒVIN
VOUT*2ǓƫVOUT 2
−VOUT ROUTǒROUTVIN 2)2Rsw_eqVINVOUT*4VdRsw_eqVIN
−4Rsw_eqVOUT 2*4rLVdVIN*4rLVOUT 2Ǔ)Rsw_eq 2VOUT 2
Ǹȧ
ȧ
ȧ
ȧ
ȣ
Ȥ
2ROUTǒVOUT 2)VdVINǓ
Vout/Vin Power Supply DC Con-
version Ratio (M) 1
1*D
Average Inductor Current (Ilave)POUT
VINh
Inductor On−slope (Sn)VIN *ILaveǒrL)Rsw_eqǓ
LRi
Compensation Ramp (mc)1)Sa
Sn
Cout ESR Zero (wz1)1
rCFCOUT
Right−half−plane Zero (wz2)(1*D)2
LǒROUT *rCFROUT
rCF )ROUTǓ*rL
L
Low Frequency Modulator Pole
(wp1)
2
ROUT )Ts
LM3mc
COUT
Sampling Double Pole (wn)p
Ts
Sampling Quality Coefficient (Qp)1
p(mc(1*D)*0.5)
Fm
1
2M )ROUTTs
LM2ǒ1
2)Sa
SnǓ
HdhROUT
Ri
Control−output Transfer Function
(Hctrl_output(f)) FmHd
ǒ1)j2pf
wz1Ǔ
ǒ1)j2pf
wp1Ǔ
ǒ*j2pf
wz2Ǔ
ǒ1)j2pf
wnQp)ǒj2pf
wnǓ2Ǔ
Once the desired cross−over frequency (fc) gain adjustment and necessary phase boost are determined from the Hctrl_output(f)
gain and phase plots, the Table 2 equations may be used. It should be noted that minor compensation component value
adjustments may become necessary when R2 ≤ ~10 · Resd as a result of approximations for determining components R2, C1,
C2.
NCV8877
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16
Table 2. OTA COMPENSATION TRANSFER FUNCTION AND COMPENSATION VALUES
Desired OTA Gain at Cross−over
Frequency fc (G) 10desired_Gfc_gain_db
20
Desired Phase Boost at Cross−
over Frequency fc (boost) ǒqmargin *argǒHctrl_output(fc)Ǔ180°
p*90°Ǔp
180°
Select OTA Compensation Zero to
Coincide with Modulator Pole at
fp1 (fz)
wp1e
2p
Resulting OTA High Frequency
Pole Placement (fp)fzfc)fc2tan(boost)
fc*fztan(boost)
Compensation Resistor (R2)
fpG
fp*fz
VOUT
1.2 gm
1)ǒfc
fpǓ2
Ǹ
1)ǒfz
fpǓ
Ǹ
Compensation Capacitor (C1)1
2pf2R2
Compensation Capacitor (C2)1
2pfp
1.2 gm
VOUT
OTA DC Gain (G0_OTA)Vref
VOUT gmR0
Low Frequency Zero (wz1e)
1
2
ǒR2)ResdǓ
R2ResdC2ȧ
ȱ
Ȳ1*1*4R2ResdC2
ǒR2)ResdǓ2C1
Ǹȧ
ȳ
ȴ
High Frequency Zero (wz2e)
1
2
ǒR2)ResdǓ
R2ResdC2ȧ
ȱ
Ȳ1)1*4R2ResdC2
ǒR2)ResdǓ2C1
Ǹȧ
ȳ
ȴ
Low Frequency Pole (wp1e)1
2
ǒR0)R2)ResdǓ
R2ǒR0)ResdǓC2ȧ
ȱ
Ȳ1*1*4R2ǒR0)ResdǓC2
ǒR0)R2)ResdǓ2C1
Ǹȧ
ȳ
ȴ
High Frequency Pole (wp2e)1
2
ǒR0)R2)ResdǓ
R2ǒR0)ResdǓC2ȧ
ȱ
Ȳ1)1*4R2ǒR0)ResdǓC2
ǒR0)R2)ResdǓ2C1
Ǹȧ
ȳ
ȴ
OTA Transfer Function (GOTA(f))
−G0_OTA
1)j2pf
wz1e
1)j2pf
wp1e
1)j2pf
wz2e
1)j2pf
wp2e
The open−loop−response in closed−loop form to verify the gain/phase margins may be obtained from the following
expressions.
T(f) +GOTA(f)Hctrl_output(f)
NCV8877
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17
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
SEATING
PLANE
1
4
58
N
J
X 45_
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
BS
D
H
C
0.10 (0.004)
DIM
AMIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) ZSXS
M
____
1.52
0.060
7.0
0.275
0.6
0.024 1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
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