PIC24FJ16MC102-I/SS - Microchip Technology, Inc.

PIC24FJ16MC101/102

Data Sheet

High-Performance, Ultra Low Cost

16-bit Microcontrollers

Information contained in this publication regarding device

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and may be superseded by updates. It is your responsibility to

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intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

PIC32 logo, rfPIC and UNI/O are registered trademarks of

Microchip Te chnology Incorporated in the U.S.A. and other

countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, chipKIT,

chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,

dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,

FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,

Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,

MPLINK, mTouch, Omniscient C ode Generation, PICC,

PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,

rfLAB, Select Mode, Total Endurance, TSHARC,

UniWinDriver, WiperLock and ZENA are trademarks of

Microchip Te chnology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 978-1-61341-314-2

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:200 2 certif ication for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresh am, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microper ipher als, nonvol ati le memo ry and

analog product s. In addition, Microchip ’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

PIC24FJ16MC101/102

Operating Range:

• Up to 16 MIPS operation (3.0V-3.6V):

- Industrial temperature range (-40°C to +85 °C)

- Extended temperature range (-40°C to +125°C)

On-Chip Flash and SRAM:

• Flash program memory (16 Kbytes)

• Data SRAM (1 Kbyte)

• Security for program Flash

System Management:

• Flexible clock options:

- External, crystal, resonator, internal FRC

- Phase-Locked Lo op (PLL)

• High-accuracy internal FRC

- ± 0.25% typical

• Power-on Reset (POR)

• Power-up Timer (PWRT)

• Oscillator Start-up Timer (OST)

• Brown-out Reset (BOR)

• Watchdog Timer with its own RC oscillator

• Fail-Safe Clock Monitor (FSCM)

Motor Control PWM:

• 6-channel 16-bit Motor Control PWM:

- Three duty cycle generators

- Independent or Complementary mode

- Programmable dea d time and output polarity

- Edge-aligned or center-aligned

- Manual output override control

- Up to two Fault inputs

- Trigger for ADC conversions

- PWM frequency for 16-bit resolution

(@ 16 MIPS) = 488 Hz for Edge-Aligned mode,

244 Hz for Center-Aligned mode

- PWM frequency for 11-bit resolution

(@ 16 MIPS) = 15.63 kHz for Edge-Aligned mode,

7.81 kHz for Center-Aligned mode

Power Management:

• Single supply on-chip voltage regulator

• Switch between clock sources in real time

• Idle, Sleep, and Doze modes with fast wake-up

Analog Peripherals:

• 10-bit, 1.1 Msps Analog-to-Digital Converter (ADC):

- Two and four simultaneous samples

- Up to six input channels with auto-scanning

- Conversion start can be manual or

synchronized with one of four trigger sou rces

- Sleep mode conversion for low-power

applications

- ±2 LSb max integral nonli n ea ri ty

- ±1 LSb max differential nonlinearity

• Three Analog Comparators with programmable

input/output configuration:

- Up to four inputs per Comparator

- Blanking function

- Output digital filter

• Charge Time Measurement Unit (CTMU):

- Supports capacitive touch sensing for touch

screens and capacitive switches (mTouch™)

- Provides high-resolution time measurement

for advanced sensor applications

- 200 ps resolution for time measurement and

accurate temperature sensing

- On-chip high-resolution temperature

measurem ent capa b il i ty

High-Performance, Ultra Low Cost

16-bit Microcontrollers

PIC24FJ16MC101/102

Timers/Capture/Compare/PWM:

• Timer/Counters, up to three 16-bit timers:

- Can pair up to make one 32-bit timer

- One timer runs as Real-Time Clock with

external 32.768 kHz oscillator

- Programmable prescaler

• Input Capture (up to three channels):

- Capture on up, down, or both edges

- 16-bit cap ture input functions

- 4-deep FIFO on each captur e

• Output Compare (up to two channels):

- Single or Dual 16-bit Compare mode

- 16-bit Glitchle ss PWM mode

• Hardware Real-Time Clock and Calendar

(RTCC):

- Provides clock, calendar and alarm function

Digital I/O:

• Peripheral Pin Select functionality

• Up to 21 programmable digital I/O pins

• Wake-up/Interrupt-on-Change for up to 21 pins

• Output pins can drive from 3.0V to 3.6V

• Up to 5.5V output with open drain configura tion on

5V tolerant pins

• All digital input pins are 5V tolerant

• Up to 8 mA sink on designated pins

Communication Modules:

• 4-wire SPI:

- Framing supports I/O interface to simple

codecs

- Supports 8-bit and 16-bit data

- Supports all serial clock formats and

sampling modes

•I

2C™:

- Full Multi-Master Slav e mode support

- 7-bit and 10-bit addressing

- Bus collision detection and arbitration

- Integrated signal conditioning

- Slave address masking

•UART:

- Interrupt on address bit detect

- Interrupt on UART error

- Wake-up on Start bit from Sleep mode

- 4-character TX an d RX FIFO buffers

- LIN 2.0 bus support

-IrDA

® encoding and decoding in hardware

- High-Speed mode

- Hardware Flo w Control with CTS and RTS

Interrupt Controller:

• 5-cycle latency

• Up to 23 available interrupt sources

• Up to three external interrupts

• Seven programmable priority levels

• Four processor exceptions

High-Performance MCU CPU Features:

• Modified Harvard architecture

• C compiler optimized instruction set

• 16-bit-wide da ta path

• 24-bit-wide instructions

• Linear program memory addressing up to 4M

instruction words

• Linear data memory addressing up to 64 Kbytes

• 73 base instructions: mostly one word/one cycle

• Flexible and powerful indirect addressing mo de

• Software stack

• 16 x 16 integer multiply operati ons

• 32/16 and 16/16 integer divide operations

• Up to ±16-bit shifts

Packaging:

• 20-pin PDIP/SOIC/SSOP

• 28-pin SPDIP/SOIC/SSOP/QFN

• 28-pin QFN: 6x6 mm

• 36-pin TLA: 5x5 mm

Note: See Table 1 for the list of peripheral

features per device.

PIC24FJ16MC101/102

PIC24FJ16MC101/102 PRODUCT

FAMILIES

The device names, pin counts, memory sizes, and

peripheral availability of each device are listed in

Table 1. The following pages show their pinout

diagrams.

TABLE 1: PIC24FJ16MC101/102 CONTROLLER FAMILIES

Device

Pins

Program Flash (K byte)

RAM (Kbytes)

Remappable Peripherals

Motor Control PWM

PWM Faults

10-Bit, 1.1 Msps ADC

RTCC

I2C™

Comparators

CTMU

I/O Pins

Packages

Remappable Pins

16-bit Timer(1)

Input Capture

Output Compare

UART

External Interrupts(2)

SPI

PIC24FJ16MC101 20 16 1 10 3 3 2 1 3 1 6-ch 1 1 ADC,

4-ch Y13Y15PDIP,

SOIC,

SSOP

PIC24FJ16MC102 28 16 1 16 3 3 2 1 3 1 6-ch 2 1 ADC,

6-ch Y 1 3 Y 21 SPDIP,

SOIC,

SSOP,

QFN

36 16 1 16 3 3 2 1 3 1 6-ch 2 1 ADC,

6-ch Y13Y21 TLA

Note 1: Two out of thre e timers are remappable.

2: Two out of three interrupts are remappable.

PIC24FJ16MC101/102

Pin Diagrams

PIC24FJ16MC101

MCLR

VSS

PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0

PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1

VDD

VSS

PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0

FLTA1(2)/SCK1/INT0/RP7(1)/CN23/RB7

PGEC3/SOSCO/T1CK/CN0/RA4

PGED3/SOSCI/RP4(1)/CN1/RB4

PWM1H2/RP12(1)/CN14/RB12

OSCO/CLKO/CN29/RA3

OSCI/CLKI/CN30/RA2 VCAP

SDA1/SDI1/PWM1L3/RP9(1)/CN21/RB9

SCL1/SDO1/PWM1H3/RP8(1)/CN22/RB8

PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1

PWM1L1/RP15(1)/CN11/RB15

PWM1H1/RTCC/RP14(1)/CN12/RB14

PWM1L2/RP13(1)/CN13/RB13

20-Pin PDIP/SOIC/SSOP

Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available

peripherals.

2: The PWM Fault pins are enabled and asserted during any reset event. Refer to Section 15.2

“PWM Faults” for more information on the PWM faults.

PIC24FJ16MC102

MCLR

VSS

VDD

PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0

PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1

AVDD

AVSS

PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0

FLTA1(2)/ASCL1/RP6(1)/CN24/RB6

PGEC3/SOSCO/T1CK/CN0/RA4

PGED3/SOSCI/RP4(1)/CN1/RB4 VSS

OSCO/CLKO/CN29/RA3

OSCI/CLKI/CN30/RA2 VCAP

SCK1/INT0/RP7(1)/CN23/RB7

SDA1/SDI1/RP9(1)/CN21/RB9

SCL1/SDO1/RP8(1)/CN22/RB8

AN5/C3IND/C2IND/RP3(1)/CN7/RB3

AN4/C3INC/C2INC/RP2(1)/CN6/RB2

PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1

PWM1L1/RP15(1)/CN11/RB15

PWM1H1/RTCC/RP14(1)/CN12/RB14

PWM1L2/RP13(1)/CN13/RB13

PWM1H2/RP12(1)/CN14/RB12

PWM1H3/RP10(1)/CN16/RB10

PWM1L3/RP11(1)/CN15/RB11

FLTB1(2)/ASDA1/RP5(1)/CN27/RB5

28-Pin SPDIP/SOIC/SSOP

= Pins are up to 5V tolerant

PIC24FJ16MC101/102

Pin Diagrams (Continued)

28-Pin QFN

(2)

Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available

peripherals.

2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be

connected to VSS externally.

3: The PWM Fault pins are enabled and asserted during any reset event. Refer to Section 15.2

“PWM Faults” for more information on the PWM faults.

10 11

12 13 14 15

716

232425262728

PIC24FJ16MC102

MCLR

PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0

PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1

VSS

VCAP

SDA1/SDI1/RP9(1)/CN21/RB9

PWM1L2/RP13(1)/CN13/RB13

PWM1H2/RP12(1)/CN14/RB12

PWM1H3/RP10(1)/CN16/RB10

PWM1L3/RP11(1)/CN15/RB11

VSS

PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0

OSCO/CLKO/CN29/RA3

OSCI/CLKI/CN30/RA2

AN5/C3IND/C2IND/RP3(1)/CN7/RB3

AN4/C3INC/C2INC/RP2(1)/CN6/RB2

PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1

VDD

PGEC3/SOSCO/T1CK/CN0/RA4

FLTB1(3)/ASDA1/RP5(1)/CN27/RB5

PGED3/SOSCI/RP4(1)/CN1/RB4

FLTA1(3)/ASCL1/RP6(1)/CN24/RB6

SCK1/INT0/RP7(1)/CN23/RB7

SCL1/SDO1/RP8(1)/CN22/RB8

AVDD

AVSS

PWM1L1/RP15(1)/CN11/RB15

PWM1H1/RTCC/RP14(1)/CN12/RB14

= Pins are up to 5V tolerant

PIC24FJ16MC101/102

Pin Diagrams (Continued)

36-Pin TLA

Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available

peripherals.

2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be

connected to VSS externally.

3: The PWM Fault pins are enabled and asserted during any reset event. Refer to Section 15.2

“PWM Faults” for more information on the PWM faults.

N/C

PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0

PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1

MCLR

AVDD

PWM1L1/RP15

(1)

/CN11/RB15

PWM1H1/RTCC/RP14

(1)

/CN12/RB14

AVSS

N/C

VSS

SDA1/SDI1/RP9

(1)

/CN21/RB9

PWM1L2/RP13

(1)

/CN13/RB13

PWM1H2/RP12

(1)

/CN14/RB12

PWM1H3/RP10

(1)

/CN16/RB10

PWM1L3/RP11

(1)

/CN15/RB11

VDD

VCAP

VDD

PGED1/AN2/C2INA/C1INC/RP0

(1)

/CN4/RB0

PGED3/SOSCI/RP4

(1)

/CN1/RB4

OSCO/CLKO/CN29/RA3

AN5/C3IND/C2IND/RP3

(1)

/CN7/RB3

AN4/C3INC/C2INC/RP2

(1)

/CN6/RB2

PGEC1/AN3/

REFIN

/CV

REFOUT

/C2INB/C1IND/RP1

(1)

/CN5/RB1

VSS

OSCI/CLKI/CN30/RA2

N/C (Vss)

N/C

FLTB1(3)/ASDA1/RP5(1)/CN27/RB5

PGEC3/SOSCO/T1CK/CN0/RA4

FLTA1(3)/ASCL1/RP6(1)/CN24/RB6

SCK1/INT0/RP7(1)/CN23/RB7

SCL1/SDO1/RP8(1)/CN22/RB8

VDD

N/C (VDD)

PIC24FJ16MC102

= Pins are up to 5V tolerant

33 32 31 30 29 28

11 12 13 14 15

16 17 18

PIC24FJ16MC101/102

Table of Content s

PIC24FJ16MC101/102 Product Families............................................................................................................................................... 5

1.0 Device Overview ........................................................................................................................................................................ 11

2.0 Guidelines for Getting Started with 16-bit Microcontrollers........................................................................................................ 17

3.0 CPU............................................................................................................................................................................................ 21

4.0 Memory Organization................................................................................................................................................................. 27

5.0 Flash Program Memory.............................................................................................................................................................. 51

6.0 Resets ....................................................................................................................................................................................... 55

7.0 Interrupt Controller ..................................................................................................................................................................... 63

8.0 Oscillator Configuration.............................................................................................................................................................. 93

9.0 Power-Saving Features............................................................................................................................................................ 101

10.0 I/O Ports................................................................................................................................................................................... 107

11.0 Timer1...................................................................................................................................................................................... 123

12.0 Timer2/3 Feature ..................................................................................................................................................................... 125

13.0 Input Ca pture............................................................................................................................................................................ 131

14.0 Output Compare....................................................................................................................................................................... 133

15.0 Motor Control PWM Module..................................................................................................................................................... 137

16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 153

17.0 Inter-Integrated Circuit™ (I2C™).............................................................................................................................................. 159

18.0 Universal Asynchronous Receiver Transmitter (UART)........................................................................................................... 167

19.0 10-bit Analog-to -Digital Converter (ADC)................................................................................................................................. 173

20.0 Comparator Module.................................................................................................................................................................. 185

21.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 199

22.0 Charge Time Measurement Unit (CTMU) ............................................................................................................................... 209

23.0 Special Features ...................................................................................................................................................................... 215

24.0 Instruction Set Summary.......................................................................................................................................................... 223

25.0 Development Support............................................................................................................................................................... 231

26.0 Electrical Characteristics.......................................................................................................................................................... 235

27.0 Packaging Information.............................................................................................................................................................. 277

Appendix A: Revision History............................................................................................................................................................. 295

Index ................................................................................................................................................................................................. 297

The Microchip Web Site..................................................................................................................................................................... 301

Customer Change Notification Service.............................................................................................................................................. 301

Customer Support.............................................................................................................................................................................. 301

Reader Response................................................................................................. ............................................................................. 302

Product Identification System ............................................................................................................................................................ 303

PIC24FJ16MC101/102

TO OUR VALUED CUSTOMERS

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

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silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

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Customer Notific at ion Syst em

PIC24FJ16MC101/102

1.0 DEVICE OVERVIEW

This document contains device specific information for

the PIC24FJ16MC101/102 Microcontroller (MCU)

devices. Central to all PIC24F devices is the 16-bit

modified Harvard architecture, first introduced with

Microchip’s dsPIC® digital signal controllers.

Figure 1-1 shows a genera l block diagram of the core

and peripheral modules in the PIC24FJ16MC101/102

family of devices. Table 1-1 lists the functions of the

various pins shown in the pinout diagrams.

Note 1: This data sheet sum marizes the features

of the PIC24FJ16MC101/102 devices.

However, it i s not intended to be a co m-

prehensive reference source. To comple-

ment the information in this data sheet,

refer to the latest family reference sec-

tions of the “PIC24F Family Reference

Manual”, which are available from the

Microchip web site (www.microchip.com).

2: It is important to note that the

specifications in Section 26.0 “Electri-

cal Characteristics” of this data sheet,

supercede any specifications that may be

provided in PIC24F Family Reference

Manual sections.

PIC24FJ16MC101/102

FIGURE 1-1: PIC24FJ16MC101/102 BLOCK DIAGRAM

OSC1/CLKI

OSC2/CLKO

VDD, VSS

Timing

Generation

MCLR

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Precision

Reference

Band Gap

FRC/LPRC

Oscillators

Regulator

Voltage

VCAP

IC1-IC3 I2C1

PORTA

Note: Not all pins or features are implemented on all device pinout configurations. See “Pin Diagrams” for the specific pins

and features present on each device.

Instruction

Decode and

Control

PCH PCL

Program Counter

16-bit ALU

Instruction Reg

PCU

16 x 16

W Register Array

ROM Latch

EA MUX

Interrupt

Controller

PSV and Table

Data Access

Control Block

Stack

Control

Logic

Loop

Control

Logic

Address Latch

Program Memory

Data Latch

Literal Data

16 16

Data Latch

Address

Latch

X RAM

X Data Bus

17 x 17 Multiplier

Divide Support

Control Signals

to Various Blocks

ADC1

Timers

PORTB

Address Generator Unit s

1-3

CNx

UART1 OC/

PWM1-2 RTCC

PWM

6 Ch

Remappable

Pins

SPI1

CTMU External

Interrupts

1-3

Comparators

1-3

PIC24FJ16MC101/102

TABLE 1-1: PINOUT I/O DESCRIPTIONS

Pin Name Pin

Type Buffer

Type PPS Description

AN0-AN5 I Analog No Analog input channels.

CLKI

CLKO I

OST/

CMOS

—

No External clock source input. Always associated with OSC1 pin function.

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator

mode. Optionally functions as CLKO in RC and EC modes. Always

associated with OSC2 pin function.

OSC1

OSC2

I/O

ST/

CMOS

—

Oscillator crystal input. ST buffer when configured in RC mode; CMOS

otherwise.

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator

mode. Optionally functions as CLKO in RC and EC modes.

SOSCI

SOSCO I

OST/

CMOS

—

No 32.768 kHz low-power oscillator crystal input; CMOS otherwise.

32.768 kHz low-power oscillator crystal output.

CN0-CN7

CN11-CN16

CN21-CN24

CN27

CN29-CN30

IST

Change notification inputs. Can be software programmed for internal weak

pull-ups on all inputs.

IC1-IC3 I ST Yes Capture inputs 1/2/3.

OCFA

OC1-OC2 I

OST

—Yes

Yes Compare Fault A input (for Compare Channels 1 and 2).

Compare outputs 1 through 2.

INT0

INT1

INT2

Yes

External interrupt 0.

External interrupt 1.

External interrupt 2.

RA0-RA4 I/O ST No PORTA is a bidirectional I/O port.

RB0-RB15 I/O ST No PORTB is a bidirectional I/O port.

T1CK

T2CK

T3CK

Yes

Timer1 external clock input.

Timer2 external clock input.

Timer3 external clock input.

U1CTS

U1RTS

U1RX

U1TX

—

Yes

UART1 clear to send.

UART1 ready to send.

UART1 receive.

UART1 transmit.

SCK1

SDI1

SDO1

SS1

I/O

—

Yes

Synchronous serial clock input/output for SPI1.

SPI1 data in.

SPI1 data out.

SPI1 slave synchronization or frame pulse I/O.

SCL1

SDA1

ASCL1

ASDA1

I/O

Synchronous serial clock input/output for I2C1.

Synchronous serial data input/output for I2C1.

Alternate synchronous serial clock input/o utput for I2C1.

Alternate synchronous serial data input/output for I2C1.

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

PPS = Peripheral Pin Select

Note 1: An external pull-down resistor is required for the FLTA1 pin on PIC24FJ16MC101 (20-pin) devi ces .

2: The FLTB1 pin is not available on PIC24FJ16MC101 (20-pin) devices.

3: The PWM Fault pins are enab led during any reset event. Refer to Section 15.2 “PWM Faults” for more

information on the PWM faults.

PIC24FJ16MC101/102

FLTA1(1,3)

FLTB1(2,3)

PWM1L1

PWM1H1

PWM1L2

PWM1H2

PWM1L3

PWM1H3

—

PWM1 Fault A input.

PWM1 Fault B input.

PWM1 Low output 1.

PWM1 High out pu t 1.

PWM1 Low output 2.

PWM1 High out pu t 2.

PWM1 Low output 3.

PWM1 High out pu t 3.

RTCC O Digital No RTCC Alarm output.

CTPLS

CTED1

CTED2

Digital

Yes

CTMU Pulse Output.

CTMU External Edge Input 1.

CTMU External Edge Input 2.

CVREF

C1INA

C1INB

C1INC

C1IND

C1OUT

C2INA

C2INB

C2INC

C2IND

C2OUT

C3INA

C3INB

C3INC

C3IND

C3OUT

Analog

Digital

Analog

Digital

Analog

Digital

Yes

Comparator Voltage Positive Reference Input.

Comparator 1 Positive Input A.

Comparator 1 Negative Input B.

Comparator 1 Negative Input C.

Comparator 1 Negative Input D.

Comparator 1 Output.

Comparator 2 Positive Input A.

Comparator 2 Negative Input B.

Comparator 2 Negative Input C.

Comparator 2 Negative Input D.

Comparator 2 Output.

Comparator 3 Positive Input A.

Comparator 3 Negative Input B.

Comparator 3 Negative Input C.

Comparator 3 Negative Input D.

Comparator 3 Output.

PGED1

PGEC1

PGED2

PGEC2

PGED3

PGEC3

I/O

Data I/O pin for programming/debugging communicati on channel 1.

Clock input pin for programming/de bugging communication channel 1.

Data I/O pin for programming/debugging communicati on channel 2.

Clock input pin for programming/de bugging communication channel 2.

Data I/O pin for programming/debugging communicati on channel 3.

Clock input pin for programming/de bugging communication channel 3.

MCLR I/P ST No Master Clear (Reset) input. This pin is an active-low Reset to the device.

AVDD P P No Positive suppl y for analog modules. This pin must be connected at all times.

For devices without this pin, this signal is connected to VDD internally.

AVSS P P No Ground reference for analog modules. For devices without this pin, this signal

is connected to VSS internally.

VDD P — No Positive supply for peripheral logic and I/O pins.

VCAP P — No CPU logic filter capacitor connection.

VSS P — No Ground reference for logic and I/O pins.

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin

Type Buffer

Type PPS Description

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

PPS = Peripheral Pin Select

Note 1: An external pull-down resistor is required for the FLTA1 pin on PIC24FJ16MC101 (20-pin) devices.

2: The FLTB1 pin is not available on PIC24FJ16MC101 (20-pin ) devices.

3: The PWM Fault pins are enabled during any reset event. Refer to Section 15.2 “PWM Faults” for more

information on the PWM faults.

PIC24FJ16MC101/102

1.1 Referenced Sources

This device data sheet is based on the following

individual chapters of the “PIC24F Family Reference

Manual”. These documents should be considered as

the primary reference for the operation of a particular

module or device feature.

•Section 1. “Introduction” (DS39718)

•Section 2. “CPU” (DS39703)

•Section 3. “Data Memory” (DS39717)

•Section 4. “Program Memory” (DS39715)

•Section 6. “Oscillator” (DS39700)

•Section 7. “Reset” (DS39712)

•Section 8. “Interrupts” (DS39707)

•Section 9. “Watchdog Timer (WDT)” (DS39697)

•Section 10. “Power-Saving Features” (DS39698)

•Section 11. “Charge Time Measurement Unit (CTMU)” (DS39724)

•Section 12. “I/O Ports with Peripheral Pin Select (PPS)” (DS39711)

•Section 14. “Timers” (DS39704)

•Section 15. “Input Capture” (DS39701)

•Section 16. “Output Compare” (DS39706)

•Section 21. “UART” (DS39708)

•Section 23. “Serial Peripheral Interface (SPI)” (DS39 699)

•Section 24. “Inter-Integrated Circuit™ (I2C™)” (DS39702)

•Section 29. “Real-Time Clock and Calendar (RTCC)” (DS39696)

•Section 32. “High-Level Device Integration” (DS39719)

•Section 33. “Programming and Diagnostics” (DS39716)

•Section 46. “10-bit Analog-to-Digital Converter (ADC) with 4 Simultaneous Conversions” (DS39737)

•Section 47. “Motor Control PWM” (DS39735)

•Section 48. “Comparator with Blanking” (DS39741)

Note: To access the documents listed below,

browse to the specific device product

page of the Microchip web site

(www.microchip.com).

In addition to parameters, features, and

other documentation, the resulting page

provides links to the related family

reference manual sections.

PIC24FJ16MC101/102

Notes:

PIC24FJ16MC101/102

2.0 GUIDELINES FOR GETTING

STARTED WITH 16-BIT

MICROCONTROLLERS

2.1 Basic Connection Requirements

Getting started with the PIC24FJ16MC101/102 family

of 16-bit microcontrollers (MCUs) requi res attention to

a minimal set of device pin connections before

proceeding with development. Th e following is a list of

pin names, which must always be connected:

• All VDD and VSS pins

(see Section 2.2 “Decoupling Capacitors”)

• All AVDD and AVSS pins, if present on the device

(regardless if ADC module is not used)

(see Section 2.2 “Decoupling Capacitors”)

•V

CAP

(see Section 2.3 “CPU Logic Filter Capa ci tor

Connection (VCAP)”)

•MCLR

(see Section 2.4 “Master Clear (MCLR) Pin”)

• PGECx/PGEDx pins used for In-Circuit Serial

Programming™ (ICSP™) and debugging purposes

(see Section 2.5 “ICSP Pins”)

• OSC1 and OSC2 pins when external oscillator

source is used

(see Section 2.6 “External Oscillato r Pin s”)

2.2 Decoupling Capacitors

The use of decoupling capacitors on every pair of

power supply pins, such as VDD, VSS, AVDD, and

AVSS is required.

Consider the following criteria when using decoupling

capacitors:

•Value and type of capacitor: Recommendation

of 0.1 µF (100 nF), 10 V – 20 V. This capacitor

should be a low-ESR and have resonance

frequency in the range of 20 MHz and higher. It is

recommended that ceramic capacitors be used.

•Placement on the printed circuit board: The

decoupling capacitors should be placed as close

to the pins as possible. It is recommended to

place the capacitors on the same side of the

board as the device. If space is constricted, the

capacitor can be placed on another layer on the

PCB using a via; however, ensure that the trace

length from the pin to the capacitor is within

one-quarter inch (6 mm) in length.

•Handling high freque nc y nois e : If the board is

experiencing high frequency noise, upward of

tens of MHz, add a second ceramic-type capacitor

in parallel to the above described decoupling

capacitor. The value of the second capacitor can

be in the range of 0.01 µF to 0.001 µF. Place this

second capacitor next to the primary decoupling

capacitor. In high-speed circuit designs, consider

implementing a decade pair of capacitances as

close to the power and ground pins as possible.

For example, 0.1 µF in parallel with 0.001 µF.

•Maximizing performance: On the board layout

from the power supply circuit, run the power and

return traces to the decoupling capacitors first,

and then to the device pins. This ensures that the

decoupling capacitors are first in the power chain.

Equally important is to keep the trace length

between the capacitor and the power pins to a

minimum thereby reducing PCB track inductance.

Note 1: This data sheet summarizes the features

of the PIC24FJ16MC101/102 family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to the “PIC24F Family Refer-

ence Manual”. Please see the Microchip

web site (www.microchip.com) for the lat-

est PIC24F Family Reference Manual

sections.

2: It is important to note that the

specifications in Section 26.0 “Electri-

cal Characteristics” of this data sheet,

supercede any specifications that may be

provided in PIC24F Family Reference

Manual sections.

3: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

PIC24FJ16MC101/102

FIGURE 2-1: RECOMMENDED

MINIMUM CONNECT I ON

2.2.1 TANK CAPACITORS

On boards with power traces running longer than six

inches in length, it is suggested to use a tank capacitor

for integrated circuits including MCUs to supp ly a local

power source. The value of the tank capacitor should

be determined based on the trace resistance that con-

nects the power supply source to the device, and the

maximum current drawn by the device in the applica-

tion. In other words, select the tank capacitor so that it

meets the acceptable voltage sag at the device. T ypical

values range from 4.7 µF to 47 µF.

2.3 CPU Logic Filter Capacitor

Connection (VCAP)

A low-ESR (< 5 Ohms) capacitor is required on the

VCAP pin, which is used to stabilize the voltage

regulator output voltage. The VCAP pin must not be

connected to VDD, and must have a capacitor between

4.7 µF and 10 µF, 16V connected to ground. The typ e

can be ceramic or tantalum. Refer to Section 26.0

“Electrical Characteristics” for additional

information.

The placement of this capacitor should be close to th e

VCAP. It is recommended that the trace length not

exceed one-quarter inch (6 mm). Refer to Section 23.2

“On-Chip Voltage Regulator” for details.

2.4 Master Clear (MCLR) Pin

The MCLR pin provides two specific device

functions:

• Devic e Re set

• Device programming and debugging

During device programming and debugging, the

resistance and capacitance that can be added to the

pin must be considered. Device programmers and

debuggers drive the MCLR pin. Consequently,

specific voltage levels (VIH and VIL) and fast signal

transitions must not be adversely affected. Therefore,

specific values of R and C will need to be adjusted

based on the application a nd PCB requirements.

For example, as shown in Figure 2-2, it is

recommended that the capacitor C, be isolated from

the MCLR pin during programming and debugging

operations.

Place the components shown in Figure 2-2 within

one-quarter inch (6 mm) from the MCLR pin.

FIGURE 2-2: EXAMPLE OF MCLR PIN

CONNECTIONS

PIC24F

VDD

VSS

VDD

VSS

VDD

AVDD

AVSS

VDD

VSS

0.1 µF

Ceramic 0.1 µF

Ceramic

0.1 µF

Ceramic

0.1 µF

Ceramic

VDD

MCLR

0.1 µF

Ceramic

VCAP

10 Ω

10 µF

Tantalum

Note 1: R≤ 10 kΩ is recommended. A suggested

starting value is 10 kΩ. Ensure that the MCLR

pin VIH and VIL specifications are met.

2: R1 ≤ 470Ω will limit any current flowing into

MCLR from the external capacitor C, in the

event of MCLR pin breakdown, due to

Electrostatic Discharge (ESD) or Electrical

Overstress (EOS). Ensure that the MCLR pin

VIH and VIL specifications are met.

VDD

MCLR

PIC24F

PIC24FJ16MC101/102

2.5 ICSP Pins

The PGECx and PGEDx pins are used for In-Circuit

Serial Programming™ (ICSP™) and debugging pur-

poses. It is recommended to keep the trace length

between the ICSP connector and the ICSP pins on the

device as short as possible. If the ICSP connector is

expected to experience an ESD event, a series resistor

is recommended, with the value in the range of a few

tens of Ohms, not to exceed 100 Ohms.

Pull-up resisto rs, series diodes, and capacitors on th e

PGECx and PGEDx pins are not recommended as they

will interfere with the programmer/debugger

communications to the device. If such discrete

components are an application requirement, they

should be removed from the circuit during

programming and debugging. Alternately, refer to the

AC/DC characteristics and timing requirements infor-

mation in the “PIC24FJXXMCXXX Flash Programming

Specification” for information on capacitive loading

limits and pin input voltage high (VIH) and input low

(VIL) requirements.

Ensure that the “Communication Ch annel Sele ct” (i.e .,

PGECx/PGEDx pins) programmed into the device

matches the physical connections for the ICSP to

MPLAB® ICD 2, MPLAB ICD 3, or MPLAB REAL

ICE™.

For more information on ICD 2, ICD 3, and REAL ICE

connection requirements, refer to the following

documents that are available on the Microchip web

site.

•“MPLAB® ICD 2 In-Circuit Debugger User’s

Guide” (DS51331)

•“Using MPLAB® ICD 2” (poster) (DS51265)

•“MPLAB® ICD 2 Design Advisory” (DS51566)

•“Using MPLAB® ICD 3” (poster) (DS51765)

•“MPLAB® ICD 3 Design Advisory” (DS51764)

•“MPLAB® REAL ICE™ In-Circuit Debugger

User’s Guide” (DS51616)

•“Using MPLAB® REAL ICE™” (poster) (DS51749)

2.6 External Oscillator Pins

Many MCUs have options for at least two oscillators: a

high-frequency primary oscillator and a low-frequency

secondary oscillator (refer to Section 8.0 “Oscillator

Configuration” for details).

The oscillator circuit should be placed on the same

side of the board as the device. Also, place the

oscillator circuit close to the respective oscillato r pins,

not exceeding one-half inch (12 mm) distance

between them. The load capacitors should be placed

next to the oscillator itself, on the same side of the

board. Use a grounded copper pour around the

oscillator circuit to isolate them from surrounding

circuits. The grounded copper pour should be routed

directly to the MCU ground. Do not run any signal

traces or power traces inside the ground pour. Also, if

using a two-sided board, avoid any traces on the

other side of the board where the crystal is placed. A

suggested layout is shown in Figure 2-3.

FIGURE 2-3: SUGGESTED PLACEMENT

OF THE OSCILLATOR

CIRCUIT

Main Oscillator

Guard Ring

Guard Trace

Secondary

Oscillator

PIC24FJ16MC101/102

2.7 Oscillator Value Conditions on

Device Start-up

If the PLL of the target device is enabled and

configured for the device start-up oscillator, the

maximum oscillator source frequency must be limited

to 4 MHz < FIN < 8 MHz (for MSPLL mode) or 3 MHz <

FIN < 8 MHz (for ECPLL mode) to comply with device

PLL start-up conditions. HSPLL mode is not supported.

This means that if the external oscillator frequency is

outside this range, the application must start-up in th e

FRC mode first. The fixed PLL settings of 4x after a

POR with an oscillator frequency outside this range will

violate the device operating speed.

Once the device powers up, the application firmware

can enable the PLL, and then perform a clock switch to

the Oscillator + PLL clock source. Note that clock

switching must be enabled in the device Configuratio n

word.

2.8 Configuration of Analog and

Digital Pins During ICSP

Operations

If MPLAB ICD 2, MPLAB ICD 3, or MPLAB REAL ICE

in-circuit emulator is selected as a debugger, it

automatically initializes all of the analog-to-digital input

pins (ANx) as “digital” pins, by setting all bits in the

AD1PCFGL regist er.

The bits in the register that correspond to the

analog-to-digital pins that are initialized by MPLAB ICD

2, MPLAB ICD 3, or MPLAB REAL ICE in-circuit

emulator, must not be cleared by the user application

firmware; otherwise, communication errors will result

between the debugger and the device.

If your application needs to use certain analog-to-digital

pins as analog input pins during the debug session, the

user application must clear the corresponding bits in

the AD1PCFGL register during initialization of the ADC

module.

When MPLAB ICD 2, MPLAB ICD 3, or MPLAB REAL

ICE in-circuit emulator is used as a programmer, the

user application firmware must correctly configure the

AD1PCFGL register. Automatic initialization of this

Failure to correctly configure the register(s) will result in

all analog-to-digital pins being recognized as analog

input pins, resulting in the port value being read as a

logic ‘0’, which may affect user application functionality .

2.9 Unused I/Os

Unused I/O pi ns should be configured as outputs and

driven to a logic-low state.

Alternately, connect a 1k to 10k resistor between VSS

and unused pins.

PIC24FJ16MC101/102

3.0 CPU

The PIC24FJ16MC101/102 CPU module has a 16-bit

(data) modified Harvard architecture with an enhanced

instruction set and addressi ng modes. The CPU has a

24-bit instruction word with a variable length opcode

field. The Program Counter (PC) is 23 bits wide and

addresses up to 4M by 24 bits of user program memory

space. The actual amount of program memory

implemented varies by device. A single-cycle

instruction prefetch mechanism is used to help

maintain throughput and provides predictable

execution. All instructions execute in a single cycle,

with the exception of instructions that change the

program flow, the double-word move (MOV.D)

instruction and the table instructions. Overhead-free,

single-cycle program loop constructs are supported

using the REPEAT instruction, which is interruptible at

any point.

The PIC24FJ16MC101/102 devices have sixteen, 16-bit

working registers in the programmer’s model. Each of the

working registers can serve as a data, address or

address offset register. The 16th working register (W15)

operates as a software Stack Pointer (SP) for interrupts

and calls.

The PIC24FJ16MC101/102 instruction set includes

many addressing modes and is designe d for optimum

C compiler efficiency. For most instructions,

PIC24FJ16MC101/102 devices are capable of

executing a data (or program data) memory read, a

working register (data) read, a data memory write, and

a program (instruction) memory read per instruction

cycle. As a result, three parameter instructions can be

supported, allowing A + B = C operations to be

executed in a single cycle.

A block diagram of the CPU is shown in Figure 3-1,

and the programmer’s model for the

PIC24FJ16MC101/102 is shown in Figure 3-2.

3.1 Data Addressing Overview

The data sp ace can be linearly addressed as 32K words

or 64 Kbytes using an Address Generation Unit (AGU).

The upper 32 Kbytes of the data sp ace memory map can

optionally be mapped into program space at any 16K

program word boundary defined by the 8-bit Program

S pace Visibility Page register (PSVP AG). The program to

data space mapping feature lets any instruction access

program space as if it were data space.

The data space also includes 2 Kbytes of DMA RAM,

which is primarily used for DMA data transfers, but may

be used as general purpose RAM.

3.2 Special MCU Features

The PIC24FJ16MC101/102 features a 17-bit by 17-bit,

single-cycle multiplier. The multiplier can perform

signed, unsigned and mixed-sign multiplication. Using

a 17-bit by 17-bit multiplier for 16-bit by 16-bit

multiplication makes mixed-sign multiplication

possible.

The PIC24FJ16MC101/102 su pports 16/16 and 32/16

integer divide operations. All divide instructions are

iterative operations. They must be executed within a

REPEAT loop, resulting in a total execution time of 19

instruction cycles. The divide operation can be

interrupted during any of those 19 cycles without loss

of data.

A multi-bit data shifter is used to perform up to a 16-bit,

left or right shift in a single cycle.

Note 1: This data sheet summarizes the fe atures

of the PIC24FJ16MC101/102 family of

devices. However, it is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to Section 2. “CPU”

(DS39703) in the “PIC24F Family Refer-

ence Manual”, which is available from the

Microchip web site (www.microchip.com).

2: It is important to note that the

specifications in Section 26.0 “Electri-

cal Characteristics” of this data sheet,

supercede any specifications that may be

provided in PIC24F Family Reference

Manual sections.

3: Some registers and associated bits

described in this section may not be avail-

able on all devices . Refer to Section 4.0

“Memory Organization” in this data

sheet for device-specific register and bit

information.

PIC24FJ16MC101/102

FIGURE 3-1: PIC24FJ16MC101/102 CPU CORE BLOCK DIAGRAM

Instruction

Decode and

Control

PCH PCL

Program Counter

16-bit ALU

Instruction Reg

PCU

16 x 16

W Register Array

ROM Latch

EA MUX

Interrupt

Controller

Stack

Control

Logic

Loop

Control

Logic

Control Signals

to Various Blocks

Literal Data

16 16

To Peripheral Modules

Data Latch

Address

Latch

X RAM

Address Generator Units

X Data Bus

17 x 17

Divide Support

PSV and Table

Data Access

Control Block

Program Memory

Data Latch

Address Latch

Multiplier

PIC24FJ16MC101/102

FIGURE 3-2: PIC24FJ16MC101/102 PROGRAMMER’S MODEL

PC22 PC0

7 0

D0D15

Program Counter

Data Table Page Address

STATUS Register

Working Registers

W10

W11

W12

W13

W14/Frame Pointer

W15/Stack Pointer

7 0Program Space Visibility Page Address

— — ——

RCOUNT

15 0REPEAT Loop Counter

IPL2 IPL1

SPLIM Stack Pointer Limit Register

SRL

PUSH.S Shadow

DO Shadow

— —

15 0Core Configuration Register

Legend

CORCON

— DC RA N

TBLPAG

PSVPAG

IPL0 OV

W0/WREG

SRH

PIC24FJ16MC101/102

3.3 CPU Control Registers

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — —DC

bit 15 bit 8

R/W-0(1) R/W-0(2) R/W-0(2) R-0 R/W-0 R/W-0 R/W-0 R/W-0

IPL<2:0>(2) RA N OV Z C

bit 7 bit 0

Legend:

C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’

S = Set only bit W = Writable bit -n = Value at PO R

‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-9 Unimplemented: Read as ‘0’

bit 8 DC: MCU ALU Half Carry/Borrow bit

1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)

of the result occurred

0 = No carry-out from th e 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized

data) of the result occurred

bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2)

111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled

110 = CPU Interrupt Priority Level is 6 (14)

101 = CPU Interrupt Priority Level is 5 (13)

100 = CPU Interrupt Priority Level is 4 (12)

011 = CPU Interrupt Priority Level is 3 (11)

010 = CPU Interrupt Priority Level is 2 (10)

001 = CPU Interrupt Priority Level is 1 (9)

000 = CPU Interrupt Priority Level is 0 (8)

bit 4 RA: REPEAT Loop Active bit

1 = REPEAT loop in progress

0 = REPEAT loop not in progress

bit 3 N: MCU ALU Negative bit

1 = Result was negative

0 = Result was non-negative (zero or positive)

bit 2 OV: MCU ALU Overflow bit

This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the magnitude which

causes the sign bit to change state.

1 = Overflow occurred for signed arithmetic (in this arithmetic operation)

0 = No overflow occurred

bit 1 Z: MCU ALU Zero bit

1 = An operation which affects the Z bit has set it at some time in the past

0 = The most recent operation which affects the Z bit has cleared it (i.e., a non-zero re sult)

bit 0 C: MCU ALU Carry/Borrow bit

1 = A carry-out from the Most Significant bit (MSb) of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note 1: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority

Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when

IPL<3> = 1.

2: The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>).

PIC24FJ16MC101/102

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 R/C-0 R/W-0 U-0 U-0

— — — —IPL3

(1) PSV — —

bit 7 bit 0

Legend: C = Clear only bit

R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set

0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’

bit 15-4 Unimplemented: Read as ‘0’

bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(1)

1 = CPU interrupt priority level is greater than 7

0 = CPU interrupt priority level is 7 or less

bit 2 PSV: Program Space Visibility in Data Space Enable bit

1 = Program space visible in data space

0 = Program space not visible in data space

bit 1-0 Unimplemented: Read as ‘0’

Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.

PIC24FJ16MC101/102

3.4 Arithmetic Logic Unit (ALU)

The PIC24FJ16MC101/102 AL U is 16 bits wide a nd is

capable of addition, subtraction, bit shifts, and logic

operations. Unless otherwise mentioned, arithmetic

operations are 2’s complement in nature. Depending

on the operation, the ALU may affect the values of the

Carry (C), Zero (Z), Negative (N), Overflow (OV), and

Digit Carry (DC) Status bits in the SR register. The C

and DC S tatus bit s operate as Borrow and Digit Borrow

bits, respectively, for subtraction ope rations.

The ALU can perform 8-bit or 16-bit operations,

depending on the mode of the instruction that is used.

Data for the ALU operation can come from the W reg-

ister array, or data memory, depending on the address-

ing mode of the instruction. Likewise , output data from

the ALU can be written to t he W register ar ray or a dat a

memory location.

Refer to the “16-bit MCU and DSC Programmer’s

Reference Manual” (DS70157) for information on the

SR bits affected by each instruction.

The PIC24FJ16MC101/102 CPU incorporates hard-

ware support for both multiplication and division. This

includes a dedicated hardware multiplier and support

hardware for 16-bit divisor division.

3.4.1 MULTIPLIER

Using the high-speed 17-bit x 17-bit multiplier, the ALU

supports unsigned, signed or mixed-sign operation in

several multiplication modes:

• 16-bit x 16-bit signed

• 16-bit x 16-bit unsigned

• 16-bit signed x 5-bit (literal) unsigned

• 16-bit unsigned x 16-bit unsigned

• 16-bit unsigned x 5-bit (literal) unsigned

• 16-bit unsigned x 16-bit signed

• 8-bit unsigned x 8-bit unsigned

3.4.2 DIVIDER

The divide block supports 32-bit/16-bit and 16-bit/16-bit

signed and unsigned integer divide operations with the

following data sizes:

• 32-bit signed/16-bit signed divide

• 32-bit unsigned/16-bit unsigned divide

• 16-bit signed/16-bit signed divide

• 16-bit unsigned/16-bit unsigned divide

The quotient for all divide instructions ends up in W0

and the remainder in W1. Sixteen-bit signed and

unsigned DIV instructions can specify any W register

for both the 16-bit divisor (Wn) and any W register

(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.

The divide algorithm takes one cycl e per bit of divisor,

so both 32-bit/16-bit and 16-bit/16-bit instructions take

the same number of cycles to execute.

3.4.3 MULTI-BIT DATA SHIFTER

The multi-bit data shifter is capable of performing up to

16-bit arithmetic or logic righ t shifts, or up to 16-bit left

shifts in a single cycle. The source can be either a

working register or a memory locati on.

The shifter requires a signed binary value to determine

both the magnitude (number of bits) and direction of the

shift operation. A positive value shifts the operand right.

A negative value shifts the operand left. A value o f ‘0’

does not modify the operand.

PIC24FJ16MC101/102

4.0 MEMORY ORGANIZATION The PIC24FJ16MC101/102 architecture features

separate program and data memory spaces and

buses. This architecture also allows the direct access

of program memory from the data space during code

execution.

4.1 Program Address Space

The program address memory space of the

PIC24FJ16MC101/102 devices is 4M instructions. The

space is addressable by a 24-bit value derived either

from the 23-bit Program Counter (PC) during program

execution, or from table operation or data space

remapping as described in Section 4.4 “Interfacing

Program and Data Memory Spa ces”.

User application access to the program memory space

is restricted to the lower half of the address range

(0x000000 to 0x7FFFFF). T he exception is the use of

TBLRD/TBLWT operations, which use TBLPAG<7> to

permit access to the Configuration bits and Device ID

sections of the configuration memory space.

The memory map for the PIC24FJ16MC101/102 family

of devices is shown in Figure 4-1.

FIGURE 4-1: PROGRAM MEMORY MAP FOR PIC24FJ16MC101/102 DEVICES

Note 1: This data sheet summarizes the features

of the PIC24FJ16MC101/102 family of

devices. However , it is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to Section 3. “Dat a Memory”

(DS39717) and Section 4. “Program

Memory” (DS39715) in the “PIC24F

Family Reference Manual”, which are

available from the Microchip web site

(www.microchip.com).

2: It is important to note that the

specifications in Section 26.0 “Electri-

cal Characteristics” of this data sheet,

supercede any specifications that may be

provided in PIC24F Family Reference

Manual sections.

Reset Address

0x000000

0x0000FE

0x000002

0x000100

Device Configuration

User Program

Flash Memory

0x002BFC

0x002BFA

(5.6K instructions)

0x800000

0xF80000

Shadow Registers

0xF80017

0xF80018

DEVID (2)

0xFEFFFE

0xFF0000

0xFFFFFE

0xF7FFFE

Unimplemented

(Read ‘0’s)

GOTO Instruction

0x000004

Reserved

0x7FFFFE

Reserved

0x000200

0x0001FE

0x000104

Alternate Vector Table

Reserved

Interrupt Vector Table

Configuration Memory Space User Memory Space

Flash Configuration

Words(1)

0x002COO

0x002BFE

Note 1: On reset, these bits are automatically copied into the device Configuration shadow registers.

PIC24FJ16MC101/102

4.1.1 PROGRAM MEMORY

ORGANIZATION

The program memory space is organized in word-

addressable blocks. Although it is treated as 24 bits

wide, it is more appropriate to think of each address of

the program memory as a lower and upper word, with

the upper byte of the upper word being unimplemented.

The lower word always has an even address, while the

upper word has an odd address (Figure 4-2).

Program memory addresses are always word-aligned

on the lower word, an d addresses are incremented or

decremented by two during code execution. This

arrangement provides compatibility with data memory

space addressing and makes data in the program

memory space accessible.

4.1.2 INTERRUPT AND TRAP VECTORS

All PIC24FJ16MC101/102 devices reserve the

addresses between 0x00000 and 0x000200 for hard-

coded program execution vectors. A hardware Reset

vector is provided to redirect code execution from the

default value of the PC on device Reset to the actual

start of code. A GOTO instruction is programmed by the

user application at 0x000000, with the actual address

for the start of code at 0x000002.

PIC24FJ16MC101/102 devices also have two interrupt

vector tables, located from 0x000004 to 0x0000FF and

0x000100 to 0x0001FF . These vector t ables allow each

of the device interrupt sources to be h andled by sepa-

rate Interrupt Service Routines (ISRs). A more detailed

discussion of the interrupt vector tables is provided in

Section 7.1 “Interrupt Vector Table”.

FIGURE 4-2: PROGRAM MEMORY ORGANIZATION

0816

PC Address

0x000000

0x000002

0x000004

0x000006

00000000

Program Memory

‘Phantom’ Byte

(read as ‘0’)

least significant word (lsw)

most significant word (msw)

Instruction Width

0x000001

0x000003

0x000005

0x000007

msw

Address (lsw Address)

PIC24FJ16MC101/102

4.2 Data Address Sp ac e

The PIC24FJ16MC101/102 CPU has a separate 16-

bit-wide data memory space. The data space is

accessed using separate Address Generation Units

(AGUs) for read and write operations. The data

memory maps is shown in Figure 4-3.

All Effective Addresses (EAs) in the data memory space

are 16 bit s wide and point to bytes within the d ata space.

This arrangement gives a data space address range of

64 Kbytes or 32K words. The lower half of the data

memory space (that is, when EA<15> = 0) is used for

implemented memory addresses, while the upper half

(EA<15> = 1) is reserved for the Program Space

Visibility area (see Section 4.4.3 “Reading Data from

Program Memory Using Program Space Visibility”).

Microchip PIC24FJ16MC101/102 devices implement

up to 1 Kbyte of data memory. Should an EA point to a

location outside of this area, an all-zero word or byte

will be returned.

4.2.1 DATA SPACE WIDTH

The data memory space is organized in byte

addressable, 16-bit wide blocks. Data is aligned in data

memory and registers as 16-bit words, but all data

space EAs resolve to bytes. The Least Significant

Bytes (LSBs) of each word have even addresses, while

the Most Significant Bytes (MSBs) have odd

addresses.

4.2.2 DATA MEMORY ORGANIZATION

AND ALIGNMENT

To maintain backward compatibility with PIC® MCU

devices and improve data space memory usage

efficiency, the PIC24FJ16MC101/102 instruction set

supports both word and byte operations. As a

consequence of byte accessibility, all effective address

calculations are internally scaled to step through word-

aligned memory . For example, the core recognizes that

Post-Modified Register Indirect Addressing mode

[Ws++] will result in a value of Ws + 1 for byte

operations and Ws + 2 for word operations.

Data byte reads will read the complete word that

contains the byte, using the LSB of any EA to

determine which byte to select. The selected byte is

placed onto the LSB of the data path. That is, data

memory and registers are organized as two parallel

byte-wide entities with shared (word) address decoding

but separate write lines. Data byte writes only write to

the corresponding side of the array or register that

matches the byte a dd re ss.

All word accesses must be aligned to an even address.

Misaligned word data fetches are not supported, so

care must be taken when mixing byte and word

operations, or translating from 8-bit MCU code. If a

misaligned read or write is attempted, an address error

trap is generated. If the error occurred on a read, the

instruction in progress is completed. If the error

occurred on a write, the instruction is execu ted but the

write does not occur. In either case, a trap is the n exe-

cuted, allowing the system and/or user application to

examine the machine state prior to execution of the

address Fault.

All byte loads into any W register are loaded into the

LSB. The MSB is not modified.

A sign-extend instruction (SE) is provided to allow user

applications to translate 8-bit signed data to 16-bit

signed values. Alternately, for 16-bit unsigned data,

user applications can clear the MSB of any W register

by executing a zero-extend (ZE) instruction on the

appropriate address.

4.2.3 SFR SPACE

The first 2 Kbytes of the Near Data S pace, from 0x0000

to 0x07FF, is primarily occupied by Special Function

Registers (SFRs). These are used by the

PIC24FJ16MC101/102 core and peripheral modules

for controlling the operation of the device.

SFRs are distributed among the modules that they

control, and are generally grouped together by module.

Much of the SFR space contains unused addresses;

these are read as ‘0’.

4.2.4 NEAR DATA SPACE

The 8-Kbyte area between 0x0000 and 0x1FFF is

referred to as the near data space. Locations in this

space are directly addressable via a 13-bit absolute

address field within all memory direct instructions.

Additionally , the whole data space is addressable using

MOV class of instructions, which support Memory Direct

Addressing mode with a 16-bit address field, or by

using Indirect Addressing mode with a working register

as an address pointer.

Note: The actual set of peripheral features and

interrupts varies by the device. Refe r to the

corresponding device tables and pinout

diagrams for device-specific informa t ion.

PIC24FJ16MC101/102

FIGURE 4-3: DATA MEMORY MAP FOR PIC24FJ16MC101/102 DEVICES WITH 1 KB RAM

0x0000

0x07FE

0x0BFE

0xFFFE

LSB

Address

16 bits

LSbMSb

MSB

Address

0x0001

0x07FF

0xFFFF

Optionally

Mapped

into Program

Memory

0x0801 0x0800

0x0C00

2 Kbyte

SFR Space

1 Kbyte

SRAM Space

0x8001 0x8000

SFR Space

X Data

Unimplemented (X)

0x0BFF

0x0C01

0x1FFF 0x1FFE

0x2001 0x2000

8 Kbyte

Near Data

Space

X Data RA M (X)

PIC24FJ16MC101/102

TABLE 4-1: CPU CORE REGISTERS MAP

SFR Name SFR

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

WREG0 0000 Working Register 0

xxxx

WREG1 0002 Working Register 1

xxxx

WREG2 0004 Working Register 2

xxxx

WREG3 0006 Working Register 3

xxxx

WREG4 0008 Working Register 4

xxxx

WREG5 000A Working Register 5

xxxx

WREG6 000C W orking Register 6

xxxx

WREG7 000E Working Register 7

xxxx

WREG8 0010 Working Register 8

xxxx

WREG9 0012 Working Register 9

xxxx

WREG10 0014 Working Register 10

xxxx

WREG11 0016 Working Register 11

xxxx

WREG12 0018 Working Register 12

xxxx

WREG13 001A Working Register 13

xxxx

WREG14 001C W orking Register 14

xxxx

WREG15 001E Working Register 15

0800

SPLIM 0020 S t ack Pointer Limit Register

xxxx

PCL 002E Program Counter Low Word Register

0000

PCH 0030 — — — — — — — — Program Counter High Byte Register

0000

TBLPAG 0032 — — — — — — — — Table Page Address Pointer Register

0000

PSVPAG 0034 — — — — — — — — Program Memory Visibility Page Address Pointer Register

0000

RCOUNT 0036 Repeat Loop Counter Register

xxxx

SR 0042 — — — — — — — DC IPL2 IPL1 IPL0 RA N OV Z C

0000

CORCON 0044 — — — — — — — — — — — —

IPL3 PSV

— —

0020

DISICNT 0052 —

— Disable Interrupts Counter

0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24FJ16MC101/102

TABLE 4-2: CHANGE NOTIFICATION REGISTER MAP FOR PIC24FJ16MC101 DEVICES

SFR

Name SFR

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

CNEN1 0060 —CN14IE CN13IE CN12IE CN11IE — — — — — CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE

0000

CNEN2 0062 —CN30IE CN29IE — — — — — CN23IE CN22IE CN21IE — — — — —

0000

CNPU1 0068 —CN14PUE CN13PUE CN12PUE CN11PUE — — — — — CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE

0000

CNPU2 006A —CN30PUE CN29PUE — — — — — CN23PUE CN22PUE CN21PUE — — — — —

0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in he xadecimal.

TABLE 4-3: CHANGE NOTIFICATION REGISTER MAP FOR PIC24FJ16MC102 DEVICES

SFR

Name SFR

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

CNEN1

0060 CN15IE CN14IE CN13IE CN12IE CN11IE

— — —

CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE

0000

CNEN2

0062

—

CN30IE CN29IE

—

CN27IE

— —

CN24IE CN23IE CN22IE CN21IE

————

CN16IE

0000

CNPU1

0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE

— — —

CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE

0000

CNPU2

006A

—

CN30PUE CN29PUE

—

CN27PUE

— —

CN24PUE CN23PUE CN22PUE CN21PUE

————

CN16PUE

0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in he xadecimal.

PIC24FJ16MC101/102

TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP

SFR

Name SFR

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

INTCON1 0080 NSTDIS — — — — — — — — — — MATHERR ADDRERR STKERR OSCFAIL —0000

INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000

IFS0 0084 —— AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF 0000

IFS1 0086 ——INT2IF — — — — — — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000

IFS2 0088 — — — — — — — — — —IC3IF — — — — — 0000

IFS3 008A FLTA1IF RTCIF — — — —PWM1IF— — — — — — — — — 0000

IFS4 008C ——CTMUIF — — — — — — — — — — —U1EIFFLT1BIF0000

IEC0 0094 —— AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE 0000

IEC1 0096 ——INT2IE — — — — — — — — INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000

IEC2 0098 — — — — — — — — — —IC3IE — — — — — 0000

IEC3 009A FLTA1IE RTCIE — — — —PWM1IE— — — — — — — — — 0000

IEC4 009C ——CTMUIE — — — — — — — — — — — U1EIE FLT1BIE 0000

IPC0 00A4 — T1IP<2:0> —OC1IP<2:0>— IC1IP<2:0> — INT0IP<2:0> 4444

IPC1 00A6 — T2IP<2:0> —OC2IP<2:0>— IC2IP<2:0> — — — — 4440

IPC2 00A8 — U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0> 4444

IPC3 00AA — — — — — — — — —AD1IP<2:0>— U1TXIP<2:0> 0044

IPC4 00AC — CNIP<2:0> — CMIP<2:0> — MI2C1IP<2:0> — SI2C1IP<2:0> 4444

IPC5 00AE — — — — — — — — — — — — — INT1IP<2:0> 0004

IPC7 00B2 — — — — — — — — — INT2IP<2:0> — — — — 0040

IPC9 00B6 — — — — — — — — — IC3IP<2:0> — — — — 0040

IPC14 00C0 — — — — — — — — — PWM1IP<2:0> — — — — 0040

IPC15 00C2 — FLTA1IP<2:0> —RTCIP<2:0>— — — — — — — — 4400

IPC16 00C4 — — — — — — — — —U1EIP<2:0>—FLTB1IP<2:0>0040

IPC19 00CA — — — — — — — — —CTMUIP<2:0>— — — — 0040

INTTREG 00E0 — — — —ILR<3:0> — VECNUM<6:0> 0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in he xadecimal.

PIC24FJ16MC101/102

TABLE 4-5: TIMER REGISTER MAP

SFR

Name SFR

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

TMR1 0100 T imer1 Register

0000

PR1 0102 Period Register 1

FFFF

T1CON 0104 TON

—

TSIDL

— — — — — —

TGATE TCKPS<1:0>

—

TSYNC TCS

—

0000

TMR2 0106 T imer2 Register

0000

TMR3HLD 0108 T imer3 Holding Register (for 32-bit timer operations only)

xxxx

TMR3 010A T imer3 Register

0000

PR2 010C Period Register 2

FFFF

PR3 010E Period Register 3

FFFF

T2CON 0110 TON

—

TSIDL

— — — — — —

TGATE TCKPS<1:0> T32

—

TCS

—

0000

T3CON 0112 TON

—

TSIDL

— — — — — —

TGATE TCKPS<1:0>

— —

TCS

—

0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in he xadecimal.

TABLE 4-6: INPUT CAPTURE REGISTER MAP

SFR Name SFR

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

IC1BUF 0140 Input 1 Capture Register

xxxx

IC1CON 0142

— —

ICSIDL

— — — — —

ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>

0000

IC2BUF 0144 Input 2 Capture Register

xxxx

IC2CON 0146

— —

ICSIDL

— — — — —

ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>

0000

IC3BUF 0148 Input 3 Capture Register

xxxx

IC3CON 014A

— —

ICSIDL

— — — — —

ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>

0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in he xadecimal.

TABLE 4-7: OUTPUT COMPARE REGISTER MAP

SFR Name SFR

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

OC1RS 0180 Output Compare 1 Secondary Register

xxxx

OC1R 0182 Output Compare 1 Register

xxxx

OC1CON 0184

— —

OCSIDL

— — — — — — — —

OCFLT OCTSEL OCM<2:0>

0000

OC2RS 0186 Output Compare 2 Secondary Register

xxxx

OC2R 0188 Output Compare 2 Register

xxxx

OC2CON 018A

— —

OCSIDL

— — — — — — — —

OCFLT OCTSEL OCM<2:0>

0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in he xadecimal.

PIC24FJ16MC101/102

TABLE 4-8: 6-OUTPUT PWM1 REGISTER MAP

SFR Name Addr . Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset St ate

P1TCON 01C0 PTEN —PTSIDL————— PTOPS<3:0> PTCKPS<1:0> PTMOD<1:0>

0000 0000 0000 0000

P1TMR 01C2 PTDIR PWM T i mer Coun t Value Reg ister

0000 0000 0000 0000

P1TPER 01C4 — PWM Time Base Period Register

0111 1111 1111 1111

P1SECMP 01C6 SEVTDIR PWM Special Event Compare Register

0000 0000 0000 0000

PWM1CON1

01C8 — — — — —PMOD3PMOD2PMOD1 — PEN3H PEN2H PEN1H — PEN3L PEN2L PEN1L

0000 0000 0000 0000

PWM1CON2

01CA — — — —SEVOPS<3:0>— — — — — IUE OSYNC UDIS

0000 0000 0000 0000

P1DTCON1 01CC DTBPS<1:0> DTB<5:0> DTAPS<1:0> DTA<5:0>

0000 0000 0000 0000

P1DTCON2 01CE — — — — — — — — — — DTS3A DTS3I DTS2A DTS2I DTS1A DTS1I

0000 0000 0000 0000

P1FLTACON 01D0 —— FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L FLTAM — — — — FAEN3 FAEN2 FAEN1

0000 0000 0000 0111

P1FLTBCON 01D2 —— FBOV3H FBOV3L FBOV2H FBOV2L FBOV1H FBOV1L FLTBM — — — — FBEN3 FBEN2 FBEN1

0000 0000 0000 0111

P1OVDCON 01D4 —— POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L —— POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L

0011 1111 0000 0000

P1DC1 01D6 PWM Duty Cycle 1 Register

0000 0000 0000 0000

P1DC2 01D8 PWM Duty Cycle 2 Register

0000 0000 0000 0000

P1DC3 01DA PWM Duty Cycle 3 Register

0000 0000 0000 0000

PWM1KEY 01DE PWMKEY<15:0>

0000 0000 0000 0000

Legend: u = uninitialized bit, — = unimplemented, read as ‘0’

TABLE 4-9: I2C1 REGISTER MAP

SFR Name SFR

Addr Bit 15Bit 14Bit 13Bit 12Bit 11Bit 10Bit 9Bit 8Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 All

Resets

I2C1RCV 0200 — ——————— Receive Register

0000

I2C1TRN 0202 — ——————— T ransmit Register

00FF

I2C1BRG 0204 — —————— Baud Rate Generator Register

0000

I2C1CON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN

1000

I2C1STAT 0208 ACKSTAT TRSTAT ——— BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF

0000

I2C1ADD 020A — ————— Address Register

0000

I2C1MSK 020C — ————— Address Mask Register

0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in he xadecimal.

PIC24FJ16MC101/102

TABLE 4-10: UART1 REGISTER MAP

SFR Name SFR

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL

0000

U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA

0110

U1TXREG 0224 — — — — — — — UART Transmit Register

xxxx

U1RXREG 0226 — — — — — — — UART Receive Register

0000

U1BRG 0228 Baud Rate Generator Prescaler

0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in he xadecimal.

TABLE 4-11: SPI1 REGISTER MAP

SFR

Name SFR

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

SPI1STAT 0240 SPIEN — SPISIDL ——————SPIROV———— SPITBF SPIRBF

0000

SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE<2:0> PPRE<1:0>

0000

SPI1CON2 0244 FRMEN SPIFSD FRMPOL ——————————— FRMDLY —

0000

SPI1BUF 0248 SPI1 T ransmit and Receive Buffer Register

0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in he xadecimal.

PIC24FJ16MC101/102

TABLE 4-12: ADC1 REGISTER MAP FOR PIC24FJ16MC101 DEVICES

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

ADC1BUF0 0300 ADC Data Buffer 0 xxxx

ADC1BUF1 0302 ADC Data Buffer 1 xxxx

ADC1BUF2 0304 ADC Data Buffer 2 xxxx

ADC1BUF3 0306 ADC Data Buffer 3 xxxx

ADC1BUF4 0308 ADC Data Buffer 4 xxxx

ADC1BUF5 030A ADC Data Buffer 5 xxxx

ADC1BUF6 030C ADC Data Buffer 6 xxxx

ADC1BUF7 030E ADC Data Buffer 7 xxxx

ADC1BUF8 0310 ADC Data Buffer 8 xxxx

ADC1BUF9 0312 ADC Data Buffer 9 xxxx

ADC1BUFA 0314 ADC Data Buff er 10 xxxx

ADC1BUFB 0316 ADC Data Buffer 11 xxxx

ADC1BUFC 0318 ADC Data Buffer 12 xxxx

ADC1BUFD 031A ADC Data Buffer 13 xxxx

ADC1BUFE 031C ADC Data Buff er 14 xxxx

ADC1BUFF 031E ADC Data Buffer 15 xxxx

AD1CON1 0320 ADON —ADSIDL— — — FORM<1:0> SSRC<2:0> — SIMSAM ASAM SAMP DONE 0000

AD1CON2 0322 VCFG<2:0> —— CSCNA CHPS<1:0> BUFS —SMPI<3:0>BUFMALTS0000

AD1CON3 0324 ADRC — — SAMC<4:0> ADCS<7:0> 0000

AD1CHS123 0326 — — — — — CH123NB<1:0> CH123SB — — — — — CH123NA<1:0> CH123SA 0000

AD1CHS0 0328 CH0NB —— CH0SB<4:0> CH0NA —— CH0SA<4:0> 0000

AD1PCFGL 032C — — — — — — — — — — — — PCFG3 PCFG2 PCFG1 PCFG0 0000

AD1CSSL 0330 — — — — — — — — — — — — CSS3 CSS2 CSS1 CSS0 0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24FJ16MC101/102

TABLE 4-13: ADC1 REGISTER MAP FOR PIC24FJ16MC102 DEVICES

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

ADC1BUF0 0300 ADC Data Buffer 0 xxxx

ADC1BUF1 0302 ADC Data Buffer 1 xxxx

ADC1BUF2 0304 ADC Data Buffer 2 xxxx

ADC1BUF3 0306 ADC Data Buffer 3 xxxx

ADC1BUF4 0308 ADC Data Buffer 4 xxxx

ADC1BUF5 030A ADC Data Buffer 5 xxxx

ADC1BUF6 030C ADC Data Buffer 6 xxxx

ADC1BUF7 030E ADC Data Buffer 7 xxxx

ADC1BUF8 0310 ADC Data Buffer 8 xxxx

ADC1BUF9 0312 ADC Data Buffer 9 xxxx

ADC1BUFA 0314 ADC Data Buffer 1 0 xxxx

ADC1BUFB 0316 ADC Data Buffer 11 xxxx

ADC1BUFC 0318 ADC Data Buffer 12 xxxx

ADC1BUFD 031A ADC Data Buffer 13 xxxx

ADC1BUFE 031C ADC Data Buffer 14 xxxx

ADC1BUFF 031E ADC Data Buffer 15 xxxx

AD1CON1 0320 ADON —ADSIDL — — — FORM<1:0> SSRC<2:0> — SIMSAM ASAM SAMP DONE 0000

AD1CON2 0322 VCFG<2:0> —— CSCNA CHPS<1:0> BUFS —SMPI<3:0>BUFMALTS0000

AD1CON3 0324 ADRC — — SAMC<4:0> ADCS<7:0> 0000

AD1CHS123 0326 — — — — — CH123NB<1:0> CH123SB — — — — — CH123NA<1:0> CH123SA 0000

AD1CHS0 0328 CH0NB —— CH0SB<4:0> CH0NA —— CH0SA<4:0> 0000

AD1PCFGL 032C — — — — — — — — — — PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000

AD1CSSL 0330 — — — — — — — — — — CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24FJ16MC101/102

TABLE 4-14: CTMU REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

CTMUCON1 033A CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG — — — — — — — — 0000

CTMUCON2 033C EDG1MOD EDG1POL EDG1SEL<3:0> EDG2STAT EDG1STAT EDG2MOD EDG2POL EDG2SEL<3:0> — — 0000

CTMUICON 033E ITRIM<5:0> IRNG<1:0> — — — — — — — — 0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 4-15: REAL-TIME CLOCK AND CALENDAR REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

ALRMVAL 0620 Alarm Value Register Window based on APTR<1:0>

xxxx

ALCFGRPT 0622 ALRMEN CHIME AMASK<3:0> ALRMPTR<1:0> ARPT<7:0>

0000

RTCVAL 0624 RTCC Value Register Window based on RTCPTR<1:0>

xxxx

RCFGCAL 0626 RTCEN — RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR<1:0> CAL<7:0>

0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in he xadecimal.

TABLE 4-16: PAD CONFIGURATION REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

PADCFG1 02FC ——————————————RTSECSEL —

0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in he xadecimal.

PIC24FJ16MC101/102

TABLE 4-17: COMPARATOR REGISTER MAP

File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

All

Resets

CMSTAT 0650 CMSIDL — — — — C3EVT C2EVT C1EVT ————— C3OUT C2OUT C1OUT 0000

CVRCON 0652 — — — — — VREFSEL BGSEL<1:0> CVREN CVROE CVRR —CVR<3:0>0000

CM1CON 0654 CON COE CPOL — — — CEVT COUT EVPOL<1:0> — CREF —— CCH<1:0> 0000

CM1MSKSRC 0656 — — — — SELSRCC<3:0> SELSRCB<3:0> SELSRCA<3:0> 0000

CM1MSKCON 0658 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN 0000

CM1FLTR 065A — — — — — — — — — CFSEL<2:0> CFLTREN CFDIV<2:0> 0000

CM2CON 065C CON COE CPOL — — — CEVT COUT EVPOL<1:0> — CREF —— CCH<1:0> 0000

CM2MSKSRC 065E — — — — SELSRCC<3:0> SELSRCB<3:0> SELSRCA<3:0> 0000

CM2MSKCON 0660 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN 0000

CM2FLTR 0662 — — — — — — — — — CFSEL<2:0> CFLTREN CFDIV<2:0> 0000

CM3CON 0664 CON COE CPOL — — — CEVT COUT EVPOL<1:0> — CREF —— CCH<1:0> 0000

CM3MSKSRC 0666 — — — — SELSRCC<3:0> SELSRCB<3:0> SELSRCA<3:0> 0000

CM3MSKCON 0668 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN 0000

CM3FLTR 066A — — — — — — — — — CFSEL<2:0> CFLTREN CFDIV<2:0> 0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in he xadecimal.

TABLE 4-18: PERIPHERAL PIN SELECT INPUT REGISTER MAP

File

Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

RPINR0 0680 — — — INT1R<4:0> — — — — — — — — 1F00

RPINR1 0682 — — — — — — — — — — —INT2R<4:0>

001F

RPINR3 0686 — — —T3CKR<4:0>— — —T2CKR<4:0>

1F1F

RPINR7 068E — — — IC2R<4:0> — — — IC1R<4:0> 1F1F

RPINR8 0690 — — — — — — — — — — — IC3R<4:0> 001F

RPINR11 0696 — — — — — — — — — — —OCFAR<4:0>

001F

RPINR18 06A4 — — — U1CTSR<4:0> — — —U1RXR<4:0>

1F1F

RPINR21 06AA — — — — — — — — — — — SS1R<4:0> 001F

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24FJ16MC101/102

TABLE 4-19: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR PIC24FJ16MC101 DEVICES

File

Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets

RPOR0 06C0 — — — RP1R<4:0> — — — RP0R<4:0> 0000

RPOR2 06C4 — — — — — — — — — — —RP4R<4:0>

0000

RPOR3 06C6 — — — RP7R<4:0> — — — — — — — — 0000

RPOR4 06C8 — — — RP9R<4:0> — — —RP8R<4:0>

0000

RPOR6 06CC — — —RP13R<4:0>— — — RP12R<4:0> 0000

RPOR7 06CE — — —RP15R<4:0>— — — RP14R<4:0> 0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 4-20: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR PIC24FJ16MC102 DEVICES

File

Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

RPOR0 06C0 — — — RP1R<4:0> ——— RP0R<4:0> 0000

RPOR1 06C2 — — —RP3R<4:0>——— RP2R<4:0> 0000

RPOR2 06C4 — — —RP5R<4:0>——— RP4R<4:0> 0000

RPOR3 06C6 — — —RP7R<4:0>——— RP6R<4:0> 0000

RPOR4 06C8 — — —RP9R<4:0>——— RP8R<4:0> 0000

RPOR5 06CA — — —RP11R<4:0>———RP10R<4:0>

0000

RPOR6 06CC — — — RP13R<4:0> ———RP12R<4:0>

0000

RPOR7 06CE — — — RP15R<4:0> ———RP14R<4:0>

0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24FJ16MC101/102

TABLE 4-21: PORTA REGISTER MAP

File

Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets

TRISA 02C0

— — — — — — — — — — —

TRISA4 TRISA3 TRISA2 TRISA1 TRISA0

001F

PORTA 02C2

— — — — — — — — — — — RA4 RA3 RA2 RA1 RA0

xxxx

LATA 02C4

— — — — — — — — — — — LATA4 LATA3 LATA2 LATA1 LATA0

xxxx

ODCA 02C6

— — — — — — — — — — —

ODCA4 ODCA3 ODCA2 ODCA1 ODCA0

0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 4-22: PORTB REGISTER MAP FOR PIC24FJ16MC1 01 DEVICES

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets

TRISB 02C8 TRISB15 TRISB14 TRISB13 TRISB12

— —

TRISB9 TRISB8 TRISB7

— —

TRISB4

— —

TRISB1 TRISB0 F393

PORTB 02CA RB15 RB14 RB13 RB12

— —

RB9 RB8 RB7

— —

RB4

— —

RB1 RB0 xxxx

LATB 02CC LATB15 LATB14 LATB13 LATB12

— —

LATB9 LATB8 LATB7

— —

LATB4

— —

LATB1 LATB0 xxxx

ODCB 02CE ODCB15 ODCB14 ODCB13 ODCB12

— —

ODCB9 ODCB8 ODCB7

— —

ODCB4

— —

ODCB1 ODCB0 0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal

TABLE 4-23: PORTB REGISTER MAP FOR PIC24FJ16MC1 02 DEVICES

File

Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Reset s

TRISB 02C8 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0

FFFF

PORTB 02CA RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0

xxxx

LATB 02CC LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0

xxxx

ODCB 02CE

ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0

0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24FJ16MC101/102

TABLE 4-24: SYSTEM CONTROL REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

RCON 0740 TRAPR IOPUWR ———— CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR

xxxx

(1)

OSCCON 0742 —COSC<2:0>— NOSC<2:0> CLKLOCK IOLOCK LOCK —CF— LPOSCEN OSWEN 0300

(2)

CLKDIV 0744 ROI DOZE<2:0> DOZEN FRCDIV<2:0> — — — — — — — — 3040

OSCTUN 0748 — — — — — — — — — —TUN<5:0>0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: RCON register Reset values dependent on type of Reset.

2: OSCCON register Reset values depen dent on the FOSC Configuration bits and by type of Reset.

TABLE 4-25: NVM REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

NVMCON 0760 WR WREN WRERR ——————ERASE——NVMOP<3:0>

0000

(1)

NVMKEY 0766

———————— NVMKEY<7:0>

0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: Reset value shown is for POR only. Value on other Reset states is depe ndent on the state of memory write or erase operations at the time of Reset.

TABLE 4-26: PMD REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

PMD1 0770 — — T3MD T2MD T1MD —PWM1MD —I2C1MD —U1MD —SPI1MD — — AD1MD 0000

PMD2 0772 — — — — — IC3MD IC2MD IC1MD — — — — — —OC2MDOC1MD0000

PMD3 0774 — — — — — CMPMD RTCCMD — — — — — — — — — 0000

PMD4 0776 — — — — — — — — — — — — —CTMUMD — — 0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24FJ16MC101/102

4.2.5 SOFTWARE STACK

In addition to its use as a working register, the W15

used as a software Stack Pointer. The Stack Pointer

always points to the first available free word and grows

from lower to higher addresses. It pre-decrements for

stack pops and post-increments for stack pushes, as

shown in Figure 4-4. For a PC push during any CALL

instruction, the MSb of the PC is zero-extended before

the push, ensuring that the MSb is always clear.

The Stack Pointer Limit register (SPLIM) associated

with the S t ack Pointer sets an upper address boundary

for the stack. SPLIM is uninitialized at Reset. As is the

case for the Stack Pointer, SPLIM<0> is forced to ‘0’

because all stack operations must be word aligned.

Whenever an EA is generated using W15 as a source

or destination pointer, the resulting address is

compared with the value in SPLIM. If the contents of

the Stack Pointer (W15) and the SPLIM register are

equal and a push operation is performed, a stack error

trap will not occur. However, the stack error trap will

occur on a subsequent push operation. For example, to

cause a stack error trap when the stack grows beyond

address 0x0C00 in RAM, i nitialize the SPLIM with the

value 0x0BFE.

Similarly, a S t ack Pointer underflow (stack error) trap is

generated when the Stack Pointer address is found to

be less than 0x0800. This prevents the stack from

interfering with the SFR space.

A write to the SPLIM register should not be immediately

followed by an indirect read operation using W15.

FIGURE 4-4: CALL ST ACK FRAME

4.2.6 DATA RAM PROTECTION FEATURE

The PIC24FXXXX product family supports Data RAM

protection features that enable segments of RAM to be

protected when used in conjunction with Boot and

Secure Code Segment Security . BSRAM (Secure RAM

segment for BS) is accessible only from the Boot

Segment Flash code, when enabled. SSR AM (Secure

RAM segment for RAM) is accessible only from the

Secure Segment Flash code, when enabled. See

Table 4-1 for an overvie w of the BSRAM and SSRAM

SFRs.

4.3 Instruction Addressing Modes

The addressing modes shown in Table 4-27 form the

basis of the addressing modes that are optimized to

support the specific features of individual instructions.

The addressing modes provided in the MAC class of

instructions differ from those provided in other

instruction types.

4.3.1 FILE REGISTER INSTRUCTIONS

Most file register instructions use a 13-bit address field

(f) to directly address data present in the first 8192

bytes of data memory (near data space). Most file

which is denoted as WREG in these instructions. The

destination is typically either the same file register or

WREG (with the exception of the MUL instruction),

which writes the result to a regist er or register p air. The

MOV instruction allows additional flexibility and can

access the entire data space.

4.3.2 MCU INSTRUCTIONS

The three-operand MCU instructions are of the form:

Operand 3 = Operand 1 <function> Operand 2

where Operand 1 is always a workin g register (that is,

the addressing mode can only be register direct), which

is referred to as Wb. Operand 2 can be a W register,

fetched from data memory, or a 5-bit literal. T he result

location can be either a W register or a data memory

location. The following addressing modes are

supported by MCU instructions:

• Register Direct

• Register Indirect

• Register Indirect Post-Modified

• Register Indirect Pre-Modified

• 5-bit or 10-bit Literal

Note: A PC push during exception processing

concatenates the SRL register to the MSb

of the PC prior to the push.

PC<15:0>

000000000

015

W15 (before CALL)

W15 (after CALL)

Stack Grows Toward

Higher Address

0x0000

PC<22:16>

POP : [--W15]

PUSH : [W15++]

Note: Not all instructions support all of the

addressing modes given above.

Individual instructions can support

different subsets of these addressing

modes.

PIC24FJ16MC101/102

TABLE 4-27: FUNDAMENTAL ADDRESSING MODES SUPPORTED

4.3.3 MOVE INSTRUCTIONS

Move instructions provide a greater degree of address-

ing flexibility than other instructions. In addition to the

addressing modes supported by most MCU

instructions, move instructions also support Register

Indirect with Register Offset Addressing mode, also

referred to as Register Indexed mode.

In summary, the following addressing modes are

supported by move instructions:

• Register Direct

• Register Indirect

• Register Indirect Post-modified

• Register Indirect Pre-modified

• Register Indirect with Register Offset (Indexed)

• Register Indirect with Literal Offset

• 8-bit Literal

• 16-bit Literal

4.3.4 OTHER INSTRUCTIONS

In addition to the addressing modes outlined previously,

some instructions use literal constants of various sizes.

For example, BRA (branch) instructions use 16-bit signed

literals to specify the branch destination directly , whereas

the DISI instruction uses a 14-bit unsigned literal field. In

some instructions, such as ADD Acc, the source of an

operand or result is implied by the opcode itself. Certain

operations, such as NOP, do not have any operands.

4.4 Interfacing Program and Data

Memory Spaces

The PIC24FJ16MC101/10 2 architecture uses a 24-bit-

wide program space and a 16-bit-wide data space. The

architecture is also a modified Harvard scheme, mean-

ing that data can also be present in the program space.

To use this data successfully, it must be accessed in a

way that preserves the alignment of information in both

spaces.

Aside from normal execution, the PIC24FJ16MC101/

102 architecture provides two methods by which

program space can be accessed during operation:

• Using table instructions to access individual

bytes, or words, anywhere in the program space

• Remapping a portion of the program space into

the data space (Program Space Visibility)

Table instructio ns allow an application to read o r write

to small areas of the program memo ry. Th is capability

makes the method ideal for acce ssing data tables that

need to be updated periodically. It also allows access

to all bytes of the program word. The remapping

method allows an application to access a large block of

data on a read-only basis, which is ideal for lookups

from a large table of static data. The application can

only access the lsw of the program word.

Addressing Mode Description

File Register Direct The address of the file register is specified explicitly.

or decremented) by a constant value.

to form the EA.

(Register Indexed) The sum of Wn and Wb forms the EA.

Note: For the MOV instructions, the addressing

mode specified in the instruction can differ

for the source and destination EA.

However, the 4-bit Wb (Register Offset)

field is shared by both source and

destination (but typically only used by

one).

Note: Not all instructions support all the

addressing modes given above. Individual

instructions may support different subsets

of these addressing modes.

PIC24FJ16MC101/102

4.4.1 ADDRESSING PROGRAM SPACE

Since the address ranges for the data and program

spaces are 16 and 24 bits, respectively, a method is

needed to create a 23-bit or 24-bit program address

from 16-bit data registers. The solution depends on the

interface method to be used.

For table operations, the 8-bit Table Page register

(TBLP AG) is use d to define a 32K word region within the

program space. This is concatenated w ith a 16-bit EA to

arrive at a full 24-bit program space add ress. In this for-

mat, the MSb of TBLPAG is used to determine if the

operation occurs in the user memory (TBLPAG<7> = 0)

or the configuration memory (TBLPAG<7> = 1).

For remapping operations, the 8-bit Program Space

Visibility register (PSVPAG) is used to define a

16K word page in the program space. When the MSb

of the EA is ‘1’, PSVP AG is concatenated with the lower

15 bits of the EA to form a 23-bit program space

address. Unlike table operatio ns, th is limits remappi ng

operations strictly to the user memory area .

Table 4-28 and Figure 4-5 show how the program EA is

created for table operations and remapping accesses

from the data EA.

TABLE 4-28: PROGRAM SPACE ADDRESS CONSTRUCTION

Access Type Access

Space Program Space Address

<23> <22:16> <15> <14:1> <0>

Instruction Access

(Code Execution) User 0PC<22:1> 0

0xx xxxx xxxx xxxx xxxx xxx0

TBLRD/TBLWT

(Byte/Word Read/Write) User TBLPAG<7:0> Data EA<15:0>

0xxx xxxx xxxx xxxx xxxx xxxx

Configuration TBLPAG<7:0> Data EA<15:0>

1xxx xxxx xxxx xxxx xxxx xxxx

Program Space Visibility

(Block Remap/Read) User 0PSVPAG<7:0> Data EA<14:0>(1)

0 xxxx xxxx xxx xxxx xxxx xxxx

Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of

the address is PSVPAG<0>.

PIC24FJ16MC101/102

FIGURE 4-5: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

0Program Counter

23 bits

PSVPAG

8 bits

15 bits

Program Counter(1)

Select

TBLPAG

8 bits

16 bits

Byte Select

1/0

User/Configuration

Table Operations(2)

Program Space Visibility(1)

Space Select

24 bits

23 bits

(Remapping)

1/0

Note 1: The Least Significant bit of program space addresses is always fixed as ‘0’ to

maintain word alignment of data in the program and data spaces.

2: Table operations are not required to be word aligned. Table read operations are permitted

in the configuration memory space.

PIC24FJ16MC101/102

4.4.2 DATA ACCESS FROM PROGRAM

MEMORY USING TABLE

INSTRUCTIONS

The TBLRDL and TBLWTL instructions offer a direct

method of reading or writing the lower word of any

address within the program space without going

through data space. The TBLRDH and TBLWTH

instructions are the only method to read or write the

upper 8 bits of a program space word as data.

The PC is incremented by two for each successive

24-bit program word. This allows program memory

addresses to directly map to data space addresses.

Program memory can thus be regard ed as two 16-bit-

wide word address spaces, residing side by side, each

with the same address range. TBLRDL and TBLWTL

access the space that contains the least significant

data word. TBLRDH and TBLWTH access the space that

contains the upper data byte.

Two table instructions are provided to move byte or

word-sized (16-bit) data to and from program space.

Both function as either byte or word operati ons.

•TBLRDL (Table Read Low):

- In Word mode, this instruction maps the

lower word of the program space location

(P<15:0>) to a data address (D<15:0>).

- In Byte mode, either the upper or lower byte

of the lower program word is mapped to the

lower byte of a data address. The upper byte

is selected when Byte Select is ‘1’; the lower

byte is selected when it is ‘0’.

•TBLRDH (Table Read High):

- In W ord mode, this instruction maps the entire

upper word of a program address (P<23:16>)

to a data address. Note that D<15:8>, the

‘phantom byte’, will always be ‘0’.

- In Byte mode, this instruction maps the upper

or lower byte of the program word to D<7:0>

of the data address, in the TBLRDL instruc-

tion. The data is always ‘0’ when the upper

‘phantom’ byte is selected (Byte Select = 1).

In a similar fashion, two table instructions, TBLWTH

and TBLWTL, are used to write individual bytes or

words to a program space address. The details of

their operation are explained in Section 5.0 “Flash

Program Memory”.

For all table operations, the area of program memory

space to be accessed is determined by the Table Page

memory space of the device, including user and

configuration spaces. When TBLPAG<7> = 0, the table

page is located in the user memory space. When

TBLPAG<7> = 1, the page is located in configuration

space.

FIGURE 4-6: ACCESSING PROGRA M ME MORY WITH TABLE INSTRUCTIONS

081623

00000000

‘Phantom’ Byte

TBLRDH.B (Wn<0> = 0)

TBLRDL.W

TBLRDL.B (Wn<0> = 1)

TBLRDL.B (Wn<0> = 0)

23 15 0

TBLPAG

0x000000

0x800000

0x020000

0x030000

Program Space

The address for the table operation is determined by th e data EA

within the page defined by the TBLPAG register.

Only read operations are shown; wr ite operations are also valid in

the user memory area.

PIC24FJ16MC101/102

4.4.3 READING DATA FROM PROGRAM

MEMORY USING PROGRAM SPACE

VISIBILITY

The upper 32 Kbytes of data space may optionally be

mapped into any 16K word page of the program space.

This option provides transparent access to stored

constant data from the data space without the need to

use special instructions (such as TBLRDL and

TBLRDH).

Program space access through the data space occurs

if the MSb of the data space EA is ‘1’ and program

space visibility is enabled by setting the PSV bit in the

Core Control register (CORCON<2>). The location of

the program memory space to be mapped into the data

space is determined by the Program Space Visibility

Page register (PSVPAG). This 8-bit register defines

any one of 256 possible pages of 16K words in

program space. In effect, PSVPAG functions as the

upper 8 bits of the program memory address, with the

15 bits of the EA functioning as the lower bits. By

incrementing the PC by 2 for each program memory

word, the lower 15 bits of data sp ace addresses directly

map to the lower 15 bits in the correspondin g p rogram

space addresses.

Data reads to this area add a cycle to the instruction

being executed, since two program memory fetches

are required.

Although each data space address 0x8000 and higher

maps directly into a corresponding program memory

address (see Figure 4-7), only the lower 16 bits of the

24-bit program word are used to contain the data. The

upper 8 bits of any program space location used as

data should be programmed with ‘1111 1111’ or

‘0000 0000’ to force a NOP. This prevents possible

issues should the area of code ever be accidentally

executed.

For operations that use PSV and are executed outside

a REPEAT loop, the MOV and MOV.D instructions

require one instruction cycle in addition to the specified

execution time. All other instructions require two

instruction cycles in addition to the specified execution

time.

For operations that use PSV, and are executed inside

a REPEAT loop, these instances require two instruction

cycles in addition to the specified execution time of the

instruction:

• Execution in the first iteration

• Execution in the last iteration

• Execution prior to exiting th e loop due to an

interrupt

• Execution upon re-entering the loop after an

interrupt is serviced

Any other iteration of the REPEAT loop will allow the

instruction using PSV to access data, to execute in a

single cycle.

FIGURE 4-7: PROGRAM SPACE VISIBILITY OPERATION

Note: PSV access is temporarily disabled during

table reads/writes.

23 15 0

PSVPAG Data Space

Program Space

0x0000

0x8000

0xFFFF

02 0x000000

0x800000

0x010000

0x018000

When CORCON<2> = 1 and EA<15> = 1:

The data in the page

designated by

PSVPAG is mapped

into the upper half of

the data memory

space...

Data EA<14:0>

...while the lower 15 bits

of the EA specify an

exact address within

the PSV area. This

corresponds exactly to

the same lower 15 bits

of the actual program

space address.

PSV Area

PIC24FJ16MC101/102

NOTES:

PIC24FJ16MC101/102

5.0 FLASH PROGRAM MEMORY

The PIC24FJ16MC101/102 devices contain internal

Flash program memory for storing and executing

application code. The memory is readable, writable,

and erasable during normal operation over the entire

VDD range.

Flash memory can be pro grammed in tw o w ays :

• In-Circuit Serial Programming™ (ICSP™)

programming capability

• Run-T ime Self-Programming (RTSP)

ICSP allows a device to be serially programmed while

in the end application circuit. This is done with two lines

for programming clock and programming data (one of

the alternate programming pin pairs: PGECx/PGEDx),

and three other lines for power (VDD), ground (VSS) and

Master Clear (MCLR). This allows users to manufac-

ture boards with unprogrammed devices, and then pro-

gram the microcontroller just before shipping the

product. This also allows the most recent firmware or a

custom firmware to be programmed.

RTSP is accomplished using TBLRD (table read) and

TBLWT (table write) instructions. With RTSP, the user

application can write program memory d ata in a single

program memory word, and erase program memory in

blocks or ‘pages’ of 512 instructions (1536 bytes).

5.1 Table Instructions and Flash

Programming

Regardless of the method used, all programming of

Flash memory is done with the table-read and table-

write instructions. These allow direct read and write

access to the program memory space from the data

memory while the devi ce is in no rmal operating mode.

The 24-bit target address in the program memory is

formed using bits <7:0> of the TBLP AG register and the

Effective Address (EA) from a W register specified in

the table instruction, as shown in Figure 5-1.

The TBLRDL and the TBLWTL instructions are used to

read or write to bits <15:0> of program memory.

TBLRDL and TBLWTL can access program memory in

both Word and Byte modes.

The TBLRDH and TBLWTH instructions are used to read

or write to bits <23:16> of program memory. TBLRDH

and TBLWTH can also access program memory in Word

or Byte mode.

FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS

Note 1: This data sheet summarizes the features

of the PIC24FJ16MC101/102 family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 4. “Program

Memory” (DS39715) in the “PIC24F

Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com).

2: It is important to note that the

specifications in Section 26.0 “Electri-

cal Characteristics” of this data sheet,

supercede any specifications that may be

provided in PIC24F Family Reference

Manual sections.

3: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Program Counter

24 bits

Program Counter

TBLPAG Reg

8 bits

Working Reg EA

16 bits

Byte

24-bit EA

1/0

Select

Using

Tabl e Instruction

Using

User/Configuration

Space Select

PIC24FJ16MC101/102

5.2 RTSP Operation

The PIC24FJ16MC101/102 Flash program memory

array is organized into rows of 64 instructions or 192

bytes. RTSP allows the user application to erase a

page of memory, which consists of eight rows (512

instructions); and to program one word. Table 26-12

shows typical erase and programming times. The 8-

row erase pages are edge -aligned from the begi nning

of program memory, on boundaries of 1536 bytes.

5.3 Programming Operations

A complete programming sequence is necessary for

programming or erasing the internal Flash in RTSP

mode. The processor stalls (waits) until the operation is

finished.

For erase and program times, refer to parameters

DI37a and DI37b (Page Erase Time), and DI38a and

DI38b (Word Write Cycle Time), in Table 26-12: “DC

Characteristics: Program Memory”.

Setting the WR bit (NVMCON<15>) starts the opera-

tion, and the WR bit is automatically cle ared when the

operation is finished.

5.3.1 PROGRAMMING ALGORITHM FOR

FLASH PROGRAM MEMORY

Programmers can program one word (24 bits) of

program Flash memory at a time. To do this, it is

necessary to erase the 8-row erase page that contains

the desired address of the location the user wants to

change.

For protection against accide ntal operations, the write

initiate sequence for NVMKEY must be used to allow

any erase or program operation to proceed. After the

programming command has been executed, the user

application must wait for the programming time until

programming is complete. The two instructions

following the start of the programming sequence

should be NOPs.

Refer to Section 4. “Program Memory” (DS39715) in

the “PIC24F Family Reference Manual” for details and

codes examples on programmi ng using RTSP.

5.4 Control Registers

Two SFRs are used to read and write the program

Flash memory: NVMCON and NVMKEY.

The NVMCON register (Register 5-1) controls which

blocks are to be erased, which memory type is to be

programmed, and the start of the programming cycle.

NVMKEY is a write-only register that is used for write

protection. To start a programming or erase sequence,

the user application must consecutively write 0x55 and

0xAA to the NVMKEY register. Refer to Section 5.3

“Programming Operations” for further details.

Note: Performing a page erase operation on the

last page of program memory will clear the

Flash Configuration words, thereby

enabling code protection as a result.

Therefore, users shoul d avoid performi ng

page erase operations on the last page of

program memory.

PIC24FJ16MC101/102

R/SO-0(1) R/W-0(1) R/W-0(1) U-0 U-0 U-0 U-0 U-0

WR WREN WRERR — — — — —

bit 15 bit 8

U-0 R/W-0(1) U-0 U-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1)

— ERASE ——NVMOP<3:0>

(2)

bit 7 bit 0

Legend: SO = Settable only bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 WR: Write Control bit

1 = Initiates a Flash memory program or erase operation. The operation is self-timed an d the bit is

cleared by hardware once operation is complete

0 = Program or erase operation is complete and inactive

bit 14 WREN: Write Enable bit

1 = Enable Flash program/erase operations

0 = Inhibit Flash program/erase operations

bit 13 WRERR: Write Sequence Error Flag bit

1 = An improper program or erase sequence attempt or termination has occurred (bit is set

automatically on any set attempt of the WR bit)

0 = The program or erase operation completed normally

bit 12-7 Unimplemented: Read as ‘0’

bit 6 ERASE: Erase/Program Enable bit

1 = Perform the erase operation specified by NVMOP<3:0> on the next WR command

0 = Perform the program operation specifie d by NV MOP<3:0> on the next WR command

bit 5-4 Unimplemented: Read as ‘0’

bit 3-0 NVMOP<3:0>: NVM Operation Select bits(2)

If ERASE = 1:

1111 = No operation

1101 = Erase General Segment

1100 = No operation

0011 = No operation

0010 = Memory page erase operation

0001 = No operation

0000 = No operation

If ERASE = 0:

1111 = No operation

1101 = No operation

1100 = No operation

0011 = Memory word program operation

0010 = No operation

0001 = No operation

0000 = No operation

Note 1: These bits can only be reset on POR.

2: All other combinations of NVMOP<3:0> are unimplemented.

PIC24FJ16MC101/102

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0

NVMKEY<7:0>

bit 7 bit 0

Legend: SO = Settable only bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-8 Unimplemented: Read as ‘0’

bit 7-0 NVMKEY<7:0>: Key Register (write-only) bit s

PIC24FJ16MC101/102

6.0 RESETS

The Reset module combines all Reset sources and

controls the device Master Reset Signal, SYSRST. The

following is a list of device Reset sources:

• POR: Power-on Reset

• BOR: Brown-out Reset

•MCLR

: Master Clear Pin Reset

•SWR: RESET Instruction

• WDTO: Watchdog Timer Reset

• CM: Configuration Misma tch Rese t

• TRAPR: Trap Conflict Reset

• IOPUWR: Illegal Condition Device Reset

- Illegal Opcode Reset

- Uninitialized W Register Reset

- Security Reset

A simplified block diagram of the Reset module is

shown in Figure 6-1.

Any active source of Reset will make the SYSRST sig-

nal active. On system Reset, some of the registers

associated with the CPU a nd pe ripherals a re fo rced to

a known Reset state, and some are unaffected.

All types of device Reset set a corresponding status bit

in the RCON register to indicate the type of Reset (see

All bits that are set, with the exception of the POR bit

(RCON<0>), are cleared during a POR event. The user

application can set or clear any bit at any time during

code execution. The RCON bits only serve as status

bits. Setting a particular Reset status bit in software

does not cause a device Reset to occur.

The RCON register also has other bits associated with

the Watchdog Timer and device power-saving states.

The function of these bits is discussed in other sections

of this data sheet.

FIGURE 6-1: RESET SYSTEM BLOCK DIAGRAM

Note 1: This data sheet summarizes the features

of the PIC24FJ16MC101/102 family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 7. “Reset”

(DS39712) in the “PIC24F Family

Reference Manual”, which is available

from the Microchip web site

(www.microchip.com).

2: It is important to note that the

specifications in Section 26.0 “Electri-

cal Characteristics” of this data sheet,

supercede any specifications that may be

provided in PIC24F Family Reference

Manual sections.

3: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Note: Refer to the specific perip heral section or

Section 3.0 “CPU” of this data sheet for

Note: The status bits in the RCON register

should be cleared after they are read so

that the next RCON register value after a

device Reset is mean i n gful.

MCLR

VDD

Internal

Regulator BOR

Sleep or Idle

RESET Instruction

WDT

Module

Glitch Filter

Trap Conflict

Illegal Opcode

Uninitialized W Register

SYSRST

VDD Rise

Detect POR

Configuration Mismatch

PIC24FJ16MC101/102

R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

TRAPR IOPUWR — — — —CMVREGS

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1

EXTR SWR SWDTEN(2) WDTO SLEEP IDLE BOR POR

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 TRAPR: Trap Reset Flag bit

1 = A Trap Conflict Reset has occurred

0 = A Trap Conflict Reset has not occurred

bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit

1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an

Address Pointer caused a Reset

0 = An illegal opcode or uninitialized W Reset has not occurred

bit 13-10 Unimplemented: Read as ‘0’

bit 9 CM: Configuration Mismatch Flag bit

1 = A configuration mismatch Reset has occurred

0 = A configuration mismatch Re set has not occurred

bit 8 VREGS: Voltage Regulator Stand-by During Sleep bit

1 = Voltage regulator is active during Sleep

0 = Voltage regulator goes into St and-by mode during Sleep

bit 7 EXTR: External Reset (MCLR) Pin bit

1 = A Master Clear (pin) Reset has occurred

0 = A Master Clear (pin) Reset has not occurred

bit 6 SWR: Software Reset (Instruction) Flag bit

1 = A RESET instruction has been executed

0 = A RESET instruction has not been executed

bit 5 SWDTEN: Software Enable/Disable of WDT bit (2)

1 = WDT is enabled

0 = WDT is disabled

bit 4 WDTO: Watchdog Timer Time-out Flag bit

1 = WDT time-out has occurred

0 = WDT time-out has not occurred

bit 3 SLEEP: Wake-up from Sleep Flag bit

1 = Device has been in Sleep mode

0 = Device has not been in Sleep mode

bit 2 IDLE: Wake-up from Idle Fl ag bit

1 = Device was in Idle mode

0 = Device was not in Idle mode

bit 1 BOR: Brown-out Reset Flag bit

1 = A Brown-out Reset has occurred

0 = A Brown-out Reset has not occurred

bit 0 POR: Power-on Reset Flag bit

1 = A Power-on Reset has occurred

0 = A Power-on Reset has not occurred

Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not

cause a device Reset.

2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enab led, regardless of the

SWDTEN bit setting.

PIC24FJ16MC101/102

6.1 System Reset

The PIC24FJ16MC101/102 family of devices have two

types of Reset :

• Cold Reset

• Warm Reset

A cold Reset is the result of a POR or a BOR. On a cold

Reset, the FNOSC configuration bits in the FOSC

device configuration register selects the device clock

source.

A warm Reset is the result of all other Reset sources,

including the RESET instruction. On warm Reset, the

device will continue to operate from the current clock

source as indicated by the Current Oscillator Selection

bits (COSC<2:0>) in the Oscillator Control register

(OSCCON<14:12>).

The device is kept in a Reset state until the system

power supplies have stabilized at appropriate levels

and the oscillator clock is ready. The sequence in

which this oc curs is shown in Figure 6-2.

TABLE 6-1: OSCILLATOR DELAY

Oscillator Mode Oscillator

Startup Delay Osci lla to r Startup

Timer PLL Lock Time Total Delay

FRC, FRCDIV16, FRCDIVN TOSCD ——TOSCD

FRCPLL TOSCD —TLOCK TOSCD + TLOCK

MS TOSCD TOST —TOSCD + TOST

HS TOSCD TOST —TOSCD + TOST

EC ——— —

MSPLL TOSCD TOST TLOCK TOSCD + TOST + TLOCK

ECPLL — — TLOCK TLOCK

SOSC TOSCD TOST —TOSCD + TOST

LPRC TOSCD ——TOSCD

Note 1: TOSCD = Oscillator Start-up Delay (1.1 μs max for FRC, 70 μs max for LPRC). Crystal Oscillator start-up

times vary with crystal characteristics, load capacitance, etc.

2: TOST = Oscillator Start-up Timer Delay (1024 oscillator clock period). For example, TOST = 102.4 μs for a

10 MHz crystal and TOST = 32 ms for a 32 kHz crystal.

3: TLOCK = PLL lock time (1.5 ms nominal), if PLL is enabled.

PIC24FJ16MC101/102

FIGURE 6-2: SYSTEM RESET TIMING

Reset Run

Device Status

VDD

VPOR Vbor

VBOR

POR

BOR

SYSRST

TPWRT

TPOR

TBOR

Oscillator Clock

TOSCD TOST TLOCK

Time

FSCM TFSCM

1. POR: A POR circuit holds the device in Reset when the power suppl y is t urned on. The POR circuit is active unt il V DD crosses the

VPOR threshold and the delay TPOR has elap sed.

2. BOR: The on-chip volta ge regulat or has a BOR circuit tha t keeps the device in Reset unt il VDD crosses the VBOR threshold and the

delay TBOR has elapsed. The delay TBOR ensures the voltage regulator output becomes stable.

3. PWRT Timer: The power-up timer cont inues to hold the processor in Reset for a specific period of t ime (TPWRT) after a BOR. The

delay TPWRT ensures that the system power supplies have st abilized at the appropriate level for full-speed operation. Af ter the delay

TPWRT has elapsed, the SYSRST becomes inactive, which in turn enables the selected oscillator to start generating clock cycles.

4. Oscillator Delay: The total delay for the clock to be ready for various clock source selections are given in Table 6-1. Refer to

Section 8. 0 “O scil la t or Configuration” for more information.

5. When the oscillator clock is ready , the processor begins execut ion from location 0x000 000. The user appli cation programs a GOTO

instruction at the Reset address, which redirects program execution to the appropriate start-up routine.

6. The Fail-Safe Clock Monitor (FSCM), if enabled, begins to monitor the system clock wh en the system clock is ready and th e del ay

TFSCM elapsed.

TABLE 6-2: OSCILLATOR PARAMETERS

Symbol Parameter Value

VPOR POR threshold 1.8V nominal

TPOR POR extension time 30 μs maximum

VBOR BOR threshold 2.5V nominal

TBOR BOR extension time 100 μs maximum

TPWRT Power-up time

delay 64 ms nominal

TFSCM Fail-safe C lock

Monitor Delay 900 μs maximum

Note: When the device exits the Reset condi-

tion (begins normal operation), the

device operating parameters (voltage,

frequency, temperature, etc.) must be

within their operating ranges, otherwise

the device may not function correctly . The

user application must ensure that the

delay between the time power is first

applied, and the time SYSRST becomes

inactive, is long enough to get all

operating parameters within

specification.

PIC24FJ16MC101/102

6.2 POR

A POR circuit ensures the device is reset from power-

on. The POR circuit is active until VDD crosses the

VPOR threshold and the delay TPOR has elapsed. The

delay TPOR ensures the internal device bias circuits

become stable.

The device supply voltage characteristics must meet

the specified starting voltage and rise rate require-

ments to generate the POR. Refer to Section 26.0

“Electrical Characteristics” for details.

The POR status bit (POR) in the Reset Control regi s t e r

(RCON<0>) is set to indicate the Power-on Reset.

6.3 BOR and PWRT

The on-chip regulator has a BOR circuit that resets the

device when the VDD is too low (VDD < VBOR) for proper

device operation. The BOR circuit keeps the device in

Reset until VDD crosses the VBOR threshold and the

delay TBOR has elapsed. The delay TBOR ensures the

voltage regulator output becomes stable.

The BOR status bit (BOR) in the Reset Control re g is t e r

(RCON<1>) is set to indicate the Brown-out Reset.

The device will not run at full speed after a BOR as the

VDD should rise to acceptable levels for full-speed

operation. The PWRT provides power-up time delay

(TPWRT) to ensure that the system power supplies have

stabilized at the appropriate leve ls for full-speed oper-

ation before the SYSRST is released.

Refer to Section 23.0 “Special Features” for further

details.

Figure 6-3 shows the typical brown-out scenarios. The

Reset delay (TBOR + TPWRT) is initiated each time VDD

rises above the VBOR trip point.

FIGURE 6-3: BROWN-OUT SITUATIONS

VDD

SYSRST

VBOR

VDD

SYSRST

VBOR

VDD

SYSRST

VBOR

TBOR + TPWRT

VDD dips before PWRT expires

TBOR + TPWRT

PIC24FJ16MC101/102

6.4 External Reset (EXTR)

The external Reset is gen erated by driving the MCLR

pin low . The MCLR pin is a Schmitt trigger input with an

additional glitch filter . Reset pulses that are longer than

the minimum pulse width will generate a Reset. Refer

to Section 26.0 “Electrical Characteristics” for

minimum pulse width specifications. The External

Reset (MCLR) Pin (EXTR) bit in the Reset Control

6.4.1 EXTERNAL SUPERVISORY

CIRCUIT

Many systems have external supervisory circuits that

generate Reset signals to Reset multiple devices in the

system. This external Reset signal can be directly con-

nected to the MCLR pin to Reset the devi ce when the

rest of system is Reset.

6.4.2 INTERNAL SUPERVISORY CIRCUIT

When using the internal power supervisory circuit to

Reset the device, the external Reset pin (MCLR)

should be tied directly or resistively to VDD. In this case,

the MCLR pin will not be used to generate a Reset. The

external Reset pin (MCLR) does not have an internal

pull-up and must not be left unconnected.

6.5 Software RESET Instruction (SWR)

Whenever the RESET instruction is executed, the

device will assert SYSRST, placing the device in a spe-

cial Reset state. This Reset state will not re-initialize the

clock. The clock source in effect prior to the RESET

instruction will remain. SYSRST is released at the next

instruction cycle, and the Reset vector fetch will

commence.

The Software Reset (Instruction) Flag bit (SWR) in the

Reset Control reg ist er (RCON<6>) is set to indicate the

software Reset.

6.6 Watchdog Time-out Reset (WDTO)

Whenever a Watchdog T ime-out occurs, the device will

asynchronously assert SYSRST. T he clock so urce will

remain unchanged. A WDT time-out during Sleep or

Idle mode will wake-up the processor , but will not reset

the processor.

The Watchdog Time r Time-out Flag b it (WDTO) in the

Reset Control reg ist er (RCON<4>) is set to indicate the

Watchdog Reset. Refer to Section 23.4 “Watchdog

Timer (WDT)” for more information on Watchdog

Reset.

6.7 Trap Conflict Reset

If a lower-priority hard trap occurs while a higher-prior-

ity trap is being processed, a hard trap conflict Reset

occurs. The hard traps include exceptions of priority

level 13 through level 15, inclusive. The address error

(level 13) and oscillator error (level 14) traps fall into

this category.

The Trap Reset Flag bit (TRAPR) in the Reset Control

reg is ter (RCON<15>) is set to indicate the T rap Conflict

Reset. Refer to Section 7.0 “Interrupt Controller” for

more information on trap conflict Resets.

6.8 Configuration Mismatch Reset

To maintain the integrity of the peripheral pin select

control registers, they are constantly monitored with

shadow registers in hardware. If an unexpected

change in any of the registers occur (such as cell dis-

turbances caused by ESD or o ther external events), a

configuration mismatch Reset occurs.

The Configuration Mismatch Flag bit (CM) in the Reset

Control register (RCON<9>) is set to indicate the con-

figuration mismatch Reset. Refer to Section 10.0 “I/O

Ports” for more information on the configuration

mismatch Reset.

Note: The configuration mismatch feature and

associated Reset flag is not available on

all devices.

PIC24FJ16MC101/102

6.9 Illegal Condition Device Reset

An illegal condition device Reset occurs due to the

following sources:

• Illegal Opcode Reset

• Uninitialized W Registe r Reset

• Security Reset

The Illegal Opcode or Uninitialized W Access Reset

Flag bit (IOPUWR) in the Reset Control register

(RCON<14>) is set to indicate the illegal condition

device Re se t.

6.9.1 ILLEGAL OPCODE RESET

A device Reset is generated if the device attempts to

execute an illegal opcode value that is fetched from

program memory.

The illegal opcode Reset function can prevent the

device from executing program memory sections that

are used to store constant data. To take advantage of

the illegal opcode Re set, use only the lower 16 bits of

each program memory section to store the data values.

The upper 8 bits should be programmed with 0x3F,

which is an illegal opcode value.

6.9.2 UNINITIALIZED W REGISTER

RESET

Any attempts to use the unini tialized W register as an

address pointer will Reset the device. The W register

array (with the excep tion of W15) is cleared during al l

Resets and is considered uninitialized until written to.

6.9.3 SECURITY RESET

If a Program Flow Change (PFC) or Vector Flow

Change (VFC) targets a restricted location in a pro-

tected segment (Boot and Secure Segment), that

operation will cause a security Reset.

The PFC occurs when the Program Counter is

reloaded as a result of a Call, Ju mp, Computed Jump,

Return, Return from Subroutine, or other form of

branch instruction.

The VFC occurs when the Program Counter is

reloaded with an Interrupt or Trap vector.

6.10 Using the RCON Status Bits

The user application can read the Reset Control regis-

ter (RCON) after any device Reset to determine the

cause of the Reset.

Table 6-3 provides a summary of Reset flag bit

operation.

TABLE 6-3: RESET FLAG BIT OPERATION

Note: The status bits in the RCON register

should be cleared after they are read so

that the next RCON register value after a

device Reset will be meaningful.

Flag Bit Set by: Cleared by:

TRAPR (RCON<15>) Trap conflict event POR, BOR

IOPWR (RCON<14>) Illegal opcode or uninitialized

W register access or Security Reset POR, BOR

CM (RCON<9>) Configuration Mismatch POR, BOR

EXTR (RCON<7>) MCLR Reset POR

SWR (RCON<6>) RESET instruction POR, BOR

WDTO (RCON<4>) WDT Time-out PWRSAV instruction,

CLRWDT instruction, POR, BOR

SLEEP (RCON<3>) PWRSAV #SLEEP instruction POR, BOR

IDLE (RCON<2>) PWRSAV #IDLE instruction POR, BOR

BOR (RCON<1>) POR, BOR —

POR (RCON<0>) POR —

Note: All Reset flag bits can be set or cleared by user software.

PIC24FJ16MC101/102

NOTES:

PIC24FJ16MC101/102

7.0 INTERRUPT CONTROLLER

The Interrupt Contro ller reduce s the nu merous perip h-

eral interrupt request signals to a single interrupt

request signal to the PIC24FJ16MC101/102 CPU. It

has the following features:

• Up to eight processor exceptions and software traps

• Seven user-selectable priority levels

• Interrupt Vector Table (IVT) with up to 118 vectors

• A unique vector for each interrupt or exception

source

• Fixed priority within a specified user priority le vel

• Alternate Interrupt Vector Table (AIVT) for debug

support

• Fixed interrupt entry and return latencies

7.1 Interrupt Vector Table

The Interrupt V ector Table (IVT) is shown in Figure 7-1.

The IVT resides in program memory , starting at location

000004h. The IVT contains 126 vectors consisting of

eight non-maskable trap vectors, plus up to 118

sources of interrupt. In general, each interrupt source

has its own vector. Each interrupt vector contains a 24-

bit-wide address. The value programmed into each

interrupt vector location is the starting address of the

associated In te rru pt Service Routine (ISR).

Interrupt vectors are prioritized in terms of their natural

priority. This priority is linked to their position in the

vector table. Lower addresses generally have a higher

natural priority. For example, the interrupt associated

with vector 0 will take priority over interrupts at any

other vector address.

PIC24FJ16MC101/102 devices implement up to 26

unique interrupts and 4 nonmaskable traps. These are

summarized in Table 7-1 and Table 7-2.

7.1.1 ALTERNATE INTERRUPT VECTOR

TABLE

The Alternate Interrupt Vector Table (AIVT) is located

after the IVT, as shown in Figure 7-1. Access to the

AIVT is provided by the ALTIVT control bit

(INTCON2<15>). If the ALTIVT bit is set, all interrupt

and exception processes use the alternate vectors

instead of the default vectors. The alternate vectors are

organized in the same manner as the default vectors.

The AIVT supports debugging by providing a way to

switch between an application and a support

environment without requiring the interrupt vectors to

be reprogrammed. This feature also enables switching

between applications to facilitate evaluation of different

software algorithms at run time. If the AIVT is not

needed, the AIVT should be programmed with the

same addresses used in the IVT.

7.2 Reset Sequence

A device Reset is not a true exception because the

interrupt controller is not involved in the Reset process.

The PIC24FJ16MC101/102 device clears its registers

in response to a Reset, forcing the PC to zero. The

microcontroller then begins program execution at

location 0x000000. A GOTO instruction at the Reset

address can redirect program execution to the

appropriate start-up routine.

Note 1: This data sheet summarizes the features

of the PIC24FJ16MC101/102 family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 8. “Interrupts”

(DS39707) in the “PIC24F Family

Reference Manual”, which is available

from the Microchip web site

(www.microchip.com).

2: It is important to note that the

specifications in Section 26.0 “Electri-

cal Characteristics” of this data sheet,

supercede any specifications that may be

provided in PIC24F Family Reference

Manual sections.

3: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Note: Any unimplemented or unused vector

locations in the IVT and AIVT should be

programmed with the address of a default

interrupt handler routine that contains a

RESET instruction.

PIC24FJ16MC101/102

FIGURE 7-1: PIC24FJ16MC101/102 INTERRUPT VECTOR TABLE

Reset – GOTO Instruction 0x000000

Reset – GOTO Address 0x000002

Reserved 0x000004

Oscillator Fail Trap Vector

Address Error Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

Reserved

Interrupt Vector 0 0x000014

Interrupt Vector 1

Interrupt Vector 52 0x00007C

Interrupt Vector 53 0x00007E

Interrupt Vector 54 0x000080

Interrupt Vector 116 0x0000FC

Interrupt Vector 117 0x0000FE

Reserved 0x000100

Reserved 0x000102

Reserved

Oscillator Fail Trap Vector

Address Error Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

Reserved

Interrupt Vector 0 0x000114

Interrupt Vector 1

Interrupt Vector 52 0x00017C

Interrupt Vector 53 0x00017E

Interrupt Vector 54 0x000180

Interrupt Vector 116

Interrupt Vector 117 0x0001FE

Start of Code 0x000200

Decreasing Natural Order Priority

Interrupt Vector Table (IVT)(1)

Alternate Interrupt Vector Table (AIVT)(1)

Note 1: See Table 7-1 for the list of implemented interrupt vectors.

PIC24FJ16MC101/102

TABLE 7-1: INTERRUPT VECTORS

Vector

Number

Interrupt

Request (IRQ)

Number IVT Address AIVT Address Interrupt Source

8 0 0x000014 0x0 00114 INT0 – External Interrupt 0

9 1 0x000016 0x0 00116 IC1 – Input Capture 1

10 2 0x000018 0x000118 OC1 – Output Compare 1

11 3 0x00001A 0x00011A T1 – Timer1

12 4 0x00001C 0x00011C Reserved

13 5 0x00001E 0x00 011E IC2 – Input Capture 2

14 6 0x000020 0x000120 OC2 – Output Compare 2

15 7 0x000022 0x000122 T2 – Timer2

16 8 0x000024 0x000124 T3 – Timer3

17 9 0x00002 6 0x000126 SPI1E – SPI1 Error

18 10 0x00 0028 0x000128 SPI1 – SPI1 Transfer Done

19 11 0x00002A 0x00012A U1RX – UART1 Receiver

20 12 0x00002C 0x00012C U1TX – UART1 Transmitter

21 13 0x00002E 0x00012E ADC1 – ADC1

22 14 0x000030 0x000130 Reserved

23 15 0x000032 0x000132 Reserved

24 16 0x000034 0x000134 SI2C1 – I2C1 Slave Events

25 17 0x00 0036 0x000136 MI2C1 – I2C1 Master Events

26 18 0x00 0038 0x000138 CMP – Comparator Interrupt

27 19 0x00003A 0x0 0013A Change Notification Interrupt

28 20 0x00003C 0x00013C INT1 – External Interrupt 1

29-36 21-28 0x00003E-

0x00004C 0x00013E-

0x00014C Reserved

37 29 0x00004E 0 x00014E INT2 – External Interrupt 2

38-44 30-36 0x000050-

0x00005A 0x000150-

0x00015C Reserved

45 37 0x00005E 0x0 0015E IC3 – Input Capture 3

46-64 38-56 0x000060-

0x000084 0x000160-

0x000184 Reserved

65 57 0x000086 0x000186 PWM1 – PWM1 Period Match

66-69 58-61 0x000088-

0x00008E 0x000188-

0x00018E Reserved

70 62 0x000090 0x000190 RTCC – Real-Time Clock and Calendar

71 63 0x000092 0x000192 FLTA1 – PWM1 Fault A

72 64 0x000094 0x000194 FLTB1 – PWM1 Fault B

73 65 0x000096 0x000196 U1E – UART1 Error

74-84 66-76 0x000098-

0x0000AC 0x000198-

0x0001AC Reserved

85 77 0x0000AE 0x0001AE CTMU – Charge Time Measurement Unit

86-125 78-117 0x0000B0-

0x0000FE 0x0001B0-

0x0001FE Reserved

PIC24FJ16MC101/102

TABLE 7-2: TRAP VECTORS

7.3 Interrupt Control and Status

Registers

The PIC24FJ16MC101/102 devices implement a total

of 22 registers for the interrupt controller:

• INTCON1

• INTCON2

•IFSx

•IECx

•IPCx

•INTTREG

7.3.1 INTCON1 AND INTCON2

Global interrupt control functions are controlled from

INTCON1 and INTCON2. INTCON1 contains the

Interrupt Nesting Disable bit (NSTDIS) as well as the

control and status flags for the processor trap sources.

The INTCON2 register controls the external interrupt

request signal behavior and the use of the Alternate

Interrupt Vector Table.

7.3.2 IFSx

The IFS registers maintain all of the interrupt request

flags. Each source of interrupt has a status bit, which is

set by the respective peripherals or external signal and

is cleared via software.

7.3.3 IECx

The IEC registers maintain all of the interrupt enable

bits. These control bits are used to individually enabl e

interrupts from the peripherals or external signals.

7.3.4 IPCx

The IPC registers are used to set the interrupt priority

level for each source of interrupt. Each user interrupt

source can be assigned to one of eight priority levels.

7.3.5 INTTREG

The INTTREG register contains the associated

interrupt vector number and the new CPU interrupt

priority level, which are latched into vector number

(VECNUM<6:0>) and interrupt level (ILR<3:0>) bit

fields in the INTTREG register. The new interrupt

priority level is the priority of the pending interrupt.

The interrupt sources are assigned to the IFSx, IECx

and IPCx registers in the same sequence that they are

listed in Table 7-1. For example, the INT0 (External

Interrupt 0) is shown as h aving vector nu mber 8 and a

natural order priority of 0. Thus, the INT0IF bit is found

in IFS0<0>, the INT0IE bit in IEC0<0>, and the INT0IP

bits in the first positions of IPC0 (IPC0<2:0>).

7.3.6 STATUS/CONTROL REGISTERS

Although they are not specifically part of the interrupt

control hardware, two of the CPU Control registers

contain bits that control interrupt functionality.

• The CPU STATUS register, SR, contains the

IPL<2:0> bits (SR<7:5>). These bits indicate the

current CPU interrupt priority level. The user

application can change the current CPU priority

level by writing to the IPL bits.

• The CORCON register contains the IPL3 bit

which, together with IPL<2:0>, also in dicates the

current CPU priority level. IPL3 is a read-only bit

so that trap events cannot be masked by the user

software.

All Interrupt registers are described in Register 7-1

through Register 7-27 in the following pages.

Vector Number IVT Address AIVT Address Trap Source

0 0x000004 0x000104 Reserved

1 0x000006 0x000106 Oscillator Failure

2 0x000008 0x000108 Address Error

3 0x00000A 0x00010A Stack Error

4 0x00000C 0x00010C Math Error

5 0x00000E 0x00010E Reserved

6 0x000010 0x000110 Reserved

7 0x000012 0x000112 Reserved

PIC24FJ16MC101/102

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — —DC

bit 15 bit 8

R/W-0(3) R/W-0(3) R/W-0(3) R-0 R/W-0 R/W-0 R/W-0 R/W-0

IPL2(2) IPL1(2) IPL0(2) RA N OV Z C

bit 7 bit 0

Legend:

C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’

S = Set only bit W = Writable bit -n = Value at PO R

‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2)

111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled

110 = CPU Interrupt Priority Level is 6 (14)

101 = CPU Interrupt Priority Level is 5 (13)

100 = CPU Interrupt Priority Level is 4 (12)

011 = CPU Interrupt Priority Level is 3 (11)

010 = CPU Interrupt Priority Level is 2 (10)

001 = CPU Interrupt Priority Level is 1 (9)

000 = CPU Interrupt Priority Level is 0 (8)

Note 1: For complete register details, see Register 3-1: “SR: CPU Status Register”.

2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority

Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when

IPL<3> = 1.

3: The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) = 1.

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 R/C-0 R/W-0 U-0 U-0

— — — — IPL3(2) PSV — —

bit 7 bit 0

Legend: C = Clear only bit

R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set

0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’

bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(2)

1 = CPU interrupt priority level is greater than 7

0 = CPU interrupt priority level is 7 or less

Note 1: For complete register details, see Register 3-2: “CORCON: Core Control Register”.

2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.

PIC24FJ16MC101/102

R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

NSTDIS — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0

— — — MATHERR ADDRERR STKERR OSCFAIL —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 NSTDIS: Interrupt Nesting Disable bit

1 = Interrupt nesting is disab led

0 = Interrupt nesting is ena bled

bit 14-5 Unimplemented: Read as ‘0’

bit 4 MATHERR: Arithmetic Error Status bit

1 = Math error trap has occurred

0 = Math error trap has not occurred

bit 3 ADDRERR: Address Error Trap Status bit

1 = Address error trap has occurred

0 = Address error trap has not occurred

bit 2 STKERR: Stack Error Trap Status bit

1 = Stack error trap has occurred

0 = Stack error trap has not occurred

bit 1 OSCFAIL: Oscillator Failure Trap Status bit

1 = Oscillator failure trap has occurred

0 = Oscillator failure trap has not occurred

bit 0 Unimplemented: Read as ‘0’

PIC24FJ16MC101/102

R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0

ALTIVT DISI — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — INT2EP INT1EP INT0EP

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 ALTIVT: Enable Alternate In te rru pt Vector Table bit

1 = Use alternate vector table

0 = Use standard (default) vector table

bit 14 DISI: DISI Instruction Status bit

1 = DISI instruction is active

0 = DISI instruction is not active

bit 13-3 Unimplemented: Read as ‘0’

bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit

1 = Interrupt on negative edge

0 = Interrupt on positive edge

bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit

1 = Interrupt on negative edge

0 = Interrupt on positive edge

bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit

1 = Interrupt on negative edge

0 = Interrupt on positive edge

PIC24FJ16MC101/102

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF

bit 15 bit 8

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13 AD1IF: ADC1 Conversion Complete Interrupt Fl ag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 12 U1TXIF: UART1 Transmitter Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 11 U1RXIF: UART1 Receiver Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 10 SPI1IF: SPI1 Event Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 9 SPI1EIF: SPI1 Fault Interrupt Flag Sta tu s bi t

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 8 T3IF: Timer3 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 7 T2IF: Timer2 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 6 OC2IF: Output Compare Channel 2 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 5 IC2IF: Input Capture Channel 2 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 4 Unimplemented: Read as ‘0’

bit 3 T1IF: Timer1 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

PIC24FJ16MC101/102

bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 0 INT0IF: External Interrupt 0 Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

PIC24FJ16MC101/102

U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

——INT2IF— — — — —

bit 15 bit 8

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — INT1IF CNIF CMPIF MI2C1IF SI2C1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13 INT2IF: External Interrupt 2 Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 12-5 Unimplemented: Read as ‘0’

bit 4 INT1IF: External Interrupt 1 Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 3 CNIF: Input Change Notification Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 2 CMPIF: Comparator Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 1 MI2C1IF: I2C1 Master Events Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

PIC24FJ16MC101/102

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

——IC3IF— — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-6 Unimplemented: Read as ‘0’

bit 5 IC3IF: Input Capture Channel 3 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 4-0 Unimplemented: Read as ‘0’

R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 U-0

FLTA1IF RTCCIF — — — —PWM1IF—

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 FLTA1IF: PWM1 Fault A Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 14 RTCCIF: RTCC Interrupt Flag St atus bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 13-10 Unimplemented: Read as ‘0’

bit 9 PWM1IF: PWM1 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 8-0 Unimplemented: Read as ‘0’

PIC24FJ16MC101/102

U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

——CTMUIF— — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

— — — — — — U1EIF FLTB1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13 CTMUIF: CTMU Interrupt Flag Status bi t

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 12-2 Unimplemented: Read as ‘0’

bit 1 U1EIF: UART1 Erro r Interrupt Fla g Stat us bi t

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 0 FLTB1IF: PWM1 Fault B Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

PIC24FJ16MC101/102

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE

bit 15 bit 8

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13 AD1IE: ADC1 Conversion Comp lete Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 12 U1TXIE: UART1 Transmitter Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 11 U1RXIE: UART1 Receiver Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 10 SPI1IE: SPI1 Event Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 9 SPI1EIE: SPI1 Event Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 8 T3IE: Timer3 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 7 T2IE: Timer2 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 6 OC2IE: Output Compare Channel 2 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 5 IC2IE: Input Capture Channel 2 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 4 Unimplemented: Read as ‘0’

bit 3 T1IE: Timer1 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

PIC24FJ16MC101/102

bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 0 INT0IE: External Interrupt 0 Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

PIC24FJ16MC101/102

U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

——INT2IE— — — — —

bit 15 bit 8

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — INT1IE CNIE CMPIE MI2C1IE SI2C1IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13 INT2IE: External Interrupt 2 Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 12-5 Unimplemented: Read as ‘0’

bit 4 INT1IE: External Interrupt 1 Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 3 CNIE: Input Change Notification Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 2 CMPIE: Comparator Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

PIC24FJ16MC101/102

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

——IC3IE— — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-6 Unimplemented: Read as ‘0’

bit 5 IC3IE: Input Capture Channel 3 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 4-0 Unimplemented: Read as ‘0’

R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 U-0

FLTA1IE RTCCIE — — — —PWM1IE—

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 FLTA1IE: PWM1 Fault A Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 14 RTCCIE: RTCC Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 13-10 Unimplemented: Read as ‘0’

bit 9 PWM1IE: PWM1 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 8-0 Unimplemented: Read as ‘0’

PIC24FJ16MC101/102

U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

——CTMUIE— — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

— — — — — — U1EIE FLTB1IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13 CTMUIE: CTMU Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 12-2 Unimplemented: Read as ‘0’

bit 1 U1EIE: UART1 Error Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 0 FLTB1IE: PWM1 Fault B Interrupt Enable bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

PIC24FJ16MC101/102

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— T1IP<2:0> —OC1IP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

—IC1IP<2:0>— INT0IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

PIC24FJ16MC101/102

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— T2IP<2:0> —OC2IP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

—IC2IP<2:0>— — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 3-0 Unimplemented: Read as ‘0’

PIC24FJ16MC101/102

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— U1RXIP<2:0> — SPI1IP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— SPI1EIP<2:0> — T3IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 SPI1IP<2:0>: SPI1 Event Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 SPI1EIP<2:0>: SPI1 Error Interrupt Priority bit s

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

PIC24FJ16MC101/102

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

—AD1IP<2:0>— U1TXIP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-7 Unimplemented: Read as ‘0’

bit 6-4 AD1IP<2:0>: ADC1 Conversion Complete Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

PIC24FJ16MC101/102

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— CNIP<2:0> —CMPIP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— MI2C1IP<2:0> — SI2C1IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 CNIP<2:0>: Change Noti fication Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 CMPIP<2:0>: Comparator Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 MI2C1IP<2:0>: I2C1 Master Events Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

PIC24FJ16MC101/102

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0

— — — — — INT1IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-3 Unimplemented: Read as ‘0’

bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— INT2IP<2:0> — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-7 Unimplemented: Read as ‘0’

bit 6-4 INT2IP<2:0>: External Interrupt 2 Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 3-0 Unimplemented: Read as ‘0’

PIC24FJ16MC101/102

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

—IC3IP<2:0>— — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-7 Unimplemented: Read as ‘0’

bit 6-4 IC3IP<2:0>: External Interrupt 3 Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 3-0 Unimplemented: Read as ‘0’

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— PWM1IP<2:0> — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-7 Unimplemented: Read as ‘0’

bit 6-4 PWM1IP<2:0>: PWM1 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 3-0 Unimplemented: Read as ‘0’

PIC24FJ16MC101/102

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

—FLTA1IP<2:0>— RTCCIP<2:0>

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 FLTA1IP<2:0>: PWM1 Fault A Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 RTCCIP<2:0>: RTCC Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 7-0 Unimplemented: Read as ‘0’

PIC24FJ16MC101/102

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0

—U1EIP<2:0>—FLTB1IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-7 Unimplemented: Read as ‘0’

bit 6-4 U1EIP<2:0>: UART1 Error Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 FLTB1IP<2:0>: PWM1 Fault B Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

PIC24FJ16MC101/102

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

—CTMUIP<2:0>— — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-7 Unimplemented: Read as ‘0’

bit 6-4 CTMUIP<2:0>: CTMU Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 3-0 Unimplemented: Read as ‘0’

PIC24FJ16MC101/102

U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0

— — — —ILR<3:0>

bit 15 bit 8

U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

— VECNUM<6:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-12 Unimplemented: Read as ‘0’

bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits

1111 = CPU Interrupt Priority Level is 15

•

0001 = CPU Interrupt Priority Level is 1

0000 = CPU Interrupt Priority Level is 0

bit 7 Unimplemented: Read as ‘0’

bit 6-0 VECNUM<6:0>: Vector Number of Pending Interrupt bits

0111111 = Interrupt Vector pending is number 135

•

0000001 = Interrupt Vector pending is number 9

0000000 = Interrupt Vector pending is number 8

PIC24FJ16MC101/102

7.4 Interrupt Setup Procedures

7.4.1 INITIALIZATION

To configure an interrupt source at initialization:

1. Set the NSTDIS bit (INTCON1<15>) if nested

interrupts are not desired.

2. Select the user-assigned priority level for the

interrupt source by writing the control bits into

the appropriate IPCx register. The priority level

will depend on the specific application and type

of interrupt source. If multiple priority levels ar e

not desired, the IPCx re gister control bits for all

enabled interrupt sources can be programmed

to the same non-zero value.

3. Clear the interrupt flag status bit associated with

the peripheral in the asso ciated IFSx register.

4. Enable the interrupt sou rce by setting the inter-

rupt enable control bit associated with the

source in the appropriate IECx register.

7.4.2 INTERRUPT SERVICE ROUTINE

The method used to declare an ISR and initialize the

IVT with the correct vector address depends on the

programming language (C or assembler) and the

language development tool suite used to develop the

application.

In general, the user application must clear the interrupt

flag in the appropriate IFSx register for the source of

interrupt that the ISR handles. Otherwise, program will

re-enter the ISR immediately after exiting the routine. If

the ISR is coded in assembly language, it must be

terminated using a RETFIE instruction to unstack the

saved PC value, SRL value and old CPU priority level.

7.4.3 TRAP SERVICE ROUTINE

A Trap Service Routine (TSR) is coded like an ISR,

except that the appropriate trap status flag in the

INTCON1 register must be cleared to avoid re-entry

into the TSR.

7.4.4 INTERRUPT DISABLE

All user interrupts can be disabled using this

procedure:

1. Push the current SR value onto the software

stack using the PUSH instruction.

2. Force the CPU to priority level 7 by inclusive

ORing the value OEh with SRL.

To enable user interrupts, the POP instruction can be

used to restore the previous SR value.

The DISI instruction provides a convenient way to

disable interrupts of priority levels 1-6 for a fixed period

of time. Level 7 interrupt sources are not disabled by

the DISI instruction.

Note: At a device Reset, the IPCx registers

are initialized such that all user

interrupt sources are assigned to

priority level 4.

Note: Only user interrupts with a priority level of

7 or lower can be disab led. Trap sources

(level 8-level 15) cannot be disabled.

PIC24FJ16MC101/102

NOTES:

PIC24FJ16MC101/102

8.0 OSCILLATOR

CONFIGURATION The PIC24FJ16MC101/102 oscillator system provides:

• External and internal osci llator options as clock

sources

• An on-chip 4x Phase-Locked Loop (PLL) to scale

the internal operating frequency to the required

system clock frequency

• An internal FRC oscillator that can also be used

with the PLL, thereby allowing full-spee d

operation without any external clock generation

hardware

• Clock switching between various clock sources

• Programmable clock postscaler for system power

savings

• A Fail-Safe Clock Monitor (FSCM) that detects

clock failure and takes fail-safe measures

• A Clock Control register (OSCCON)

• Nonvolatile Configuration bits for main oscillator

selection

A simplified diagram of th e oscillator system is shown

in Figure 8-1.

FIGURE 8-1: PIC24FJ16MC101/102 OSCILLATOR SYSTEM DIAGRAM

Note 1: This data sheet summarizes the features

of the PIC24FJ16MC101/102 family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 6. “Oscillator”

(DS39700) in the “PIC24F Family

Reference Manual”, which is available

from the Microchip web site

(www.microchip.com).

2: It is important to note that the

specifications in Section 26.0 “Electri-

cal Characteristics” of this data sheet,

supercede any specifications that may be

provided in PIC24F Family Reference

Manual sections.

3: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Note 1: If the Oscillator is used with MS or HS modes, an extended parallel resistor with the value of 1 MΩ must be connected.

2: The term FP refers to th e clock source for all peripheral s, whil e FCY refers to the clock sour ce for t he CPU. Througho ut thi s document,

FP and FCY are used interchangeably, except in the case of DOZE mode. FP and FCY are different when DOZE mode is used with a

doze ratio of 1:2 or lower.

Secondary Oscillator (SOSC)

LPOSCEN

SOSCO

SOSCI

Timer 1

MSPLL, ECPLL,

MS, HS, EC

FRCDIV<2:0>

WDT, PWRT, FSCM

FRCDIVN

SOSC

FRCDIV16

FRCPLL

NOSC<2:0> FNOSC<2:0>

Reset

FRC

Oscillator

LPRC

Oscillator

DOZE<2:0>

S1/S3

FRC

LPRC

÷16

Clock Switch

Clock Fail

÷2

TUN<5:0>

4x PLL

FCY(2)

FRCDIV

DOZE

OSC2

OSC1 Primary Oscillator (POSC)

R(1)

POSCMD<1:0>

FP(2)

Fosc

(To peripherals)

PIC24FJ16MC101/102

8.1 CPU Clocking System

The PIC24FJ16MC101/102 devices provide seven

system clock options:

• Fast RC (FRC) Oscillator

• FRC Oscillator with 4x PLL

• Primary (MS, HS or EC) Oscillator

• Primary Oscillator with 4x PLL

• Secondary (LP) Oscillator

• Low-Power RC (LPRC) Oscillator

• FRC Oscillator with postscaler

8.1.1 SYSTEM CLOCK SOURCES

8.1.1.1 Fast RC

The Fast RC (FRC) internal oscillator runs at a nominal

frequency of 7.37 MHz. User software can tune the

FRC frequency. User software can optionally specify a

factor (ranging from 1:2 to 1:256) by which the FRC

clock frequency is divided. This factor is selected using

the FRCDIV<2:0> (CLKDIV<10:8>) bits.

The FRC frequency depends on the FRC accuracy

(see Table 26-18) and the value of the FRC Oscillator

Tuning register (see Register 8-3).

8.1.1.2 Primary

The primary oscillator can u se one of the following as

its clock source:

• MS (Crystal): Crystals and ceramic resonators in

the range of 4 MHz to 10 MHz. The crystal is

connected to the OSC1 and OSC2 pins.

• HS (High-Speed Crystal): Crystals in the range of

10 MHz to 32 MHz. The crystal is connected to

the OSC1 and OSC2 pins.

• EC (External Clock): The external clock signal is

directly applied to the OSC1 pin.

8.1.1.3 Secondary

The secondary (LP) oscillator is designed for low power

and uses a 32.768 kHz crystal or ceramic resonator.

The LP oscillator uses the SOSCI and SOSCO pins.

8.1.1.4 Low-Power RC

The Low-Power RC (LPRC) internal oscIllator runs at a

nominal frequency of 32.76 8 kHz. It is also used as a

reference clock by the Watchdog Timer (WDT) and

Fail-Safe Clock Monitor (FSCM).

8.1.1.5 PLL

The clock signals generated by the FRC and primary

oscillators can be optionally applied to an on-chip 4x

Phase-Locked Loop (PLL) to provide faster output

frequencies for device operation. PLL configuration is

described in Section 8.1.3 “PLL Configuration”.

8.1.2 SYSTEM CLOCK SELECTION

The oscillator source used at a device Power-on

Reset event is selected using Configuration bit

settings. The oscillator Configuration bit settings are

located in the Configuration registers in the program

memory. (Refer to Section 23.1 “Configuration

Bits” for further details.) The Initial Oscillator

Selection Configuration bits, FNOSC<2:0>

(FOSCSEL<2:0>), and the Primary Oscillator Mode

Select Configuration bits, POSCMD<1:0>

(FOSC<1:0>), select the oscillato r source that is used

at a Power-on Reset. The FRC primary oscillator is

the default (unprogrammed) selection.

The Configuration bits allow users to choose among 12

different clock modes, shown in Table 8-1.

The output of the oscilla tor (or the output of the PLL if

a PLL mode has been selected) FOSC is divided by 2 to

generate the device instruction clock (FCY) and the

peripheral clock time base (FP). FCY defines the

operating speed of the device, and speeds up to 40

MHz are supported by the PIC24FJ16MC101/102

architecture.

Instruction execution speed or device operating

frequency, FCY, is given by:

EQUATION 8-1: DEVICE OPERATING

FREQUENCY

FCY FOSC

-------------=

PIC24FJ16MC101/102

8.1.3 PLL CONFIGURATION

The primary oscillator and internal FRC oscillator can

optionally use an on-chip 4x PLL to obtain higher

speeds of operation.

For example, suppose a 8 MHz crystal is being used

with the selected oscillator mode o f MS with PLL. This

provides a Fosc of 8 MHz * 4 = 32 MHz. The resultant

device operating speed is 32/2 = 16 MIPS.

EQUATION 8-2: MS WITH PLL MODE

EXAMPLE

TABLE 8-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION

FCY FOSC

------------- 1

---8000000 4⋅()16 MIPS== =

Oscillator Mode Oscillator

Source POSCMD<1:0> FNOSC<2:0> See

Note

Fast RC Oscillator with Divide-by-n (FRCDIVN) Internal xx 111 1, 2

Fast RC Oscillator with Divide-by-16 (FRCDIV16) Internal xx 110 1

Low-Power RC Oscillator (LPRC) Internal xx 101 1

Secondary (T imer1) Oscillator (SOSC) Secondary xx 100 1

Primary Oscillator (MS) with PLL (MSPLL) Primary 01 011 —

Primary Oscillator (EC) with PLL (ECPLL) Primary 00 011 1

Primary Oscillator (HS) Primary 10 010 —

Primary Oscillator (MS) Primary 01 010 —

Primary Oscillator (EC) Primary 00 010 1

Fast RC Oscillator (FRC) with Divide-by-n and

PLL (FRCPLL) Internal xx 001 1

Fast RC Oscillator (FRC) Internal xx 000 1

Note 1: OSC2 pin function is determined by th e OSCIOFNC Configuration bit.

2: This is the default oscillator mode for an unprogrammed (erased) device.

PIC24FJ16MC101/102

U-0 R-0 R-0 R-0 U-0 R/W-y R/W-y R/W-y

— COSC<2:0> — NOSC<2:0>(2)

bit 15 bit 8

R/W-0 R/W-0 R-0 U-0 R/C-0 U-0 R/W-0 R/W-0

CLKLOCK IOLOCK LOCK —CF — LPOSCEN OSWEN

bit 7 bit 0

Legend: y = Value set from Configuratio n bits on POR C = Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 COSC<2:0>: Current Osci llator Selection bits (read-only)

111 = Fast RC Oscillator (FRC) with Divide-by-n

110 = Fast RC Oscillator (FRC) with Divide-by-16

101 = Low-Power RC Oscillator (LPRC)

100 = Secondary Oscillator (SOSC)

011 = Primary Oscillator (MS, EC) with PLL

010 = Primary Oscillator (MS, HS, EC)

001 = Fast RC Oscillator (FRC) with Divide-by-n and with PLL (FRCPLL)

000 = Fast RC Oscillator (FRC)

bit 11 Unimplemented: Read as ‘0’

bit 10-8 NOSC<2:0>: New Oscilla tor Selection bits(2)

111 = Fast RC Oscillator (FRC) with Divide-by-n

110 = Fast RC Oscillator (FRC) with Divide-by-16

101 = Low-Power RC Oscillator (LPRC)

100 = Secondary Oscillator (SOSC)

011 = Primary Oscillator (MS, EC) with PLL

010 = Primary Oscillator (MS, HS, EC)

001 = Fast RC Oscillator (FRC) with Divide-by-n and PLL (FRCPLL)

000 = Fast RC Oscillator (FRC)

bit 7 CLKLOCK: Clock Lock Enable bit

If clock switching is enabled and FSCM is disabled, (FOSC<FCKSM> = 0b01)

1 = Clock switching is disabled, system clock source is locked

0 = Clock switching is enabled, system clock source can be modified by clock switching

bit 6 IOLOCK: Peripheral Pin Select Lock bit

1 = Peripherial pin select is locked, write to peripheral pin select registers not allowed

0 = Peripherial pin select is not locked, write to peripheral pin select registers allowed

bit 5 LOCK: PLL Lock Status bit (rea d-on l y)

1 = Indicates that PLL is in lock, or PLL start-up timer is satisfied

0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled

bit 4 Unimplemented: Read as ‘0’

bit 3 CF: Clock Fail Detect bit (read/clear by application)

1 = FSCM has detected clock failure

0 = FSCM has not detected clock failure

bit 2 Unimplemented: Read as ‘0’

Note 1: Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS39700) in the

“PIC24F Family Reference Manual” for details.

2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.

This applies to clock switches in either direction. In these inst an ce s, th e ap p l ic ation must switch to FRC

mode as a transition clock source between the two PLL modes.

PIC24FJ16MC101/102

bit 1 LPOSCEN: Secondary (LP) Oscillator Enable bit

1 = Enable Secondary Oscillator

0 = Disable Secondary Oscillator

bit 0 OSWEN: Oscillator Switch Enable bit

1 = Request oscillator switch to selection specified by NOSC<2:0> bits

0 = Oscillator switch is complete

Note 1: Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS39 700) in the

“PIC24F Family Reference Manual” for details.

2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.

This applies to clock switches in eith er direction. In these instances, the application must switch to FRC

mode as a transition clock source between the two PLL modes.

PIC24FJ16MC101/102

R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0

ROI DOZE<2:0>(2,3) DOZEN(1,2,3) FRCDIV<2:0>

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleare d x = Bit is unknown

bit 15 ROI: Recover on Interrupt bit

1 = Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1

0 = Interrupts have no effect on the DOZEN bit

bit 14-12 DOZE<2:0>: Processor Clock Reduction Select bits(2,3)

111 = FCY/128

110 = FCY/64

101 = FCY/32

100 = FCY/16

011 = FCY/8 (default)

010 = FCY/4

001 = FCY/2

000 = FCY/1

bit 11 DOZEN: DOZE Mode Ena ble bit(1,2,3)

1 = DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks

0 = Processor clock/peripheral clock ratio forced to 1:1

bit 10-8 FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits

111 = FRC divide by 256

110 = FRC divide by 64

101 = FRC divide by 32

100 = FRC divide by 16

011 = FRC divide by 8

010 = FRC divide by 4

001 = FRC divide by 2

000 = FRC divide by 1 (default)

bit 7-0 Unimplemented: Read as ‘0’

Note 1: This bit is cle are d wh en the ROI bit is set and an interrupt occurs.

2: If DOZEN = 1, writes to DOZE<2:0> are ignored.

3: If DOZE<2:0> = 000, the DOZEN bit cannot be set by the user; writes are ignored.

PIC24FJ16MC101/102

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— TUN<5:0>(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-6 Unimplemented: Read as ‘0’

bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(1)

011111 = Center frequency +11.625% (8.23 MHz)

011110 = Center frequency +11.25% (8.20 MHz)

•

000001 = Center frequency +0.375% (7.40 MHz)

000000 = Center frequency (7.37 MHz nominal)

111111 = Center frequency -0.375% (7.345 MHz)

•

100001 = Center frequency -11.625% (6.52 MHz)

100000 = Center frequency -12% (6.49 MHz)

Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the

FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither

characterized nor tested.

PIC24FJ16MC101/102

8.2 Clock Switching Operation

Applications are free to switch among any of the four

clock sources (Primary, LP, FRC, and LPRC) under

software control at any time . To limit the possible sid e

effect s of this flexibility, PIC24FJ16MC101/102 devices

have a safeguard lock built into the switch process.

8.2.1 ENABLING CLOCK SWITCHING

To enable clock switching, th e FCKSM1 Configuration

bit in the Configuration register must be programmed to

‘0’. (Refer to Section 23.1 “Configuration Bits” for

further details.) If the FCKSM1 Configuration bit is

unprogrammed (‘1’), the clock switching function and

Fail-Safe Clock Monitor function are disabled. This is

the default setting.

The NOSC control bits (OSCCON<10:8>) do not

control the clock selection when clock switching is

disabled. However, the COSC bits (OSCCON<14:12>)

reflect the clock source selected by the FNOSC

Configuration bits.

The OSWEN control bit (OSCCON<0>) has no effect

when clock switching is disabled. It is he ld at ‘0’ at all

times.

8.2.2 OSCILLATOR SWITCHING SEQUENCE

Performing a clock switch requires this basic

sequence:

1. If desired, read the COSC bits

(OSCCON<14:12>) to determine the current

oscillator source.

2. Perform the unlock seque nce to allow a write to

the OSCCON register high byte.

3. Write the appropriate value to the NOSC control

bits (OSCCON<10:8>) for the new oscillator

source.

4. Perform the unlock seque nce to allow a write to

the OSCCON register low byte.

5. Set the OSWEN bit (OSCCON<0>) to initiate

the oscillator switch.

Once the basic sequence is completed, the system

clock hardware responds automatically as follows:

1. The clock switching hardware compares the

COSC status bits with the new value of the

NOSC control bits. If they are the same, the

clock switch is a redundant operation. In this

case, the OSWEN bit is cleared automatically

and the clock switch is aborted.

2. If a valid clock switch has been initiated, the

LOCK (OSCCON<5>) and the CF

(OSCCON<3>) status bits are cleared.

3. The new oscillator is turned on by the hardware

if it is not currently running. If a crystal oscillator

must be turned on, th e hardware waits until the

Oscillator Start-up Timer (OST) expires. If the

new source is using the PLL, the hardware waits

until a PLL lock is detected (LOCK = 1).

4. The hardware waits for 10 clock cycles from the

new clock source and then performs the clock

switch.

5. The hardware clears the OSWEN bit to indicate a

successful clock transition. In addition, the NOSC

bit values are transferred to the COSC status bits.

6. The old clock source is turned off at this time,

with the exception of LPRC (if WDT or FSCM

are enabled) or LP (if LPOSCEN remains set).

8.3 Fail-Safe Clock Monitor (FSCM)

The Fail-Safe Clock Monitor (FSCM) allows the device

to continue to operate even in the event of an oscillator

failure. The FSCM function is enabled by programming.

If the FSCM function is enabled, the LPRC internal

oscillator runs at all times (except during Sleep mode)

and is not subject to control by the Watchdog Timer.

In the event of an oscillator failure, the FSCM

generates a clock failure trap event and switches the

system clock over to the FRC oscillator. Then the

application program can either attempt to restart the

oscillator or execute a controlled shutdown. The trap

can be treated a s a warm Reset by simply loading the

Reset address into the oscillator fail trap vector.

If the PLL multiplier is used to scale the system clock,

the internal FRC is also multiplied by the same factor

on clock failure. Essentially, the device switches to

FRC with PLL on a clock failure.

Note: Primary Oscillator mode has three different

submodes (MS, HS, and EC), which are

determined by the POSCMD<1:0> C onfig-

uration bits. While an application can

switch to and from Primary Oscillator

mode in software, it cannot switch among

the different primary submodes without

reprogramming the device.

Note 1: The processor continues to execute code

throughout the clock switching sequence.

Timing-sensitive code should not be

executed during this time.

2: Direct clock switches between any pri-

mary oscillator mode with PLL and

FRCPLL mode are not permitted. This

applies to clock switches in either direc-

tion. In these instances, the application

must switch to FRC mode as a transition

clock source between the two PLL modes.

3: Refer to Section 6. “Oscillator”

(DS39700) in the “PIC24F Family

Reference Manu al” fo r details.

PIC24FJ16MC101/102

9.0 POWER-SAVING FEATURES

The PIC24FJ16MC101/1 02 devices provide the ability

to manage power consumption by selectively

managing clocking to the CPU and the peripherals. In

general, a lower clock frequency and a reduction in the

number of circuits being clocked constitutes lower

consumed power. PIC24FJ1 6MC101/102 devices can

manage power consumption in four different ways:

• Clock frequency

• Instruction-based Sleep and Idle modes

• Software-controlled Doze mode

• Selective peripheral control in software

Combinations of these methods can be used to selec-

tively tailor an application’s power consumption while

still maintaining critical application features, such as

timing-sensitive communications .

9.1 Clock Frequency and Clock

Switching

PIC24FJ16MC101/102 devices allow a wide range of

clock frequencies to be selected under application

control. If the system clock configuration is not locked,

users can choose low-power or high-precision

oscillators by simply changing the NOSC bits

(OSCCON<10:8>). The process of changing a system

clock during operation, as well as limitations to the

process, are discussed in more detail in Section 8.0

“Oscillator Configuration” .

9.2 Instruction-Based Power-Saving

Modes

PIC24FJ16MC101/102 devices have two special

power-saving modes that are entered through the

execution of a special PWRSAV instruction. Sleep mode

stops clock operation and halts all code execution. Idle

mode halts the CPU and code execution, but allows

peripheral modules to continue operation. The

assembler syntax of the PWRSAV instruction is shown in

Example 9-1.

Sleep and Idle modes can be exited as a result of an

enabled interrupt, WDT time-out or a device Reset. When

the device exits these mo des, it is said to w ake-up.

9.2.1 SLEEP MODE

The following occur in Sleep mode:

• The system clock source is shut down. If an

on-chip oscillator is used, it is turned off.

• The device current consumption is reduce d to a

minimum, provided that no I/O pin is sourcing

current

• The Fail-Safe Clock Monitor does not operate,

since the system clock source is disabled

• The LPRC clock continues to run in Sleep mode if

the WDT is enabled

• The WDT, if enabled, is automatically cleared

prior to entering Sleep mode

• Some device features or peripherals may continue

to operate. This includes items such as the input

change notification on the I/O ports, or peripherals

that use an external clock input.

• Any peripheral that requires the system clock

source for its operation is disabled

The device will wake-up from Sleep mode on any of the

these events:

• Any interrupt source that is individually enabled

• Any form of device Reset

• A WDT time-out

On wake-up from Sleep mode, the processor restarts

with the same clock source that was active when Sleep

mode was entered.

EXAMPLE 9-1: PWRSAV INSTRUCTION SYNTAX

Note 1: This data sheet summarizes the features

of the PIC24FJ16MC101/102 family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 9. “Watchdog

Timer (WDT)” (DS39697) and Section

10. “Power-Saving Features”

(DS39698) in the “PIC24F Family

Reference Manual”, which are available

from the Microchip web site

(www.microchip.com).

2: It is important to note that the

specifications in Section 26.0 “Electri-

cal Characteristics” of this data sheet,

supercede any specifications that may be

provided in PIC24F Family Reference

Manual sections.

3: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Note: SLEEP_MODE and IDLE_MODE are

constants defined in the assembler

include file for the selected device.

PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode

PWRSAV #IDLE_MODE ; Put the device into IDLE mode

PIC24FJ16MC101/102

9.2.2 IDLE MODE

The following occur in Idle mode:

• The CPU stops executing instructions

• The WDT is automatically cleared

• The system clock source remains active. By

default, all peripheral modules continue to operate

normally from the system clock source, but can

also be selectively disabled (see Section 9.4

“Peripheral Module Disable”).

• If the WDT or FSCM is enabled, the LPRC also

remains active.

The device will wake from Idle mode on any of these

events:

• Any interrupt that is individually enabled

• Any device Reset

• A WDT time-out

On wake-up from Idle mode, the clock is reapplied to

the CPU and instruction execution will begin (2-4 clock

cycles later), starting with the instruction following the

PWRSAV instruction, or the first instruction in the ISR.

9.2.3 INTERRUPTS COINCIDENT WITH

POWER-SAVE INSTRUCTIONS

Any interrupt that coincides with the execution of a

PWRSAV instruction is held off until entry into Sleep or

Idle mode has completed. The device then wakes up

from Sleep or Idle mode.

9.3 Doze Mode

The preferred strategies for reducing power

consumption are changing clock speed and invoking

one of the power-saving modes. In some

circumstances, this may not be practical. For example,

it may be necessary for an application to maintain

uninterrupted synchronous communication, even while

it is doing nothing else. Reducing system clock spee d

can introduce communication errors, while using a

power-saving mode can stop communications

completely.

Doze mode is a simple and effective alternative method

to reduce power consumption while the device is still

executing code. In this mode, the system clock

continues to operate from the same source and at the

same speed. Peripheral modules continue to be

clocked at the same speed, while the CPU clock speed

is reduced. Synchronization between the two clock

domains is maintained, allowing the peripherals to

access the SFRs while the CPU executes code at a

slower rate.

Doze mode is enabled by setting the DOZEN bit

(CLKDIV<11>). The ratio between peripheral and core

clock speed is determined by the DOZE<2:0> bits

(CLKDIV<14:12>). There are eight possible

configurations, from 1:1 to 1:128, with 1:1 being the

default setting.

Programs can use Doze mode to selectively reduce

power consumption in event-driven applications. This

allows clock-sensitive functions, such as synchronous

communications, to continu e witho ut interruption while

the CPU idles, waiting for something to invoke an

interrupt routine. An automatic return to full-speed CPU

operation on interrupts can be enabled by setting the

ROI bit (CLKDIV<15>). By default, interrupt events

have no effect on Doze mode operation.

For example, suppose the device is operating at

20 MIPS and the UART module has been configured

for 500 kbps based on this device operating speed. If

the device is placed in Doze mode with a clock

frequency ratio of 1:4, the UART module continues to

communicate at the required bit rate of 500 kbps, but

the CPU now starts executing instructions at a

frequency of 5 MIPS.

9.4 Peripheral Module Disable

The Peripheral Module Disable (PMD) registers

provide a method to disable a peripheral module by

stopping all clock sources supplied to that module.

When a peripheral is disabled using the appropriate

PMD control bit, the peripheral is in a minimum po wer

consumption state. The control and status registers

associated with the peripheral are also disabled, so

writes to those registers will have no effect and read

values will be invalid.

A peripheral module is enabled only if both the

associated bit in the PMD register is cleared and the

peripheral is supported by the specific PIC24FXXXX

variant. If the peripheral is present in the device, it is

enabled in the PMD registe r by default.

Note: If a PMD bit is set, the corresponding

module is disabled after a delay of one

instruction cycle. Similarly, if a PMD bit is

cleared, the corresponding module is

enabled after a delay of one instruction

cycle (assuming the module control regis-

ters are already configured to enable

module operation).

PIC24FJ16MC101/102

U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0

—— T3MD T2MD T1MD —PWM1MD—

bit 15 bit 8

R/W-0 U-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0

I2C1MD —U1MD—SPI1MD——AD1MD

(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13 T3MD: Timer3 Module Disable bit

1 = T imer3 module is disabled

0 = T imer3 module is enabled

bit 12 T2MD: Timer2 Module Disable bit

1 = T imer2 module is disabled

0 = T imer2 module is enabled

bit 11 T1MD: Timer1 Module Disable bit

1 = T imer1 module is disabled

0 = T imer1 module is enabled

bit 10 Unimplemented: Read as ‘0’

bit 9 PWM1MD: PWM1 Module Disable bit

1 = PWM1 module is disabled

0 = PWM1 module is enabled

bit 18 Unimplemented: Read as ‘0’

bit 7 I2C1MD: I2C1 Module Disable bit

1 = I2C1 module is disabled

0 = I2C1 module is enabled

bit 6 Unimplemented: Read as ‘0’

bit 5 U1MD: UART1 Module Disable bit

1 = UART1 module is disabled

0 = UART1 module is enabled

bit 4 Unimplemented: Read as ‘0’

bit 3 SPI1MD: SPI1 Module Disable bit

1 = SPI1 module is disabled

0 = SPI1 module is enabled

bit 2-1 Unimplemented: Read as ‘0’

bit 0 AD1MD: ADC1 Module Disable bit(1)

1 = ADC1 module is disabled

0 = ADC1 module is enabled

Note 1: PCFGx bits have no effect if the ADC module is disabled by setting this bit. When the bit is set, all port

pins that have been multiplexed with ANx will be in Digital mode.

PIC24FJ16MC101/102

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

————— IC3MD IC2MD IC1MD

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

——————OC2MDOC1MD

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-11 Unimplemented: Read as ‘0’

bit 10 IC3MD: Input Capture 3 Module Disable bit

1 = Input Capture 3 module is disabled

0 = Input Capture 3 module is enabled

bit 9 IC2MD: Input Capture 2 Module Disable bit

1 = Input Capture 2 module is disabled

0 = Input Capture 2 module is enabled

bit 8 IC1MD: Input Capture 1 Module Disable bit

1 = Input Capture 1 module is disabled

0 = Input Capture 1 module is enabled

bit 7-2 Unimplemented: Read as ‘0’

bit 1 OC2MD: Output Compare 2 Module Disable bit

1 = Output Compare 2 module is disabled

0 = Output Compare 2 module is enabled

bit 0 OC1MD: Output Compare 1 Module Disable bit

1 = Output Compare 1 module is disabled

0 = Output Compare 1 module is enabled

PIC24FJ16MC101/102

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0

————— CMPMD RTCCMD —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-11 Unimplemented: Read as ‘0’

bit 10 CMPMD: Comparator Module Disable bit

1 = Comparator module is disabled

0 = Comparator module is enabled

bit 9 RTCCMD: RTCC Module Disable bit

1 = RTCC module is disabled

0 = RTCC module is enabled

bit 8-0 Unimplemented: Read as ‘0’

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0

—————CTMUMD— —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-4 Unimplemented: Read as ‘0’

bit 3 CTMUMD: CTMU Module Disable bit

1 = CTMU module is disabled

0 = CTMU module is enabled

bit 2-0 Unimplemented: Read as ‘0’

PIC24FJ16MC101/102

NOTES:

PIC24FJ16MC101/102

10.0 I/O PORTS

All of the device pins (except VDD, VSS, MCLR, and

OSC1/CLKI) are shared among the peripherals and the

parallel I/O ports. All I/O input ports feature Schmitt

Trigger inputs for improved noise immunity.

10.1 Parallel I/O (PIO) Ports

Generally a parallel I/O port that shares a pin with a

peripheral is subservient to the peripheral. The

peripheral’s output buffer data and control signals are

provided to a pair of multiplexers. The multiplexers

select whether the peripheral or the associated port

has ownership of the output data and control signals of

the I/O pin. The logic also prevents “loop through,” in

which a port’s digital output can drive the input of a

peripheral that shares the same pin. Figure 10-1 shows

how ports are shared with other peripherals and the

associated I/O pin to which they are connected.

When a peripheral is enabled and the peripheral is

actively driving an associated pin, the use of the pin as

a general purpose output pin is disabled. The I/O pin

can be read, but the output driver for the parallel port bit

is disabled. If a peripheral is enabled, but the peripheral

is not actively driving a pin, that pin can be driven by a

port.

All port pins have three registers directly associated

with their operation as digital I/O. The data direction

or an output. If the data direction bit is a ‘1’, the pin is

an input. All port pins are defined as inputs after a

Reset. Reads from the latch (LATx) read the latch.

Writes to the latch write the latch. Reads from the port

(PORTx) read the port pins, while writes to the port pins

write the latch.

Any bit and its associated data and control registers

that are not valid for a particular device will be

disabled. This means the corresponding LATx and

TRISx registers and the port pin will read as zeros.

When a pin is shared with another peripheral or

function that is defined as an input only, it is

nevertheless regarded as a dedicated port because

there is no other competing source of outputs.

FIGURE 10-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE

Note 1: This data sheet summarizes the features

of the PIC24FJ16MC101/102 family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 12. “I/O Ports

with Peripheral Pin Select (PPS)”

(DS39711) in the “PIC24F Family

Reference Manual”, which is available

from the Microchip web site

(www.microchip.com).

2: It is important to note that the

specifications in Section 26.0 “Electri-

cal Characteristics” of this data sheet,

supercede any specifications that may be

provided in PIC24F Family Reference

Manual sections.

3: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

WR LAT +

TRIS Latch

I/O Pin

WR Port

Data Bus

Data Latch

Read Port

Read TRIS

WR TRIS

Peripheral Output Data Output Enable

Peripheral Input Data

I/O

Peripheral Module

Peripheral Output Enable

PIO Module

Output Multiplexers

Output Data

Input Data

Peripheral Module Enable

Read LAT

PIC24FJ16MC101/102

10.1.1 OPEN-DRAIN CONFIGURATION

In addition to the PORT, LAT, and TRIS registers for

data control, some port pins can also be individually

configured for either digital or open-drain output. This

is controlled by the Open-Drain Control register,

ODCx, associated with each port. Setting any of the

bits configures the corresponding pin to act as an

open-drain output.

The open-drain feature allows the generation of

outputs higher than VDD (e.g., 5V) on any desired 5V

tolerant pins by using external pull-up resistors. The

maximum open-drain voltage allowed is the same as

the maximum VIH specification.

See “Pin Diagrams” for the available pins and their

functionality.

10.2 Configuring Analog Port Pins

The AD1PCFG and TRIS registers control the opera-

tion of the analog-to-digital port pins. The port pins that

are to function as analog inputs must have their corre-

sponding TRIS bit set (i nput). If the TRIS bi t is cleare d

(output), the digital output level (VOH or VOL) will be

converted.

The AD1PCFGL register has a default value of 0x0000;

therefore, all pins that share ANx functions are analo g

(not digital) by default.

When the PORT register is read, all pins configured as

analog input channels will read as cleared (a low level).

Pins configured as digital inputs will not convert an

analog input. Analog levels on any pin defined as a

digital input (including the ANx pins) can cause the

input buffer to consume current that exceeds the

device specifications.

10.2.1 I/O PORT WRITE/READ TIMING

One instruction cycle is required between a port

direction change or port write operation and a read

operation of the same port. Typically this instruction

would be an NOP. An demonstration is shown in

Example 10-1.

10.3 Input Change Notification

The input change notification function of the I/O ports

allows the PIC24FJ16MC101 /102 devices to generate

interrupt requests to the processor in response to a

change-of-state on selected input pins. This feature

can detect input change-of-states even in Sleep mode,

when the clocks are disabled. Depending on the device

pin count, up to 21 external signals (CNx pin) can be

selected (enabled) for generating an interrupt request

on a change-of-state.

Four control registers are associated with the CN mod-

ule. The CNEN1 and CNEN2 registers contain the

interrupt enable control bits for each of the CN input

pins. Setting any of these bits enables a CN interrupt

for the corresponding pins.

Each CN pin also has a weak pull-up connected to it.

The pull-ups act as a current source connected to the

pin, and eliminate the need for external resistors when

push-button or keypad devices are connected. The

pull-ups are enabled separately using the CNPU1 and

CNPU2 registers, which contain the control bits for

each of the CN pins. Setting any of the control bits

enables the weak pull-ups for the corresponding pins.

EXAMPLE 10-1: PORT WRITE/READ EXAMPLE

Note: Pull-ups on change notification pins

should always be disabled when the port

pin is configured as a digital output.

MOV 0xFF00, W0 ; Configure PORTB< 15:8> a s input s

MOV W0, TRISBB ; and PORTB<7:0> a s outpu ts

NOP ; Delay 1 cycle

btss PORTB, #13 ; Next Instruction

PIC24FJ16MC101/102

10.4 Peripheral Pin Select

Peripheral pin select configuration enables peripheral

set selection and placement on a wide range of I/O

pins. By increasing the pinout options available on a

particular device, programmers can better tailor the

microcontroller to their entire application, rather than

trimming the application to fit the device .

The peripheral pin select configuration feature oper-

ates over a fixed subset of digital I/O pins. Program-

mers can independently map the input and/or output

of most digital peripherals to any one of these I/O

pins. Peripheral pin select is performed in software,

and generally does not require the device to be

reprogrammed. Hardware safeguards are included

that prevent accidental or spurious changes to the

peripheral mapping, once it has been established.

10.4.1 AVAILABLE PINS

The peripheral pin select feature is used with a range

of up to 16 pins. The number of available pins depends

on the particular device and its pin count. Pins that

support the peripheral pin select feature include the

designation “RPn” in their full pin designation, where

“RP” designates a remappable peripheral and “n” is the

remappable pin number.

10.4.2 CONTROLLING PERIPHERAL PIN

SELECT

Peripheral pin select features are controlled through

two sets of special function registers: one to map

peripheral inputs, and one to map outputs. Because

they are separately controlled, a particular peripheral’s

input and output (if the peripheral has both) can be

placed on any selectable function pin without

constraint.

The association of a pe ripheral to a peripheral select-

able pin is handled in two different ways, depending on

whether an input or output is being mappe d.

10.4.2.1 Input Mapping

The inputs of the peripheral pin select options are

mapped on the basis of the peripheral. A control

will be mapped to. The RPINRx registers are used to

configure peripheral input mapp ing (see Register 10-1

through Register 10-8). Each register contains sets of

5-bit fields, with each set associated with one of the

remappable peripherals. Programming a given

peripheral’s bit field with an appropriate 5-bit value

maps the RPn pin with that value to that peripheral.

For any given device, the valid range of values for any

bit field corresponds to the maximum number of

peripheral pin selections supported by the device.

Figure 10-2 Illustrates remappable pin selection for

U1RX input.

FIGURE 10-2: REMAPPABLE MUX

INPUT FOR U1RX

Note: For input mapping only , the Peripheral Pin

Select (PPS) functionality does not have

priority over the TRISx settings. There-

fore, when configuring the RPx pin for

input, the corresponding bit in the TRISx

(i.e., set to ‘1’).

RP0

RP1

RP2

U1RX input

U1RXR<4:0>

to peripheral

PIC24FJ16MC101/102

TABLE 10-1: SEL E C TAB L E INPUT SOURCES (M A PS I N P U T T O FUNCTION)(1)

10.4.2.2 Output Mapping

In contrast to inputs, the outputs of the peripheral pin

select options are mapped on the basis of the pin. In

this case, a control register associated with a particular

pin dictates the peripheral output to be mapped. The

RPORx registers are used to control output mapping.

Like the RPINRx registers, each register contains sets

of 5-bit fields, with each set associated with one RPn

pin (see Register 10-9 through Register 10-16). The

value of the bit field corresponds to one of the perip h-

erals, and that peripheral’s output is mapped to the pin

(see Table 10-2 and Figure 10-3).

The list of peripherals for output mapping also includes

a null value of ‘00000’ because of the mapping

technique. This permits any given pin to remain

unconnected from the output of any of the pin

selectable peripherals.

FIGURE 10-3: MULTIPLEXING OF

REMAPPABLE OUTPUT

FOR RPn

Input Name Function Name Register Configuration

Bits

External Interrupt 1 INT1 RPINR0 INT1R<4:0>

External Interrupt 2 INT2 RPINR1 INT2R<4:0>

Timer2 External Clock T2CK RPINR3 T2CKR<4:0>

Timer3 External Clock T3CK RPINR3 T3CKR<4:0>

Input Capture 1 IC1 RPINR7 IC1R<4:0>

Input Capture 2 IC2 RPINR7 IC2R<4:0>

Input Capture 3 IC3 RPINR8 IC3R<4:0>

Output Compare Fault A OCFA RPINR11 OCFAR<4:0>

UART1 Receive U1RX RPINR18 U1RXR<4:0>

UART1 Clear To Send U1CTS RPINR18 U1CTSR<4:0>

SPI1 Slave Select Input SS1 RPINR21 SS1R<4:0>

Note 1: Unless otherwise noted, all inputs use the Schmitt inpu t buffers.

RPnR<4:0>

default

U1TX Output enable

U1RTS Output enable 4

UPDN Output enable 19

OC2 Output enable

default

U1TX Output

U1RTS Output 4

UPDN Output 19

OC2 Output

Output enable

Output Data RPn

PIC24FJ16MC101/102

TABLE 10-2: OUTPUT SELECTION FOR REMAPPABLE PIN (RPn)

10.4.3 CONTROLLING CONFIGURATION

CHANGES

Because peripheral remapping can be changed during

run time, some restrictions on peripheral remapping are

needed to prevent accidental configuration changes.

PIC24FJ16MC101/102 devices include three features to

prevent alterations to the peripheral map:

• Control register lock sequence

• Continuous state monitoring

• Configuration bit pin select lock

10.4.3.1 Control Register Lock Sequence

Under normal operation, writes to the RPINRx and

RPORx registers are not allowed. Attempted writes

appear to execute normally, but the contents of the

registers remain unchanged. To change these

registers, they must be unlocked in hardware. The

(OSCCON<6>). Setting IOLOCK prevents writes to the

control registers; clearing IOLOCK allows writes.

To set or clear IOLOCK, a specific command sequence

must be executed:

1. Write 0x46 to OSCCON<7 :0>.

2. Write 0x57 to OSCCON<7 :0>.

3. Clear (or set) IOLOCK as a single operation.

Unlike the similar seq uence with the oscillator’s LOCK

bit, IOLOCK remains in one state until changed. This

allows all of the peripheral pin selects to be configure d

with a single unlock sequence followed by an update to

all control registers, then locked with a second lock

sequence.

10.4.3.2 Continuous State Monitoring

In addition to being protected from direct writes, the

contents of the RPINRx and RPORx registers are

constantly monitored in hardware by shadow registers.

If an unexpected change in any of the registers occurs

(such as cell disturbances caused by ESD or other

external events), a configuration mismatch Reset will

be triggered.

10.4.3.3 Configuration Bit Pin Select Lock

As an additional level of safety, the device can be

configured to prevent more than one write session to

the RPINRx and RPORx registers. The IOL1WAY

(FOSC<IOL1WAY>) configuration bit blocks the

IOLOCK bit from being cleared after it has been set

once. If IOLOCK remains set, the register unlock

procedure will not execute, and the peripheral pin

select control registers cannot be written to. The only

way to clear the bit and re-enable peripheral remapping

is to perform a device Reset.

In the default (unprogrammed) state, IOL1WAY is set,

restricting users to one write session. Programming

IOL1WAY allows user applications unlimited access

(with the proper use of the unlock sequence) to the

peripheral pin select registers.

10.5 Peripheral Pin Select Registers

The PIC24FJ16MC101/102 family of devices

implement 21 registers for remappable peripheral

configuration:

• Input Remappable Peripheral Registers (13)

• Output Remappable Peripheral Registers (8)

Function RPnR<4:0> Output Name

NULL 00000 RPn tied to default port pin

C1OUT 00001 RPn ti e d to Co mparator 1 Output

C2OUT 00010 RPn ti e d to Co mparator 2 Output

U1TX 00011 RPn tied to UART1 T ransmit

U1RTS 00100 RPn tied to UART1 Ready To Send

SS1 01001 RPn tied to SPI1 Slave Select Output

OC1 10010 RPn tied to Output Compare 1

OC2 10011 RPn tied to Output Compare 2

CTPLS 11101 RPn tied to CTMU Pulse Output

C3OUT 11110 RPn ti e d to Co mparator 3 Output

Note: MPLAB® C30 provides built-in C

language functions for unlocking the

OSCCON register:

__builtin_write_OSCCONL(value)

__builtin_write_OSCCONH(value)

See MPLAB IDE Help for more

information.

Note: Input and Output Register values can only

be changed if OSCCON<IOLOCK> = 0.

See Section 10.4.3.1 “Control Register

Lock Sequence” for a specific command

sequence.

PIC24FJ16MC101/102

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — —INT1R<4:0>

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 Unimplemented: Read as ‘0’

bit 12-8 INT1R<4:0>: Assign External Interrupt 1 (INTR1) to the corresponding RPn pin

11111 = Input tied VSS

01111 = Input tied to RP15

00001 = Input tied to RP1

00000 = Input tied to RP0

bit 7-0 Unimplemented: Read as ‘0’

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — —INT2R<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-5 Unimplemented: Read as ‘0’

bit 4-0 INT2R<4:0>: Assign External Interrupt 2 (INTR2) to the corresponding RPn pin

11111 = Input tied VSS

01111 = Input tied to RP15

00001 = Input tied to RP1

00000 = Input tied to RP0

PIC24FJ16MC101/102

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — —T3CKR<4:0>

bit 15 bit 8

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — —T2CKR<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 Unimplemented: Read as ‘0’

bit 12-8 T3CKR<4:0>: Assign Timer3 External Clock (T3CK) to the corresponding RPn pin

11111 = Input tied VSS

01111 = Input tied to RP15

00001 = Input tied to RP1

00000 = Input tied to RP0

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 T2CKR<4:0>: Assign Timer2 External Clock (T2CK) to the corresponding RPn pin

11111 = Input tied VSS

01111 = Input tied to RP15

00001 = Input tied to RP1

00000 = Input tied to RP0

PIC24FJ16MC101/102

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — IC2R<4:0>

bit 15 bit 8

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — IC1R<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 Unimplemented: Read as ‘0’

bit 12-8 IC2R<4:0>: Assign Input Capture 2 (IC2) to the corresponding RPn pin

11111 = Input tied VSS

01111 = Input tied to RP15

00001 = Input tied to RP1

00000 = Input tied to RP0

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 IC1R<4:0>: Assign Input Capture 1 (IC1) to the corresponding RPn pin

11111 = Input tied VSS

01111 = Input tied to RP15

00001 = Input tied to RP1

00000 = Input tied to RP0

PIC24FJ16MC101/102

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — IC3R<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-5 Unimplemented: Read as ‘0’

bit 4-0 IC3R<4:0>: Assign Input Capture 3 (IC3) to the corresponding pin RPn pin

11111 = Input tied VSS

01111 = Input tied to RP15

00001 = Input tied to RP1

00000 = Input tied to RP0

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — —OCFAR<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-5 Unimplemented: Read as ‘0’

bit 4-0 OCFAR<4:0>: Assign Output Capture A (OCFA) to the corresponding RPn pin

11111 = Input tied VSS

01111 = Input tied to RP15

00001 = Input tied to RP1

00000 = Input tied to RP0

PIC24FJ16MC101/102

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — U1CTSR<4:0>

bit 15 bit 8

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — —U1RXR<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 Unimplemented: Read as ‘0’

bit 12-8 U1CTSR<4:0>: Assign UART1 Clear to Send (U1CTS) to the corresponding RPn pin

11111 = Input tied VSS

01111 = Input tied to RP15

00001 = Input tied to RP1

00000 = Input tied to RP0

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 U1RXR<4:0>: Assign UART1 Receive (U1RX) to the corresponding RPn pin

11111 = Input tied VSS

01111 = Input tied to RP15

00001 = Input tied to RP1

00000 = Input tied to RP0

PIC24FJ16MC101/102

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — SS1R<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-5 Unimplemented: Read as ‘0’

bit 4-0 SS1R<4:0>: Assign SPI1 Slave Select Input (SS1IN) to the corresponding RPn pin

11111 = Input tied VSS

01111 = Input tied to RP15

00001 = Input tied to RP1

00000 = Input tied to RP0

PIC24FJ16MC101/102

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — RP1R<4:0>

bit 15 bit 8

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — RP0R<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 Unimplemented: Read as ‘0’

bit 12-8 RP1R<4:0>: Peripheral Output Function is Assigned to RP1 Output Pin bits (see Table 10-2 for

peripheral function numbers)

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 RP0R<4:0>: Peripheral Output Function is Assigned to RP0 Output Pin bits (see Table 10-2 for

peripheral function numbers)

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — RP3R<4:0>

bit 15 bit 8

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — RP2R<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 Unimplemented: Read as ‘0’

bit 12-8 RP3R<4:0>: Peripheral Output Function is Assigned to RP3 Output Pin bits (see Table 10-2 for

peripheral function numbers)

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 RP2R<4:0>: Peripheral Output Function is Assigned to RP2 Output Pin bits (see Table 10-2 for

peripheral function numbers)

PIC24FJ16MC101/102

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — —RP5R<4:0>

bit 15 bit 8

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — —RP4R<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 Unimplemented: Read as ‘0’

bit 12-8 RP5R<4:0>: Peripheral Output Function is Assigned to RP5 Output Pin bits (see Table 10-2 for

peripheral function numbers)

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 RP4R<4:0>: Peripheral Output Function is Assigned to RP4 Output Pin bits (see Table 10-2 for

peripheral function numbers)

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — —RP7R<4:0>

bit 15 bit 8

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — —RP6R<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 Unimplemented: Read as ‘0’

bit 12-8 RP7R<4:0>: Peripheral Output Function is Assigned to RP7 Output Pin bits (see Table 10-2 for

peripheral function numbers)

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 RP6R<4:0>: Peripheral Output Function is Assigned to RP6 Output Pin bits (see Table 10-2 for

peripheral function numbers)

PIC24FJ16MC101/102

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — RP9R<4:0>

bit 15 bit 8

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — RP8R<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 Unimplemented: Read as ‘0’

bit 12-8 RP9R<4:0>: Peripheral Output Function is Assigned to RP9 Output Pin bits (see Table 10-2 for

peripheral function numbers)

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 RP8R<4:0>: Peripheral Output Function is Assigned to RP8 Output Pin bits (see Table 10-2 for

peripheral function numbers)

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — —RP11R<4:0>

bit 15 bit 8

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — RP10R<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 Unimplemented: Read as ‘0’

bit 12-8 RP11R<4:0>: Periph eral Output Function is Assigned to RP11 Output Pin bits (see Table 10-2 for

peripheral function numbers)

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 RP10R<4:0>: Peripheral Output Function is Assigned to RP10 Output Pin bits (see Table 10-2 for

peripheral function numbers)

PIC24FJ16MC101/102

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — RP13R<4:0>

bit 15 bit 8

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — RP12R<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 Unimplemented: Read as ‘0’

bit 12-8 RP13R<4:0>: Peripheral Output Function is Assigned to RP13 Output Pin bits (see Table 10-2 for

peripheral function numbers)

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 RP12R<4:0>: Peripheral Output Function is Assigned to RP12 Output Pin bits (see Table 10-2 for

peripheral function numbers)

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — RP15R<4:0>

bit 15 bit 8

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — RP14R<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 Unimplemented: Read as ‘0’

bit 12-8 RP15R<4:0>: Peripheral Output Function is Assigned to RP15 Output Pin bits (see Table 10-2 for

peripheral function numbers)

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 RP14R<4:0>: Peripheral Output Function is Assigned to RP14 Output Pin bits (see Table 10-2 for

peripheral function numbers)

PIC24FJ16MC101/102

NOTES:

PIC24FJ16MC101/102

11.0 TIMER1

The Timer1 module is a 16-bit timer, which can serve

as the time counter for the real-time clock, or operate

as a free-running interval timer/counter. Timer1 can

operate in three modes:

• 16-bit Timer

• 16-bit Synchronous Counter

• 16-bit Asynchronous Counter

Timer1 also supports these features:

• Timer gate operation

• Selectable prescaler settings

• Timer operation during CPU Idle and Sleep

modes

• Interrupt on 16-bit Period register match or falling

edge of external gate signal

Figure 11-1 presents a block diagram of the 16-bit timer

module.

To configure Timer1 for operation:

1. Load the timer value into the TMR1 register.

2. Load the timer period value into the PR1

3. Select the timer prescaler ratio using the

TCKPS<1:0> bits in the T1CON register.

4. Set the Clock and Gating modes usi ng the TCS

and TGATE bits in the T1CON register.

5. Set or clear the TSYNC bit in T1CON to select

synchronous or asynchronous operation.

6. If interrupts are required, set the interrupt enable

bit, T1IE. Use the priority bits, T1IP<2:0>, to set

the interrupt priority.

7. Set the TON bit (= 1) in the T1CON register.

FIGURE 11-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM

Note 1: This data sheet summarizes the features

of the PIC24FJ16MC101/102 family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 14. “Timers”

(DS39704) in the “PIC24F Family

Reference Manual”, which is available

from the Microchip web site

(www.microchip.com).

2: It is important to note that the

specifications in Section 26.0 “Electri-

cal Characteristics” of this data sheet,

supercede any specifications that may be

provided in PIC24F Family Reference

Manual sections.

3: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

TON

SOSCI

SOSCO/

PR1

Set T1IF

Equal Comparator

TMR1

Reset

SOSCEN

TSYNC

TCKPS<1:0>

Prescaler

1, 8, 64, 256

TGATE

TCY

T1CK

TCS

TGATE

Sync

Gate

Sync

PIC24FJ16MC101/102

R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

TON(1) —TSIDL— — — — —

bit 15 bit 8

U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0

— TGATE TCKPS<1:0> —TSYNCTCS

(1) —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 TON: Timer1 On bit(1)

1 = Starts 16-bit Timer1

0 = Stops 16-bit Ti mer1

bit 14 Unimplemented: Read as ‘0’

bit 13 TSIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode

0 = Continue module operati on in Idle mode

bit 12-7 Unimplemented: Read as ‘0’

bit 6 TGATE: Timer1 Gated Time Accumulation Enable bit

When TCS = 1:

This bit is ignored.

When TCS = 0:

1 = Gated time accumulation enabled

0 = Gated time accumulation disable d

bit 5-4 TCKPS<1:0> Timer1 Input Clock Prescale Select bits

11 = 1:256

10 = 1:64

01 = 1:8

00 = 1:1

bit 3 Unimplemented: Read as ‘0’

bit 2 TSYNC: Timer1 External Clock Input Synchroni zation Select bit

When TCS = 1:

1 = Synchronize external clock input

0 = Do not synchronize external clock input

When TCS = 0:

This bit is ignored.

bit 1 TCS: Ti mer1 Clock Source Select bit(1)

1 = External clock from pin T1CK (on the rising edge )

0 = Internal clock (FCY)

bit 0 Unimplemented: Read as ‘0’

Note 1: When TCS = 1 and TON = 1, writes to the TMR1 register are inhibited from the CPU.

PIC24FJ16MC101/102

12.0 TIMER2/3 FEATURE

The Timer2/3 feature has three 2-bit timers that can

also be configured as two independent 16-bit timers

with selectable operating modes.

As a 32-bit timer, the Timer2/3 feature permits

operation in three modes:

• Two Independent 16-bit timers (e.g., Timer2 and

Timer3) with all 16-bit operating modes (except

Asynchronous Counter mode)

• Single 32-bit timer (Timer2/3)

• Single 32-bit synchronous counter (Timer2/3)

The Timer2/3 feature also supports:

• Timer gate operation

• Selectable prescaler settings

• Timer operation during Idle and Sleep modes

• Interrupt on a 32-bit period register match

• T ime base for Input Capture and Output Compare

modules (Timer2 and Timer3 only)

• ADC1 event trigger (Timer2/3 only)

Individually , all eight of the 16-bit timers can function as

synchronous timers or counters. They also offer the

features listed above, except for the event tri gger. The

operating modes and enabled features are determined

by setting the appropriate bit(s) in the T2CON, T3CON

registers. T2CON registers are shown in generic form

in Register 12-1. T3CON registers are shown in

For 32-bit timer/counter operation, Timer2 is the least

significant word, and Timer3 is the most significant

word (msw) of the 32-bit timers.

12.1 32-bit Operation

To configure the Timer2/3 feature timers for 32-bit

operation:

1. Set the T32 cont ro l bi t .

2. Select the prescaler ratio for Timer2 using the

TCKPS<1:0> bits.

3. Set the Clock and Gating modes using the

corresponding TCS and TGATE bits.

4. Load the timer period value. PR3 contains the

msw of the value, while PR2 contains the least

significant word (lsw).

5. If interrupts are required, set the interrupt enable

bit, T3IE. Use the priority bits, T3IP<2:0>, to set

the interrupt priority. While Timer2 controls the

timer, the interrupt appears as a Timer3

interrupt.

6. Set the corresponding TON bit.

The timer value at any point is stored in the register

pair, TMR3:TMR2, which always contains the msw of

the count, while TMR2 contains the lsw.

12.2 16-bit Operation

To configure any of the timers for individual 16-bit

operation:

1. Clear the T32 bit correspondin g to that timer.

2. Select the timer prescaler ratio using the

TCKPS<1:0> bits.

3. Set the Clock and Gating modes usi ng the TCS

and TGATE bits.

4. Load the timer period value into the PRx

5. If interrupts are required, set the interrupt enable

bit, TxIE. Use the priority bits, TxIP<2:0>, to set

the interrupt priority.

6. Set the TON bit.

Note 1: This data sheet summarizes the features

of the PIC24FJ16MC101/102 family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 14. “Timers”

(DS39704) in the “PIC24F Family

Reference Manual”, which is available

from the Microchip web site

(www.microchip.com).

2: It is important to note that the

specifications in Section 26.0 “Electri-

cal Characteristics” of this data sheet,

supercede any specifications that may be

provided in PIC24F Family Reference

Manual sections.

3: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Note: For 32-bit operation, T3CON control bits

are ignored. Only T2CON control bits are

used for setup and control. Timer2 clock

and gate inputs are used for the 32-bit

timer modules, but an interrupt is

generated with the Timer3 interrupt flags.

PIC24FJ16MC101/102

FIGURE 12-1: TIMER2/3 (32-BIT) BLOCK DIAGRAM(1)

Set T3IF

Equal Comparator

PR3 PR2

Reset

LSbMSb

Note 1: The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective

to the T2CON register.

2: The ADC event trigger is available only on Timer2/3.

Data Bus<15:0>

TMR3HLD

Read TMR2

Write TMR2 16

TGATE

TON TCKPS<1:0>

TCY

TCS

TGATE

T2CK

ADC Event Trigger(2)

Gate

Sync Prescaler

1, 8, 64, 256

Sync

TMR3 TMR2

To CTMU Filter

PIC24FJ16MC101/102

FIGURE 12-2: TIMER2 (16-BIT) BLOCK DIAGRAM

FIGURE 12-3: TIMER3 (16-BIT) BLOCK DIAGRAM

TON TCKPS<1:0>

Prescaler

1, 8, 64, 256

TCY TCS

TGATE

T2CK

PR2

Set T2IF

Equal Comparator

TMR2

Reset

TGATE

Gate

Sync

To CTMU Filter

Prescaler

(/n)

Gate

Sync

TGATE

TCS

TMRx

Comparator

PRx

FCY

TGATE

Falling Edge

Detect Set TxIF flag

Sync

TCKPS<1:0>

Equal

Reset

TxCK ADC SOC Trigger

Prescaler

(/n)

TCKPS<1:0>

To CTMU Filter

PIC24FJ16MC101/102

R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

TON —TSIDL— — — — —

bit 15 bit 8

U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0

— TGATE TCKPS<1:0> T32 —TCS—

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 TON: Timer2 On bit

When T32 = 1:

1 = Starts 32-bit Timer2/3

0 = Stops 32-bit Ti mer2/3

When T32 = 0:

1 = Starts 16-bit Timer2

0 = Stops 16-bit Ti mer2

bit 14 Unimplemented: Read as ‘0’

bit 13 TSIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode

0 = Continue module operati on in Idle mode

bit 12-7 Unimplemented: Read as ‘0’

bit 6 TGATE: Timer2 Gated Time Accumulation Enable bit

When TCS = 1:

This bit is ignored.

When TCS = 0:

1 = Gated time accumulation enabled

0 = Gated time accumulation disable d

bit 5-4 TCKPS<1:0>: Timer2 Input Clock Prescale Select bi ts

11 = 1:256

10 = 1:64

01 = 1:8

00 = 1:1

bit 3 T32: 32-bit Timer Mode Select bit

1 = Timer2 and Ti mer3 form a single 32-bit timer

0 = Timer2 and Timer3 act as two 16-bit timers

bit 2 Unimplemented: Read as ‘0’

bit 1 TCS: Ti mer2 Clock Source Select bit

1 = External clock from pin T2CK (on the rising edge )

0 = Internal clock (FCY)

bit 0 Unimplemented: Read as ‘0’

PIC24FJ16MC101/102

R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

TON(2) —TSIDL

(1) — — — — —

bit 15 bit 8

U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0

— TGATE

(2) TCKPS<1:0>(2) ——TCS

(2) —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 TON: Timer3 On bit(2)

1 = Starts 16-bit Timer3

0 = Stops 16-bit Ti mer3

bit 14 Unimplemented: Read as ‘0’

bit 13 TSIDL: Stop in Idle Mode bit(1)

1 = Discontinue timer operation when device enters Idle mode

0 = Continue timer operation in Idle mode

bit 12-7 Unimplemented: Read as ‘0’

bit 6 TGATE: Timer3 Gated Time Accumulation Enable bit(2)

When TCS = 1:

This bit is ignored.

When TCS = 0:

1 = Gated time accumulation enabled

0 = Gated time accumulation disabled

bit 5-4 TCKPS<1:0>: Timer3 Input Clock Prescale Select bits(2)

11 = 1:256 prescale value

10 = 1:64 prescale value

01 = 1:8 prescale value

00 = 1:1 prescale value

bit 3-2 Unimplemented: Read as ‘0’

bit 1 TCS: Ti mer3 Clock Source Select bit(2)

1 = External clock from T3CK pin

0 = Internal clock (FOSC/2)

bit 0 Unimplemented: Read as ‘0’

Note 1: When 32-bit timer operation is enabled (T32 = 1) in the Ti mer Control register (T2CON<3>), the TSIDL bit

must be cleared to operate the 32-bit timer in Idle mode.

2: When the 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (T2CON<3>), these bits

have no effect.

PIC24FJ16MC101/102

NOTES:

PIC24FJ16MC101/102

13.0 INPUT CAPTURE

The Input Capture module is useful in applications

requiring frequency (period) and pulse measurement.

The PIC24FJ16MC101/102 devices support up to eight

input capture channels.

The Input Capture module ca ptures the 1 6-bit val ue of

the selected Time Base register when an event occurs

at the ICx pin. The events that cause a capture event

are listed below in three categories:

1. Simple Capture Event modes:

• Capture timer value on every falling edge of

input at ICx pin

• Capture timer value on every rising edge of

input at ICx pin

2. Capture timer value on every edge (rising and

falling)

3. Prescaler Capture Event modes:

• Capture timer value on every 4th rising edge

of input at ICx pin

• Capture timer value on every 16th rising

edge of input at ICx pin

Each Input Capture channel can select one of two

16-bit timers (Timer2 or Timer3) for the time base.

The selected timer can use either an internal or

external clock.

Other operational features include:

• Device wake-up from capture pin during CPU

Sleep and Idle modes

• Interrupt on Input Capture event

• 4-word FIFO buffer for capture values:

- Interrupt optionally generated after 1, 2, 3, or

4 buffer locations are filled

• Use of Input Capture to provide additional

sources of external interru pts

FIGURE 13-1: INPUT CAPTURE BLOCK DIAGRAM

Note 1: This data sheet summarizes the features

of the PIC24FJ16MC101/102 family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 15. “Input

Capture” (DS39701) in the “PIC24F

Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com).

2: It is important to note that the

specifications in Section 26.0 “Electri-

cal Characteristics” of this data sheet,

supercede any specifications that may be

provided in PIC24F Family Reference

Manual sections.

3: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

ICxBUF

ICx Pin ICM<2:0> (ICxCON<2 :0>)

Mode Select

Set Flag ICxIF

(in IFSn Register)

TMR2 TMR3

Edge Detection Logic

16 16

FIFO

R/W

Logic

ICxI<1:0>

ICOV, ICBNE (ICxCON<4:3>)

ICxCON Interrupt

Logic

System Bus

From 16-bit Timers

ICTMR

(ICxCON<7>)

FIFO

Prescaler

Counter

(1, 4, 16) and

Clock Synchronizer

Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.

PIC24FJ16MC101/102

13.1 Input Capture Registers

U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

——ICSIDL— — — — —

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R-0, HC R-0, HC R/W-0 R/W-0 R/W-0

ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13 ICSIDL: Input Capture Module Stop in Idle Control bit

1 = Input capture module will halt in CPU Idle mode

0 = Input capture module will continue to ope rate in CPU Idle mode

bit 12-8 Unimplemented: Read as ‘0’

bit 7 ICTMR: Input Capture Timer Select bits

1 = TMR2 contents are captured on capture event

0 = TMR3 contents are captured on capture event

bit 6-5 ICI<1:0>: Select Number of Captures per Interrupt bits

11 = Interrupt on every fourth capture event

10 = Interrupt on every third capture event

01 = Interrupt on every second capture event

00 = Interrupt on every capture event

bit 4 ICOV: Input Capture Overflow Status Flag bit (read-only)

1 = Input capture overflow occurred

0 = No input capture overflow occurred

bit 3 ICBNE: Input Capture Buffer Empty Status bit (read-only)

1 = Input capture buffer is not empty, at least one more capture value can be read

0 = Input capture buffer is empty

bit 2-0 ICM<2:0>: Input Capture Mode Select bits

111 = Input capture functions as interrupt pin on ly when device is in Sleep or Idle mode

(Rising edge detect only, all other control bits are not applicable.)

110 = Unused (module disabled)

101 = Capture mode, every 16th rising edge

100 = Capture mode, every 4th rising edge

011 = Capture mode, every rising edge

010 = Capture mode, every falling edge

001 = Capture mode, every edge (rising and falling)

(ICI<1:0> bits do not control interrupt generation for this mode.)

000 = Input capture module turned off

PIC24FJ16MC101/102

14.0 OUTPUT COMPARE T he Output Compare module can select either Timer2

or Timer3 for its time base. The module compares the

value of the timer with the value of one or two compare

registers depending on the operating mode selected.

The state of the output pin changes when the timer

value matches the compare register value. The Output

Compare module generates either a single output

pulse or a sequence of output pulses, by cha ngin g the

state of the output pin on the compare match events.

The Output Compare module can also generate

interrupts on compare match events.

The Output Compare module has multiple operating

modes:

• Active-Low One-Shot mode

• Active-Hi g h On e-Shot mode

• Toggle mode

• Delayed One-Shot mode

• Continuous Pulse mode

• PWM mode without fault protection

• PWM mode with fault protection

FIGURE 14-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM

Note 1: This data sheet summarizes the features

of the PIC24FJ16MC101/102 family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 16. “Output

Compare” (DS39706) of the “PIC24F

Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com).

2: It is important to note that the

specifications in Section 26.0 “Electri-

cal Characteristics” of this data sheet,

supercede any specifications that may be

provided in PIC24F Family Reference

Manual sections.

3: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

OCxR

Comparator

Output

Logic

OCM<2:0>

OCx

Set Flag bit

OCxIF

OCxRS

Mode Select

OCTSEL 01

OCFA

TMR2 TMR2

TMR3 TMR3

Rollover Rollover

Output

Logic

Output

Enable Enable

PIC24FJ16MC101/102

14.1 Output Compare Modes

Configure the Output Compare modes by setting the

appropriate Output Compare Mode bits (OCM<2:0>) in

the Output Compare Control register (OCxCON<2:0>).

Table 14-1 li sts the different bit settings for the Output

Compare modes. Figure 14-2 illustrates the output

compare operation for various modes. The user

application must disable the associated timer when

writing to the output compare control registers to avoid

malfunctions.

TABLE 14-1: OUTPUT COMP ARE MODES

FIGURE 14-2: OUTPUT COMPARE OPERATION

Note: See Section 16. “Output Compare”

(DS39706) in the “PIC24F Family Refer-

ence Manual” (DS70209) for OCxR and

OCxRS register restrictions.

OCM<2:0> Mode OCx Pin Initial State OCx Interrupt Generation

000 Module Disabled Controlled by GPIO register —

001 Active-Low One-Shot 0OCx Rising edge

010 Active-High One-Shot 1OCx Falling edge

011 Toggle Mode Current output is maintained OCx Rising and Falling edge

100 Delayed One-Shot 0OCx Falling edge

101 Continuous Pulse mode 0OCx Falling edge

110 PWM mode without fault

protection 0, if OCxR is zero

1, if OCxR is non-zero No interrupt

111 PWM mode with fault protection 0, if OCxR is zero

1, if OCxR is non-zero OCFA Falling edge for OC1 to OC4

OCxRS

TMRy OCxR

Timer is reset on

period match

Continuous Pulse Mode

(OCM = 101)

PWM Mode

(OCM = 110 or 111)

Active-Low One-Shot

(OCM = 001)

Active-High One-Shot

(OCM = 010)

Toggle Mode

(OCM = 011)

Delayed One-Shot

(OCM = 100)

Output Compare

Mode enabled

PIC24FJ16MC101/102

U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

——OCSIDL — — — — —

bit 15 bit 8

U-0 U-0 U-0 R-0 HC R/W-0 R/W-0 R/W-0 R/W-0

— — — OCFLT OCTSEL OCM<2:0>

bit 7 bit 0

Legend: HC = Cleared in Hardware HS = Set in Hardware

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13 OCSIDL: Stop Output Compare in Idle Mode Contro l bit

1 = Output Compare x will halt in CPU Idle mode

0 = Output Compare x will continue to operate in CPU Idle mode

bit 12-5 Unimplemented: Read as ‘0’

bit 4 OCFLT: PWM Fault Condition Status bit

1 = PWM Fault condition has occurred (cleared in hardware only)

0 = No PWM Fault condition has occurred

(This bit is only used when OCM<2:0> = 111.)

bit 3 OCTSEL: Output Compare Timer Select bit

1 = Ti mer3 is the clock source for Compare x

0 = Ti mer2 is the clock source for Compare x

bit 2-0 OCM<2:0>: Output Compare Mode Select bits

111 = PWM mode on OCx, Fault pin enabled

110 = PWM mode on OCx, Fault pin disabled

101 = Initialize OCx pin low, generate continuous output pulses on OCx pin

100 = Initialize OCx pin low, generate sin gle output pulse on OCx pin

011 = Compare event toggles OCx pin

010 = Initialize OCx pin high, compare event forces OCx pin low

001 = Initialize OCx pin low, compare event forces OCx pin high

000 = Output compare channel is disabled

PIC24FJ16MC101/102

NOTES:

PIC24FJ16MC101/102

15.0 MOTOR CONTROL PWM

MODULE

The PIC24FJ16MC101/102 devices ha ve a 6-channel

Pulse-Width Modulation (PWM) module.

The PWM module has the following features:

• Up to 16-bit resolution

• On-the-fly PWM frequency changes

• Edge-Aligned and Center-Aligned Output modes

• Single Pulse Generation mode

• Interrupt support for asymmetrical updates in

Center-Aligned mode

• Output override control for Electrically

Commutative Motor (ECM) operation or BLDC

• Special Event comparator for sche d ul i n g ot he r

peripheral events

• Fault pins to optionally drive each of the PWM

output pins to a defined state

• Duty cycle updates configurable to be immediate

or synchronized to the PWM time base

15.1 PWM1: 6-Channel PWM Module

This module simplifies the task of generating multiple

synchronized PWM outputs. The following power and

motion control applications are supported by the PWM

module:

• 3-Phase AC Induction Motor

• Switched Reluctance (SR) Motor

• Brushless DC (BLDC) Motor

• Uninterruptible Power Supply (UPS)

This module contains three duty cycle generators,

numbered 1 through 3. The module has six PWM

output pins, numbered PWM1H1/PWM1L1 through

PWM1H3/PWM1L3. The six I/O pins are grouped into

high/low numbered pairs, denoted by the suffix H or L,

respectively. For complementary loads, the low PWM

pins are always th e complement of the corresponding

high I/O pin.

Note 1: This data sheet summarizes the features

of the PIC24FJ16MC101/102 family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 47. “Motor Con-

trol PWM” (DS39735), in the “PIC24F

Family Reference Manual”, which is

available on the Microchip web site

(www.microchip.com).

2: It is important to note that the

specifications in Section 26.0 “Electri-

cal Characteristics” of this data sheet,

supercede any specifications that may be

provided in PIC24F Family Reference

Manual sections.

3: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

PIC24FJ16MC101/102

FIGURE 15-1: 6-CHANNEL PWM MODULE BLOCK DIAGRAM (PWM1)

P1DC3

P1DC3 Buffer

PWM1CON1

PWM1CON2

P1TPER

Comparator

Channel 3 Dead-Time

Generator and

P1TCON

P1SECMP

Comparator Special Event Trigge r

P1OVDCON

PWM Enable and Mode SFRs

PWM Manual

Control SFR

Channel 2 Dead-Time

Generator and

Channel 1 Dead-Time

Generator and

PWM

Generator 2(1)

PWM

Generator 1(1)

PWM Generator 3

SEVTDIR

PTDIR

P1DTCON1 Dead-Time Control SFRs

PWM1L1

PWM1H1

PWM1L2

PWM1H2

Note 1: The details of PWM Generator 1 and 2 are not shown for clarity.

2: On PIC24FJ16MC101 (20-pin) devices, the FLTA1 pin is supported, but requires an external pull-down resistor for

correct functionality.

3: On PIC24FJ16MC102 (28-pin) devices, the FLTA1 and FLTB1 pins are supported and do not require an external

pull-down resistor.

16-bit Data Bus

PWM1L3

PWM1H3

P1DTCON2

P1FLTACON Fault A Pin Control SFRs

PWM Time Base

Output

Driver

Block

FLTA1(2,3)

Override Logic

Special Event

Postscaler

P1TPER Buf fe r

P1TMR

P1FLTBCON Fault B Pin Control SFRs

FLTB1(3)

PIC24FJ16MC101/102

15.2 PWM Faults

The Motor Control PWM module incorporates up to two

fault inputs, FLTA1 and FLTB1. These fault inputs are

implemented with Class B safety features. These fe a-

tures ensure that the PWM outputs enter a safe state

when either of the fault inputs is asserted.

The FLTA and FLTB pins, when enabled and having

ownership of a pin, also enable a soft internal pull-down

resistor . The soft pull-down provides a safety feature by

automatically asserting the fault should a break occur

in the fault signal connection.

The implementation of internal pull-down resistors is

dependent on the device variant. Table 15-1 describes

which devices and pins implement the internal pull-

down resistors.

TABLE 15-1: INTERNAL PULL-DOWN

RESISTORS ON PWM FAULT

PINS

On devices without internal pull-downs on the Fault pin,

it is recommended to connect an external pull-down

resistor for Class B safety features.

15.2.1 PWM FAULTS AT RESET

During any reset event, the PWM module maintains

ownership of both PWM Fault pins. At reset, both faults

are enabled in latched mode to gua ra ntee the fai l-safe

power-up of the application. The application software

must clear both the PWM faults before enabling the

Motor Control PWM module.

The Fault con dition must be cleared by the external cir-

cuitry driving the fault input pin high and clearing the

fault inte rrupt flag. After the fault pin condi tion has been

cleared, the PWM module restores the PWM output

signals on the next PWM perio d or half-period bound-

ary.

Refer to Section 47. “Motor Control PWM”

(DS39735), in the “PIC24F F amily Reference Manual”

for more information on the PWM faults.

15.3 Write-protected Registers

On PIC24FJ16MC101/102 devices, write protection is

implemented for the PWMxCON1, PxFLTACON and

PxFLTBCON registers. The write protection feature

prevents any inadvertent writes to these registers. The

write protection feature can be controlled by the

PWMLOCK configuration bit in the FOSCSEL configu-

ration register. T he default state of the write protection

feature is enabled (PWMLOCK = 1). The write protec-

tion feature can be disabled by configuring PWMLOCK

(FOSCSEL<6>) = 0.

The user application can gain access to these locked

registers either by confi guring th e PWMLOCK (FOSC-

SEL<6>) = 0, or by performing the unlock sequence. To

perform the unlock sequence, the user application

must write two consecutive values of (0xABCD and

0x4321) to the PWMxKEY register to perform the

unlock operation. The write access to the PWMxCON1,

PxFLTACON or PxFLTBCON registers must be the

next SFR access following the unlock process. There

can be no other SFR accesses during the unlock pro-

cess and subsequent write access.

To write to all registers, the PWMxCON1, PxFLTACON

and PxFLTBCON registers require three unlock

operations.

The correct unlocking sequence is described in

Example 15-1 and Example 15-2.

Device Fault Pin Internal Pull-

down

Implemented?

PIC24FJ16MC101 FLTA1 No

PIC24FJ16MC102 FLTA1 Yes

FLTB1 Yes

Note: The number of PWM faults mapped to the

device pins depend on the specific

variant. Regardless of the variant, both

faults will be enabled during any reset

event. The application must clear both

FLTA1 and FLTB1 before enabling the

Motor Control PWM module. Refer to the

specific device pin diagrams to see which

fault pins are mapped to the device pins.

PIC24FJ16MC101/102

EXAMPLE 15-1: ASSEMBLY CODE EXAMPLE FOR WRITE-PROTECTED REGISTER UNLOCK

AND FAULT CLEARING SEQUENCE

EXAMPLE 15-2: C CODE EXAMPLE FOR WRITE-PROTECTED REGISTER UNLOCK AND FAULT

CLEARING SEQUENCE

; FLTA1 pin must be pulled high externally in order to clear and disable the fault

; Writing to P1FLTBCON register requires unlock sequence

mov #0xabcd,w10 ; Load first unlock key to w10 register

mov #0x4321,w11 ; Load second unlock key to w11 register

mov #0x0000,w0 ; Load desired value of P1FLTACON register in w0

mov w10, PWM1KEY ; Write first unlock key to PWM1KEY register

mov w11, PWM1KEY ; Write second unlock key to PWM1KEY register

mov w0,P1FLTACON ; Write desired value to P1FLTACON register

; FLTB1 pin must be pulled high externally in order to clear and disable the fault

; Writing to P1FLTBCON register requires unlock sequence

mov #0xabcd,w10 ; Load first unlock key to w10 register

mov #0x4321,w11 ; Load second unlock key to w11 register

mov #0x0000,w0 ; Load desired value of P1FLTBCON register in w0

mov w10, PWM1KEY ; Write first unlock key to PWM1KEY register

mov w11, PWM1KEY ; Write second unlock key to PWM1KEY register

mov w0,P1FLTBCON ; Write desired value to P1FLTBCON register

; Enable all PWMs using PWM1CON1 register

; Writing to PWM1CON1 register requires unlock sequence

mov #0xabcd,w10 ; Load first unlock key to w10 register

mov #0x4321,w11 ; Load second unlock key to w11 register

mov #0x0077,w0 ; Load desired value of PWM1CON1 register in w0

mov w10, PWM1KEY ; Write first unlock key to PWM1KEY register

mov w11, PWM1KEY ; Write second unlock key to PWM1KEY register

mov w0,PWM1CON1 ; Write desired value to PWM1CON1 register

// FLTA1 pin must be pulled high externally in order to clear and disable the fault

// Writing to P1FLTACON register requires unlock sequence

// Use builtin function to write 0x0000 to P1FLTACON register

__builtin_write_PWMSFR(&P1FLTACON, 0x0000, &PWM1KEY);

// FLTB1 pin must be pulled high externally in order to clear and disable the fault

// Writing to P1FLTBCON register requires unlock sequence

// Use builtin function to write 0x0000 to P1FLTBCON register

__builtin_write_PWMSFR(&P1FLTBCON, 0x0000, &PWM1KEY);

// Enable all PWMs using PWM1CON1 register

// Writing to PWM1CON1 register requires unlock sequence

// Use builtin function to write 0x0077 to PWM1CON1 register

__builtin_write_PWMSFR(&PWM1CON1, 0x0077, &PWM1KEY);

PIC24FJ16MC101/102

R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

PTEN —PTSIDL— — — — —

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PTOPS<3:0> PTCKPS<1:0> PTMOD<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 PTEN: PWM Time Base Timer Enable bit

1 = PWM time base is on

0 = PWM time base is off

bit 14 Unimplemented: Read as ‘0’

bit 13 PTSIDL: PWM Time Base Stop in Idle Mode bit

1 = PWM time base halts in CPU Idle mode

0 = PWM time base runs in CPU Idle mode

bit 12-8 Unimplemented: Read as ‘0’

bit 7-4 PTOPS<3:0>: PWM Time Base Output Postscale Select bits

1111 = 1:16 postscale

•

0001 = 1:2 post scale

0000 = 1:1 post scale

bit 3-2 PTCKPS<1:0>: PWM Time Base Input Clock Prescale Select bits

11 = PWM time base input clock period is 64 TCY (1:64 prescale)

10 = PWM time base input clock period is 16 TCY (1:16 prescale)

01 = PWM time base input clock period is 4 TCY (1:4 prescale)

00 = PWM time base input clock period is TCY (1:1 prescale)

bit 1-0 PTMOD<1:0>: PWM Time Base Mode Select bits

11 = PWM time base operates in a Continuous Up/Down Count mode with interrupts for double

PWM updates

10 = PWM time base operates in a Continuous Up/Down Cou nt mode

01 = PWM time base operates in Single Pulse mode

00 = PWM time base operates in a Free-Running mode

PIC24FJ16MC101/102

R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PTDIR PTMR<14:8>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PTMR<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 PTDIR: PWM Time Base Count Direction Status bit (read-only)

1 = PWM time base is counting down

0 = PWM time base is counting up

bit 14-0 PTMR <14:0>: PWM Time Base Register Count Value bits

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— PTPER<14:8>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PTPER<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-0 PTPER<14:0>: PWM Time Base Period Value bits

PIC24FJ16MC101/102

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SEVTDIR(1) SEVTCMP<14:8>(2)

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SEVTCMP<7:0>(2)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 SEVTDIR: Specia l Event Trig ger Time Base Direction bit(1)

1 = A Special Event Trigger will occur when the PWM time base is counting down

0 = A Special Event Trigger will occur when the PWM time base is counting up

bit 14-0 SEVTCMP<14:0>: Special Event Compare Value bits(2)

Note 1: SEVTDIR is compared with PTDIR (PXTMR<15>) to generate the Special Event Trigger.

2: PxSECMP<14:0> is compared with PXTMR<14:0> to generate the Special Event Trigger.

PIC24FJ16MC101/102

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — PMOD3 PMOD2 PMOD1

bit 15 bit 8

U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0

— PEN3H PEN2H PEN1H — PEN3L PEN2L PEN1L

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-11 Unimplemented: Read as ‘0’

bit 10-8 PMOD3:PMOD1: PWM I/O Pair Mode bits

1 = PWM I/O pin pair is in the Independent PWM Output mode

0 = PWM I/O pin pair is in the Complementary Output mode

bit 7 Unimplemented: Read as ‘0’

bit 6-4 PEN3H:PEN1H: PWMxH I/O Enable bits

1 = PWMxH pin is enabled for PWM output

0 = PWMxH pin disabled, I/O pin becomes general purpose I/O

bit 3 Unimplemented: Read as ‘0’

bit 2-0 PEN3L:PEN1L: PWMxL I/O Enable bits

1 = PWMxL pin is enabled for PWM output

0 = PWMxL pin disabled, I/O pin becomes general purpose I/O

Note 1: The PWMxCON1 register is a write-protected register. Refer to Sec tion 15.3 “Write-pro te cted

Registers” for more informati on on the unlock sequence.

PIC24FJ16MC101/102

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — — SEVOPS<3:0>

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — IUE OSYNC UDIS

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-12 Unimplemented: Read as ‘0’

bit 11-8 SEVOPS<3:0>: PWM Special Event Trigger Output Postscale Select bits

1111 = 1:16 postscale

•

0001 = 1:2 post scale

0000 = 1:1 post scale

bit 7-3 Unimplemented: Read as ‘0’

bit 2 IUE: Immediate Update Enable bit

1 = Updates to the active PxDC registers are immediate

0 = Updates to the active PxDC registers are synchronized to the PWM time base

bit 1 OSYNC: Output Override Synchronization bit

1 = Output overrides via the PxOVDCON register are synchronized to the PWM time base

0 = Output overrides via the PxOVDCON register occur on next TCY boundary

bit 0 UDIS: PWM Update Disable bit

1 = Updates from Duty Cycle and Period Buffer registers are disabled

0 = Updates from Duty Cycle and Period Buffer registers are enabled

PIC24FJ16MC101/102

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DTBPS<1:0> DTB<5:0>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DTAPS<1:0> DTA<5:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 DTBPS<1:0>: Dead-Time Unit B Prescale Select bits

11 = Clock period for Dead-Time Unit B is 8 TCY

10 = Clock period for Dead-Time Unit B is 4 TCY

01 = Clock period for Dead-Time Unit B is 2 TCY

00 = Clock period for Dead-Time Unit B is TCY

bit 13-8 DTB<5:0>: Unsigned 6-bit Dead-T i me Value for Dead-Time Unit B bits

bit 7-6 DTAPS<1:0>: Dead-Time Unit A Prescale Select bits

11 = Clock period for Dead-Time Unit A is 8 TCY

10 = Clock period for Dead-Time Unit A is 4 TCY

01 = Clock period for Dead-Time Unit A is 2 TCY

00 = Clock period for Dead-Time Unit A is TCY

bit 5-0 DTA<5:0>: Unsigned 6-bit Dead-Time Value for Dead-Time Unit A bits

PIC24FJ16MC101/102

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— DTS3A DTS3I DTS2A DTS2I DTS1A DTS1I

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-6 Unimplemented: Read as ‘0’

bit 5 DTS3A: Dead-Time Select for PWM3 Signal Going Active bit

1 = Dead time provided from Unit B

0 = Dead time provided from Unit A

bit 4 DTS3I: Dead-Time Select for PWM3 Signal Going Inactive bit

1 = Dead time provided from Unit B

0 = Dead time provided from Unit A

bit 3 DTS2A: Dead-Time Select for PWM2 Signal Going Active bit

1 = Dead time provided from Unit B

0 = Dead time provided from Unit A

bit 2 DTS2I: Dead-Time Select for PWM2 Signal Going Inactive bit

1 = Dead time provided from Unit B

0 = Dead time provided from Unit A

bit 1 DTS1A: Dead-Time Select for PWM1 Signal Going Active bit

1 = Dead time provided from Unit B

0 = Dead time provided from Unit A

bit 0 DTS1I: Dead-Time Select for PWM1 Signal Going Inactive bit

1 = Dead time provided from Unit B

0 = Dead time provided from Unit A

PIC24FJ16MC101/102

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L

bit 15 bit 8

R/W-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1

FLTAM — — — — FAEN3 FAEN2 FAEN1

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13-8 FAOVxH<3:1>:FAOVxL<3:1>: Fault Input A PWM Override Value bits

1 = The PWM output pin is driven active on an external Fault inpu t event

0 = The PWM output pin is driven inactive on an external Fault input event

bit 7 FLTAM: Fault A Mode bit

1 = The Fault A input pin functions in the Cycle-by-Cycle mode

0 = The Fault A input pin latches all control pins to the programmed states in PxFLTACON<13:8>

bit 6-3 Unimplemented: Read as ‘0’

bit 2 FAEN3: Fault Input A Enable bit

1 = PWMxH3/PWMxL3 pin pair is controlled by Fault Input A

0 = PWMxH3/PWMxL3 pin pair is not controlled by Fault Input A

bit 1 FAEN2: Fault Input A Enable bit

1 = PWMxH2/PWMxL2 pin pair is controlled by Fault Input A

0 = PWMxH2/PWMxL2 pin pair is not controlled by Fault Input A

bit 0 FAEN1: Fault Input A Enable bit

1 = PWMxH1/PWMxL1 pin pair is controlled by Fault Input A

0 = PWMxH1/PWMxL1 pin pair is not controlled by Fault Input A

Note 1: On PIC24FJ16MC101 (20-pin) devices, the FLTA1 pin is supported, but requires an external pull-down

resistor for correct functionality.

2: On PIC24FJ16MC102 (28-pin) devices, the FLTA1 and FLTB1 pins are supported and do not require an

external pull-down resistor .

3: The PxFLTACON register is a write-protected register. Refer to Section 15.3 “Write-protected

Registers” for more informati on on the unlock sequence.

4: Comparator outputs are not internally connected to the PWM Fault co ntrol logic. If using the Comparator

modules for Fault generation, the user must externally connect the desired comparator output pin to the

dedicated FLTA1 or FLTB1 input pin.

5: During any reset event, the FLTA1 pin is enabled by default and must be cleared as described in

Section 15.2 “PWM Faults”.

PIC24FJ16MC101/102

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— FBOV3H FBOV3L FBOV2H FBOV2L FBOV1H FBOV1L

bit 15 bit 8

R/W-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1

FLTBM — — — — FBEN3 FBEN2 FBEN1

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13-8 FBOVxH<3:1>:FBOVxL<3:1>: Fault Input B PWM Override Value bits

1 = The PWM output pin is driven active on an external Fault inpu t event

0 = The PWM output pin is driven inactive on an external Fault input event

bit 7 FLTBM: Fault B Mode bit

1 = The Fault B input pin functions in the Cycle-by-Cycle mode

0 = The Fault B input pin latches all control pins to the programmed states in PxFLTBCON<13:8>

bit 6-3 Unimplemented: Read as ‘0’

bit 2 FBEN3: Fault Input B Enable bit

1 = PWMxH3/PWMxL3 pin pair is controlled by Fault Input B

0 = PWMxH3/PWMxL3 pin pair is not controlled by Fault Input B

bit 1 FBEN2: Fault Input B Enable bit

1 = PWMxH2/PWMxL2 pin pair is controlled by Fault Input B

0 = PWMxH2/PWMxL2 pin pair is not controlled by Fault Input B

bit 0 FBEN1: Fault Input B Enable bit

1 = PWMxH1/PWMxL1 pin pair is controlled by Fault Input B

0 = PWMxH1/PWMxL1 pin pair is not controlled by Fault Input B

Note 1: On PIC24FJ16MC101 (20-pin) devices, the FLTA1 pin is supported, but requires an external pull-down

resistor for correct functionality.

2: On PIC24FJ16MC102 (28-pin) devices, the FLTA1 and FLTB1 pins are supported and do not require an

external pull-down resistor .

3: The PxFLTACON register is a write-protected register. Refer to Section 15.3 “Write-protected

Registers” for more information on the unlock sequence.

4: Comparator outputs are not internally connected to the PWM Fault control log ic. If using the Comparator

modules for Fault generation, the user must externally connect the desired comparator output pin to the

dedicated FLTA1 or FLTB1 input pin.

5: During any reset event, the FLTB1 pin is enabled by default and must be cleared as described in

Section 15.2 “PWM Faults”.

PIC24FJ16MC101/102

U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

—— POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L

bit 15 bit 8

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13-8 POVDxH<3:1>:POVDxL<3:1>: PWM Output Override bits

1 = Output on PWMx I/O pin is controlled by the PWM generator

0 = Output on PWMx I/O pin is controlled by the value in the corresponding POUTxH:POUTxL bit

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 POUTxH<3:1>:POUTxL<3:1>: PWM Manua l Output bits

1 = PWMx I/O pin is driven active when the corresponding POVDxH:POVDxL bit is cleared

0 = PWMx I/O pin is driven inactive when the corresponding POVDxH:POVDxL bit is cleared

PIC24FJ16MC101/102

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PDC1<15:8>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PDC1<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 PDC1<15:0>: PWM Duty Cycle 1 Value bits

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PDC2<15:8>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PDC2<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 PDC2<15:0>: PWM Duty Cycle 2 Value bits

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PDC3<15:8>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PDC3<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 PDC3<15:0>: PWM Duty Cycle 3 Value bits

PIC24FJ16MC101/102

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PWMKEY<15:8>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PWMKEY<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 PWMKEY<15:0>: PWM Key Unlock bits

If the PWMLOCK Configuration bit is asserted (PWMLOCK = 1), the PWMxCON1, PxFLTACON and

PxFLTBCON registers are writable only after the proper sequence is written to the PWMxKEY

If the PWMLOCK Configuration bit is deasserted (PWMLOCK = 0) the PWMxCON1, PxFLTACON

and PxFLTBCON registers are writable at all times.

Refer to Section 47. “Motor Control PWM” (DS39735) in the “PIC24F Family Reference Manual”

for further details about the unlock sequence.

PIC24FJ16MC101/102

16.0 SERIAL PERIPHERAL

INTERFACE (SPI) The Serial Peripheral Interface (SPI) module is a syn-

chronous serial interface useful for communicating with

other peripheral or microcontroller devices. These

peripheral devices can be serial EEPROMs, shift regis-

ters, display drivers, analog-to-digital converters, etc.

The SPI module is compatible with SPI and SIOP from

Motorola®.

Each SPI module consists of a 16-bit shift register,

SPIxSR (where x = 1 or 2), used for shifting data in and

out, and a buffer register, SPIxBUF. A control register,

SPIxCON, configures the module. Additionally, a status

The serial interface consists of four pins:

• SDIx (serial data input)

• SDOx (serial data output)

• SCKx (shift clock input or output)

• SSx (active low slave select).

In Master mode operation, SCK is a clock output. In

Slave mode, it is a clock input.

FIGURE 16-1: SPI MODULE BLOCK DIAGRAM

Note 1: This data sheet summarizes the features

of the PIC24FJ16MC101/102 family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 23. “Serial

Peripheral Interface (SPI)” (DS39699)

in the “PIC24F Family Reference

Manual”, which is available from the

Microchip web site

(www.microchip.com).

2: It is important to note that the

specifications in Section 26.0 “Electri-

cal Characteristics” of this data sheet,

supercede any specifications that may be

provided in PIC24F Family Reference

Manual sections.

3: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Internal Data Bus

SDIx

SDOx

SSx

SCKx

SPIxSR

bit 0

Shift Control

Edge

Select

FCY

Primary

1:1/4/16/64

Enable

Prescaler

Sync

SPIxBUF

Control

Transfer

Write SPIxBUF

Read SPIxBUF

SPIxCON1<1:0>

SPIxCON1<4:2>

Master Clock

Clock

Control

Secondary

Prescaler

1:1 to 1:8

SPIxRXB SPIxTXB

PIC24FJ16MC101/102

R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

SPIEN — SPISIDL — — — — —

bit 15 bit 8

U-0 R/C-0 U-0 U-0 U-0 U-0 R-0 R-0

— SPIROV — — — — SPITBF SPIRBF

bit 7 bit 0

Legend: C = Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 SPIEN: SPIx Enable bit

1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins

0 = Disables module

bit 14 Unimplemented: Read as ‘0’

bit 13 SPISIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode

0 = Continue module operati on in Idle mode

bit 12-7 Unimplemented: Read as ‘0’

bit 6 SPIROV: Receive Overflow Flag bit

1 = A new byte/word is completely received and discarded. The user software has not read the

previous data in the SPIxBUF register.

0 =No overflow has occurred.

bit 5-2 Unimplemented: Read as ‘0’

bit 1 SPITBF: SPIx Transmit Buffer Full Status bit

1 = Transmit not yet started, SPIxTXB is full

0 = Transmit started, SPIxTXB is empty

Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB.

Automatically cleared in hardware when SPIx modu le transfers data from SPIxTXB to SPIxSR.

bit 0 SPIRBF: SPIx Receive Buffer Full Status bit

1 = Receive complete, SPIxRXB is full

0 = Receive is not complete, SPIxRXB is empty

Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB.

Automatically cleared in hardware when core reads SPIxBUF locati on, reading SPIxRXB.

PIC24FJ16MC101/102

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — DISSCK DISSDO MODE16 SMP CKE(1)

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SSEN(2) CKP MSTEN SPRE<2:0>(3) PPRE<1:0>(3)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 Unimplemented: Read as ‘0’

bit 12 DISSCK: Disable SCKx pin bit (SPI Master modes only)

1 = Internal SPI clock is disabled, pin functions as I/O

0 = Internal SPI clock is enabled

bit 11 DISSDO: Disable SDOx pin bit

1 = SDOx pin is not used by module; pin functions as I/O

0 = SDOx pin is controlled by the module

bit 10 MODE16: Word/Byte Communication Select bit

1 = Communication is word-wide (16 bits)

0 = Communication is byte-wide (8 bits)

bit 9 SMP: SPIx Data Input Sample Phase bit

Master mode:

1 = Input data sampled at end of data output time

0 = Input data sampled at middle of data output time

Slave mode:

SMP must be cleared when SPIx is used in Slave mode.

bit 8 CKE: SPIx Clock Edge Select bit(1)

1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6)

0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6)

bit 7 SSEN: Slave Select Enable bit (Slave mode)

1 = SSx pin used for Slave mode

0 = SSx pin not used by module. Pin controlled by port function.

bit 6 CKP: Clock Polarity Select bit

1 = Idle state for clock is a high level; active state is a low level

0 = Idle state for clock is a low level; active state is a high level

bit 5 MSTEN: Master Mode Enable bit

1 = Master mode

0 = Slave mode

Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes

(FRMEN = 1).

2: This bit must be cleared when FRMEN = 1.

3: Do not set both Primary and Secondary prescalers to a value of 1:1.

PIC24FJ16MC101/102

bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode)(3)

111 = Secondary prescale 1:1

110 = Secondary prescale 2:1

•

000 = Secondary prescale 8:1

bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode)(3)

11 = Primary prescale 1:1

10 = Primary prescale 4:1

01 = Primary prescale 16:1

00 = Primary prescale 64:1

Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes

(FRMEN = 1).

2: This bit must be cleared when FRMEN = 1.

3: Do not set both Primary and Secondary prescalers to a value of 1:1.

PIC24FJ16MC101/102

R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0

FRMEN SPIFSD FRMPOL — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0

— — — — — — FRMDLY —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 FRMEN: Framed SPIx Support bit

1 = Framed SPIx support enabled (SSx pin used as frame sync pulse input/output)

0 = Framed SPIx support disabled

bit 14 SPIFSD: Frame Sync Pulse Direction Control bit

1 = Frame sync pulse input (slave)

0 = Frame sync pulse output (master)

bit 13 FRMPOL: Frame Sync Pulse Polarity bit

1 = Frame sync pulse is active-high

0 = Frame sync pulse is active-low

bit 12-2 Unimplemented: Read as ‘0’

bit 1 FRMDLY: Frame Sync Pulse Edge Select bit

1 = Frame sync pulse coincides with first bit clock

0 = Frame sync pulse precedes first bit clock

bit 0 Unimplemented: This bit must not be set to ‘1’ by the user application.

PIC24FJ16MC101/102

NOTES:

PIC24FJ16MC101/102

17.0 INTER-INTEGRATED CIRCUIT™

(I2C™)

The Inter-Integrated Circu it™ (I 2C™) module provides

complete hardware support for both Slave and Multi-

Master modes of the I2C serial communication

standard, with a 16-bit interface.

The I2C module has a 2-pin in terface:

• The SCLx pin is clock

• The SDAx pin is data

The I2C module offers the following key features:

•I

2C interface supporting both Master and Slave

modes of operation.

•I

2C Slave mode supports 7-bit and 10-bit addressing

•I

2C Master mode supports 7-bit and 10-bit addressing

•I

2C port allows bidirectional transfers between

master and slaves

• Serial clock synchronization for I2C port can be

used as a handshake mechanism to suspend and

resume serial transfer (SCLREL control)

•I

2C supports multi-master operation, detects bus

collision and arbitrates accordingly

17.1 Operating Modes

The hardware fully implements all the master and slave

functions of the I2C Standard and Fast mode

specifications, as well as 7-bit and 10-bit addressing.

The I2C module can operate either as a slave or a

master on an I2C bus.

The following types of I2C operation are supported:

•I

2C slave operation with 7-bit addressing

•I

2C slave operation with 10-bit addressing

•I

2C master operation with 7-bit or 10-bit addressing

For details about the communication sequence in each

of these modes, refer to the Microchip web site

(www.microchip.com) for the latest “PIC24F Family

Reference Manual” sections.

17.2 I2C Registers

I2CxCON and I2CxSTAT are control and status

registers, respectively. The I2CxCON register is

readable and writable. The lower six bits of I2CxSTAT

are read-only. The remaining bits of the I2CSTAT are

read/write:

• I2CxRSR is the shift register used for shifting data

• I2CxRCV is the receive buffer and the register to

which data bytes are written, or from which data

bytes are read

• I2CxTRN is the transmit register to which bytes

are written during a transmit operation

• I2CxADD register holds the slave add ress

• ADD10 status bit indicates 10-bit Address mode

• I2CxBRG acts as the Baud Rate Generator (BRG)

reload value

In receive operations, I2CxRSR and I2CxRCV together

form a double-buffered receiver. When I2CxRSR

receives a complete byte, it is transferred to I2CxRCV,

and an interrupt pulse is generated.

Note 1: This data sheet summarizes the features

of the PIC24FJ16MC101/102 family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 24. “Inter-Inte-

grated Circuit™ (I2C™)” (DS39702) in

the “PIC24F Family Reference Manual”,

which is available from the Microchip web

site (www.microchip.com).

2: It is important to note that the

specifications in Section 26.0 “Electri-

cal Characteristics” of this data sheet,

supercede any specifications that may be

provided in PIC24F Family Reference

Manual sections.

3: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

PIC24FJ16MC101/102

FIGURE 17-1: I2C™ BLOCK DIAGRAM (X = 1)

Internal

Data Bus

SCLx

SDAx

Shift

Match Detect

I2CxADD

Start and Stop

Bit Detect

Clock

Address Match

Clock

Stretching

I2CxTRN LSb

Shift Clock

BRG Down Counter

Reload

Control

TCY/2

Start and Stop

Bit Generation

Acknowledge

Generation

Collision

Detect

I2CxCON

I2CxSTAT

Control Logic

Read

LSb

Write

Read

I2CxBRG

I2CxRSR

Write

Read

Write

Read

Write

Read

Write

Read

Write

Read

I2CxMSK

I2CxRCV

PIC24FJ16MC101/102

R/W-0 U -0 R/W-0 R/W-1 HC R/W-0 R /W-0 R/W-0 R/ W-0

I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 HC R/W-0 HC R/W-0 HC R/W-0 HC R/W-0 HC

GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN

bit 7 bit 0

Legend: U = Unimplemented bit, read as ‘0’

R = Readable bit W = Writable bit HS = Set in hardware HC = Cleare d in hardware

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 I2CEN: I2Cx Enable bit

1 = Enables the I2Cx module and co nfigures the SDAx and SCLx pins as serial port pins

0 = Disables the I2Cx module. All I2C pins are controlled by port functions.

bit 14 Unimplemented: Read as ‘0’

bit 13 I2CSIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters an Idle mode

0 = Continue module operati on in Idle mode

bit 12 SCLREL: SCLx Release Control bit (when operating as I2C slave)

1 = Release SCLx clock

0 = Hold SCLx clock low (clock stretch)

If STREN = 1:

Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear

at beginning of every slave data byte transmission. Hardware clear at end every of slave address byte

reception. Hardware clear at every slave data byte reception.

If STREN = 0:

Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware clear at beginning of every slave

data byte transmission. Hardware clear at end of every slave address byte reception.

bit 11 IPMIEN: Inte lligent Peripheral Management Interface (IPMI) Enable bit

1 = IPMI mode is enabled; all addresses Acknowledged

0 = IPMI mode disabled

bit 10 A10M: 10-bit Slave Address bit

1 = I2CxADD is a 10-bit slave address

0 = I2CxADD is a 7-bit slave address

bit 9 DISSLW: Disable Slew Rate Control bit

1 = Slew rate control disabled

0 = Slew rate control enabled

bit 8 SMEN: SMBus Input Levels bit

1 = Enable I/O pin thresholds compliant with SMBus specification

0 = Disable SMBus input thresholds

bit 7 GCEN: General Call Enable bit (when operating as I 2C slave)

1 = Enable interrupt when a general call address is received in the I2CxRSR

(module is enabled for reception)

0 = General call address disabled

bit 6 STREN: SCLx Clock S tretch Enable bit (when operating as I2C slave)

Used in conjunction with SCLREL bit.

1 = Enable software or receive clock stretching

0 = Disable software or receive clock stretching

PIC24FJ16MC101/102

bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive)

Value that will be transmitted when the software initiates an Acknowledge sequ ence.

1 = Send NACK during Acknowledge

0 = Send ACK during Acknowledge

bit 4 ACKEN: Acknowledge Sequence Enable bit

(when operating as I2C master, applicable durin g master receive)

1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.

Hardware clear at end of master Acknowledge sequence.

0 = Acknowledge sequence not in progress

bit 3 RCEN: Receive Enable bit (when operating as I2C master)

1 = Enables Receive mode for I2C. Hardware clear at end of eighth bit of maste r receiv e data byte.

0 = Receive sequence not in progres s

bit 2 PEN: Stop Condition Enable bit (when operating as I2C master)

1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence.

0 = Stop condition not in progress

bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I2C master)

1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of

master Repeated Start sequence.

0 = Repeated Start condition not in prog ress

bit 0 SEN: Start Condition Enable bit (w hen operating as I2C master)

1 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Sta rt sequence.

0 = Start condition not in progress

PIC24FJ16MC101/102

R-0 HSC R-0 HSC U-0 U-0 U-0 R/C-0 HS R-0 HSC R-0 HSC

ACKSTAT TRSTAT — — — BCL GCSTAT ADD10

bit 15 bit 8

R/C-0 HS R/C-0 HS R-0 HSC R/C-0 HSC R/C-0 HSC R-0 HSC R-0 HSC R-0 HSC

IWCOL I2COV D_A P S R_W RBF TBF

bit 7 bit 0

Legend: U = Unimplemented bit, read as ‘0’

R = Readable bit W = Writable bit HS = Set in hardware HSC = Hardware set/cleared

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 ACKSTAT: Acknowledge Status bit

(when operating as I2C master, applicable to master transmit operation)

1 = NACK received from slave

0 = ACK received from slave

Hardware set or clear at end of slave Acknowledge.

bit 14 TRSTAT: Transmit Status bit (when operating as I2C master, applicable to ma ster transmit operation)

1 = Master transmit is in progress (8 bits + ACK)

0 = Master transmit is not in progress

Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge.

bit 13-11 Unimplemented: Read as ‘0’

bit 10 BCL: Master Bus Collision Detect bit

1 = A bus collision has been detected duri ng a master operation

0 = No collision

Hardware set at detection of bus collision.

bit 9 GCSTAT: Ge neral Call Status bit

1 = General call address was received

0 = General call addre ss was not received

Hardware set when address matches general call address. Hardware clear at Stop detection.

bit 8 ADD10: 10-bit Address Status bit

1 = 10-bit address was matched

0 = 10-bit address was not matched

Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection.

bit 7 IWCOL: Write Collision Detect bit

1 = An attempt to write the I2CxTRN register failed because the I2C module is busy

0 = No collision

Hardware set at occurrence of write to I2CxTRN while busy (clea red by software).

bit 6 I2COV: Receive Overflow Flag bit

1 = A byte was received while the I2CxRCV register is still holding the previous byte

0 = No overflow

Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software).

bit 5 D_A: Data/Address bit (when operating as I2C slave)

1 = Indicates that the last byte received was data

0 = Indicates that the last byte received was device address

Hardware clear at device address match. Hardware set by reception of slave byte.

bit 4 P: Stop bit

1 = Indicates that a Stop bit has been detected last

0 = S t op bit was not detected last

Hardware set or clear when Start, Repeated Start or Stop detected.

PIC24FJ16MC101/102

bit 3 S: Start bit

1 = Indicates that a Start (or Repeated Start) bit has been detected last

0 = Start bit was not detected last

Hardware set or clear when Start, Repeated Start or Stop detected.

bit 2 R_W: Read/Write Information bit (when operating as I2C slave)

1 = Read – indicates data transfer is output from slave

0 = Write – indicates data transfer is input to slave

Hardware set or clear after reception of I2C device address byte.

bit 1 RBF: Receive Buffer Full Status bit

1 = Receive complete, I2CxRCV is full

0 = Receive not complete, I2CxRCV is empty

Hardware set when I2CxRCV is written with received byte. Hardware clear when software

reads I2CxRC V.

bit 0 TBF: Transmit Buffer Full Status bit

1 = Transmit in progress, I2CxTRN is full

0 = Transmit complete, I2CxTRN is empty

Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission.

PIC24FJ16MC101/102

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

— — — — — — AMSK9 AMSK8

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimple me nted bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-10 Unimplemented: Read as ‘0’

bit 9-0 AMSKx: Mask for Address bit x Select bit

1 = Enable masking for bit x of incoming message address; bit match not required in this position

0 = Disable masking for bit x; bit match required in this position

PIC24FJ16MC101/102

NOTES:

PIC24FJ16MC101/102

18.0 UNIVERSAL ASYNCHRONOUS

RECEIVER TRANSMITTER

(UART)

The Universal Asynchronous Receiver Transmitter

(UART) module is one of the serial I/O modules

available in the PIC24FJ16MC101/102 device family.

The UART is a full-duplex asynchronous system that

can communicate with peripheral devices, such as

personal computers, LIN 2.0, and RS-232, and RS-485

interfaces. The module a lso supports a hardware flow

control option with the UxCTS and UxRTS pins and

also includes an IrDA® encoder and decoder.

The primary features of the UART module are:

• Full-Duplex, 8-bit or 9-bit Data Transmission

through the UxTX and UxRX pins

• Even, Odd, or No Parity Options (for 8-bit data)

• One or two stop bits

• Hardware flow control option with UxCTS an d

UxRTS pins

• Fully integrated Baud Rate Generator with 16-bit

prescaler

• Baud rates ranging from 0.4 Mbps to 6 bps at 16x

mode at 16 MIPS

• Baud rates ranging from 1.6 Mbps to 24.4 bps at 4x

mode at 16 MIPS

• 4-deep First-In First-Out (FIFO) Transmit Data

buffer

• 4-deep FIFO Receive Data buffer

• Parity, framing and buf fer overrun error detection

• Support for 9-bit mode with Address Detect

(9th bit = 1)

• Transmit and Receive interrupts

• A separate interrupt for all UART error conditions

• Loopback mode for diagnostic support

• Support for sync and break charac ters

• Support for automatic baud rate detection

•IrDA

® encoder and decoder logic

• 16x baud clock output for IrDA® support

A simplified block diagram of the UART module is

shown in Figure 18-1. The UART module consists of

these key hardware elements:

• Baud Rate Generator

• Asynchronous Transmitter

• Asynchronous Receiver

FIGURE 18-1: UART SIMPLIFIED BLOCK DIAGRAM

Note 1: This data sheet summarizes the features

of the PIC24FJ16MC101/102 family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 21. “UART”

(DS39708) in the “PIC24F Family

Reference Manual”, which is available

from the Microchip web site

(www.microchip.com).

2: It is important to note that the

specifications in Section 26.0 “Electri-

cal Characteristics” of this data sheet,

supercede any specifications that may be

provided in PIC24F Family Reference

Manual sections.

3: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

UxRX

Hardware Flow Control

UART Receiver

UART Transmitter UxTX

Baud Rate Generator

UxRTS/BCLK

IrDA®

UxCTS

PIC24FJ16MC101/102

R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

UARTEN(1) — USIDL IREN(2) RTSMD —UEN<1:0>

bit 15 bit 8

R/W-0 HC R/W-0 R/W-0 HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL

bit 7 bit 0

Legend: HC = Hardware cleared

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 UARTEN: UARTx Enabl e bi t(1)

1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>

0 = UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption

minimal

bit 14 Unimplemented: Read as ‘0’

bit 13 USIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode

0 = Continue module operation in Idle mode

bit 12 IREN: IrDA® Encoder and Decoder Enable bit(2)

1 = IrDA encoder and decoder enabled

0 = IrDA encoder and decoder disabled

bit 11 RTSMD: Mode Selection for UxRTS Pin bit

1 =UxRTS

pin in Simplex mode

0 =UxRTS pin in Flow Control mode

bit 10 Unimplemented: Read as ‘0’

bit 9-8 UEN<1:0>: UARTx Pin Enable bits

11 = UxTX, UxRX and BCLK pins are enabled and used; UxCTS pin controlled by port latches

10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used

01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by port latches

00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLK pins controlled by

port latches

bit 7 WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit

1 = UARTx will continue to sample the UxRX pin; interrupt generated on falling edge; bit cleared

in hardware on following rising edge

0 = No wake-up enabled

bit 6 LPBACK: UARTx Loopback Mode Select bit

1 = Enable Loopback mode

0 = Loopback mode is disabled

bit 5 ABAUD: Auto-Baud Enab le bit

1 = Enable baud rate measurement on the next character – requires reception of a Sync field (55h)

before other data; cleared in hardware upon completi on

0 = Baud rate measurement disabled or completed

Note 1: Refer to Section 21. “UART” (DS39708) in the “PIC24F Family Reference Manual” for information on

enabling the UART module for receive or transmit operation.

2: This feature is only available for the 16x BRG mode (BRGH = 0).

PIC24FJ16MC101/102

bit 4 URXINV: Receive Polarity Inversion bit

1 = UxRX Idle state is ‘0’

0 = UxRX Idle state is ‘1’

bit 3 BRGH: High Baud Rate Enable bit

1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)

0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode)

bit 2-1 PDSEL<1:0>: Parity and Data Selection bits

11 = 9-bit data, no parity

10 = 8-bit data, odd parity

01 = 8-bit data, even parity

00 = 8-bit data, no parity

bit 0 STSEL: Stop Bit Selection bit

1 = Two Stop bits

0 = One Stop bit

Note 1: Refer to Section 21. “UART” (DS39708) in the “PIC24F Family Reference Manual” fo r information on

enabling the UART module for receive or transmit operation.

2: This feature is only available for the 16x BRG mode (BRGH = 0).

PIC24FJ16MC101/102

R/W-0 R/W-0 R/W-0 U-0 R/W-0 HC R/W-0 R-0 R-1

UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN(1) UTXBF TRMT

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/C-0 R-0

URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA

bit 7 bit 0

Legend: HC = Hardware cleared C = Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15,13 UTXISEL<1:0>: Transmission Interrupt Mode Selection bits

11 = Reserved; do not use

10 = Interrupt when a character is transferred to the Transmit Shift Register, and as a result, the

transmit buffer becomes empty

01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit

operations are completed

00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is

at least one character open in the transmit buffer)

bit 14 UTXINV: Transmit Polarity Inversion bit

If IREN = 0:

1 = UxTX Idle state is ‘0’

0 = UxTX Idle state is ‘1’

If IREN = 1:

1 =IrDA

® encoded UxTX Idle state is ‘1’

0 = IrDA encoded UxTX Idle state is ‘0’

bit 12 Unimplemented: Read as ‘0’

bit 11 UTXBRK: Transmit Break bit

1 = Send Sync Break on next transmission – S tart bit, followed by twelve ‘0’ bits, followed by Stop bit;

cleared by hardware upon completion

0 = Sync Break transmission disabled or completed

bit 10 UTXEN: Transmit Enable bit(1)

1 = Transmit enabled, UxT X pin controlled by UARTx

0 = Tran smit disabled, any pending transmission is abo rted and buffer is reset. UxTX pin control led

by port.

bit 9 UTXBF: Transmit Buf f er Full Status bit (read-only)

1 = Transmit buffer is full

0 = Transmit buffer is not full, at least one more character can be written

bit 8 TRMT: Transmit Shift Register Empty bit (read-only)

1 = Transmit Shif t Register is empty and transmit buf fer is empty (the last transmission has completed)

0 = Transmit Shift Register is not empty, a transmission is in progress or queued

bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bits

11 = Interrupt is set on UxRSR transfer making the receive buffer full (i.e., has 4 data characters)

10 = Interrupt is set on UxRSR transfer making the receive buffer 3/4 full (i.e., has 3 data characters)

0x = Interrupt is set when any character is receiv ed and transferred from the UxRSR to the receive

buffer. Receive buffer has one or more characters.

Note 1: Refer to Section 21. “UART” (DS39708) in the “PIC24F Family Reference Manual” for information on

enabling the UART module for transmit operation.

PIC24FJ16MC101/102

bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1)

1 = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect.

0 = Address Detect mode disabled

bit 4 RIDLE: Receiver Idle bit (read-on ly)

1 = Receiver is Idle

0 = Receiver is active

bit 3 PERR: Parity Error Status bit (read-only)

1 = Parity error has been detected for the current character (characte r at t he top of the receive FIFO)

0 = Parity error has not been detected

bit 2 FERR: Framing Error Status bit (read-only)

1 = Framing error has been detected for the current character (character at the top of the receive

FIFO)

0 = Framing error has not been detected

bit 1 OERR: Receive Buffer Overrun Error Status bit (read-only/clear-only)

1 = Receive buffer has overflowed

0 = Receive buffer has not overflowed. Clearing a previously set OERR bit (1→0 transition) will reset

the receiver buffer and the UxRSR to the empty state.

bit 0 URXDA: Receive Buffer Data Available bit (read-only)

1 = Receive buffer has data, at least one more character can be read

0 = Receive buffer is empty

Note 1: Refer to Section 21. “UART” (DS39708) in the “PIC24F Family Reference Manual” fo r information on

enabling the UART module for transmit operation.

PIC24FJ16MC101/102

NOTES:

PIC24FJ16MC101/102

19.0 10-BIT

ANALOG-TO-DIGITAL

CONVERTER (ADC)

The PIC24FJ16MC101/102 devices have up to six

ADC module input channels.

19.1 Key Features

The 10-bit ADC configuration has the following key

features:

• Successive Approximation (SAR) conversion

• Conversion speeds of up to 1.1 Msps

• Up to six analog input pins

• Four Sample and Hold circuits for simultaneous

sampling of up to four analog input pins

• Automatic Channel Scan mode

• Selectable conversion trigger source

• Selectable Buffer Fill modes

• Four result alignment options (signed/unsigned,

fractional/integer)

• Operation during CPU Sleep and Idle modes

• 16-word conversion result buffer

Depending on the particular device pinout, the ADC

can have up to six analog input pins, designated AN0

through AN5.

Block diagrams of the ADC module are shown in

Figure 19-1 and Figure 19-2.

19.2 ADC Initialization

To configure the ADC module:

1. Select port pins as analog inputs

(ADxPCFGH<15:0> or ADxPCFGL<15:0>).

2. Select voltage reference source to match

expected range on analog inputs

(ADxCON2<15:13>).

3. Select the analog conversion clock to match the

desired data rate with the processor clock

(ADxCON3<7:0>).

4. Determine how many sample-and-hold chan-

nels will be used (ADxCON2<9:8> and

ADxPCFGH<15:0> or ADxPCFGL<15:0>).

5. Select the appropriate sample/conversion

sequence (ADxCON1<7:5> and

ADxCON3<12:8>).

6. Select the way conversion results are presented

in the buffer (ADxCON1<9:8>).

7. Turn on the ADC module (ADxCON1<15>).

8. Configure ADC interrupt (if required):

a) Clear the ADxIF bit.

b) Select the ADC interrupt priority.

Note 1: This data sheet summarizes the features

of the PIC24FJ16MC101/102 family of

devices. It is not intended to be a compre-

hensive reference source. To comple-

ment the information in this data sheet,

refer to Section 46. “10-bit Analog-to-

Digital Converter (ADC) with 4 Simul-

taneous Conversions” (DS39737) in

the “PIC24F Family Reference Manual”,

which is available from the Microchip web

site (www.microchip.com).

2: It is important to note that the

specifications in Section 26.0 “Electri-

cal Characteristics” of this data sheet,

supercede any specifications that may be

provided in PIC24F Family Reference

Manual sections.

3: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

PIC24FJ16MC101/102

FIGURE 19-1: ADC1 BLOCK DIAGRAM FOR PIC24FJ16MC101 DEVICES

SAR ADC

S/H0

S/H1

ADC1BUF0

ADC1BUF1

ADC1BUF2

ADC1BUFF

ADC1BUFE

AN0

AN3

AN1

AVss

CH0SB<4:0>

CH0NA CH0NB

AN0

AN3

CH123SA

AVss

CH123SB

CH123NA CH123NB

S/H2

AN1

CH123SA

AVss

CH123SB

CH123NA CH123NB

S/H3

AN2

CH123SA

AVss

CH123SB

CH123NA CH123NB

CH1

CH0

CH2

CH3

CH0SA<4:0>

Channel

Scan

CSCNA

Alternate

AVDD AVSS

Input Selection

VREFH VREFL

CTMU(1)

Note 1: Internally connected to CTMU module.

2: This selection is only used with CTMU capacitive and time measurement.

Open(2) CTMUI(1)

PIC24FJ16MC101/102

FIGURE 19-2: ADC1 BLOCK DIAGRAM FOR PIC24FJ16MC102 DEVICES

SAR ADC

S/H0

S/H1

ADC1BUF0

ADC1BUF1

ADC1BUF2

ADC1BUFF

ADC1BUFE

AN0

AN5

AN1

AVss

CH0SB<4:0>

CH0NA CH0NB

AN0

AN3

CH123SA

AVss

CH123SB

CH123NA CH123NB

S/H2

AN1

AN4

CH123SA

AVss

CH123SB

CH123NA CH123NB

S/H3

AN2

AN5

CH123SA

AVss

CH123SB

CH123NA CH123NB

CH1

CH0

CH2

CH3

CH0SA<4:0>

Channel

Scan

CSCNA

Alternate

Input Selection

VREFH VREFL

AVDD AVSS

CTMU(1)

Note 1: Internally connected to CTMU module.

2: This selection is only used with CTMU capacitive and time measurement.

Open(2) CTMUI(1)

PIC24FJ16MC101/102

FIGURE 19-3: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM

ADC Internal

RC Clock(1)

TOSC(1) X2

ADC Conversion

Clock Multiplier

1, 2, 3, 4, 5,..., 64

ADxCON3<15>

TCY

TAD

ADxCON3<5:0>

Note 1: See the ADC specifications in Section 26.0 “Electrical Characteristics” for the exact RC clock value.

PIC24FJ16MC101/102

R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0

ADON —ADSIDL— — — FORM<1:0>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0

HC,HS R/C-0

HC, HS

SSRC<2:0> — SIMSAM ASAM SAMP DONE

bit 7 bit 0

Legend: HC = Cleared by hardware HS = Set by hardware C = Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 ADON: ADC Operating Mode bit

1 = ADC module is operating

0 = ADC is off

bit 14 Unimplemented: Read as ‘0’

bit 13 ADSIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode

0 = Continue module operation in Idle mode

bit 12-10 Unimplemented: Read as ‘0’

bit 9-8 FORM<1:0>: Data Output Format bits

11 = Signed fractional (DOUT = sddd dddd dd00 0000, where s = .NOT.d<9>)

10 = Fractional (DOUT = dddd dddd dd00 0000)

01 = Signed integer (DOUT = ssss sssd dddd dddd, where s = .NOT.d<9>)

00 = Integer (DOUT = 0000 00dd dddd dddd)

bit 7-5 SSRC<2:0>: Sample Clock Source Select bits

111 = Internal counter ends samp ling and starts conversion (auto-convert)

110 = CTMU

101 = Reserved

100 = Reserved

011 = Motor Control PW M i nterval ends sampling and starts conversion

010 = GP timer 3 compare ends sampling and starts conversion

001 = Active transition on INT0 pin ends sampling and starts conversion

000 = Clearing sample bit ends sampling and starts conversion

bit 4 Unimplemented: Read as ‘0’

bit 3 SIMSAM: Simultaneous Sample Select bit (applicable only when CHPS<1:0> = 01 or 1x)

1 = Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or

Samples CH0 and CH1 simultaneously (when CHPS<1:0> = 01)

0 = Samples multiple channels individually in sequence

bit 2 ASAM: ADC Sample Auto-Start bit

1 = Sampling begins immediately after last conversion. SAMP bit is auto-set.

0 = Sampling begins when SAMP bit is set

bit 1 SAMP: ADC Sample Enable bit

1 = ADC sample-and-hold amplifiers are sampling

0 = ADC sample-and-hold amplifiers are holding

If ASAM = 0, software can write ‘1’ to begin sampling. Automatically set by hardware if ASAM = 1.

If SSRC = 000, software can write ‘0’ to end sampling and start conversion. If SSRC ≠ 000,

automatically cleared by hardware to end sampling and start conversi on.

PIC24FJ16MC101/102

bit 0 DONE: ADC Conversion S tatus bit

1 = ADC conversion cycle is completed

0 = ADC conversion not started or in progress

Automatically set by hardware when ADC conversion is complete. Software can write ‘0’ to clear

DONE status (software not allowed to write ‘1’). Clearing this bit will NOT affect any operation in

progress. Automatically cleared by hardware at start of a new conversion.

PIC24FJ16MC101/102

R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0

VCFG<2:0> —— CSCNA CHPS<1:0>

bit 15 bit 8

R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

BUFS — SMPI<3:0> BUFM ALTS

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 VCFG<2:0>: Converter Voltage Reference Configuration bits

bit 12-11 Unimplemented: Read as ‘0’

bit 10 CSCNA: Scan Input Selections fo r CH0+ during Sample A bit

1 = Scan inputs

0 = Do not scan inputs

bit 9-8 CHPS<1:0>: Select Channels Utilized bits

1x = Converts CH0, CH1, CH2 and CH3

01 = Converts CH0 and CH1

00 = Converts CH0

bit 7 BUFS: Buffer Fill Status bit (valid only when BUFM = 1)

1 = ADC is currently filling second half of buffer, user should access data in the first half

0 = ADC is currently filling first half of buffer, user application should access data in the second half

bit 6 Unimplemented: Read as ‘0’

bit 5-2 SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits

1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence

1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence

•

0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence

0000 = Interrupts at the completion of conversion for each sample/conve rt sequence

bit 1 BUFM: Buffer Fill Mode Select bit

1 = Starts filling first half of buffer on first interrupt and the second half of buffer on next interrupt

0 = Always starts filling buffer from the beginning

bit 0 ALTS: Alternate Input Sample Mode Select bit

1 = Uses channel input selects for Sample A on first sample and Sample B on next sample

0 = Always uses channel input selects for Sample A

ADREF+ ADREF-

xxx AVDD AVSS

PIC24FJ16MC101/102

R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADRC —— SAMC<4:0>(1)

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADCS<7:0>(2)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 ADRC: ADC Conversion Clock Source bit

1 = ADC internal RC clock

0 = Clock derived from system clock

bit 14-13 Unimplemented: Read as ‘0’

bit 12-8 SAMC<4:0>: Auto Sample Time bits(1)

11111 = 31 TAD

•

00001 = 1 TAD

00000 = 0 TAD

bit 7-0 ADCS<7:0>: ADC Conversion Clock Select bits(2)

11111111 = Reserved

•

01000000 = Reserved

00111111 = TCY · (ADCS<7:0> + 1) = 64 · TCY = TAD

•

00000010 = TCY · (ADCS<7:0> + 1) = 3 · TCY = TAD

00000001 = TCY · (ADCS<7:0> + 1) = 2 · TCY = TAD

00000000 = TCY · (ADCS<7:0> + 1) = 1 · TCY = TAD

Note 1: This bit only used if AD1CON1<7:5> (SSRC<2:0>) = 1.

2: This bit is not used if AD1CON3<15> (ADRC) = 1.

PIC24FJ16MC101/102

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — CH123NB<1:0> CH123SB

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — CH123NA<1:0> CH123SA

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-11 Unimplemented: Read as ‘0’

bit 10-9 CH123NB<1:0>: Channel 1, 2, 3 Negative Input Select for Sample B bits

11 = Reserved

10 = Reserved

0x = CH1, CH2, CH3 negative input is AVss

bit 8 CH123SB: Channel 1, 2, 3 Positive Input Select for Sample B bit

PIC24FJ16MC101 devices only:

1 = CH1 positive input is AN3, CH2 and CH3 positive inputs are not connected

0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2

PIC24FJ16MC102 devices only:

1 = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5

0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2

bit 7-3 Unimplemented: Read as ‘0’

bit 2-1 CH123NA<1:0>: Channel 1, 2, 3 Negative Input Select for Sample A bits

11 = Reserved

10 = Reserved

0x = CH1, CH2, CH3 negative input is AVss

bit 0 CH123SA: Channel 1, 2, 3 Positive Input Select for Sample A bit

PIC24FJ16MC101 devices only:

1 = CH1 positive input is AN3, CH2 and CH3 positive inputs are not connected

0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2

PIC24FJ16MC102 devices only:

1 = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5

0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2

PIC24FJ16MC101/102

R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CH0NB —— CH0SB<4:0>(1)

bit 15 bit 8

R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CH0NA —— CH0SA<4:0>(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 CH0NB: Channel 0 Negative Input Select for Sample B bit

1 = Channel 0 negative input is AN1

0 = Channel 0 negative input is AVss

bit 14-13 Unimplemented: Read as ‘0’

bit 12-8 CH0SB<4:0>: Channel 0 Positive Input Select for Sample B bits(1)

PIC24FJ16MC101 devices only:

01110 = No channels connected; all inputs are floating (used for CTMU)

01101 = Channel 0 positive input is connected to CTMU temperature sensor

00011 = Channel 0 positive input is AN3

00010 = Channel 0 positive input is AN2

00001 = Channel 0 positive input is AN1

00000 = Channel 0 positive input is AN0

PIC24FJ16MC102 devices only:

01110 = No channels connected; all inputs are floating (used for CTMU)

01101 = Channel 0 positive input is connected to CTMU temperature sensor

00101 = Channel 0 positive input is AN5

00100 = Channel 0 positive input is AN4

00011 = Channel 0 positive input is AN3

00010 = Channel 0 positive input is AN2

00001 = Channel 0 positive input is AN1

00000 = Channel 0 positive input is AN0

bit 7 CH0NA: Channel 0 Negative Input Select for Sample A bit

1 = Channel 0 negative input is AN1

0 = Channel 0 negative input is AVss

bit 6-5 Unimplemented: Read as ‘0’

bit 4-0 CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits(1)

PIC24FJ16MC101 devices only:

01110 = No channels connected; all inputs are floating (used for CTMU)

01101 = Channel 0 positive input is connected to CTMU temperature sensor

00011 = Channel 0 positive input is AN3

00010 = Channel 0 positive input is AN2

00001 = Channel 0 positive input is AN1

00000 = Channel 0 positive input is AN0

PIC24FJ16MC102 devices only:

01110 = No channels connected; all inputs are floating (used for CTMU)

01101 = Channel 0 positive input is connected to CTMU temperature sensor

00101 = Channel 0 positive input is AN5

00100 = Channel 0 positive input is AN4

00011 = Channel 0 positive input is AN3

00010 = Channel 0 positive input is AN2

00001 = Channel 0 positive input is AN1

00000 = Channel 0 positive input is AN0

Note 1: All other values than those listed are Reserved.

PIC24FJ16MC101/102

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— CSS5 CSS4 CSS3 CSS2 CSS1 CSS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-6 Unimplemented: Read as ‘0’

bit 5-0 CSS<5:0>: ADC Input Scan Selection bits

1 = Select ANx for input scan

0 = Skip ANx for input scan

Note 1: On devices without 6 analog inputs, all AD1CSSL bits can be selected by user applica tion. However,

inputs selected for scan without a corresponding input on device converts VREFL.

2: CSSx = ANx, where x = 0 through 5.

3: CTMU temperature sensor input cannot be scanned.

PIC24FJ16MC101/102

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

——PCFG5

(4) PCFG4(4) PCFG3(4) PCFG2(4) PCFG1(4) PCFG0(4)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-6 Unimplemented: Read as ‘0’

bit 5-0 PCFG<5:0>: ADC Port Configuration Control bits(4)

1 = Port pin in Digital mode, port read input enabled, ADC input multiplexer connected to AVSS

0 = Port pin in Analog mode, port read input disabled, ADC samples pin voltage

Note 1: On devices without 6 analog inputs, all PCFG bits are R/W by user. Ho wever, PCFG bits are ignored on

ports without a corresponding input on device.

2: PCFGx = ANx, where x = 0 through 5.

3: PCFGx bits have no effect if the ADC module is disabled by setting ADxMD bit in the PMDx register . When

the bit is set, all port pins that have been multiplexed with ANx will be in Digital mode.

4: Pins shared with analog functions (i.e., ANx), are analog by default and therefore, must be set by the user

to enable any digital function on that pin. Reading any port pin with the analog function enabled will return

a ‘0’, regardless of the signal input level.

PIC24FJ16MC101/102

20.0 COMPARATOR MODULE The PIC24FJ16MC101/102 Comparator module pro-

vides three comparators that can be configured in dif-

ferent ways. As shown in Figure 20-1, individual

comparator options are specified by the Comparator

module’s Special Function Register (SFR) control bits.

These options allow users to:

• Select the edge for trigger and interrupt generation

• Select low-powe r control

• Configure the comparator voltage reference and

band gap

• Configure output blanking and masking

The comparator operating mode is determined by the

input selections (i.e., whether the input voltage is

compared to a second input voltage, to an internal

voltage reference.

Note 1: This data sheet summarizes the features

of the PIC24FJ16MC101/102 families of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 48. “Comparator

with Blanking” (DS39741) of the

“PIC24F Family Reference Manual”,

which is available from the Microchip

websit e ( www.microchip.com).

2: It is important to note that the

specifications in Section 26.0 “Electri-

cal Characteristics” of this data sheet,

supercede any specifications that may be

provided in PIC24F Family Reference

Manual sections.

3: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

PIC24FJ16MC101/102

FIGURE 20-1: COMPARATOR I/O OPERATING MODES

Comparator Voltage

C1 Blanking

Function Digital

Filter

Reference

(Figure 20-2)CVREF

(Figure 20-3)(Figure 20-4)

–

VIN-

VIN+

–

VIN-

VIN+

–

VIN-

VIN+

BGSEL<1:0>

AVDD AVSS

1.2V(1)

MUX

C1INB

C1INC

C1IND

MUX

C1INA

INTREF

MUX

C2INB

C2INC

C2IND

MUX

C2INA

INTREF

CVREFIN

MUX

C3INB

C3INC

C3IND

MUX

C3INA

INTREF

CVREFIN

CVREFIN C1OUT

CPOL

Interrupt

Logic

EVPOL<1:0>

COE

COUT

Blanking

Function Digital

Filter

(Figure 20-3)(Figure 20-4)C2OUT

CPOL

Interrupt

Logic

EVPOL<1:0>

COE

COUT

Blanking

Function Digital

Filter

(Figure 20-3)(Figure 20-4)C3OUT

CPOL

Interrupt

Logic

EVPOL<1:0>

COE

COUT

Note 1: This reference voltage is generated internally on the device. Refer to Section 26.0 “Electrical Characteristics” for

the specified voltage range.

PIC24FJ16MC101/102

FIGURE 20-2: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

FIGURE 20-3: USER PROGRAMMABLE BLANKING FUNCTION BLOCK DIAGRAM

16-to-1 MUX

CVREN

AVDD(1)

16 St eps

CVRR

CVREF

CVR3

CVR2

CVR1

CVR0

CVRCON<3:0>

AVSS(1)

CVRSRC

CVRCON<CVROE>

CVREFIN

VREFSEL

Note 1: This pin is VDD and VSS on devices that have

no AVDD or AVSS pins.

SELSRCA<3:0>

SELSRCB<3:0>

SELSRCC<3:0>

AND

CMxMSKCON

MUX A

MAI

MBI

MCI

Analog Comparator Output To Digital

Signals Filter

Blanking

Signals

ANDI

MASK

“AND-OR” function

MAI

MBI

MCI

HLMS

MAI

MUX BMUX C

Blanking

Logic

PIC24FJ16MC101/102

FIGURE 20-4: DIGITAL FILTER INTERCONNECT BLOCK DIAGRAM

CXOUT

CFLTREN

Digital Filter

Timer2

FOSC

FCY

CFSEL<2:0>

÷CFDIV

From Blanking Logic

Timer3

PWM Special Event Trigger

PIC24FJ16MC101/102

R/W-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0

CMSIDL — — — — C3EVT C2EVT C1EVT

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0

— — — — — C3OUT C2OUT C1OUT

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 CMSIDL: Stop in Idle Mode bit

1 = Discontinue operation of all comparators when device enters Idle mode

0 = Continue operation of all comparators in Idle mode

bit 14-11 Unimplemented: Read as ‘0’

bit 10 C3EVT: Comparator 3 Event Status bit

1 = Comparator event occurred

0 = Comparator event did not occur

bit 9 C2EVT: Comparator 2 Event Status bit

1 = Comparator event occurred

0 = Comparator event did not occur

bit 8 C1EVT: Comparator 1 Event Status bit

1 = Comparator event occurred

0 = Comparator event did not occur

bit 7-3 Unimplemented: Read as ‘0’

bit 2 C3OUT: Comparator 3 Output Status bit

When CPOL = 0:

1 = VIN+ > VIN-

0 = VIN+ < VIN-

When CPOL = 1:

1 = VIN+ < VIN-

0 = VIN+ > VIN-

bit 1 C2OUT: Comparator 2 Output Status bit

When CPOL = 0:

1 = VIN+ > VIN-

0 = VIN+ < VIN-

When CPOL = 1:

1 = VIN+ < VIN-

0 = VIN+ > VIN-

bit 0 C1OUT: Comparator 1 Output Status bit

When CPOL = 0:

1 = VIN+ > VIN-

0 = VIN+ < VIN-

When CPOL = 1:

1 = VIN+ < VIN-

0 = VIN+ > VIN-

PIC24FJ16MC101/102

R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0

CON COE CPOL — — — CEVT COUT

bit 15 bit 8

R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0

EVPOL<1:0> —CREF—— CCH<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 CON: Comparator Enable bit

1 = Comparator is enabled

0 = Comparator is disabled

bit 14 COE: Comparator Output Enable bit

1 = Compar ator output i s pr e s en t on th e C x OU T pi n

0 = Comparator output is internal only

bit 13 CPOL: Comparator Output Pola rity S el e ct bi t

1 = Comparator output is inverted

0 = Comparator output is not inverted

bit 12-10 Unimplemented: Read as ‘0’

bit 9 CEVT: Comparator Event bit

1 = Comparator event according to EVPOL<1:0> settings occurred; disables future triggers and

interrupts until the bi t i s cle ared

0 = Comparator event did not occur

bit 8 COUT: Comparator Output bit

When CPOL = 0 (non-inverte d po l a rity):

1 = VIN+ > VIN-

0 = VIN+ < VIN-

When CPOL = 1 (inverted polarity):

1 = VIN+ < VIN-

0 = VIN+ > VIN-

bit 7-6 EVPOL<1:0>: Trigger/Event/Interrupt Polarity Select bits

11 = Trigger/Event/Interrupt generated on any change of the comparator output (while CEVT = 0)

10 = Trigger/Event/Interrupt generated only on high to low transition of the polarity-selected

comparat or ou tput (while CEVT = 0)

If CPOL = 1 (inverted polarity):

Low-to-high transition of the comparator output

If CPOL = 0 (non-i n verted polarit y ):

High-to-low transition of the comparator output

01 = Trigger/Event/Interrupt generated only on low to high transition of the polarity-selected

comparat or ou tput (while CEVT = 0)

If CPOL = 1 (inverted polarity):

High-to-low transition of the comparator output

If CPOL = 0 (non-i n verted polarit y ):

Low-to-high transition of the comparator output

00 = Trigger/Event/Interrupt generation is disabled

PIC24FJ16MC101/102

bit 5 Unimplemented: Read as ‘0’

bit 4 CREF: Comparator Reference Select bit (VIN+ input)

1 = VIN+ input connects to internal CVREFIN voltage

0 = VIN+ input connects to CxINA pin

bit 3-2 Unimplemented: Read as ‘0’

bit 1-0 CCH<1:0>: Comparator Channel Select bits

11 = VIN- input of comparator connects to INTREF

10 = VIN- input of comparator connects to CXIND pin

01 = VIN- input of comparator connects to CXINC pin

00 = VIN- input of comparator connects to CXINB pin

PIC24FJ16MC101/102

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 RW-0

— — — — SELSRCC<3:0>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SELSRCB<3:0> SELSRCA<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Uni mp lemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unkno wn

bit 15-12 Unimplemented: Read as ‘0’

bit 11-8 SELSRCC<3:0>: Mask C Input Select bits

1111 = Reserved

1110 = Reserved

1101 = Reserved

1100 = Reserved

1011 = Reserved

1010 = Reserved

1001 = Reserved

1000 = Reserved

0111 = Reserved

0110 = Reserved

0101 = PWM1H3

0100 = PWM1L3

0011 = PWM1H2

0010 = PWM1L2

0001 = PWM1H1

0000 = PWM1L1

bit 7-4 SELSRCB<3:0>: Mask B Input Select bits

1111 = Reserved

1110 = Reserved

1101 = Reserved

1100 = Reserved

1011 = Reserved

1010 = Reserved

1001 = Reserved

1000 = Reserved

0111 = Reserved

0110 = Reserved

0101 = PWM1H3

0100 = PWM1L3

0011 = PWM1H2

0010 = PWM1L2

0001 = PWM1H1

0000 = PWM1L1

PIC24FJ16MC101/102

bit 3-0 SELSRCA<3:0>: Mask A Input Select bits

1111 = Reserved

1110 = Reserved

1101 = Reserved

1100 = Reserved

1011 = Reserved

1010 = Reserved

1001 = Reserved

1000 = Reserved

0111 = Reserved

0110 = Reserved

0101 = PWM1H3

0100 = PWM1L3

0011 = PWM1H2

0010 = PWM1L2

0001 = PWM1H1

0000 = PWM1L1

PIC24FJ16MC101/102

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Uni mp lemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unkno wn

bit 15 HLMS: High or Low Level Masking Select bits

1 = The masking (blanking) function will prevent any asserted (‘0’) comparator signal from propagating

0 = The masking (blanking) function will prevent any asserted (‘1’) comparator signal from propagating

bit 14 Unimplemented: Read as ‘0’

bit 13 OCEN: OR Gate C Input Inverted Enable bit

1 = MCI is connected to OR gate

0 = MCI is not connected to OR gate

bit 12 OCNEN: OR Gate C Input Inverted Enable bit

1 = Inverted MCI is connected to OR gate

0 = Inverted MCI is not connected to OR gate

bit 11 OBEN: OR Gate B Input Inverted Enable bit

1 = MBI is connected to OR gate

0 = MBI is not connected to OR gate

bit 10 OBNEN: OR Gate B Input Inverted En able bit

1 = Inverted MBI is connected to OR gate

0 = Inverted MBI is not connected to OR gate

bit 9 OAEN: OR Gate A Input Enable bit

1 = MAI is connected to OR gate

0 = MAI is not connected to OR gate

bit 8 OANEN: OR Gate A Input Inverted Enable bit

1 = Inverted MAI is connected to OR gate

0 = Inverted MAI is not connected to OR gate

bit 7 NAGS: Negative AND Gate Output Select

1 = Inverted ANDI is connected to OR gate

0 = Inverted ANDI is not connected to OR gate

bit 6 PAGS: Positive AND Gate Output Select

1 = ANDI is connected to OR gate

0 = ANDI is not connected to OR gate

bit 5 ACEN: AND Gate A1 C Input Inverted Enable bit

1 = MCI is connected to AND gate

0 = MCI is not connected to AND gate

bit 4 ACNEN: AND Gate A1 C Input Inverted Enable bit

1 = Inverted MCI is connecte d to AND gate

0 = Inverted MCI is not conne cted to AND gate

bit 3 ABEN: AND Gate A1 B Input Inverted Enable bit

1 = MBI is connected to AND gate

0 = MBI is not connected to AND gate

PIC24FJ16MC101/102

bit 2 ABNEN: AND Gate A1 B Input Inverted Enable bit

1 = Inverted MBI is connected to AND gate

0 = Inverted MBI is not connected to AND gate

bit 1 AAEN: AND Gate A1 A Input En able bit

1 = MAI is connected to AND gate

0 = MAI is not connected to AND gate

bit 0 AANEN: AND Gate A1 A Input Inverted Enable bit

1 = Inverted MAI is connected to AND gate

0 = Inverted MAI is not connected to AND gate

PIC24FJ16MC101/102

U-0 U-0 U-0 U-0 U-0 U-0 U-0 I-0

— — — — — — — —

bit 15 bit 8

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— CFSEL<2:0> CFLTREN CFDIV<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Uni mp lemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unkno wn

bit 15-7 Unimplemented: Read as ‘0’

bit 6-4 CFSEL<2:0>: Comparator Filter Input Clock Select bits

111 = Reserved

110 = Reserved

101 = T i mer3

100 = T i mer2

011 = Reserved

010 = PWM Special Event Trigger

001 = FOSC

000 = FCY

bit 3 CFLTREN: Comparator Filter Enable bit

1 = Digital filter enabled

0 = Digital filter disabled

bit 2-0 CFDIV<2:0>: Comparator Filter Clock Divide Select bits

111 = Clock Divide 1:128

110 = Clock Divide 1:64

101 = Clock Divide 1:32

100 = Clock Divide 1:16

011 = Clock Divide 1:8

010 = Clock Divide 1:4

001 = Clock Divide 1:2

000 = Clock Divide 1:1

PIC24FJ16MC101/102

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — VREFSEL BGSEL<1:0>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

CVREN CVROE(1) CVRR —CVR<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-11 Unimplemented: Read as ‘0’

bit 10 VREFSEL: Voltage Reference Select bit

1 = CVREFIN = CVREF pin

0 = CVREFIN is generated by the resistor network

bit 9-8 BGSEL<1:0>: Band Gap Reference Source Select bits

11 = INTREF = CVREF pin

10 = INTREF = 1.2V (nom in a l ) (2)

0x = Reserved

bit 7 CVREN: Comparator Voltage Reference Enable bit

1 = Comparator voltage reference circuit powered on

0 = Comparator voltage reference circuit powered down

bit 6 CVROE: Comparator Voltage Reference Output Enable bit(1)

1 = Voltage level is output on CVREF pin

0 = Voltage level is disconnected from CVREF pin

bit 5 CVRR: Comparator Voltage Reference Range Selection bit

1 = CVRSRC/24 step size

0 = CVRSRC/32 step size

bit 4 Unimplemented: Read as ‘0’

bit 3-0 CVR<3:0>: Comparator Voltage Reference Value Selection 0 ≤ CVR<3:0> ≤ 15 bits

When CVRR = 1:

CVREFIN = (CVR<3:0>/24) • (CVRSRC)

When CVRR = 0:

CVREFIN = 1/4 • (CVRSRC) + (CVR<3:0>/3 2) • (CVRSRC)

Note 1: CVROE overrides the TRIS bit setting.

2: This reference voltage is generated internally on the device. Refer to Section 26.0 “Electrical

Characteristics” for the speci fied voltage range.

PIC24FJ16MC101/102

NOTES:

PIC24FJ16MC101/102

21.0 REAL-TIME CLOCK AND

CALENDAR (RTCC)

This chapter discusses the Real-Time Clock and

Calendar (RTCC) module, which is available on

PIC24FJ16MC101/102 devices, and its operation.

Some of the key features of the RTCC module are:

• Time: hours, minutes, and seconds

• 24-hour format (military time)

• Calendar: weekday, date, month and ye ar

• Alarm configurable

• Year range: 2000 to 2099

• Leap year correction

• BCD format for compact firmware

• Optimized for low-power operation

• User calibration with auto-adjust

• Calibration range: ±2.64 seconds error per month

• Requirements: External 32.768 kHz clock crystal

• Alarm pulse or seconds clock output on RTCC pin

The RTCC module is intended for applications where

accurate time must be maintained for extended periods

of time with minimum to no intervention from the CPU.

The RTCC module is optimized for low-power usage to

provide extended battery lifetime while keeping track of

time.

The RTCC module is a 100-year clock and calendar

with automatic leap year detection. The range of the

clock is from 00:00:00 (midnight) on January 1, 2000 to

23:59:59 on December 31, 2099.

The hours are available in 24-hour (military time)

format. The clock provides a granularity of one second

with half-second visibility to the user.

FIGURE 21-1: RTCC BLOCK DIAGRAM

Note 1: This data sheet summarizes the features

of the PIC24FJ16MC101/102 family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 29. “Real-Time

Clock and Calendar (RTCC)”

(DS39696) in the “PIC24F Family

Reference Manual”, which is available on

the Microchip web site

(www.microchip.com).

2: It is important to note that the

specifications in Section 26.0 “Electri-

cal Characteristics” of this data sheet,

supercede any specifications that may be

provided in PIC24F Family Reference

Manual sections.

3: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

RTCC Prescalers

RTCC Timer

Comparator

Compare Registers

Repeat Counter

with Masks

RTCC Interrupt Logic

RCFGCAL

ALCFGRPT

Alarm

Event

32.768 kHz Input

from SOSC Oscillator

0.5s

RTCC Clock Domain

Alarm Pulse

RTCC Interrupt

CPU Clock Domain

RTCVAL

ALRMVAL

RTCC Pin

RTCOE

PIC24FJ16MC101/102

21.1 RTCC Module Registers

The RTCC module registers are organized into three

categories:

• RTCC Control Registers

• RTCC Value Registers

• Alarm Value Registers

21.1.1 REGISTER MAPPING

To limit the register interface, the RTCC Timer and

Alarm Time registers are accessed through

corresponding register pointers. The RTCC Value

RTCPTR bits (RCFGCAL<9:8>) to select the desired

timer register pair (see Table 21-1).

By writing the RTCVALH byte, the R TCC Pointer value,

RTCPTR<1:0> bits, decrement by one until they reach

‘00’. Once they reach ‘00’, the MINUTES and

SECONDS value will be accessible through RTCVALH

and RTCVALL until the pointer value is manually

changed.

TABLE 21-1: RTCVAL REGISTER MAPPING

The Alarm Value register window (ALRMVALH and

ALRMVALL) uses the ALRMPTR bits

(ALCFGRPT<9:8>) to select the desired Alarm register

pair (see Table 21-2).

By writing the ALRMVALH byte, the Alarm Pointer

value, ALRMPTR<1:0> bits, decrement by one until

they reach ‘00’. Once they reach ‘00’, the ALRMMIN

and ALRMSEC value will be accessible through

ALRMVALH and ALRMVALL until the pointer value is

manually changed.

TABLE 21-2: ALRMVAL REGISTER

MAPPING

Considering that the 16-bit core does not distinguish

between 8-bit and 16-bit read operations, the user must

be aware that when reading either the ALRMVALH or

ALRMVALL bytes will decrement the ALRMPTR<1:0>

value. The same applies to the RTCVALH or R TCV ALL

bytes with the RTCPTR<1:0> being decremented.

21.1.2 WRITE LOCK

In order to perform a write to any of the RTCC Timer

registers, the RTCWREN bit (RCFGCAL<13>) must be

set (refer to Example 21-1).

EXAMPLE 21-1: SETTING THE RTCWREN BIT

RTCPTR

<1:0>

RTCC Value Re gister Window

RTCVAL<15:8> RTCVAL<7:0>

00 MINUTES SECONDS

01 WEEKDAY HOURS

10 MONTH DAY

11 — YEAR

ALRMPTR

<1:0>

Alarm Value Register Window

ALRMVAL<15:8> ALRMVAL<7:0>

00 ALRMMIN ALRMSEC

01 ALRMWD ALRMHR

10 ALRMMNTH ALRMDAY

11 ——

Note: This only applies to read operations and

not write operations.

Note: To avoid accidental writes to the timer , it is

recommended that the RTCWREN bit

(RCFGCAL<13>) is kept clear at any

other time. For the RTCWREN bit to be

set, there is only 1 instruction cycle time

window allowed between the 55h/AA

sequence and the setting of RTCWREN;

therefore, it is recommended that code

follow the procedure in Example 21-1.

MOV #NVMKEY, W1 ;move the address of NVMKEY into W1

MOV #0x55, W2

MOV #0xAA, W3

MOV W2, [W1] ;start 55/AA sequence

MOV W3, [W1]

BSET RCFGCAL, #13 ;set the RTCWREN bit

PIC24FJ16MC101/102

(1)

R/W-0 U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0

RTCEN(2) — RTCWREN RTCSYNC HALFSEC(3) RTCOE RTCPTR<1:0>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CAL<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 RTCEN: RTCC Enable bit(2)

1 = RTCC module is enabled

0 = RTCC module is disabled

bit 14 Unimplemented: Read as ‘0’

bit 13 RTCWREN: RTCC Value Registers Write Enable bit

1 = RTCVALH and RTCVALL registers can be written to by the user

0 = RTCVALH and RTCVALL registers are locked out from being written to by the user

bit 12 RTCSYNC: RTCC Value Registers Read Synchronization bit

1 = RTCV ALH, R TCV ALL and ALCFGRPT registers can change while reading due to a rollover ripple

resulting in an invalid data read. If the register is read twice and results in the same data, the data

can be assumed to be valid.

0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple

bit 11 HALFSEC: Half-Second Status bit(3)

1 = Second half period of a second

0 = First half period of a second

bit 10 RTCOE: RTCC Output Enable bit

1 = RTCC output enabled

0 = RTCC output disabled

bit 9-8 RTCPTR<1:0>: RTCC Value Register Window Pointer bits

Points to the corresponding RTCC Value registers when reading RTCVALH and RT CVALL registers;

the RTCPTR<1:0> value decrements on every read or write of RTCVALH until it reaches ‘00’.

RTCVAL<15:8>:

00 = MINUTES

01 = WEEKDAY

10 = MONTH

11 = Reserved

RTCVAL<7:0>:

00 = SECONDS

01 = HOURS

10 = DAY

11 = YEAR

Note 1: The RCFGCAL register is only affected by a POR.

2: A write to the RTCEN bit is only allowed when RTCWREN = 1.

3: This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register.

PIC24FJ16MC101/102

bit 7-0 CAL<7:0>: RTC Drift Calibration bits

01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute

•

00000001 = Minimum positive adjustmen t; adds 4 RTC clock pulses every one minute

00000000 = No adjustment

11111111 = Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute

•

10000000 = Maximum negative adjustment; subtracts 512 RTC clock pulses every one minute

(1)

(CONTINUED)

Note 1: The RCFGCAL register is only affected by a POR.

2: A write to the RTCEN bit is only allowed when RTCWREN = 1.

3: This bit is read -o n ly. It is cleared to ‘0’ on a write to the lower half of the MINSEC register.

PIC24FJ16MC101/102

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0

— — — — — — RTSECSEL(1) —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimpleme nted bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-2 Unimplemented: Read as ‘0’

bit 1 RTSECSEL: RTCC Seconds Clock Output Select bit(1)

1 = RTCC seconds clock is selected for the RTCC pin

0 = RTCC alarm pulse is selected for the RTCC pin

bit 0 Unimplemented: Read as ‘0’

Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL) bit needs to be set.

PIC24FJ16MC101/102

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ALRMEN CHIME AMASK<3:0> ALRMPTR<1:0>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ARPT<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 ALRMEN: Alarm Enable bit

1 = Ala rm is enabled (cleared automatically after an alarm event wheneve r ARPT<7:0> = 0x00 and

CHIME = 0)

0 = Alarm is disabled

bit 14 CHIME: Chime Enable bit

1 = Chime is enabled; ARPT<7:0> bits are allowed to roll over from 0x00 to 0xFF

0 = Chime is disabled; ARPT<7:0> bits stop once they reach 0x00

bit 13-10 AMASK<3:0>: Alarm Mask Configuration bits

0000 = Every half second

0001 = Every second

0010 = Every 10 seconds

0011 = Every minute

0100 = Every 10 minutes

0101 = Every hour

0110 = Once a day

0111 = Once a week

1000 = Once a month

1001 = Once a year (except when configured for February 29th, once every 4 years)

101x = Reserved – do not use

11xx = Reserved – do not use

bit 9-8 ALRMPTR<1:0>: Alarm Value Register Window Pointer bits

Points to the correspondi ng Alarm Value register s when reading ALRMVALH and ALRMVALL registers;

the ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches ‘00’.

ALRMVAL<15:8>:

00 = ALRMMIN

01 = ALRMWD

10 = ALRMMNTH

11 = Unimplemented

ALRMVAL<7:0>:

00 = ALRMSEC

01 = ALRMHR

10 = ALRMDAY

11 = Unimplemented

bit 7-0 ARPT<7:0>: Alarm Repeat Counter Value bits

11111111 = Alarm will repeat 255 more times

•

00000000 = Alarm will not repeat

The counter decrements on any alarm event. The counter is prevented from rolling over from 0x00 to

0xFF unless CHIME = 1.

PIC24FJ16MC101/102

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

YRTEN<3:0> YRONE<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-8 Unimplemented: Read as ‘0’

bit 7-4 YRTEN<3:0>: Binary Coded Decimal Value of Year’s Tens Digit; contains a value from 0 to 9

bit 3-0 YRONE<3:0>: Binary Coded Decimal Value of Year’s Ones Digit; contains a value from 0 to 9

Note 1: A write to the YEAR register is only allowed when RTCWREN = 1.

U-0 U-0 U-0 R-x R-x R-x R-x R-x

— — —

MTHTEN0 MTHONE<3:0>

bit 15 bit 8

U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

— —

DAYTEN<1:0> DAYONE<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 Unimplemented: Read as ‘0’

bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit; contains a value of 0 or 1

bit 11-8 MTHONE<3:0>: Binary Coded Decimal V alue of Month’s Ones Digit; contains a value from 0 to 9

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit; contains a value from 0 to 3

bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit; contains a value from 0 to 9

Note 1: A write to this register is only allowed when RTCWREN = 1.

PIC24FJ16MC101/102

U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x

— — — — — WDAY<2:0>

bit 15 bit 8

U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

—— HRTEN<1:0> HRONE<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-11 Unimplemented: Read as ‘0’

bit 10-8 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit; contains a value from 0 to 6

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit; contains a value from 0 to 2

bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit; contains a value from 0 to 9

Note 1: A write to this register is only allowed when RTCWREN = 1.

U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

— MINTEN<2:0> MINONE<3:0>

bit 15 bit 8

U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

— SECTEN<2:0> SECONE<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit; contains a value from 0 to 5

bit 11-8 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit; contains a value from 0 to 9

bit 7 Unimplemented: Read as ‘0’

bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit; contains a value from 0 to 5

bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit; cont ains a value from 0 to 9

PIC24FJ16MC101/102

U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x

— — —

MTHTEN0 MTHONE<3:0>

bit 15 bit 8

U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

— —

DAYTEN<1:0> DAYONE<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 Unimplemented: Read as ‘0’

bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit; contains a value of 0 or 1

bit 11-8 MTHONE<3:0>: Binary Coded Decimal V alue of Month’s Ones Digit; contains a value from 0 to 9

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit; contains a value from 0 to 3

bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit; contains a value from 0 to 9

Note 1: A write to this register is only allowed when RTCWREN = 1.

VALUE REGISTER(1)

U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x

— — — — — WDAY2 WDAY1 WDAY0

bit 15 bit 8

U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

—— HRTEN<1:0> HRONE<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-11 Unimplemented: Read as ‘0’

bit 10-8 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit; contains a value from 0 to 6

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit; contains a value from 0 to 2

bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit; contains a value from 0 to 9

Note 1: A write to this register is only allowed when RTCWREN = 1.

PIC24FJ16MC101/102

VALUE REGISTER

U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

— MINTEN<2:0> MINONE<3:0>

bit 15 bit 8

U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

— SECTEN<2:0> SECONE<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit; contains a value from 0 to 5

bit 11-8 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit; contains a value from 0 to 9

bit 7 Unimplemented: Read as ‘0’

bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit; contains a value from 0 to 5

bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit; contains a value from 0 to 9

PIC24FJ16MC101/102

22.0 CHARGE TI ME

MEASUREMENT UNIT (CTMU) The Ch arge Time Measurement Unit is a flexible a na-

log module that provides accurate differential time

measurement between pulse sources, as well as

asynchronous pulse generation. Its key features

include:

• Four edge input trigger sources

• Polarity control for each edge source

• Control of edge sequence

• Control of response to edges

• Precise time measurement resolution of 200 ps

• Accurate current source suitable for capacitive

measurement

• On-chip temperature measurement using a

built-in diode

Together with other on-chip analog modules, the CTMU

can be used to precisely measure time, measure

capacitance, measure relative changes in capacitance

or generate output pulses that are indepe ndent of the

system clock.

The CTMU module is ideal for interfacing with capaci-

tive-based sensors.The CTMU is controlled through

three registers: CTMUCON1, CTMUCON2 and

CTMUICON. CTMUCON1 enables the module, the

Edge delay generation, sequ encin g of e dges and con-

trols the current source and the output trigger.

CTMUCON2 controls the edge source selection, ed ge

source polarity selection and edge sampling mode. The

CTMUICON register controls the selection and trim of

the current source.

Figure 22-1 shows the CTMU blo c k diagram.

Note 1: This data sheet summarizes the fea-

tures of the PIC24FJ16MC101/102 fam-

ily of devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 11. “Charge

Time Measurement Unit (CTMU)”

(DS39724) in the “PIC24F Family

Reference Manual”, which is available

from the Microchip web site

(www.microchip.com).

2: It is important to note that the

specifications in Section 26.0 “Electri-

cal Characteristics” of this data sheet,

supercede any specifications that may be

provided in PIC24F Family Reference

Manual sections.

3: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

PIC24FJ16MC101/102

FIGURE 22-1: CTMU BLOCK DIAGRAM

CTED1

CTED2

Current Source

Edge

Control

Logic

CTMUCON1 or CTMUCON2

Pulse

Generator

CTMUI to ADC

Comparat or 2

Timer1

OC1

Current

Control

ITRIM<5:0>

IRNG<1:0>

CTMUICON

CTMU

Control

Logic

EDG1STAT

EDG2STAT

Analog-to-Digital

CTPLS

IC1

CMP2

C2INA

CDelay

CTMU TEMP

CTMU

Temperature

Sensor

Current Control Selection TGEN EDG1STAT, EDG2STAT

CTMU TEMP 0EDG1STAT = EDG2STAT

CTMUI 0EDG1STAT ≠ EDG2STAT

CTMUP 1EDG1STAT ≠ EDG2STAT

No Connect 1EDG1STAT = EDG2STAT

Trigger

TGEN

CTMUP

External capacitor

for pulse generation

PIC24FJ16MC101/102

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CTMUEN — CTMUSIDL TGEN(1) EDGEN EDGSEQEN IDISSEN(2) CTTRIG

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemente d bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 CTMUEN: CTMU Enab le bit

1 = Module is enabled

0 = Module is disabled

bit 14 Unimplemented: Read as ‘0’

bit 13 CTMUSIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Id le mode

0 = Continue module operation in Id le mode

bit 12 TGEN: Time Generation Enable bit(1)

1 = Enables edge delay generation

0 = Disables edge delay generation

bit 11 EDGEN: Edge Enable bit

1 = Edges are not blocked

0 = Edges are blocked

bit 10 EDGSEQEN: Edge Sequence Enable bit

1 = Edge 1 event must occur before Edge 2 event can occur

0 = No edge sequence is needed

bit 9 IDISSEN: Analog Current Source Control bit(2)

1 = Analog cur rent source outp u t is grounded

0 = Analog current source output is not grounded

bit 8 CTTRIG: Trigger Control bit

1 = Trigger output is enabled

0 = Trigger output is disabled

bit 7-0 Unimplemented: Read as ‘0’

Note 1: If TGEN = 1, the peripheral inputs and outp uts must be configured to an available RPn pin. For more

information, see Section 10.4 “Peripheral Pin Select”.

2: The ADC module Sample & Hold capacitor is not automatically discharged between sample/conversion

cycles. Software using the ADC as p art of a capacit ance measurement, must discharge the ADC cap acitor

before conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this function. The ADC

must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor array.

PIC24FJ16MC101/102

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

EDG1MOD EDG1POL EDG1SEL<3:0> EDG2STAT EDG1STAT

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0

EDG2MOD EDG2POL EDG2SEL<3:0> — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 EDG1MOD: Edge 1 Edge Sampl ing Selection bit

1 = Edge 1 is edge sensitive

0 = Edge 1 is level sensitive

bit 14 EDG1POL: Edge 1 Polarity Select bit

1 = Edge 1 programmed for a positive edge response

0 = Edge 1 programmed for a negative edge response

bit 13-10 EDG1SEL<3:0>: Edge 1 Source Select bi ts

1xxx = Reserved

01xx = Reserved

0011 = CTED1 pin

0010 = CTED2 pin

0001 = OC1 module

0000 = Timer1 module

bit 9 EDG2STAT: Edge 2 Status bit

Indicates the status of Edge 2 and can be written to control the edge source.

1 = Edge 2 has occurred

0 = Edge 2 has not occurred

bit 8 EDG1STAT: Edge 1 Status bit

Indicates the status of Edge 1 and can be written to control the edge source.

1 = Edge 1 has occurred

0 = Edge 1 has not occurred

bit 7 EDG2MOD: Edge 2 Edge Sampling Selection bit

1 = Edge 2 is edge sensitive

0 = Edge 2 is level sensitive

bit 6 EDG2POL: Edge 2 Polarity Select bit

1 = Edge 2 programmed for a positive edge response

0 = Edge 2 programmed for a negative edge response

bit 5-2 EDG2SEL<3:0>: Edge 2 Source Select bits

1xxx = Reserved

01xx = Reserved

0011 = CTED2 pin

0010 = CTED1 pin

0001 = Comparator 2 module

0000 = IC1 module

bit 1-0 Unimplemented: Read as ‘0’

PIC24FJ16MC101/102

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ITRIM<5:0> IRNG<1:0>

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemente d bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-10 ITRIM<5:0>: Current Source Trim bits

011111 = Nominal current output specified by IRNG<1:0> + 62%

011110 = Nominal current output specified by IRNG<1:0> + 60%

•

000001 = Nominal current output specified by IRNG<1:0> + 2%

000000 = Nominal current output specified by IRNG<1:0>

111111 = Nominal current output specified by IRNG<1:0> – 2%

•

100010 = Nominal current output specified by IRNG<1:0> – 62%

100001 = Nominal current output specified by IRNG<1:0> – 64%

bit 9-8 IRNG<1:0>: Current Source Range Select bits

11 = 100 × Base Current(1)

10 = 10 × Base Current

01 = Base current level (0.55 μA nominal)

00 = Reserved

bit 7-0 Unimplemented: Read as ‘0’

Note 1: This setting must be used for the CTMU temperature sensor.

PIC24FJ16MC101/102

NOTES:

PIC24FJ16MC101/102

23.0 SPECIAL FEATURES

PIC24FJ16MC101/102 devices include several

features intended to maximize application flexibility and

reliability, and minimize cost through elimination of

external components. These are:

• Flexible configuration

• Watchdog T imer (WDT)

• Code Protection

• In-Circuit Serial Programming™ (ICSP™)

• In-Circuit emulation

23.1 Configuration Bits

The Configuration Shad ow register bits can be co nfig-

ured (read as ‘0’), or left unprogramme d (read as ‘1’),

to select various device configurations. These read-

only bits are mapped starting at program memory loca-

tion 0xF80000. A detailed explanation of the various bit

functions is provided in Table 23-3.

Note that address 0xF80000 is beyond the user pro-

gram memory space and belongs to the configuration

memory space (0x800000-0xFFFFFF) whi ch can only

be accessed using table reads.

In PIC24FJ16MC101/102 devices, the configuration

bytes are implemented as volatile memory. This means

that configuration data must be programmed each time

the device is powered up. Configuration data is stored in

the two words at the top of the on-chip program memory

space, known as the Flash Configuration Words. Their

specific locations are shown in Table 23-2. These are

packed representations of the actual device Configura-

tion bits, whose actual locations are distributed among

several locations in configuration space. The configura-

tion data is automatically loaded from the Flash Config-

uration Words to the proper Configuration registers

during device Resets.

When creating applications for these devices, users

should always specifically allocate the location of the

Flash Configuration Word for configuration data. This is

to make certain that program code is not stored in this

address when the code is compiled.

The upper byte of all Flash Configuration Words in pro-

gram memory should always be ‘1111 1111’. This

makes them appear to be NOP instructions in the

remote event that their locations are ever executed by

accident. Since Configuration bits are not implemented

in the corresponding locations, writing ‘1’s to these

locations has no effect on device operation.

Note 1: This data sheet summarizes the features

of the PIC24FJ16MC101/102 devices. It

is not intended to be a comprehensive

reference source. To complement the

information in this data sheet, refer to

Section 9. “Watchdog Timer (WDT)”

(DS39697) and Section 33. “Program-

ming and Diagnostics” (DS39716) in

the “PIC24F Family Reference Manual”,

which are available from the Microchip

web site (www.microchip.com).

2: It is important to note that the

specifications in Section 26.0 “Electri-

cal Characteristics” of this data sheet,

supercede any specifications that may be

provided in PIC24F Family Reference

Manual sections.

3: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information. Note: Configuration data is reloaded on all types

of device Resets.

Note: Performing a page erase operation on the

last page of program memory clears the

Flash Configuration Words, enabling code

protection as a result. Therefore, users

should avoid performing page erase

operations on the last page of program

memory.

PIC24FJ16MC101/102

The Configuration Shadow register map is shown in Table 23-1.

TABLE 23-1: CONFIGURATION SHADOW REGISTER MAP

The Configuration Flash Words map is shown in Table 23-2.

TABLE 23-2: CONFIGURATION FLASH WORDS

File Name Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

FGS F80004 — — — — — —GCPGWRP

FOSCSEL F80006 IESO PWMLOCK — WDTWIN<1:0> FNOSC<2:0>

FOSC F80008 FCKSM<1:0> IOL1WAY —— OSCIOFNC POSCMD<1:0>

FWDT F8000A FWDTEN WINDIS PLLKEN WDTPRE WDTPOST<3:0>

FPOR F8000C PWMPIN HPOL LPOL ALTI2C1 — — — —

FICD F8000E Reserved(1) — Reserved(2) Reserved(2) ——ICS<1:0>

Legend: — = unimplemented, read as ‘1’.

Note 1: This bit is reserved for use by development tools and must be programmed as ‘1’.

2: This bit is reserved; program as ‘0’.

File

Name Addr. Bits 23-16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CONFIG2 002BFC — IESO PWMLOCK PWMPIN WDTWIN<1:0> FNOSC<2:0> FCKSM<1:0> OSCIOFNC IOL1WAY LPOL ALTI2C1 POSCMD<1:0>

CONFIG1 002BFE — Reserved(2) Reserved(2) GCP GWRP Reserved(3) HPOL ICS<1:0> FWDTEN WINDIS PLLKEN WDTPRE WDTPOST<3:0>

Legend: — = unimplemented, read as ‘1’.

Note 1: During a Power-on Reset (POR), the contents of these Flash locations are transferred to the Configuration Shadow regist ers.

2: This bit is reserved; program as ‘0’.

3: This bit is reserved for use by developme nt tools and must be programmed as ‘1’.

PIC24FJ16MC101/102

TABLE 23-3: PIC24F CONFIGURATION BITS DESCRIPTION

Bit Field RTSP Effect Description

GCP Immediate General Segment C od e -Pro te c t bi t

1 = User program memory is not code-protected

0 = Code protection is enabled for the entire program memo ry space

GWRP Imme diate General Segment Write-Protect bit

1 = User program memory is not write-protected

0 = User program memory is write-protected

IESO Immediate Two-speed Oscillator Start-up Enable bit

1 = Start-up device with FRC, then automati cally switch to the

user-selected oscillator source when ready

0 = Start-up device with user-selected oscillato r sour ce

PWMLOCK Immediate PWM Lock Enable bit

1 = Certain PWM registers may only be written after key sequence

0 = PWM registers may be written without key

WDTWIN<1:0> Immediate Watchdog Window Select bits

11 = WDT Window is 25% of WDT period

10 = WDT Window is 37.5% of WDT period

01 = WDT Window is 50% of WDT period

00 = WDT Window is 75% of WDT period

FNOSC<2:0> Immediate Oscillator Selection bits

111 = Fast RC Oscillator with divide-by-N (FRCD IVN)

110 = Reserved; do not use

101 = Low-Power RC Oscillator (LPRC)

100 = Secondary Oscillator (Sosc)

011 = Primary Oscillator with PLL module (MS + PLL, EC + PLL)

010 = Primary Oscillator (MS, HS, EC)

001 = Fast RC Oscillator with divide-by-N with PLL modu le (FRCDIVN + PLL)

000 = Fast RC Oscillator (FRC)

FCKSM<1:0> If clock switch is

enabled, RTSP

effect is on any

device Reset;

otherwise,

Immediate

Clock Switching Mode bits

1x = Clock switching is disabled, Fail-Safe Clock Monitor is disab led

01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled

00 = Clock switching is enabled , Fa il-Safe Clock Monitor is enabled

IOL1WAY Immediate Peripheral pin select configuration

1 = Allow only one reconfiguration

0 = Allow multiple reconfigurations

OSCIOFNC Imme diate OSC2 Pin Function bit (except in MS and HS modes)

1 = OSC2 is clock output

0 = OSC2 is general purpose digital I/O pin

POSCMD<1:0> Immediate Primary Oscillator Mode Select bits

11 = Primary oscillator disabled

10 = HS Crystal Oscillator mode (10 MHz - 32 MHz)

01 = MS Crystal Oscillator mode (3 MHz - 10 MHz)

00 = EC (External Clock) mode (DC - 32 MHz)

FWDTEN Imme diate Watchdog Timer Enable bit

1 = Watchdog Timer always enabled (LPRC oscillator cannot be disabled.

Clearing the SWDTEN bit in the RCON register will have no effect.)

0 = W atchdog T imer enabled/disabled by user software (LPRC can be disabled

by clearing the SWDTEN bit in the RCON register)

WINDIS Immediate Watchdog Timer Wi ndow Enable bit

1 = Watchdog Timer in Non-Window mode

0 = Watchdog Timer in Window mode

PIC24FJ16MC101/102

WDTPRE Immediate Watchdog Timer Prescaler bit

1 = 1:128

0 = 1:32

WDTPOST<3:0> Immediate Watchdog Timer Postscaler bits

1111 = 1:32,768

1110 = 1:16,384

•

0001 = 1:2

0000 = 1:1

PLLKEN Immediate PLL Lock Enabl e bit

1 = Clock switch to PLL will wait until the PLL lock signal is valid

0 = Clock switch will not wait for the PLL lock signal

ALTI2C Immediate Alternate I2C pins

1 = I2C™ mapped to SDA1/SCL1 pins

0 = I2C mapped to ASDA1/ASCL1 pins

ICS<1:0> Immediate ICD Communication Channel Select bits

11 = Communicate on PGEC1 and PGED1

10 = Communicate on PGEC2 and PGED2

01 = Communicate on PGEC3 and PGED3

00 = Reserved, do not use

PWMPIN Immediate Motor Control PWM Module Pin Mode bit

1 = PWM module pins controlled by PORT register at device Reset (tri-stated)

0 = PWM module pins controlled by PW M module at device Re set (config ured

as output pins)

HPOL Immediate Motor Control PW M High Side Polarity bit

1 = PWM module high side output pi ns have active-high output polarity

0 = PWM module high side output pins have active-low output polarity

LPOL Immediate Motor Control PWM Low Side Polarity bit

1 = PWM module low side output pins have active-high output polarity

0 = PWM module low side output pins have active-low output polarity

TABLE 23-3: PIC24F CONFIGURATION BITS DESCRIPTION (CONTINUED)

Bit Field RTSP Effect Description

PIC24FJ16MC101/102

RRRRRRRR

DEVID<23:16>

bit 23 bit 16

RRRRRRRR

DEVID<15:8>

bit 15 bit 8

RRRRRRRR

DEVID<7:0>

bit 7 bit 0

Legend: R = Read-Only bit U = Unimplemented bit

bit 23-0 DEIDV<23:0>: Device Identifier bits

Note 1: Refer to the “PIC24FJXXMC Family Flash Programming Specification” (DS70512) for the list of device ID

values.

RRRRRRRR

DEVREV<23:16>

bit 23 bit 16

RRRRRRRR

DEVREV<15:8>

bit 15 bit 8

RRRRRRRR

DEVREV<7:0>

bit 7 bit 0

Legend: R = Read-only bit U = Unimplemented bit

bit 23-0 DEVREV<23:0>: Device Revision bits(1)

Note 1: Refer to the “PIC24FJXXMC Family Flash Programming Specification” (DS75012) for the list of device

revision values.

PIC24FJ16MC101/102

23.2 On-Chip Voltage Regulator

All of the PIC24FJ16MC101/102 devices power their

core digital logic at a nominal 2.5V. This can create a

conflict for designs that are required to operate at a

higher typical voltage, such as 3.3V. To simplify system

design, all devices in the PIC24FJ16MC101/102 family

incorporate an on-chip regulator that allows the device

to run its core logic from VDD.

The regulator provides power to the core from the other

VDD pins. When the regulator is enabled, a low-ESR

(less than 5 ohms) capacitor (such as tantalum or

ceramic) must be connected to the VCAP pin

(Figure 23-1). This helps to maintain the stability of the

regulator. The recommended value for the filter capac-

itor is provided in Table 26-13 located in Section 26.0

“Electrical Characteristics”.

On a POR, it takes approximately 20 μs for the on-chip

voltage regulator to generate an output voltage. During

this time, designated as TSTARTUP, code execution is

disabled. TSTARTUP is applied every time the device

resumes operation after any power-down.

FIGURE 23-1: CONNECTIONS FOR THE

ON-CHIP VOLTAGE

REGULATOR(1,2,3)

23.3 BOR: Brown-out Reset

The Brown-out Reset (BOR) module is based on an

internal voltage reference circuit that monitors the reg-

ulated supply voltage VCAP. The main purpose of the

BOR module is to generate a device Reset when a

brown-out condition occurs. Brown-out conditions are

generally caused by glitches on the AC mains (for

example, missing portions of the AC cycle waveform

due to bad power transmission lines, or voltage sags

due to excessive current draw when a large inductive

load is turned on).

A BOR generates a Reset pulse, which resets the

device. The BOR selects the clock source, based on

the device Configuration bit values (FNOSC< 2:0> and

POSCMD<1:0>).

If an oscillator mode is selected, the BOR activates the

Oscillator Start-up Timer (OST). The system clock is

held until OST expires. If the PLL is u sed, the clock is

held until the LOCK bit (OSCCON<5>) is ‘1’.

Concurrently, the PWRT time-out (TPWRT) is applied

before the internal Reset is released. If TPWRT = 0 and

a crystal oscillator is being used, then a nominal delay

of TFSCM = 100 is applied. The total delay in this case

is TFSCM.

The BOR S tatus bit (RCON<1>) is set to indicate that a

BOR has occurred. The BOR circuit continues to oper-

ate while in Sleep or Idle mo des and rese ts the device

should VDD fall below the BOR threshold voltage.

Note: It is important for low-ESR capacitors to

be placed as close as possible to the VCAP

pin.

Note 1: These are typical operating voltage s. Ref er to

TABLE 26-13: “Internal Voltage Regulator

Specifications” located in Section 26.0 “Elec-

trical Characteristics” for the full op erating

ranges of VDD and VCAP.

2: It is important for low-ESR capacitors to be

placed as close as possible to the VCAP pin.

3: Typical VCAP pin voltage = 2.5V when VDD ≥

VDDMIN.

VDD

VCAP

VSS

PIC24F

CEFC

3.3V

10 µF

Tantalum

PIC24FJ16MC101/102

23.4 Watchdog Timer (WDT)

For PIC24FJ16MC101/102 devices, the WDT is driven

by the LPRC oscillator. When the WDT is enable d, the

clock source is also enabled.

23.4.1 PRESCALER/POSTSCALER

The nominal WDT cl ock source from LPRC is 32 kHz.

This feeds a prescaler than can be configured for either

5-bit (divide-by-32) or 7-bit (divide-by-128) operation.

The prescaler is set by the WDTPRE Configuration bit.

With a 32 kHz input, the prescaler yields a nominal

WDT time-out period (TWDT) of 1 ms in 5-bit mode, or

4 ms in 7-bit mode.

A variable postscaler divides down the WDT prescaler

output and allows for a wide range of time-out periods.

The postscaler is controlled by the WDTPOST<3:0>

Configuration bits (FWDT<3:0>), which allow the selec-

tion of 16 settings, from 1:1 to 1:32,768. Using the pres-

caler and postscaler, time-out periods ranging from

1 ms to 131 seconds can be achieved.

The WDT, prescaler, and postscaler are reset:

• On any device Reset

• On the completion of a clock switch, whether

invoked by software (i.e., setting the OSWEN bit

after changing the NOSC bits) or by hardware

(i.e., Fail-Safe Clock Monitor)

• When a PWRSAV instruction is executed

(i.e., Sleep or Idle mode is entered)

• When the device exits Sleep or Idle mode to

resume normal operation

•By a CLRWDT instruction during normal execution

23.4.2 SLEEP AND IDLE MODES

If the WDT is en abled, i t will conti nue to run during Sleep

or Idle modes. When the WDT time-out occurs, the

device will wake the device and code execution will

continue from where the PWRSAV instruction was

executed. The corresponding SLEEP or IDLE bits

(RCON<3> and RCON<2>, res pectiv ely) will need to b e

cleared in software after the device wakes up.

23.4.3 ENABLING WDT

The WDT is enabled or disabled by the FWDTEN

Configuration bit in the FWDT Configuration register.

When the FWDTEN Configuration bit is set, the WDT is

always enabled.

The WDT can be optionally controlled in software when

the FWDTEN Configuration bit has been programmed

to ‘0’. The WDT is enabled in software by setting the

SWDTEN control bit (RCON<5>). The SWDTEN con-

trol bit is cleared on any device Reset. The software

WDT option allows the user application to enable the

WDT for critical code segments and disable the WDT

during non-critical segments for maximum power

savings.

The WDT flag bit, WDTO (RCON<4>), is not automatically

cleared following a WDT time-out. To detect subsequent

WDT events, the flag must be cleared in software.

FIGURE 23-2: WDT BLOCK DIAGRAM

Note: The CLRWDT and PWRSAV instructions

clear the prescaler and postscaler counts

when executed.

Note: If the WINDIS bit (FWDT<6>) is cleared,

the CLRWDT instruction should be executed

by the application software only during the

last 1/4 of the WDT period. This CLRWDT

window can be determined by using a timer .

If a CLRWDT instruction is executed before

this window, a WDT Reset occurs.

All Device Resets

Transition to New Clock Source

Exit Sleep or Idle Mode

PWRSAV Instruction

CLRWDT Instruction

WDTPRE WDTPOST<3:0>

Watchdog Timer

Prescaler

(divide by N1) Postscaler

(divide by N2)

Sleep/Idle

WDT

WDT Window Select

WINDIS

WDT

CLRWDT Instruction

SWDTEN

FWDTEN

LPRC Clock

RS RS

Wake-up

Reset

PIC24FJ16MC101/102

23.5 In-Circuit Serial Programming

The PIC24FJ16MC101/102 devices can be serially

programmed while in the end application circuit. This

is done with two lines for clock and data and three

other lines for power, ground and the programming

sequence. Serial programming allows customers to

manufacture boards with unprogrammed devices and

then program the microcontroller just before ship-

ping the product. Serial programming also allows the

most recent firmware or a custom firmware to be

programmed. Refer to the “PIC24FJXXMC Family

Flash Programming Specification” (DS70512) for

details about In-Circuit Serial Progra mming (ICSP).

Any of the three pairs of programming clock/data pins

can be used:

• PGEC1 and PGED1

• PGEC2 and PGED2

• PGEC3 and PGED3

23.6 In-Circuit Debugger

When MPLAB® ICD 2 is selected as a debugger , the in-

circuit debugging functionality is enabled. This function

allows simple debugging functions when used with

MPLAB IDE. Debugging functionality is controlled

through the PGECx (Emulation/Debug Clock) and

PGEDx (Emulation/Debug Data) pin functions.

Any of the three pairs of debugging clock/data pins can

be used:

• PGEC1 and PGED1

• PGEC2 and PGED2

• PGEC3 and PGED3

To use the in-circuit debugger function of the device,

the design must implement ICSP connections to

MCLR, VDD, VSS, and the PGECx/PGEDx pin pair. In

addition, when the feature is enabled, some of the

resources are not available for general use. These

resources include the first 80 bytes of data RAM and

two I/O pins.

PIC24FJ16MC101/102

24.0 INSTRUCTION SET SUMMARY

The PIC24F instruction se t adds many enhancements

to the previo us PIC® MCU instruction sets, while main-

taining an easy migration from previous PIC MCU

instruction sets.

Most instructions are a single program memory word

(24 bits). Only three instructions require two program

memory locations.

Each single-word instruction is a 24-bit word, divided

into an 8-bit opcode, which specifies the instruction

type and one or more operands, which further specify

the operation of the instruction.

The instruction set is highly ortho gonal an d is gr ouped

into five basic categories:

• Word or byte-oriented operations

• Bit-oriented operations

• Literal operations

• Control operations

Table 24-1 shows the general symbols used in

describing the instructions.

The PIC24FXXXX instruction set summary in Table 24-

2 lists all the instructions, along with the status flags

affected by each instruction.

Most word or byte-oriented W register instructions

(including barrel shift instructions) have three

operands:

• The first source operand, which is typically a

• The second source operand, which is typically a

• The destination of the result, which is typically a

However , word or byte-oriented file register instructions

have two operands:

• The file register specified by the value ‘f’

• The destination, which could be either the file

‘WREG’

Most bit-oriented instructions (including simple rotate/

shift instructions) have two operands:

• The W register (with or without an address

modifier) or file register (specified by the value of

‘Ws’ or ‘f’)

• The bit in the W register or file register (specified

by a literal value or indirectly by the contents of

The literal instructions that involve data movement can

use some of the following operands:

• A literal value to be loaded into a W register or file

• The W register or file register where the literal

value is to be loaded (specified by ‘Wb’ or ‘f’)

However, literal instructions that involve arithmetic or

logical operations use some of the following operands:

• The first source operand, which is a register ‘Wb’

without any address modifier

• The second source operand, which is a literal

value

• The destination of the result (only if not the same

as the first source operand), which is typically a

The control instructions can use some of the following

operands:

• A program memory address

• The mode of the table read and table write

instructions

Note 1: This data sheet sum marizes the features

of the PIC24FJ16MC101/102 devices.

However, it i s not intended to be a co m-

prehensive reference source. To comple-

ment the information in this data sheet,

refer to the latest family reference sec-

tions of the “PIC24F Family Reference

Manual”, which are available from the

Microchip web site (www.microchip.com).

2: It is important to note that the

specifications in Section 26.0 “Electri-

cal Characteristics” of this data sheet,

supercede any specifications that may be

provided in PIC24F Family Reference

Manual sections.

PIC24FJ16MC101/102

Most instructions are a single word. Certain double-

word instructions are designed to provide all the

required information in these 48 bits. In the second

word, the 8 MSbs are ‘0’s. If this second word is exe-

cuted as an instruction (by itself), it will execute as a

NOP.

The double-word instructions execute in two instruction

cycles.

Most single-word instructions are executed in a single

instruction cycle, unless a conditional test is true, or the

program counter is changed as a result of the instruc-

tion. In these cases, the execution takes two instruction

cycles with the additional instruction cycle(s) executed

as a NOP. Notable exceptions are the BRA (uncondi-

tional/computed branch), indirect CALL/GOTO, all table

reads and writes and RETURN/RETFIE instructions,

which are single-word instructions but take two or three

cycles. Certain instructions that involve skipping over the

subsequent instruction require either two or three cycles

if the skip is performed, depending on whether the

instruction being skipped is a single-word or two-word

instruction. Moreover, double-word moves require two

cycles.

Note: For more details on the instruction set,

refer to the “16-bit MCU and DSC Pro-

grammer’s Reference Manual (DS70157).

TABLE 24-1: SYMBOLS USED IN OPCODE DESCRIPTIONS

Field Description

#text Means literal defined by “text”

(text) Means “content of text”

[text] Means “the location addressed by text”

{ } Optional field or operation

<n:m> Register bit field

.b Byte mode selection

.d Double-Word mode selection

.S Shadow register select

.w Word mode selection (default)

Acc One of two accumulators {A, B}

AWB Accumulator write back destination address register ∈ {W13, [W13]+ = 2}

bit4 4-bit bit selection field (used in word addressed instructions) ∈ {0...15}

C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero

Expr Absolute address, label or expression (resolved by the linker)

f File register address ∈ {0x0000...0x1FFF}

lit1 1-bit unsigned literal ∈ {0,1}

lit4 4-bit unsigned literal ∈ {0...15}

lit5 5-bit unsigned literal ∈ {0...31}

lit8 8-bit unsigned literal ∈ {0...255}

lit10 10-bit unsigned literal ∈ {0...255} for Byte mode, {0:1023} for Word mode

lit14 14-bit unsigned literal ∈ {0...16384}

lit16 16-bit unsigned literal ∈ {0...65535}

lit23 23-bit unsigned literal ∈ {0...8388608}; LSb must be ‘0’

None Field does not require an entry, can be blank

OA, OB, SA, SB DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate

PC Program Counter

Slit10 10-bit signed literal ∈ {-512...511}

Slit16 16-bit signed literal ∈ {-32768...32767}

Slit6 6-bit signed literal ∈ {-16...16}

Wb Base W register ∈ {W0..W15}

Wd Destination W register ∈ {Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd]}

Wdo Destination W register ∈

{Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb]}

Wm,Wn Dividend, Divisor working register pair (direct addressing)

PIC24FJ16MC101/102

Wm*Wm Multiplicand and Multiplier working register pair for Square instructions ∈

{W4 * W4,W5 * W5,W6 * W6,W7 * W7}

Wn One of 16 working registers ∈ {W0..W15}

Wnd One of 16 destination working registers ∈ {W0...W15}

Wns One of 16 source working registers ∈ {W0...W15}

WREG W0 (working register used in file register instructions)

Ws Source W register ∈ {Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws]}

Wso Source W register ∈

{Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb]}

TABLE 24-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)

Field Description

PIC24FJ16MC101/102

TABLE 24-2: INSTRUCTION SET OVERVIEW

Assembly

Mnemonic Assembly Syntax Description # of

Words # of

Cycles Status Flags

Affected

ADD ADD Acc Add Accumulators 1 1 OA,OB,SA,SB

ADD f f = f + WREG 1 1 C,DC,N,OV,Z

ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z

ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z

ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z

ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z

ADD Wso,#Slit4,Acc 16-bit Signed Add to Accumulator 1 1 OA,OB,SA,SB

ADDC ADDC f f = f + WREG + (C) 1 1 C,DC,N,OV,Z

ADDC f,WREG WREG = f + WREG + (C) 1 1 C,DC,N,OV,Z

ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C,DC,N,OV,Z

ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C,DC,N,OV,Z

ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C,DC,N,OV,Z

AND AND f f = f .AND. WREG 1 1 N,Z

AND f,WREG WREG = f .AND. WREG 1 1 N,Z

AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N,Z

AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N,Z

AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N,Z

ASR ASR f f = Arithmetic Right Shift f 1 1 C,N,OV,Z

ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C,N,OV,Z

ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C,N,OV,Z

ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N,Z

ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N,Z

BCLR BCLR f,#bit4 Bit Clear f 1 1 None

BCLR Ws,#bit4 Bit Clear Ws 1 1 None

BRA BRA C,Expr Branch if Carry 1 1 (2) None

BRA GE,Expr Branch if greater than or equal 1 1 (2) None

BRA GEU,Expr Branch if unsigned greater than or equal 1 1 (2) None

BRA GT,Expr Branch if greater than 1 1 (2) None

BRA GTU,Expr Branch if unsigned greater than 1 1 (2) None

BRA LE,Expr Branch if less than or equal 1 1 (2) None

BRA LEU,Expr Branch if unsigned less than or equal 1 1 (2) None

BRA LT,Expr Branch if less than 1 1 (2) None

BRA LTU,Expr Branch if unsigned less than 1 1 (2) None

BRA N,Expr Branch if Negative 1 1 (2) None

BRA NC,Expr Branch if Not Carry 1 1 (2) None

BRA NN,Expr Branch if Not Negative 1 1 (2) None

BRA NOV,Expr Branch if Not Overflow 1 1 (2) None

BRA NZ,Expr Branch if Not Zero 1 1 (2) None

BRA OA,Expr Branch if Accumulator A overflow 1 1 (2) None

BRA OB,Expr Branch if Accumulator B overflow 1 1 (2) None

BRA OV,Expr Branch if Overflow 1 1 (2) None

BRA SA,Expr Branch if Accumulator A saturated 1 1 (2) None

BRA SB,Expr Branch if Accumulator B saturated 1 1 (2) None

BRA Expr Branch Unconditionally 1 2 None

BRA Z,Expr Branch if Zero 1 1 (2) None

BRA Wn Computed Branch 1 2 None

BSET BSET f,#bit4 Bit Set f 1 1 None

BSET Ws,#bit4 Bit Set Ws 1 1 None

BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None

BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None

PIC24FJ16MC101/102

BTG BTG f,#bit4 Bit Toggle f 1 1 None

BTG Ws,#bit4 Bit Toggle Ws 1 1 None

BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1

(2 or 3) None

BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1

(2 or 3) None

BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1

(2 or 3) None

BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1

(2 or 3) None

BTST BTST f,#bit4 Bit Test f 1 1 Z

BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C

BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z

BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C

BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z

BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z

BTSTS.

CWs,#bit4 Bit Test Ws to C, then Set 1 1 C

BTSTS.

ZWs,#bit4 Bit Test Ws to Z, then Set 1 1 Z

CALL CALL lit23 Call subroutine 2 2 None

CALL Wn Call indirect subroutine 1 2 None

CLR CLR f f = 0x0000 1 1 None

CLR WREG WREG = 0x0000 1 1 None

CLR Ws Ws = 0x0000 1 1 None

CLR Acc,Wx,Wxd,Wy,Wyd,AWB Clear Accumulator 1 1 OA,OB,SA,SB

CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO,Sleep

COM COM f f = f 11 N,Z

COM f,WREG WREG = f 11 N,Z

COM Ws,Wd Wd = Ws 11 N,Z

CP CP f Compare f with WREG 1 1 C,DC,N,OV,Z

CP Wb,#lit5 Compare Wb with lit5 1 1 C,DC,N,OV,Z

CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C,DC,N,OV,Z

CP0 CP0 f Compare f with 0x0000 1 1 C,DC,N,OV,Z

CP0 Ws Compare Ws with 0x0000 1 1 C,DC,N,OV,Z

CPB CPB f Compare f with WREG, with Borrow 1 1 C,DC,N,OV,Z

CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C,DC,N,OV,Z

CPB Wb,Ws Compare Wb with Ws, with Borrow

(Wb – Ws – C)1 1 C,DC,N,OV,Z

CPSEQ CPSEQ Wb, Wn Compare Wb with Wn, skip if = 1 1

(2 or 3) None

CPSGT CPSGT Wb, Wn Compare Wb with Wn, skip if > 1 1

(2 or 3) None

CPSLT CPSLT Wb, Wn Compare Wb with Wn, skip if < 1 1

(2 or 3) None

CPSNE CPSNE Wb, Wn Compare Wb with Wn, skip if ≠11

(2 or 3) None

DAW DAW Wn Wn = decimal adjust Wn 1 1 C

DEC DEC f f = f – 1 1 1 C,DC,N,OV,Z

DEC f,WREG WREG = f – 1 1 1 C,DC,N,OV,Z

DEC Ws,Wd Wd = Ws – 1 1 1 C,DC,N,OV,Z

TABLE 24-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Assembly

Mnemonic Assembly Syntax Description # of

Words # of

Cycles Status Flags

Affected

PIC24FJ16MC101/102

DEC2 DEC2 f f = f – 2 1 1 C,DC,N,OV,Z

DEC2 f,WREG WREG = f – 2 1 1 C,DC,N,OV,Z

DEC2 Ws,Wd Wd = Ws – 2 1 1 C,DC,N,OV,Z

DISI DISI #lit14 Disable Interrupts for k instruction cycles 1 1 None

DIV DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C,OV

DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C,OV

DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C,OV

DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N,Z,C,OV

EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None

FBCL FBCL Ws,Wnd Find Bit Change from Left (MSb) Side 1 1 C

FF1L FF1L Ws,Wnd Find F ir st One fr om Left (MSb) Side 1 1 C

FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C

GOTO GOTO Expr Go to address 2 2 None

GOTO Wn Go to indirect 1 2 None

INC INC f f = f + 1 1 1 C,DC,N,OV,Z

INC f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z

INC Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z

INC2 INC2 f f = f + 2 1 1 C,DC,N,OV,Z

INC2 f,WREG WREG = f + 2 1 1 C,DC,N,OV,Z

INC2 Ws,Wd Wd = Ws + 2 1 1 C,DC,N,OV,Z

IOR IOR f f = f .IOR. WREG 1 1 N,Z

IOR f,WREG WREG = f .IOR. WREG 1 1 N,Z

IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N,Z

IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N,Z

IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N,Z

LAC LAC Wso,#Slit4,Acc Load Accumulator 1 1 OA,OB,OAB,

SA,SB,SAB

LNK LNK #lit14 Link Frame Pointer 1 1 None

LSR LSR f f = Logical Right Shift f 1 1 C,N,OV,Z

LSR f,WREG WREG = Logical Right Shift f 1 1 C,N,OV,Z

LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C,N,OV,Z

LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N,Z

LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N,Z

MOV MOV f,Wn Move f to Wn 1 1 None

MOV f Move f to f 1 1 N,Z

MOV f,WREG Move f to WREG 1 1 None

MOV #lit16,Wn Move 16-bit literal to Wn 1 1 None

MOV.b #lit8,Wn Move 8-bit literal to Wn 1 1 None

MOV Wn,f Move Wn to f 1 1 None

MOV Wso,Wdo Move Ws to Wd 1 1 None

MOV WREG,f Move WREG to f 1 1 None

MOV.D Wns,Wd Move Double from W(ns):W(ns + 1) to Wd 1 2 None

MOV.D Ws,Wnd Move Double from Ws to W(nd + 1):W(nd) 1 2 None

TABLE 24-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Assembly

Mnemonic Assembly Syntax Description # of

Words # of

Cycles Status Flags

Affected

PIC24FJ16MC101/102

MUL MUL.SS Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) *

signed(Ws) 1 1 None

MUL.SU Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) *

unsigned(Ws) 1 1 None

MUL.US Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) *

signed(Ws) 1 1 None

MUL.UU Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) *

unsigned(Ws) 1 1 None

MUL.SU Wb,#lit5,Wnd {Wnd + 1, Wnd} = signed(Wb) *

unsigned(lit5) 1 1 None

MUL.UU Wb,#lit5,Wnd {Wnd + 1, Wnd} = unsigned(Wb) *

unsigned(lit5) 1 1 None

MUL f W3:W2 = f * WREG 1 1 None

NEG NEG Acc Negate Accumulator 1 1 OA,OB,OAB,

SA,SB,SAB

NEG f f = f + 1 1 1 C,DC,N,OV,Z

NEG f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z

NEG Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z

NOP NOP No Operation 1 1 None

NOPR No Operation 1 1 None

POP POP f Pop f from Top-of-Stack (TOS) 1 1 None

POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None

POP.D Wnd Pop from Top-of-Stack (TOS) to

W(nd):W(nd + 1) 1 2 None

POP.S Pop Shadow Registers 1 1 All

PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None

PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None

PUSH.D Wns Push W(ns):W(ns + 1) to Top-of-Stack

(TOS) 1 2 None

PUSH.S Push Shadow Registers 1 1 None

PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO,Sleep

REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None

REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None

RESET RESET Software device Reset 1 1 None

RETFIE RETFIE Return from interrupt 1 3 (2) None

RETLW RETLW #lit10,Wn Return with literal in Wn 1 3 (2) None

RETURN RETURN Return from Subroutine 1 3 (2) None

RLC RLC f f = Rotate Left through Carry f 1 1 C,N,Z

RLC f,WREG WREG = Rotate Left through Carry f 1 1 C,N,Z

RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C,N,Z

RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N,Z

RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N,Z

RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N,Z

RRC RRC f f = Rotate Right through Carry f 1 1 C,N,Z

RRC f,WREG WREG = Rotate Right through Carry f 1 1 C,N,Z

RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C,N,Z

RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N,Z

RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z

RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z

SAC SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None

SAC.R Acc,#Slit4,Wdo Store Rounded Accumulator 1 1 None

TABLE 24-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Assembly

Mnemonic Assembly Syntax Description # of

Words # of

Cycles Status Flags

Affected

PIC24FJ16MC101/102

SE SE Ws,Wnd Wnd = sign-extended Ws 1 1 C,N,Z

SETM SETM f f = 0xFFFF 1 1 None

SETM WREG WREG = 0xFFFF 1 1 None

SETM Ws Ws = 0xFFFF 1 1 None

SFTAC SFTAC Acc,Wn Arithmetic Shift Accumulator by (Wn) 1 1 OA,OB,OAB,

SA,SB,SAB

SFTAC Acc,#Slit6 Arithmetic Shift Accumulator by Slit6 1 1 OA,OB,OAB,

SA,SB,SAB

SL SL f f = Left Shift f 1 1 C,N,OV,Z

SL f,WREG WREG = Left Shift f 1 1 C,N,OV,Z

SL Ws,Wd Wd = Left Shift Ws 1 1 C,N,OV,Z

SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N,Z

SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N,Z

SUB SUB Acc Subtract Accumulators 1 1 OA,OB,OAB,

SA,SB,SAB

SUB f f = f – WREG 1 1 C,DC,N,OV,Z

SUB f,WREG WREG = f – WREG 1 1 C,DC,N,OV,Z

SUB #lit10,Wn Wn = Wn – lit10 1 1 C,DC,N,OV,Z

SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C,DC,N,OV,Z

SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C,DC,N,OV,Z

SUBB SUBB f f = f – WREG – (C) 1 1 C,DC,N,OV,Z

SUBB f,WREG WREG = f – WREG – (C) 1 1 C,DC,N,OV,Z

SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C,DC,N,OV,Z

SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C,DC,N,OV,Z

SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C,DC,N,OV,Z

SUBR SUBR f f = WREG – f 1 1 C,DC,N,OV,Z

SUBR f,WREG WREG = WREG – f 1 1 C,DC,N,OV,Z

SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C,DC,N,OV,Z

SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 C,DC,N,OV,Z

SUBBR SUBBR f f = WREG – f – (C) 1 1 C,DC,N,OV,Z

SUBBR f,WREG WREG = WREG – f – (C) 1 1 C,DC,N,OV,Z

SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C,DC,N,OV,Z

SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 C,DC,N,OV,Z

SWAP SWAP.b Wn Wn = nibble swap Wn 1 1 None

SWAP Wn Wn = byte swap Wn 1 1 None

TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 None

TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None

TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None

TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None

ULNK ULNK Unlink Frame Pointer 1 1 None

XOR XOR f f = f .XOR. WREG 1 1 N,Z

XOR f,WREG WREG = f .XOR. WREG 1 1 N,Z

XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N,Z

XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N,Z

XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N,Z

ZE ZE Ws,Wnd Wnd = Zero-extend Ws 1 1 C,Z,N

TABLE 24-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Assembly

Mnemonic Assembly Syntax Description # of

Words # of

Cycles Status Flags

Affected

PIC24FJ16MC101/102

25.0 DEVELOPMENT SUPPORT

The PIC® microcontrollers and dsPIC® digital signal

controllers are supported with a full range of software

and hardware development tools:

• Integrated Development Environment

- MPLAB® IDE Software

• Compilers/Assemblers/Linkers

- MPLAB C Compiler for Various Device

Families

- HI-TECH C for Various Device Families

- MPASMTM Assembler

-MPLINK

TM Object Linker/

MPLIBTM Object Librarian

- MPLAB Assembler/Linker/Librarian for

Various Device Families

• Simulators

- MPLAB SIM Software Simulator

• Emulators

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debuggers

- MPLAB ICD 3

- PIC kit™ 3 Debug Express

• Device Programmers

- PICkit™ 2 Programmer

- MPLAB PM3 Device Programmer

• Low-Cost Demonstration/Development Boards,

Evaluation Kits, and Starter Kits

25.1 MPLAB Integrated Development

Environment Software

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16/32-bit

microcontroller market. The MPLAB IDE is a Windows®

operating system-based application that contains:

• A single graphical interface to all de bugging tools

- Simulator

- Programmer (sold separately)

- In-Circuit Emulator (sold separately)

- In-Circuit Debugger (sold separately)

• A full-featured editor with color-coded context

• A multiple project manager

• Customizable data windows with direct edit of

contents

• High-level source code debugging

• Mouse over variable inspection

• Drag and drop variables from source to watch

windows

• Extensive on-line help

• Integration of select third party tools, such as

IAR C Compilers

The MPLAB IDE allows you to:

• Edit your source files (either C or assembly)

• One-touch compile or assemble, and download to

emulator and simulator tools (automatically

updates all project information)

• Debug using:

- Source files (C or assembly)

- Mixed C and assembly

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

PIC24FJ16MC101/102

25.2 MPLAB C Compilers for Various

Device Families

The MPLAB C Compiler code development systems

are complete ANSI C compilers for Microchip’s PIC18,

PIC24 and PIC32 families of microcontrollers and the

dsPIC30 and dsPIC33 families of digital signal control-

lers. These compilers provide powerful integration

capabilities, superior code optimization and ease of

use.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

25.3 HI-TECH C for Various Device

Families

The HI-TECH C Compiler code development systems

are complete ANSI C compilers for Microchip’s PIC

family of microcontrollers and the dsPIC family of digital

signal controllers. These compilers provide powerful

integration capabilities, omniscient code generation

and ease of us e.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

The compilers include a macro assembler, linker, pre-

processor , and one-step driver , and can run on multiple

platforms.

25.4 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assembler for PIC10/12/16/18 MCUs.

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker , Intel® standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST fi les that contain source lines

and generated machine code and COFF files for

debugging.

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• User-defined macros to streamline

assembly code

• Conditional assembly for multi-purpose

source files

• Directives that allow complete control over the

assembly process

25.5 MPLINK Object Linker/

MPLIB Object Librarian

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler . It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB Object Librarian manages the creation and

modification of libra ry files of preco mpiled cod e. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features inclu de:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grou ping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

25.6 MPLAB Assembler, Linker and

Librarian for Various Device

Families

MPLAB Assembler produces relocatable machine

code from symbolic assembly language for PIC24,

PIC32 and dsPIC devices. MPLAB C Compiler uses

the assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or linked with other relocatable object files and

archives to create an executable file . Notable features

of the assembler include:

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command line interface

• Rich directive set

• Flexible macro language

• MPLAB IDE compatibility

PIC24FJ16MC101/102

25.7 MPLAB SIM Software Simulator

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and d sPIC® DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified a nd stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most peripherals and internal registers.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C Compilers,

and the MPASM and MPLAB Assemblers. The soft-

ware simulator offers the flexibility to develop and

debug code outside of the hardware laboratory envi-

ronment, making it an excellent, economical software

development tool.

25.8 MPLAB REAL ICE In-Circuit

Emulator System

MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC and MCU devices. It debugs and

programs PIC® Flash MCUs and dsPIC® Flash DSCs

with the easy-to-use, powerful graphical user interface of

the MPLAB Integrated Development Environment (IDE),

included with each kit.

The emulator is connected to the design engineer ’s PC

using a high-speed USB 2.0 interface and is connected

to the target with either a connector compatible with in-

circuit debugger systems (RJ11) or with the new high-

speed, noise tolerant, Low-Voltage Differential Signal

(LVDS) interconnectio n (C AT5).

The emulator is field upgradable through future firmware

downloads in MPLAB IDE. In upcoming releases of

MPLAB IDE, new devices will be supported, and new

features will be added. MPLAB REAL ICE offers

significant advantages over competitive emulators

including low-cost, full-speed emulation, run-time

variable watches, trace analysis, complex breakpoints, a

ruggedized probe interface and long (up to three meters)

interconnection cables.

25.9 MPLAB ICD 3 In-Circuit Debugger

System

MPLAB ICD 3 In-Circuit Debugger System is Micro-

chip's most cost effective high-speed hardware

debugger/programmer for Microchi p Flash Digital Sig-

nal Controller (DSC) and microcontroller (MCU)

devices. It debugs and programs PIC® Flash microcon-

trollers and dsPIC® DSCs with the powerful, yet easy-

to-use graphical user interface of MPLAB Integrated

Development Environment (IDE).

The MPLAB ICD 3 In-Circuit Debugger probe is con-

nected to the design engineer's PC using a high-speed

USB 2.0 interface and is connected to the target with a

connector compatible with the MPLAB ICD 2 or MPLAB

REAL ICE systems (RJ-11). MPLAB ICD 3 supports all

MPLAB ICD 2 headers.

25.10 PICkit 3 In-Circuit Debugger/

Programmer and

PICkit 3 Debug Express

The MPLAB PICkit 3 allows debugging and program-

ming of PIC® and dsPIC® Flash microcontrollers at a

most affordable price point using the powerful graphical

user interface of the MPLAB Integrated Development

Environment (IDE). The MPLAB PICkit 3 is connected

to the design engineer's PC using a full speed USB

interface and can be connected to the target via an

Microchip debug (RJ-11) connector (compatible with

MPLAB ICD 3 and MPLAB REAL ICE). The connector

uses two device I/O pins and the reset line to imple-

ment in-circuit debugging and In-Circuit Serial Pro-

gramming™.

The PICkit 3 Debug Express include the PICkit 3, demo

board and microcontroller , hookup cables and CDROM

with user’s guide, lessons, tutorial, compiler and

MPLAB IDE software.

PIC24FJ16MC101/102

25.11 PICkit 2 Development

Programmer/Debugger and

PICkit 2 Debug Express

The PICkit™ 2 Development Programmer/Debugger is

a low-cost development tool with an easy to use inter-

face for programming and debugging Microchip’s Flash

families of microcontrollers. The full featured

Windows® programming interface supports baseline

(PIC10F, PIC12F5xx, PIC16F5xx), midrange

(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,

dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit

microcontrollers, and many Microchip Serial EEPROM

products. With Microchip’s powerful MPLAB Integrated

Development Environment (IDE) the PICkit™ 2

enables in-circuit debugging on most PIC® microcon-

trollers. In-Circuit-Debugging runs, halts and single

steps the program while the PIC microcontroller is

embedded in the ap plication. When halted at a break-

point, the file registers can be examined and modified.

The PICkit 2 Debug Express include the PICkit 2, demo

board and microcontroller, hookup cables and CDROM

with user’s guide, lessons, tutorial, compiler and

MPLAB IDE software.

25.12 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages and a modu-

lar, detachable socket assembly to support various

package types. The ICSP™ cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Device Programmer can read, verify and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices and incorporates an MMC card for file

storage and data applications.

25.13 Demonstration/Development

Boards, Evaluation Kits, and

Star ter Kits

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards include prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displa ys, potentiometers and additiona l

EEPROM memory.

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and d sPICDEM™ demon-

stration/develop ment board series of circuit s, Microchip

has a line o f evaluation kit s and demons tration softwa re

for analog filter design, KEELOQ® security ICs, CAN,

IrDA®, PowerSmart battery management, SEEVAL®

evaluation system, Sigma-Delta ADC, flow rate

sensing, plus many more.

Also available are starter kits that contain everything

needed to experience the specified device. This usually

includes a single application and debug capability, all

on one board.

Check the Microchip web page (www.microchip.com)

for the complete list of demonstration, development

and evaluation kits.

PIC24FJ16MC101/102

26.0 ELECTRICAL CHARACTERISTICS

This section provides an overview of PIC24FJ16MC101/102 electrical characteristics. Additional information will be

provided in future revisions of this document as it becomes available.

Absolute maximum ratings for the PIC24FJ16MC1 01/102 family are listed below. Exposure to these ma ximum rating

conditions for exte nded periods may affect device reliability. Functional operation of the device at these or any other

conditions above the parameters indicate d in the operation listings of this specification is not implied.

Absolute Maximum Ratings(1)

Ambient temperature under bias.............................................................................................................-40°C to +125°C

Storage temperature .............................................................................................................................. -65°C to +150°C

Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V

Voltage on any pin that is not 5V tolerant with respect to VSS(4) ....................................................-0.3V to (VDD + 0.3V)

Voltage on any 5V tolerant pin with respect to VSS when VDD ≥ 3.0V(4) .................................................. -0.3V to +5.6V

Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V(4) .................................................... -0.3V to 3.6V

Maximum current out of VSS pin.......... .............. .............. ......................... ......................... .............. .....................300 mA

Maximum current into VDD pin(2)...........................................................................................................................250 mA

Maximum output current sunk by any I/O pin(3).... .. ... ......................... .......................... ......................... .............. .....8 mA

Maximum output current sourced by any I/O pin(3)......................................... .............. ......................... ...................8 mA

Maximum current sunk by all ports ....................... ............................................................................................... .200 mA

Maximum current sourced by all ports(2).......................... .............. ......................... .............. .............. .............. ....200 mA

Note: It is important to note that the specifications in this chapter of the data sheet, supercede any specifications

that may be provided in PIC24F Family Reference Manual sections.

Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only, and functional operation of the device at those or any other conditions

above those indicated in the operation listings o f this specification i s not implied. Exposure to maximum

rating conditions for extended periods may affect device reliability.

2: Maximum allowable current is a function of devi c e maximum power dissipation (see Table 26-2).

3: An exception is the OSCO pin, which is able to source 12 mA and sink 10 mA.

4: See the “Pin Diagrams” section for 5V tolerant pins.

PIC24FJ16MC101/102

26.1 DC Characteristics

TABLE 26-1: OPERATING MIPS VS. VOLTAGE

Characteristic VDD Range

(in Volts) Temp Range

(in °C)

Max MIPS

PIC24FJ16MC101/102

DC5 3.0-3.6V -40°C to +85°C 16

3.0-3.6V -40°C to +125°C 16

TABLE 26-2: THERMAL OPERATING CONDITIONS

Rating Symbol Min Typ Max Unit

Industrial Temperature Devices

Operating Junction Temperature Rang e TJ-40 — +125 °C

Operating Ambient Temperature Range TA-40 — +85 °C

Extended Temperature Devices

Operating Junction Temperature Rang e TJ-40 — +140 °C

Operating Ambient Temperature Range TA-40 — +125 °C

Power Dissipation:

Internal chip power dissipation:

PINT = VDD x (IDD – Σ IOH) PDPINT + PI/OW

I/O Pin Power Dissipation:

I/O = Σ ({VDD – VOH} x IOH) + Σ (VOL x IOL)

Maximum Allowed Power Dissipation PDMAX (TJ – TA)/θJA W

TABLE 26-3: THERMAL PACKAGING CHARACTERISTICS

Characteristic Symbol Typ Max Unit Notes

Package Thermal Resistance, 18-pin PDIP θJA 50 — °C/W 1

Package Thermal Resistance, 20-pin PDIP θJA 50 — °C/W 1

Package Thermal Resistance, 28-pin SPDIP θJA 50 — °C/W 1

Package Thermal Resistance, 18-pin SOIC θJA 63 — °C/W 1

Package Thermal Resistance, 20-pin SOIC θJA 63 — °C/W 1

Package Thermal Resistance, 28-pin SOIC θJA 55 — °C/W 1

Package Thermal Resistance, 20-pin SSOP θJA 90 — °C/W 1

Package Thermal Resistance, 28-pin SSOP θJA 71 — °C/W 1

Package Thermal Resistance, 28-pin QFN (6x6 mm) θJA 37 — °C/W 1

Package Thermal Resistance, 36-pin TLA (5x5 mm) θJA 31.1 — °C/W 1

Note 1: Junction to ambient thermal resistance, Theta-JA (θJA) numbers are achieved by package simulations.

PIC24FJ16MC101/102

TABLE 26-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS

DC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤TA ≤+125°C for Extende d

Param

No. Symbol Characteristic Min Typ(1) Max Units Conditions

Operating Voltage

DC10 Supply Voltage

VDD — 3.0 — 3.6 V Industrial and Extended

DC12 VDR RAM Data Retention Voltage(2) 1.8 — — V —

DC16 VPOR VDD Start Voltage

to ensure internal

Power-on Reset signal

——VSS V—

DC17 SVDD VDD Rise Rate

to ensure internal

Power-on Reset signal

0.024 — — V/ms 0-2.4V in 0.1s

DC18 VCORE VDD Core(3)

Internal regulator voltage 2.25 — 2.75 V Voltage is dependent on

load, temperature and

VDD

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

2: This is the limit to which VDD may be lowered without losing RAM data.

3: These parameters are characterized by similarity, but are not tested in manufacturing.

TABLE 26-5: ELECTRICAL CHARACTERISTICS: BOR

DC CHARACTERISTICS

Standard Operating Condition s: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min(1) Typ Max Units Conditions

BO10 VBOR BOR Event on VDD transition 2.40 2.48 2.55 V —

Note 1: Parameters are for design guidance only and are not tested in manufacturing.

PIC24FJ16MC101/102

TABLE 26-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD)

DC CHARACTERISTICS

Standard Operating Condition s: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤TA ≤+1 25°C for Extended

Parameter

No. Typical(1) Max Units Conditions

Operating Current (IDD)(2)

DC20d 0.7 1.7 mA -40°C

3.3V LPRC (31 kHz)(3)

DC20a 0.7 1.7 mA +25°C

DC20b 1.0 1.7 mA +85°C

DC20c 1.3 1.7 mA +125°C

DC21d 1.9 2.6 mA -40°C

3.3V 1 MIPS(3)

DC21a 1.9 2.6 mA +25°C

DC21b 1.9 2.6 mA +85°C

DC21c 2.0 2.6 mA +125°C

DC22d 6.5 8.5 mA -40°C

3.3V 4 MIPS(3)

DC22a 6.5 8.5 mA +25°C

DC22b 6.5 8.5 mA +85°C

DC22c 6.5 8.5 mA +125°C

DC23d 12.2 16 mA -40°C

3.3V 10 MIPS(3)

DC23a 12.2 16 mA +25°C

DC23b 12.2 16 mA +85°C

DC23c 12.2 16 mA +125°C

DC24d 16 21 mA -40°C

3.3V 16 MIPS

DC24a 16 21 mA +25°C

DC24b 16 21 mA +85°C

DC24c 16 21 mA +125°C

Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.

2: IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading

and switching rate, oscillator type, internal code exec ution pattern and temperature, also have an impact

on the current consumption. The test conditions for all IDD measurements are as follows:

• Oscillator is configured in EC mode, OSC1 is driven with external square wave from rail-to-rail

• CLKO is configured as an I/O input pin in the Configuration word

• All I/O pins are configured as inputs and pulled to VSS

•MCLR = VDD, WDT and FSCM are disabled

• CPU, SRAM, program memory and data memory are operational

• No peripheral modules are operating; however, every peripheral is bein g clocked (PMDx bits are all

zeroed)

• CPU executing while(1) statement

3: These parameters are characterized, but not tested in manufacturing.

PIC24FJ16MC101/102

TABLE 26-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)

DC CHARACTERISTICS

Standard Operating Condition s: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +8 5°C for Industrial

-40°C ≤TA ≤+1 25°C for Extended

Parameter

No. Typical(1) Max Units Conditions

Idle Current (IIDLE): Core OFF Clock ON Base Current(2)

DC40d 0.6 1.6 mA -40°C

3.3V LPRC (31 kHz)(3)

DC40a 0.6 1.6 mA +25°C

DC40b 0.9 1.6 mA +85°C

DC40c 1.2 1.6 mA +125°C

DC41d 0.5 1.1 mA -40°C

3.3V 1 MIPS(3)

DC41a 0.5 1.1 mA +25°C

DC41b 0.5 1.1 mA +85°C

DC41c 0.8 1.1 mA +125°C

DC42d 0.9 1.6 mA -40°C

3.3V 4 MIPS(3)

DC42a 0.9 1.6 mA +25°C

DC42b 1.0 1.6 mA +85°C

DC42c 1.2 1.6 mA +125°C

DC43a 1.6 2.6 mA +25°C

3.3V 10 MIPS(3)

2.6DC43d 1.6 mA -40°C

DC43b 1.7 2.6 mA +85°C

DC43c 2 2.6 mA +125°C

DC44d 2.4 3.8 mA -40°C

3.3V 16 MIPS(3)

DC44a 2.4 3.8 mA +25°C

DC44b 2.6 3.8 mA +85°C

DC44c 2.9 3.8 mA +125°C

Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.

2: Base Idle current is measured as follows:

• CPU core is off, oscillator is configured in EC mode, OSC1 is driven with external square wave from

rail-to-rail

• CLKO is configured as an I/O input pin in the Configuration word

• External Secondary Oscillator (SOSC) is disabled (i.e., SOSCO and SOSCI pins are configured as

digital I/O inputs)

• All I/O pins are configured as inputs and pulled to VSS

•MCLR = VDD, WDT and FSCM are disabled

• No peripheral modules are operating; however, every peripheral is bein g clocked (PMDx bits are all

zeroed)

• The VREGS bit (RCON<8>) = 1

3: These parameters are characterized, but not tested in manufacturing.

PIC24FJ16MC101/102

TABLE 26-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)

DC CHARACTERISTICS

Standard Operating Conditions: 3.0 V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤TA ≤+125°C for Extended

Parameter

No. Typical(1) Max Units Conditions

Power-Down Current (IPD)(2)

DC60d 27 250 µA -40°C

3.3V Base Power-Down Current(3,4)

DC60a 32 250 µA +25°C

DC60b 43 250 µA +85°C

DC60c 150 500 µA +125°C

DC61d 420 600 µA -40°C

3.3V Watchdog Timer Current: ΔIWDT(3,5)

DC61a 420 600 µA +25°C

DC61b 530 750 µA +85°C

DC61c 620 900 µA +125°C

Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated.

2: IPD (Sleep) current is measured as follows:

• CPU core is off, oscillator is configured in EC mode, OSC1 is driven with external square wave from

rail-to-rail

• CLKO is configured as an I/O input pin in the Configuration word

• External Secondary Oscillator (SOSC) is disabled (i.e., SOSCO and SOSCI pins are configured as

digital I/O inputs)

• All I/O pins are configured as inputs and pulled to VSS

•MCLR = VDD, WDT and FSCM are disabled

• All peripheral module s are disabled (PMDx bits are all ones)

• VREGS bit (RCON<8>) = 1 (i.e., core regulator is set to stand-by while the device is in Sleep mode)

• On applicable devices, RTCC is disabled plus the VREGS bit (RCON<8>) = 1

3: The Δ current is the additional current consumed when the module is enabled. Th is current should be

added to the base IPD current.

4: These currents are measured on the device containing the most memory in this family.

5: These parameters are characterized, but not tested in manufacturing.

PIC24FJ16MC101/102

TABLE 26-9: DC CHARACTERISTICS: DOZE CURRENT (IDOZE)

DC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤TA ≤+125°C for Extended

Parameter No. Typical(1) Max Doze

Ratio(2) Units Conditions

DC70a 13.2 17.2 1:2 mA +25°C 3.3V 16 MIPSDC70f 4.7 6.2 1:64 mA

DC70g 4.7 6.2 1:128 mA

DC71a 13.2 17.2 1:2 mA +85°C 3.3V 16 MIPSDC71f 4.7 6.2 1:64 mA

DC71g 4.7 6.2 1:128 mA

DC72a 13.2 17.2 1:2 mA +125°C 3.3V 16 MIPSDC72f 4.7 6.2 1:64 mA

DC72g 4.7 6.2 1:128 mA

DC73a 13.2 17.2 1:2 mA -40°C 3.3V 16 MIPSDC73f 4.7 6.2 1:64 mA

DC73g 4.7 6.2 1:128 mA

Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated.

2: IDOZE is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact

on the current consumption. The test conditions for all IDOZE measurements are as follows:

• Oscillator is configured in EC mode, OSC1 is driven with external square wave from rail-to-rail

• CLKO is configured as an I/O input pin in the Configuration word

• All I/O pins are configured as inputs and pulled to VSS

•MCLR = VDD, WDT and FSCM are disabled

• CPU, SRAM, program memory and data memory are operational

• No peripheral modules are operating; however, every peripheral is bein g clocked (PMDx bits are all

zeroes)

• CPU executing while(1) statement

PIC24FJ16MC101/102

TABLE 26-10: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS

DC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operatin g te mperature -40°C ≤ TA≤ +85°C for Industrial

-40°C ≤ TA≤+125°C for Extended

Param

No. Symbol Characteristic Min Typ(1) Max Units Conditions

VIL Input Low Voltage

DI10 I/O pins VSS —0.2VDD V

DI15 MCLR VSS —0.2VDD V

DI16 I/O pins with OSC1 or SOSCI VSS —0.2VDD V

DI18 SDA, SCL VSS — 0.3 VDD V SMBus disabled

DI19 SDA, SCL VSS — 0.8 V SMBus enabled

VIH Input High Voltage

DI20 I/O pins not 5V tolerant(4)

I/O pins 5V tolerant(4) 0.7 VDD

0.7 VDD —

—VDD

5.5 V

DI28 SDAx, SCLx 0.7 VDD —VDD V SMBus disabled

DI29 SDAx, SCLx 2.1 — VDD V SMBus enabled

ICNPU CNx Pull-up Current

DI30 50 250 400 µA VDD = 3.3V, VPIN = VSS

IIL Input Leakage Current(2,3)

DI50a MCLR pin -2 — +2 µA VSS ≤ VPIN ≤ VDD,

Pin at high-impedance

DI50b All pins except MCLR and

OSCO -2 — +2 µA VSS ≤ VPIN ≤ VDD,

Pin at high-impedance

DI50c OSCO pin -4 — +4 µA VSS ≤ VPIN ≤ VDD,

Pin at high-impedance

Note 1: Data in “Typ” column is at 3.3V, 25°C unle s s otherwise stated.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

3: Negative current is defined as current sourced by the pin.

4: See “Pin Diagrams” for a list of 5V tolerant pins.

TABLE 26-11: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS

DC CHARACTERISTICS

Standard Operating Conditions: 3 .0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤TA ≤+125°C for Extended

Param

No. Symbol Characteristic Min Typ Max Units Conditions

VOL Output Low Voltage

DO10b All I/O pins except OSCO — — 0.4 V IOL = 8 mA, VDD = 3.3V

DO10c OSCO pin — — 0.4 V IOL = 10 mA, VDD = 3.3V

VOH Output High Vo ltage

DO20b All I/O pins except OSCO 2.4 — — V IOL = -8 mA, VDD = 3.3V

DO20c OSCO pin 2.4 — — V IOL = -12 mA, VDD = 3.3V

PIC24FJ16MC101/102

TABLE 26-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS

TABLE 26-12: DC CHARACTERISTICS: PROGRAM MEMORY

DC CHARACTERISTICS

Standard Operating Conditions: 3 .0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤TA ≤+125°C for Extended

Param

No. Symbol Characteristic(3) Min Typ(1) Max Units Conditions

Program Flash Memory

D130a EPCell Endurance 10,000 — — E/W -40°C to +125°C

D131 VPR VDD for Read VMIN —3.6VVMIN = Minimum operating

voltage

D132B VPEW VDD for Self-Timed Write VMIN —3.6VVMIN = Minimum operating

voltage

D134 TRETD Characteristic Retention 20 — — Year Provided no other specifications

are violated

D135 IDDP Supply Current during

Programming —10—mA

D137a TPE Page Erase Time 20.1 — 26.5 ms TPE = 168517 FRC cycles,

TA = +100°C, See Note 2

D137b TPE Page Erase Time 19.5 — 27.3 ms TPE = 168517 FRC cycles,

TA = +125°C, See Note 2

D138a TWW Word Write Cycle Time 47.9 — 48.8 µs TWW = 355 FRC cycles,

TA = +100°C, See Note 2

D138b TWW Word Write Cycle Time 47.4 — 49.3 µs TWW = 355 FRC cycles,

TA = +125°C, See Note 2

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

2: Other conditions: FRC = 7.37 MHz, TUN<5:0> = b'011111 (for Min), TUN<5:0> = b'100000 (for Max).

This parameter depends on the FRC accuracy (see Table 26-18) and the value of the FRC Oscillator

Tuning register (see Register 8-3). For complete details on calculating the Minimum and Maximum time

see Section 5.3 “Programming Operations”.

3: These parameters are ensured by design, but are not characterized or tested in manufacturin g.

DC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA≤ +85°C for Industrial

-40°C ≤ TA≤+125°C for Extended

Param

No. Symbol Characteristics Min Typ Max Units Comments

—CEFC External Filter Capacitor

Value(1) 4.7 10 — µF Capacitor must be low

series resistance

(< 5 ohms)

Note 1: Typical VCAP voltage = 2.5V when VDD ≥ VDDMIN.

PIC24FJ16MC101/102

26.2 AC Characteristics and Timing

Parameters

This section defines PIC24FJ16MC101/102

AC characteristics and timing parameters.

TABLE 26-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC

FIGURE 26-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

TABLE 26-15: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS

AC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherw ise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤TA ≤+125°C for Extended

Operating voltage VDD range as described in Section 26.1 “DC

Characteristics”.

Param

No. Symbol Characteristic Min Typ Max Units Conditions

DO50 COSC2 OSC2/SOSC2 pin — — 15 pF In MS and HS modes when exte rnal

clock is used to drive OSC1

DO56 CIO All I/O pins and OSC2 — — 50 pF EC mode

DO58 CBSCLx, SDAx — — 400 pF In I2C™ mode

VDD/2

VSS

RL=464Ω

CL= 50 pF for all pins except OSC2

15 pF for OSC2 output

Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2

PIC24FJ16MC101/102

FIGURE 26-2: EXTERNAL CLOCK TIMING

Q1 Q2 Q3 Q4

OSC1

CLKO

Q1 Q2 Q3 Q4

OS20

OS25 OS30 OS30

OS40

OS41

OS31 OS31

TABLE 26-16: EXTERNAL CLOCK TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤TA ≤+125°C for Extended

Param

No. Symb Characteristic Min Typ(1) Max Units Conditions

OS10 FIN External CLKI Frequency

(External clocks allowed only

in EC and ECPLL modes)

DC — 32 MHz EC

Oscillator Crystal Frequency 3.0

—

MHz

kHz

SOSC

OS20 TOSC TOSC = 1/FOSC 31.25 — DC ns —

OS25 TCY Instruction Cycle Time(2,4) 62.5 — DC ns —

OS30 TosL,

TosH External Clock in (OSC1)(5)

High or Low Time 0.45 x TOSC ——nsEC

OS31 TosR,

TosF External Clock in (OSC1)(5)

Rise or Fall Time ——20nsEC

OS40 TckR CLKO Rise Time(3,5) —610ns—

OS41 TckF CLKO Fall Time(3,5) —610ns—

OS42 GMExternal Oscillator

Transconductance(4) 14 16 18 mA/V VDD = 3.3V

TA = +25ºC

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

2: Instruction cycle period (TCY) equals two times the input oscillator time-base period. All specified values

are based on characterization data for that particular oscillator type under standard operating conditions

with the device executing code. Exc eeding these specified limits may result in an unstable oscillator

operation and/or higher than expected current consumption. All devices are tested to operate at “min.”

values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the

“max.” cycle time limit is “DC” (no clock) for all devices.

3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.

4: These parameters are characterized by similarity, but are tested in manufacturin g at FIN = 32 MHz only.

5: These parameters are characterized by similarity, but are not teste d in manufacturing.

6: Data for this parameter is Preliminary. This parameter is characterized, but not tested in manufacturing.

PIC24FJ16MC101/102

TABLE 26-17: PLL CLOCK TIMING SPECIFICATIONS

AC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤TA ≤+125°C for Extended

Param

No. Symbol Characteristic Min Typ(1) Max Units Conditions

OS50 FPLLI PLL Voltage Controlled

Oscillator (VCO) Input

Frequency Range(2)

3.0 — 8 MHz ECPLL and MSPLL

modes

OS51 FSYS On-Chip VCO System

Frequency(3) 12 — 32 MHz —

OS52 TLOCK PLL Start-up Time (Lock Time)(3) —— 2ms —

OS53 DCLK CLKO Stability (Jitter)(3) -2 1 +2 % —

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: These parameters are characterized by similari ty, but are tested in manufacturing at 7.7 MHz input only.

3: These parameters are characterized by similarity, but are not tested in manufacturing. This specification is

based on clock cycle by clock cycle measurements. The effective jitter for individual time bases or commu-

nication clocks used by the user application, are derived from dividing the CLKO stability specification by

the square root of “N” (where “N” is equal to FOSC divided by the peripheral data rate clock). For example,

if FOSC = 32 MHz and the SPI bit rate is 5 MHz, the effective jitter of the SPI clock is equal to:

TABLE 26-18: AC CHARACTERISTICS: INTERNAL FAST RC (FRC) ACCURACY

AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operatin g te mp erature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤TA ≤+125°C for Extended

Param

No. Characteristic Min Typ Max Units Conditions

Internal FRC Accuracy @ 7.3728 MHz(1)

F20a FRC 1.5 ±0.25 1.5 % -40°C ≤ TA ≤ +85°C

F20b FRC -2 ±0.25 +2 % -40°C ≤ TA ≤ +125°C

Note 1: Frequency calibrated at 25°C and 3.3V. TUN bits may be used to compensate for temperature drift.

DCLK

------

--------------2%

2.53

---------- 0.79 %==

TABLE 26-19: INTERNAL LOW-POWER RC (LPRC) ACCURACY

AC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤TA ≤+125°C for Extended

Param

No. Characteristic Min Typ Max Units Conditions

LPRC @ 32.768 kHz(1,2)

F21a LPRC -20 ±10 +20 % -40°C ≤ TA ≤ +85°C

F21b LPRC -30 ±10 +30 % -40°C ≤ TA ≤ +125°C

Note 1: Change of LPRC frequency as VDD changes.

2: LPRC accuracy impacts the Watchdog Timer Time-out Period (TWDT1). See Section 23.4 “Watchdog

Timer (WDT)” for more information.

PIC24FJ16MC101/102

FIGURE 26-3: CLKO AND I/O TIMING CHARACTERISTICS

Note: Refer to Figure 26-1 for load conditions.

I/O Pin

(Input)

I/O Pin

(Output)

DI35

Old Value New Value

DI40

DO31

DO32

TABLE 26-20: I/O TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤TA ≤+125°C for Extended

Param

No. Symbol Characteristic(2) Min Typ(1) Max Units Conditions

DO31 TIOR Port Output Rise Time — 10 25 ns —

DO32 TIOF Port Output Fall Time — 10 25 ns —

DI35 TINP INTx Pin High or Low Time (input) 25 — — ns —

DI40 TRBP CNx High or Low Time (input) 2 — — TCY —

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

2: These parameters are characterized, but are not tested in manufacturing.

PIC24FJ16MC101/102

FIGURE 26-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING CHARACTERISTICS

VDD

MCLR

Internal

POR

PWRT

Time-out

OSC

Time-out

Internal

Reset

Watchdog

Timer

Reset

SY11

SY10

SY20

SY13

I/O Pins

SY13

Note: Refer to Figure 26-1 for load conditions.

FSCM

Delay

SY35

SY30

SY12

TABLE 26-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions : 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤TA ≤+125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

SY10 TMCLMCLR Pulse Width (low) 2 — — μs -40°C to +85°C

SY11 TPWRT Power-up Timer Period(1) — 64 — ms -40°C to +85°C

SY12 TPOR Power-on Reset Delay(3) 31030μs -40°C to +85° C

SY13 TIOZ I/O High-Impedance from MCLR

Low or Watchdog Timer Reset(1) ——1.2μs—

SY20 TWDT1 Watchdog Timer Time-out

Period(1) — — — ms See Section 23.4 “Watch-

dog Timer (WDT)” and

LPRC parameter F21a

(Table 26-19).

SY30 TOST Oscillator St art-up Time — 1024 *

TOSC ——TOSC = OSC1 period

SY35 TFSCM Fail-Safe Clock Monitor Delay (1) — 500 900 μs -40°C to +85°C

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

3: These parameters are characterized, but are not tested in manufacturing.

PIC24FJ16MC101/102

FIGURE 26-5: TIMER1, 2 AND 3 EXTERNAL CLOCK TIMING CHARACTERISTICS

Note: Refer to Figure 26-1 for load conditions.

Tx11

Tx15

Tx10

Tx20

TMRx OS60

TxCK

TABLE 26-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)

AC CHARACTERISTICS

Standard Opera ting Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operatin g te mperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤TA ≤+125°C for Extended

Param

No. Symbol Characteristic(2) Min Typ Max Units Conditions

TA10 TTXH TxCK High

Time Synchronous

mode Greater of:

20 or

(TCY + 20)/N

——ns

Must also meet

parameter TA15

N = prescaler

value (1, 8, 64,

256)

Asynchronous 35 — — ns

TA11 TTXLTxCK Low

Time Synchronous

mode Greater of:

20 ns or

(TCY + 20)/N

— — ns Must also meet

parameter TA15

N = prescaler

value (1, 8, 64,

256)

Asynchronous 10 — — ns

TA15 TTXP TxCK Input

Period Synchronous

mode Greater of:

40 or

(2 TCY + 40)/N

— — ns N = presca le

value

(1, 8, 64, 256)

OS60 Ft1 SOSC1/T1CK Oscillator

Input frequency Range

(oscillator enabled by

setting bit TCS

(T1CON<1>))

DC — 50 kHz —

TA20 TCKEXTMRL Delay from External TxCK

Clock Edge to Timer

Increment

0.75 TCY + 40 — 1.75 TCY + 40 ns —

Note 1: Timer1 is a Type A.

2: These parameters are characterized by similarity, but are not teste d in manufacturing.

PIC24FJ16MC101/102

TABLE 26-23: TIMER2 EXTERNAL CLOCK TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤TA ≤+125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ Max Units Conditions

TB10 TtxH TxCK High

Time Synchronous

mode Greater of:

20 or

(TCY + 20)/N

——ns

Must also meet

parameter TB15

N = prescale

value

(1, 8, 64, 256)

TB11 TtxL TxCK Low

Time Synchronous

mode Greater of:

20 or

(TCY + 20)/N

— — ns Must also meet

parameter TB15

N = prescale

value

(1, 8, 64, 256)

TB15 TtxP TxCK

Input

Period

Synchronous

mode Greater of:

40 or

(2 TCY + 40)/N

— — ns N = prescale

value

(1, 8, 64, 256)

TB20 TCKEXTMRL Delay from External TxCK

Clock Edge to Timer

Increment

0.75 TCY + 40 — 1.75 TCY + 40 ns —

Note 1: These parameters are characterized, but are not tested in manufacturing.

TABLE 26-24: TIMER3 EXTERNAL CLOCK TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Condition s: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤TA ≤+125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ Max Units Conditions

TC10 TtxH TxCK High

Time Synchronous TCY + 20 — — ns Must also meet

parameter TC15

TC11 TtxL TxCK Low

Time Synchronous TCY + 20 — — ns Must also meet

parameter TC15

TC15 TtxP TxCK Input

Period Synchronous,

with prescaler 2 TCY + 40 — — ns N = prescale

value

(1, 8, 64, 256)

TC20 TCKEXTMRL Delay from External TxCK

Clock Edge to Timer

Increment

0.75 TCY + 40 — 1.75 TCY + 40 ns —

Note 1: These parameters are characterized, but are not tested in manufacturing.

PIC24FJ16MC101/102

FIGURE 26-6: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS

ICx

IC10 IC11

IC15

Note: Refer to Figure 26-1 for load conditions.

TABLE 26-25: INPUT CAPTURE TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Condition s: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤TA ≤+1 25°C for Extended

Param

No. Symbol Characteristic(1) Min Max Units Conditions

IC10 TccL ICx Input Low Time No Prescaler 0.5 TCY + 20 — ns —

With Prescaler 10 — ns

IC11 TccH ICx Input High Time No Prescaler 0.5 TCY + 20 — ns —

With Prescaler 10 — ns

IC15 TccP ICx Input Period (TCY + 40)/N — ns N = prescale

value (1, 4, 16)

Note 1: These parameters are characterized by similarity, but are not tested in manufacturing.

PIC24FJ16MC101/102

FIGURE 26-7: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS

FIGURE 26-8: OC/PWM MODULE TIMING CHARACTERISTICS

OCx

OC11 OC10

(Output Compare

Note: Refer to Figure 26-1 for load conditions.

or PWM Mode)

TABLE 26-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions : 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤TA ≤+125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ Max Units Conditions

OC10 TccF OCx Output Fall T ime — — — ns See parameter DO32

OC11 TccR OCx Output Rise Time — — — ns See parameter DO31

Note 1: These parameters are characterized by similarity, but are not tested in manufacturing.

OCFA

OCx

OC20

OC15

Active Tri-state

TABLE 26-27: SIMPLE OC/PWM MODE TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Condition s: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤TA ≤+125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ Max Units Conditions

OC15 TFD Fault In put to PWM I/O

Change ——TCY + 20 ns ns —

OC20 TFLT Fault Input Pulse Width TCY + 20 ns — — ns —

Note 1: These parameters are characterized by similarity, but are not tested in manufacturing.

PIC24FJ16MC101/102

FIGURE 26-9: MOTOR CONTROL PWM MODULE FAULT TIMING CHARACTERISTICS

FIGURE 26-10: MOTOR CONTROL PWM MODULE TIMING CHARACTERISTICS

FLTA1

PWMx

MP30

MP20

See Note 1

Note 1: For the logic state after a Fault, refer to the FAOVxH:FAOVxL bits in the PxFLTACON register.

PWMx

MP11 MP10

Note: Refer to Figure 26-1 for load conditions.

TABLE 26-28: MOTOR CONTROL PWM MODULE TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions : 3.0V to 3.6V

(unless otherwise stated)

Operatin g te mperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤TA ≤+125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ Max Units Conditions

MP10 TFPWM PWM Output Fall Time — — — ns See parameter DO32

MP11 TRPWM PWM Output Rise Time — — — ns See parameter DO31

MP20 TFD Fault Input ↓ to PWM

I/O Change ——50ns —

MP30 TFH Minimum Pulse Width 50 — — ns —

Note 1: These parameters are characterized by similarity, but are not tested in manufacturing.

PIC24FJ16MC101/102

TABLE 26-29: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY

FIGURE 26-11: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY CKE = 0) TIMING

CHARACTERISTICS

AC CHARACTERISTICS

Standard Operating Condition s: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤TA ≤+125°C for Extended

Maximum

Data Rate

Master

Transmit Only

(Half-Duplex)

Master

Transmit/Receive

(Full-Duplex)

Slave

Transmit/Receive

(Full-Duplex) CKE CKP SMP

15 MHz Table 26-30 ——0,10,10,1

10 MHz — Table 26-31 —10,11

10 MHz — Table 26-32 —00,11

15 MHz — — Table 26-33 100

11 MHz — — Table 26-34 110

15 MHz — — Table 26-35 010

11 MHz — — Table 26-36 000

SCKx

(CKP = 0)

SCKx

(CKP = 1)

SDOx

SP10

SP21

SP20

SP35

SP20

SP21

MSb LSb

Bit 14 - - - - - -1

SP30, SP31

Note: Refer to Figure 26-1 for load conditions.

PIC24FJ16MC101/102

FIGURE 26-12: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY CKE = 1) TIMING

CHARACTERISTICS

TABLE 26-30: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤TA ≤+125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

SP10 TscP Maximum SCK Frequency — — 15 MHz See Note 3

SP20 TscF SCKx Output Fall Time — — — ns See parameter DO32

and Note 4

SP21 TscR SCKx Output Rise Time — — — ns See parameter DO31

and Note 4

SP30 TdoF SDOx Data Output Fall Time — — — ns See parameter DO32

and Note 4

SP31 TdoR SDOx Data Output Rise Time — — — ns See parameter DO31

and Note 4

SP35 TscH2doV,

TscL2doV SDOx Data Output Valid after

SCKx Edge —620ns —

SP36 TdiV2scH,

TdiV2scL SDOx Data Output Setup to

First SC Kx Edge 30 — — ns —

Note 1: These parameters are characterized, but are not tested in manufacturing.

2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

3: The minimum clock period for SCKx is 66.7 ns. Therefore, the clock generated in Master mode must not

violate this specification.

4: Assumes 50 pF load on all SPIx pins.

SCKx

(CKP = 0)

SCKx

(CKP = 1)

SDOx

SP10

SP21

SP20

SP35

SP20

SP21

MSb LSb

Bit 14 - - - - - -1

SP30, SP31

Note: Refer to Figure 26-1 for load conditions.

SP36

PIC24FJ16MC101/102

FIGURE 26-13: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = X, SMP = 1) TIMING

CHARACTERISTICS

TABLE 26-31: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING

REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤TA ≤+125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

SP10 TscP Maximum SCK Frequency — — 10 MHz See Note 3

SP20 TscF SCKx Output Fall Time — — — ns See parameter DO32

and Note 4

SP21 TscR SCKx Output Rise Time — — — ns See parameter DO31

and Note 4

SP30 TdoF SDOx Data Output Fall T ime — — — ns See parameter DO32

and Note 4

SP31 TdoR SDOx Data Output Rise Time — — — ns See parameter DO31

and Note 4

SP35 TscH2doV,

TscL2doV SDOx Data Output Valid after

SCKx Edge — 6 20 ns —

SP36 TdoV2sc,

TdoV2scL SDOx Data Output Setup to

First SCKx Edge 30 — — ns —

SP40 TdiV2scH,

TdiV2scL Setup Time of SDIx Data

Input to SCKx Edge 30 — — ns —

SP41 TscH2diL,

TscL2diL Hold Time of SDIx Data Input

to SCKx Edge 30 — — ns —

Note 1: These parameters are characterized, but are not tested in manufacturing.

2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

3: The minimum clock period for SCKx is 100 ns. The clock generated in Master mode must not violate this

specification.

4: Assumes 50 pF load on all SPIx pins.

SCKx

(CKP = 0)

SCKx

(CKP = 1)

SDOx

SP10

SP21

SP20

SP35

SP20

SP21

MSb LSb

Bit 14 - - - - - -1

SP30, SP31

Note: Refer to Figure 26-1 for load conditions.

SP36

SP41

MSb In LSb In

Bit 14 - - - -1

SDIx

SP40

PIC24FJ16MC101/102

FIGURE 26-14: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = X, SMP = 1) TIMING

CHARACTERISTICS

TABLE 26-32: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING

REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤TA ≤+125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

SP10 TscP Maximum SCK Frequency — — 10 MHz -40ºC to +125ºC and

see Note 3

SP20 TscF SCKx Output Fall Time — — — ns See parameter DO32

and Note 4

SP21 TscR SCKx Output Rise Time — — — ns See parameter DO31

and Note 4

SP30 TdoF SDOx Data Output Fall T ime — — — ns See parameter DO32

and Note 4

SP31 TdoR SDOx Data Output Rise Time — — — ns See parameter DO31

and Note 4

SP35 TscH2doV,

TscL2doV SDOx Data Output Valid after

SCKx Edge — 6 20 ns —

SP36 TdoV2scH,

TdoV2scL SDOx Data Output Setup to

First SCKx Edge 30 — — ns —

SP40 TdiV2scH,

TdiV2scL Setup Time of SDIx Data

Input to SCKx Edge 30 — — ns —

SP41 TscH2diL,

TscL2diL Hold Time of SDIx Data Input

to SCKx Edge 30 — — ns —

Note 1: These parameters are characterized, but are not tested in manufacturing.

2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

3: The minimum clock period for SCKx is 100 ns. The clock generated in Master mo de must not violate this

specification.

4: Assumes 50 pF load on all SPIx pins.

SCKx

(CKP = 0)

SCKx

(CKP = 1)

SDOx

SDIx

SP10

SP40 SP41

SP21

SP20

SP35

SP20

SP21

MSb LSb

Bit 14 - - - - - -1

MSb In LSb In

Bit 14 - - - -1

SP30, SP31

Note: Refer to Figure 26-1 for load conditions.

PIC24FJ16MC101/102

FIGURE 26-15: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING

CHARACTERISTICS

SSx

SCKx

(CKP = 0)

SCKx

(CKP = 1)

SDOx

SDI

SP50

SP60

SDIx

SP30,SP31

MSb Bit 14 - - - - - -1 LSb

SP51

MSb In Bit 14 - - - -1 LSb In

SP35

SP52

SP73

SP72

SP73

SP70

SP40 SP41

Note: Refer to Figure 26-1 for load conditions.

PIC24FJ16MC101/102

TABLE 26-33: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING

REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 3.0 V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤TA ≤+125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

SP70 TscP Maximum SCK Input Frequency — — 15 MHz See Note 3

SP72 TscF SCKx Input Fall Time — — — ns See parameter DO32

and Note 4

SP73 TscR SCKx Input Rise Time — — — ns See parameter DO31

and Note 4

SP30 TdoF SDOx Data Output Fall Time — — — ns See p arameter DO32

and Note 4

SP31 TdoR SDOx Data Output Rise Time — — — ns See p a rameter DO31

and Note 4

SP35 TscH2doV,

TscL2doV SDOx Data Output Valid af ter

SCKx Edge —620ns —

SP36 TdoV2scH,

TdoV2scL SDOx Data Output Setup to

First SCKx Edge 30 — — ns —

SP40 TdiV2scH,

TdiV2scL Setup Time of SDIx Data Input

to SCKx Edge 30 — — ns —

SP41 TscH2diL,

TscL2diL Hold Time of SDIx Data Input

to SCKx Edge 30 — — ns —

SP50 TssL2scH,

TssL2scL SSx ↓ to SCKx ↑ or SCKx Inpu t 120 — — ns —

SP51 TssH2doZ SSx ↑ to SDOx Output

High-Impedance(4) 10 — 50 ns —

SP52 TscH2ssH

TscL2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4

SP60 TssL2doV SDOx Data Output Valid after

SSx Edge ——50ns —

Note 1: These parameters are characterized, but are not tested in manufacturing.

2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCK clock generated by the Master must

not violate this specification.

4: Assumes 50 pF load on all SPIx pins.

PIC24FJ16MC101/102

FIGURE 26-16: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING

CHARACTERISTICS

SSx

SCKx

(CKP = 0)

SCKx

(CKP = 1)

SDOx

SDI

SP50

SP60

SDIx

SP30,SP31

MSb Bit 14 - - - - - -1 LSb

SP51

MSb In Bit 14 - - - -1 LSb In

SP35

SP52

SP73

SP72

SP73

SP70

SP40 SP41

Note: Refer to Figure 26-1 for load conditions.

PIC24FJ16MC101/102

TABLE 26-34: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING

REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 3.0 V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤TA ≤+125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

SP70 TscP Maximum SCK Input Frequency — — 11 MHz See Note 3

SP72 TscF SCKx Input Fall Time — — — ns See parameter DO32

and Note 4

SP73 TscR SCKx Input Rise Time — — — ns See parameter DO31

and Note 4

SP30 TdoF SDOx Data Output Fall Time — — — ns See p arameter DO32

and Note 4

SP31 TdoR SDOx Data Output Rise Time — — — ns See p a rameter DO31

and Note 4

SP35 TscH2doV,

TscL2doV SDOx Data Output Valid af ter

SCKx Edge —620ns —

SP36 TdoV2scH,

TdoV2scL SDOx Data Output Setup to

First SCKx Edge 30 — — ns —

SP40 TdiV2scH,

TdiV2scL Setup Time of SDIx Data Input

to SCKx Edge 30 — — ns —

SP41 TscH2diL,

TscL2diL Hold Time of SDIx Data Input

to SCKx Edge 30 — — ns —

SP50 TssL2scH,

TssL2scL SSx ↓ to SCKx ↑ or SCKx Inpu t 120 — — ns —

SP51 TssH2doZ SSx ↑ to SDOx Output

High-Impedance(4) 10 — 50 ns —

SP52 TscH2ssH

TscL2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4

SP60 TssL2doV SDOx Data Output Valid after

SSx Edge ——50ns —

Note 1: These parameters are characterized, but are not tested in manufacturing.

2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

3: The minimum clock period for SCKx is 91 ns. Therefore, the SCK clock generated by the Master must not

violate this specification.

4: Assumes 50 pF load on all SPIx pins.

PIC24FJ16MC101/102

FIGURE 26-17: SPIx SLAVE MODE (FULL-DUPLEX CKE = 0, CKP = 1, SMP = 0) TIMING

CHARACTERISTICS

SSX

SCKX

(CKP = 0)

SCKX

(CKP = 1)

SDOX

SP50

SP40 SP41

SP30,SP31 SP51

SP35

MSb LSb

Bit 14 - - - - - -1

MSb In Bit 14 - - - -1 LSb In

SP52

SP73

SP72

SP73

SP70

Note: Refer to Figure 26-1 f or load conditions.

SDIX

PIC24FJ16MC101/102

TABLE 26-35: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING

REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 3.0 V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤TA ≤+125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

SP70 TscP Maximum SCK Input Frequency — — 15 MHz See Note 3

SP72 TscF SCKx Input Fall Time — — — ns See parameter DO32

and Note 4

SP73 TscR SCKx Input Rise Time — — — ns See parameter DO31

and Note 4

SP30 TdoF SDOx Data Output Fall Time — — — ns See p arameter DO32

and Note 4

SP31 TdoR SDOx Data Output Rise Time — — — ns See p a rameter DO31

and Note 4

SP35 TscH2doV,

TscL2doV SDOx Data Output Valid af ter

SCKx Edge —620ns —

SP36 TdoV2scH,

TdoV2scL SDOx Data Output Setup to

First SCKx Edge 30 — — ns —

SP40 TdiV2scH,

TdiV2scL Setup Time of SDIx Data Input

to SCKx Edge 30 — — ns —

SP41 TscH2diL,

TscL2diL Hold Time of SDIx Data Input

to SCKx Edge 30 — — ns —

SP50 TssL2scH,

TssL2scL SSx ↓ to SCKx ↑ or SCKx Inpu t 120 — — ns —

SP51 TssH2doZ SSx ↑ to SDOx Output

High-Impedance(4) 10 — 50 ns —

SP52 TscH2ssH

TscL2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4

Note 1: These parameters are characterized, but are not tested in manufacturing.

2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCK clock generated by the Master must

not violate this specification.

4: Assumes 50 pF load on all SPIx pins.

PIC24FJ16MC101/102

FIGURE 26-18: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING

CHARACTERISTICS

SSX

SCKX

(CKP = 0)

SCKX

(CKP = 1)

SDOX

SP50

SP40 SP41

SP30,SP31 SP51

SP35

MSb LSb

Bit 14 - - - - - -1

MSb In Bit 14 - - - -1 LSb In

SP52

SP73

SP72

SP73

SP70

Note: Refer to Figure 26-1 for load conditions.

SDIX

PIC24FJ16MC101/102

TABLE 26-36: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING

REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 3.0 V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤TA ≤+125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

SP70 TscP Maximum SCK Input Frequency — — 11 MHz See Note 3

SP72 TscF SCKx Input Fall Time — — — ns See parameter DO32

and Note 4

SP73 TscR SCKx Input Rise Time — — — ns See parameter DO31

and Note 4

SP30 TdoF SDOx Data Output Fall Time — — — ns See p arameter DO32

and Note 4

SP31 TdoR SDOx Data Output Rise Time — — — ns See p a rameter DO31

and Note 4

SP35 TscH2doV,

TscL2doV SDOx Data Output Valid af ter

SCKx Edge —620ns —

SP36 TdoV2scH,

TdoV2scL SDOx Data Output Setup to

First SCKx Edge 30 — — ns —

SP40 TdiV2scH,

TdiV2scL Setup Time of SDIx Data Input

to SCKx Edge 30 — — ns —

SP41 TscH2diL,

TscL2diL Hold Time of SDIx Data Input

to SCKx Edge 30 — — ns —

SP50 TssL2scH,

TssL2scL SSx ↓ to SCKx ↑ or SCKx Inpu t 120 — — ns —

SP51 TssH2doZ SSx ↑ to SDOx Output

High-Impedance(4) 10 — 50 ns —

SP52 TscH2ssH

TscL2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4

Note 1: These parameters are characterized, but are not tested in manufacturing.

2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

3: The minimum clock period for SCKx is 91 ns. Therefore, the SCK clock generated by the Master must not

violate this specification.

4: Assumes 50 pF load on all SPIx pins.

PIC24FJ16MC101/102

FIGURE 26-19: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)

FIGURE 26-20: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)

IM31 IM34

SCLx

SDAx

Start

Condition Stop

Condition

IM30 IM33

Note: Refer to Figure 26-1 for load conditions.

IM11 IM10 IM33

IM11 IM10

IM20

IM26 IM25

IM40 IM40 IM45

IM21

SCLx

SDAx

Out

Note: Refer to Figure 26-1 for load conditions.

PIC24FJ16MC101/102

TABLE 26-37: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)

AC CHARACTERISTICS

Standard Operating Conditions : 3.0V to 3.6V

(unless otherwise stated)

Operatin g te mperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min(1) Max Units Conditions

IM10 TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1) — μs—

400 kHz mode TCY/2 (BRG + 1) — μs—

1 MHz mode(2) TCY/2 (BRG + 1) — μs—

IM11 THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1) — μs—

400 kHz mode TCY/2 (BRG + 1) — μs—

1 MHz mode(2) TCY/2 (BRG + 1) — μs—

IM20 TF:SCL SDAx and SCLx

Fall Time 100 kHz mode — 300 ns CB is specified to be

from 10 to 400 pF

400 kHz mode 20 + 0.1 CB300 ns

1 MHz mode(2) — 100 ns

IM21 TR:SCL SDAx and SCLx

Rise Time 100 kHz mode — 1000 ns CB is specified to be

from 10 to 400 pF

400 kHz mode 20 + 0.1 CB300 ns

1 MHz mode(2) — 300 ns

IM25 TSU:DAT Data Input

Setup Time 1 00 kHz mode 250 — ns —

400 kHz mode 100 — ns

1 MHz mode(2) 40 — ns

IM26 THD:DAT Data Input

Hold Time 100 kHz mode 0 — μs—

400 kHz mode 0 0.9 μs

1 MHz mode(2) 0.2 — μs

IM30 TSU:STA Start Condition

Setup Time 1 00 kHz mode TCY/2 (BRG + 1) — μs Only relevant for

Repeated Start

condition

400 kHz mode TCY/2 (BRG + 1) — μs

1 MHz mode(2) TCY/2 (BRG + 1) — μs

IM31 THD:STA Start Condition

Hold Time 100 kHz mode TCY/2 (BRG + 1) — μs After this period the

first clock pulse is

generated

400 kHz mode TCY/2 (BRG + 1) — μs

1 MHz mode(2) TCY/2 (BRG + 1) — μs

IM33 TSU:STO Stop Condition

Setup Time 1 00 kHz mode TCY/2 (BRG + 1) — μs—

400 kHz mode TCY/2 (BRG + 1) — μs

1 MHz mode(2) TCY/2 (BRG + 1) — μs

IM34 THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — ns —

Hold Time 400 kHz mode TCY/2 (BRG + 1) — ns

1 MHz mode(2) TCY/2 (BRG + 1) — ns

IM40 TAA:SCL Output Valid

From Clock 100 kHz mode — 3500 ns —

400 kHz mode — 1000 ns —

1 MHz mode(2) — 400 ns —

IM45 TBF:SDA Bus Free Time 1 00 kHz mode 4.7 — μs T ime the bus must be

free before a new

transmission can start

400 kHz mode 1.3 — μs

1 MHz mode(2) 0.5 — μs

IM50 CBBus Capacitive Loading — 400 pF —

IM51 TPGD Pulse Gobbler Delay 65 390 ns See Note 3

Note 1: BRG is the value of the I2C Baud Rate Generator . Refer to Section 19. “Inter-Integrated Circuit (I2C™)”

(DS70195) in the “PIC24F Family Reference Manual”. Please see the Microchip web site for the latest

PIC24F Family Reference Manua l sections.

2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).

3: Typical value for this parameter is 130 ns.

PIC24FJ16MC101/102

FIGURE 26-21: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)

FIGURE 26-22: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)

IS31 IS34

SCLx

SDAx

Start

Condition Stop

Condition

IS30 IS33

IS30 IS31 IS33

IS11

IS10

IS20

IS26 IS25

IS40 IS40 IS45

IS21

SCLx

SDAx

Out

PIC24FJ16MC101/102

TABLE 26-38: I2Cx BUS DATA T IMING REQUIREMENTS (SLAVE MODE)

AC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param. Symbol Characteristic Min Max Units Conditions

IS10 TLO:SCL Clock Lo w Time 100 kHz mode 4.7 — μs Device must operate at a

minimum of 1.5 MHz

400 kHz mode 1.3 — μs Device must operate at a

minimum of 10 MHz

1 MHz mode(1) 0.5 — μs—

IS11 THI:SCL Clock High Time 100 kHz mode 4.0 — μs Device must operate at a

minimum of 1.5 MHz

400 kHz mode 0.6 — μs Device must operate at a

minimum of 10 MHz

1 MHz mode(1) 0.5 — μs—

IS20 TF:SCL SDAx and SCLx

Fall Time 100 kHz mode — 300 ns CB is specified to be from

10 to 400 pF

400 kHz mode 20 + 0.1 CB300 ns

1 MHz mode(1) — 100 ns

IS21 TR:SCL SDAx and SCLx

Rise Time 100 kHz mode — 1000 ns CB is specified to be from

10 to 400 pF

400 kHz mode 20 + 0.1 CB300 ns

1 MHz mode(1) — 300 ns

IS25 TSU:DAT Data Input

Setup Time 100 kHz mode 250 — ns —

400 kHz mode 100 — ns

1 MHz mode(1) 100 — ns

IS26 THD:DAT Data Input

Hold Ti me 100 kHz mode 0 — μs—

400 kHz mode 0 0.9 μs

1 MHz mode(1) 00.3μs

IS30 TSU:STA Start Condition

Setup Time 100 kHz mode 4.7 — μs On ly relevant for Repeated

Start condition

400 kHz mode 0.6 — μs

1 MHz mode(1) 0.25 — μs

IS31 THD:STA Start Condition

Hold Time 100 kHz mode 4.0 — μs After this period, the first

clock pulse is generated

400 kHz mode 0.6 — μs

1 MHz mode(1) 0.25 — μs

IS33 TSU:STO S top Condition

Setup Time 100 kHz mode 4.7 — μs—

400 kHz mode 0.6 — μs

1 MHz mode(1) 0.6 — μs

IS34 THD:STO Stop Condition

Hold Ti me 100 kHz mode 4000 — ns —

400 kHz mode 600 — ns

1 MHz mode(1) 250 ns

IS40 TAA:SCL Output Valid

From Clock 100 kHz mode 0 350 0 ns —

400 kHz mode 0 1000 ns

1 MHz mode(1) 0 350 ns

IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be free

before a new transmission

can start

400 kHz mode 1.3 — μs

1 MHz mode(1) 0.5 — μs

IS50 CBBus Capacitive Loading — 400 pF —

Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).

PIC24FJ16MC101/102

TABLE 26-39: ADC MODULE SPECIFICATIONS

AC CHARACTERISTICS

Stan dard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min. Typ Max. Units Conditions

Device Supply

AD01 AVDD Module VDD Supply(2,4) Greater of

VDD – 0.3

or 2.9

— Lesser of

VDD + 0.3

or 3.6

V—

AD02 AVSS Module VSS Supply(2,5) VSS – 0.3 — VSS + 0.3 V —

AD09 IAD Operating Current — 7.0 9.0 mA See Note 1

Analog Input

AD12 VINH Input Voltage Range

VINH(2) VINL —AVDD V This voltage reflects Sample

and Hold Channels 0, 1, 2,

and 3 (CH0-CH3), positive

input

AD13 VINL Input Voltage Range

VINL(2) AVSS —AVSS + 1V V This voltage reflects Sample

and Hold Channels 0, 1, 2,

and 3 (CH0-CH3), negative

input

AD17 RIN Recommended Imped-

ance of Analog Voltage

Source(3)

——200Ω—

Note 1: These parameters are not characterized or tested in manufacturing.

2: These parameters are characterized, but are not tested in manufacturing.

3: These parameters are assured by design, but are not characterized or tested in manufacturing.

4: This pin may not be available on all devices, in which case, this pin will be connected to VDD internally.

See the “Pin Diagrams” section for availability.

5: This pin may not be available on all devices, in which case, this pin will be connected to VSS internally . See

the “Pin Diagrams” section for ava ilability.

PIC24FJ16MC101/102

TABLE 26-40: 10-BIT ADC MODULE SPECIFICATIONS

AC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤TA ≤+125°C for Extended

Param

No. Symbol Characteristic Min. Typ Max. Units Conditions

10-bit ADC Accuracy – Measurements with AVDD/AVSS(3)

AD20b Nr Resolution 10 data bits bits —

AD21b INL Integral Nonlinearity -1 — +1 LSb VINL = AVSS = 0V, AVDD = 3.6V

AD22b DNL Differential Nonlinearity >-1 — <1 LSb VINL = AVSS = 0V, AVDD = 3.6V

AD23b GERR Gain Error 3 7 15 LSb VINL = AVSS = 0V, AVDD = 3.6V

AD24b EOFF Offset Error 1.5 3 7 LSb VINL = AVSS = 0V, AVDD = 3.6V

AD25b — Monotonicity — — — — Guaranteed(1)

Dynamic Performance (10-bit Mod e)(2)

AD30b THD Total Harmonic Distortio n — — -64 dB —

AD31b SINAD Signal to Noise and

Distortion 57 58.5 — dB —

AD32b SFDR Spurious Free Dynamic

Range 72 — — dB —

AD33b FNYQ Input Signal Bandwidth — — 550 kHz —

AD34b ENOB Effective Number of Bits 9.16 9.4 — bits —

Note 1: The analog-to-digital conversion result never decreases with an increase in the input voltage, an d has no

missing codes.

2: These parameters are characterized by similarity, but are not teste d in manufacturing.

3: These parameters are characterized, but are tested at 20 ksps only.

PIC24FJ16MC101/102

FIGURE 26-23: ADC CONVERSION TIMING CHARACTERISTICS

(CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000)

FIGURE 26-24: ADC CONVERSION TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0,

ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)

AD55

TSAMP

Clear SAMPSet SAMP

AD61

ADCLK

Instruction

SAMP

AD60

DONE

ADxIF

1 2 3 4 5 6 8 5 6 7

1– Software sets ADxCON. SAMP to start sampling.

2– Sampling starts after discharge period. TSAMP is described in Section 46. “10-bit Analog-to-Digital Converter (ADC)

3– Software clears ADxCON. SAMP to start conversion.

4– Sampling ends, conversion sequence starts.

5– Convert bit 9.

8– One TAD for end of conversion.

AD50

AD55

6– Convert bit 8.

7– Convert bit 0.

Execution

with 4 Simultaneous Conversions” (DS39737) in the “PIC24F Family Reference Manual”.

1 2 3 4 5 6 4 5 6 8

1– Software sets ADxCON. ADON to start AD operation.

2– Sampling starts after discharge period. TSAMP is described in

3– Convert bit 9.

4– Convert bit 8.

5– Convert bit 0.

7 3

6– One TAD for end of conversion.

7– Begin conversion of next channel.

8– Sample for time specified by SAMC<4:0>.

ADCLK

Instruction Set ADON

Execution

SAMP TSAMP

ADxIF

DONE

AD55 AD55 TSAMP AD55

AD50

Section 46. “10-bit Analog-to-Digital Converter (ADC) with 4

Simultaneous Conversions” (DS39737) in the “PIC24F Family

Reference Manual”.

PIC24FJ16MC101/102

TABLE 26-41: 10-BIT ADC CONVERSION TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating C o nditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤TA ≤+125°C for Extended

Param

No. Symbol Characteristic Min. Typ(1) Max. Units Conditions

Clock Parameters(2)

AD50 TAD ADC Clock Period 76 — — ns —

AD51 tRC ADC Internal RC Oscillator Period — 250 — ns —

Conversion Rate

AD55 tCONV Conversion Time — 12 TAD —— —

AD56 FCNV Throughput Rate — — 1.1 Msps —

AD57 TSAMP Sample Time 2.0 TAD ——— —

Timing Parameters

AD60 tPCS Conversion Start from Sample

Trigger(1) 2.0 TAD — 3.0 TAD — Auto-Convert Trigger

(SSRC<2:0> = 111) not

selected

AD61 tPSS Sample Start from Setting

Sample (SAMP) bit(1) 2.0 TAD — 3.0 TAD ——

AD62 tCSS Conversion Completion to

Sample Start (ASAM = 1)(1) — 0.5 TAD —— —

AD63 tDPU Time to Stabilize Analog Stage

from ADC Off to ADC On(1) ——20μs—

Note 1: These parameters are characterized but not tested in manufacturing.

2: Because the sample caps will eventually lose charge, clock rates below 10 kHz may affect linearity

performance, especially at elevated temperatures.

PIC24FJ16MC101/102

TABLE 26-42: COMPARATOR TIMING SPECIFICATIONS

AC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤TA ≤+125°C for Extended

Param

No. Symbol Characteristic Min. Typ Max. Units Conditions

300 TRESP Response Time(1,2) — 150 400 ns —

301 TMC2OV Comparator Mode Change

to Output Valid(1) ——10μs—

302 TON2OV Comparator Enabl ed to

Output Valid(1) ——10µs —

Note 1: Parameters are characterized but not tested.

2: Response time measured with one comparator input at (VDD - 1.5)/2, while the other input transitions from

VSS to VDD.

TABLE 26-43: COMPARATOR MODULE SPECIFICATIONS

DC CHARACTERISTICS

Standard Operating Conditions: 3.0 V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤TA ≤+125°C for Extende d

Param

No. Symbol Characteristic Min. Typ Max. Units Conditions

D300 VIOFF Input Offset Voltage(1) —±10—mV —

D301 VICM Inpu t C ommon Mode Voltage(1) 0—AVDD-1.5V V —

D302 CMRR Common Mode Rejection Ratio(1) -54 — — dB —

D305 IVREF Internal Voltage Reference(1) 1.1161.241.364 V —

Note 1: Parameters are characterized but not tested.

TABLE 26-44: COMPARATOR REFERENCE VOLTAGE SETTLING TIME SPECIFICATIONS

AC CHARACTERISTICS

Standard Operating Conditions: 3.0 V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤TA ≤+125°C for Extended

Param

No. Symbol Characteristic Min. Typ Max. Units Conditions

VR310 TSET Settling Time(1) ——10μs—

Note 1: Setting time measured whi le CVRR = 1 and CVR3:CVR0 bits transition from ‘0000’ to ‘1111’.

TABLE 26-45: COMPARATOR REFERENCE VOLTAGE SPECIFICATIONS

DC CHARACTERISTICS

Standard Operating Conditions:3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤TA ≤+125°C for Extended

Param

No. Symbol Characteristic Min. Typ Max. Units Conditions

VRD310 CVRES Resolution CVRSRC/24 — CVRSRC/32 LSb —

VRD311 CVRAA Absolute Accuracy — — 0.5 LSb —

VRD312 CVRUR Unit Resistor Value (R) — 2k — Ω—

PIC24FJ16MC101/102

FIGURE 26-25: FORWARD VOLTAGE VERSUS TEMPERATURE

TABLE 26-46: CTMU CURRENT SOURCE SPECIFICATIONS

DC CHARACTERISTICS Standard Operating Conditions:3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤TA ≤+125°C for Extended

Param

No. Symbol Characteristic Min. Typ. Max. Units Conditions

CTMU CURRENT SOURCE

CTMUI1 IOUT1 Base Range(1) — 550 — na IR NG<1:0> bits (CTMUICON<9:8>) = 01

CTMUI2 IOUT2 10x Range(1) — 5.5 — µA IRNG<1:0> bits (CTMUICON<9:8>) = 10

CTMUI3 IOUT3 100x Range(1) — 55 — µA IRNG<1:0> bits (CTMUICON<9:8>) = 11

Internal Diode

CTMUFV1 VFForward

Voltage(2) — 0.77 — V IRNG<1:0> bits (CTMUICON<9:8>) = 0b11

@ 25ºC

CTMUFV2 VFVR Forward Voltage

Rate(2) — -1.38 — mV/ºC IRNG<1:0> bi ts (CTMUICON<9:8>) = 0b11

Note 1: Nominal value at center point of current trim range (ITRIM<5:0> bits (CTMUICON<15:10>) = 0b000000).

2: ADC module configured for conversion speed of 500 ksps.Parameters are characterized but not tested in

manufacturing.

0.700

0.750

0.800

0.850

Forward Voltage @ 25ºC

VF = 0.77 Forward Voltage Rate

VFVR = -1.38 mV/ºC

0.500

0.550

0.600

0.650

0.700

0.750

0.800

0.850

0.900

-40

-35

-30

-25

-20

-15

-10

-5

100

105

110

115

120

125

Forward Voltage (V)

Temperature (ºC)

VF @ IOUT = 55 µA

Note: This graph is a statistical summary based on a limited number of samples and this data is characterized but not tested

in manufacturing.

PIC24FJ16MC101/102

NOTES:

PIC24FJ16MC101/102

27.0 PACKAGING INFORMATION

27.1 Package Marking Information

Legend: XX...X Customer-speci fi c in fo rmation

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceabil ity code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: If the full Microchip part number cannot be marked on one line, it is carried over to the next

line, thus limiting the number of available characters for customer-specific information.

20-Lead PDIP

XXXXXXXXXXXXXXXXX

YYWWNNN

Example

PIC24FJ16MC

0730235

20-Lead SSOP

XXXXXXXXXXX

YYWWNNN

Example

PIC24FJ16

MC101-ISS

0730235

101-E/P

20-Lead SOIC

XXXXXXXXXXXXXX

YYWWNNN

Example

PIC24FJ16

MC101-ISO

0610017

PIC24FJ16MC101/102

27.1 Package Marking Information (Continued)

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: If the full Microchip part number cannot be marked on one line, it is carried over to the next

line, thus limiting the number of available characters for customer-specific information.

Example

24FJ16MC

102EML

0730235

28-Lead SSOP

XXXXXXXXXXXX

YYWWNNN

Example

24FJ16MC

102-E/SS

0730235

36-Lead TLA

XXXXXXXX

YYWWNNN

Example

24FJ16MC

102ETL

0730235

28-Lead SPDIP

XXXXXXXXXXXXXXXXX

YYWWNNN

Example

PIC24FJ16MC

0730235

28-Lead SOIC

XXXXXXXXXXXXXXXXXXXX

YYWWNNN

Example

PIC24FJ16MC

0730235

102-E/SP

102-E/SO

28-Lead QFN

XXXXXXXX

YYWWNNN

PIC24FJ16MC101/102

27.2 Package Details

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%DVHWR6HDWLQJ3ODQH $  ± ±

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2YHUDOO/HQJWK '   

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Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

PIC24FJ16MC101/102

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

PIC24FJ16MC101/102

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

PIC24FJ16MC101/102

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6WDQGRII $  ± ±

2YHUDOO:LGWK (   

0ROGHG3DFNDJH:LGWK (   

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A2 c

NOTE 1

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PIC24FJ16MC101/102

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

PIC24FJ16MC101/102

28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP]

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units INCHES

Dimension Limits MIN NOM MAX

Number of Pins N 28

Pitch e .100 BSC

Top to Seating Plane A – – .200

Molded Package Thickness A2 .120 .135 .150

Base to Seating Plane A1 .015 – –

Shoulder to Shoulder Width E .290 .310 .335

Molded Package Width E1 .240 .285 .295

Overall Length D 1.345 1.365 1.400

Tip to Seating Plane L .110 .130 .150

Lead Thickness c .008 .010 .015

Upper Lead Width b1 .040 .050 .070

Lower Lead Width b .014 .018 .022

Overall Row Spacing § eB – – .430

NOTE 1

Microchip Technology Drawing C04-070B

PIC24FJ16MC101/102

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PIC24FJ16MC101/102

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

PIC24FJ16MC101/102

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

PIC24FJ16MC101/102

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

PIC24FJ16MC101/102

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

PIC24FJ16MC101/102

28-Lead Plastic Quad Flat, No Lead Package (ML) – 6x6 mm Body [QFN]

with 0.55 mm Contact Length

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package is saw singulated.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 28

Pitch e 0.65 BSC

Overall Height A 0.80 0.90 1.00

Standoff A1 0.00 0.02 0.05

Contact Thickness A3 0.20 REF

Overall Width E 6.00 BSC

Exposed Pad Width E2 3.65 3.70 4.20

Overall Length D 6.00 BSC

Exposed Pad Length D2 3.65 3.70 4.20

Contact Width b 0.23 0.30 0.35

Contact Length L 0.50 0.55 0.70

Contact-to-Exposed Pad K 0.20 – –

DEXPOSED D2

NOTE 1

TOP VIEW BOTTOM VIEW

PAD

Microchip Technology Drawing C04-105B

PIC24FJ16MC101/102

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KWWSZZZPLFURFKLSFRPSDFNDJLQJ

PIC24FJ16MC101/102

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

PIC24FJ16MC101/102

NOTES:

PIC24FJ16MC101/102

APPENDIX A: REVISION HISTORY

Revision A (February 2011)

This is the initial released version of this document.

Revision B (June 2011)

This revision includes the following global updates:

• All JTAG references have been removed

All other major changes are referenced by their

respective section in Table A-1.

In addition, minor text and formatting changes were

incorporated throughout the docu ment.

TABLE A-1: MAJOR SECTION UPDATES

Section Name Update Description

High-Performance, Ultra Low Cost 16-bit

Microcontrollers The TMS, TDI, TDO, and TCK pin names were removed from these pin

diagrams:

• 28-pin SPDIP/SOIC/SSOP

• 28-pin QFN

• 36-pin TLA

Section 1.0 “Device Overview” Updated the Buffer Type to Digital for the CTED1 and CTED2 pins (see

Table 1-1).

Section 4.0 “Memory Organization” Updated the SR and CORCON SFRs in the CPU Core Register Map

(see Table 4-1).

Updated the SFR Address for IC2CON, IC3B UF, and IC3CON in the

Input Capture Register Map (see Table 4-6).

Added the VREGS bit to the RCON register in the System Control

Section 6.0 “Resets” Added the VREGS bit to the RCON register (see Register 6-1).

Section 8.0 “Oscillat or Config uratio n” Updated the definition for COSC<2:0> = 001 and NOSC<2:0> = 001 in

the OSCCON register (see Register 8-1).

Section 15.0 “Motor Control PWM Mod-

ule” Updated the title for Example 15-1 to include a reference to the

Assembly language.

Added Example 15-2, which provides a C code version of the write-

protected register unlock and fault clearing sequence.

Changed the bit PWMLOCK to PWMKEY in the PWM Key Unlock

Section 19.0 “10-bit Analog-to-Digital

Converter (ADC)” Updated the CH0 section and added Note 2 in both ADC block diagrams

(see Figure 19-1 and Figure 19-2).

Updated the multiplexer values in the ADC Conversion Clo ck Period

Block Diagram (see Figure 19-3.

Added the 01110 bit definitions and updated the 01101 bit definitions

for the CH0SB<4:0> and CH0SA<4:0> bits in the AD1CHS0 register

(see Register 19-5).

Section 22.0 “Charge Time

Measurement Unit (CTMU)” Removed Section 22.1 “Measuring Capacitance”, Section 22.2

“Measuring Time”, and Section 22.3 “Pulse Generation and Delay”

Updated the key features.

Added the CTMU Block Diagram (see Figure 22-1).

Updated the ITRIM<5:0> bit definitions and added Note 1 to the CTMU

Current Control register (see Register 22-3).

PIC24FJ16MC101/102

Section 23.0 “Special Features” Update d bits 5 and 4 of FPOR, modified Note 2, and removed Note 3

from the Configuration Shadow Register Map (se e Table 23-1).

Updated bit 14 of CONFIG1 and removed Note 4 from the Configuration

Flash Words (see Table 23-2).

Updated the PLLKEN Configuration bit description (see Table 23-3).

Added Note 3 to Connections for the On-Chip Voltage Regulato r (see

Figure 23-1).

Section 26.0 “Electrical Characteristics” Updated the Standard Operating Conditions to: 3.0V to 3.6V in all

tables.

Removed the Voltage on VCAP with respect to VSS entry in Absolute

Maximum Ratings(1).

Updated the VDD Range (in Volts) in Operating MIPS vs. Voltage (see

Table 26-1).

Removed parameter DC18 and updated the minimum value for

parameter DC 10 in the DC Temperature and Voltage Specifications

(see Table 26-4).

Updated the Characteristic definiti on and the Typical value for

parameter BO10 in Electrical Characteristics: BOR (see Table 26-5).

Updated Note 2 in the DC Characteristics: Operating Current (IDD) (see

Table 26-6).

Updated Note 2 in the DC Characteristics: Idle Current (IIDLE) (see

Table 26-7).

Updated Note 2 and parameters DC60C and DC61a-DC61d in the DC

Characteristics: Power-Down Current (IPD) (see Table 26-8).

Updated Note 2 in the DC Characteristics: Doze Current (IDOZE) (see

Table 26-9).

Added Note 1 to the Internal Voltage Regulator Specifications (see

Table 26-13).

Updated the Minimum and Maximum values for parameter F20a and the

Typical value for parameter F20b in AC Characteristics: Internal Fast

RC (FRC) Accuracy (see Table 26-18).

Updated the Minimum, Typical, and Maximum values for parameters

F21a and F21b in Internal Low-Power RC (LPRC) Accuracy (see

Table 26-19).

Updated the Minimum, Typical, and Maximum values for parameter

D305 in the Comparator Module Specifications (see Table 26-43).

Added parameters CTMUFV1 and CTMUFV2 and updated Note 1 and

the Conditions for all parameters in the CTMU Current Source

Specifications (see Table 26-46).

Added Forward Voltage Versus Temperature (see Figure 26-25).

TABLE A-1: MAJOR SECTION UPDATES (CONTINUED)

Section Name Update Description

PIC24FJ16MC101/102

INDEX

AC Characteristics ............................................................244

Internal Fast RC (FRC) Accuracy .............................246

Internal Low-Power RC (LPRC) Accuracy................246

Load Conditions........................................................244

ADCInitialization...............................................................173

Key Features.............................................................173

ADC Module

ADC1 Register Map....................................................37

ADC11 Register Map..................................................38

Alternate Interrupt Vector Table (AIVT) ..............................63

Analog-to-Digital Converter (ADC)....................................173

Arithmetic Logic Unit (ALU).................................................26

Assembler

MPASM Assembler...................................................232

Block Diagrams

16-bit Timer1 Module................................................123

Comparator I/O Operating Modes.............................186

Comparator Voltage Reference................................187

Connections for On-Chip Voltage Regulator.............220

CTMU Configurations

Time Measurement...........................................210

Device Clock...............................................................93

Digital Filter Interconnect..........................................188

Input Capture............................................................131

Output Compare .......................................................133

PIC24FJ12MC201/202 ...............................................12

PIC24FJ16MC101/102 CPU Core..............................22

PWM Module ............................................................138

Reset System..............................................................55

Shared Port Structure...............................................107

SPI............................................................................153

Timer2 (16-bit) ..........................................................127

Timer2/3 (32-bit) .......................................................126

UART........................................................................167

User Programmable Blanking Function....................187

Watchdog Timer (WDT)............................................221

C Compilers

MPLAB C18..............................................................232

Charge Time Measurement Unit. See CTMU.

Clock Switching.................................................................100

Enabling....................................................................100

Sequence..................................................................100

Code Examples

Port Write/Read ........................................................108

PWRSAV Instruction Syntax.....................................101

Code Protection ........................................................215, 222

Configuration Bits..............................................................215

Configuration Register Map ..............................................216

Configuring Analog Port Pins............................................108

CPUControl Register..........................................................24

CPU Clocking System.........................................................94

PLL Configuration.......................................................95

Selection.....................................................................94

Sources.......................................................................94

CTMU Module

Customer Change Notification Service............................. 301

Customer Notification Service .......................................... 301

Customer Support............................................................. 301

Data Address Space........................................................... 29

Alignment.................................................................... 29

Memory Map for PIC24FJ16MC101/102 Devices

with 1 KB RAM ................................................... 30

Near Data Space........................................................ 29

Software Stack ........................................................... 44

Width .......................................................................... 29

DC Characteristics............................................................ 236

BOR.......................................................................... 237

I/O Pin Input Specifications ...................................... 242

I/O Pin Output Specifications.................................... 242

Idle Current (IDOZE) .................................................. 241

Idle Current (IIDLE).................................................... 239

Operating Current (IDD) ............................................ 238

Power-Down Current (IPD)........................................ 240

Program Memory...................................................... 243

Temperature and Voltage Specifications.................. 237

Development Support....................................................... 231

Doze Mode ....................................................................... 102

Electrical Characteristics .................................................. 235

AC............................................................................. 244

Equations

Device Operating Frequency...................................... 94

Errata.................................................................................. 10

Flash Program Memory...................................................... 51

Control Registers........................................................ 52

Operations.................................................................. 52

Programming Algorithm.............................................. 52

RTSP Operation......................................................... 52

Table Instructions....................................................... 51

Flexible Configuration....................................................... 215

I/O Ports ........................................................................... 107

Parallel I/O (PIO)...................................................... 107

Write/Read Timing.................................................... 108

I2CAddresses................................................................. 160

Operating Modes...................................................... 159

Registers .................................................................. 159

I2C Module

I2C1 Register Map...................................................... 35

In-Circuit Debugger........................................................... 222

In-Circuit Emulation .......................................................... 215

In-Circuit Serial Programming (ICSP)....................... 215, 222

Input Capture.................................................................... 131

Registers .................................................................. 132

Input Change Notification ................................................. 108

Instruction Addressing Modes ............................................ 44

File Register Instructions............................................ 44

Fundamental Modes Supported................................. 45

MCU Instructions........................................................ 44

Move and Accumulator Instructions ........................... 45

Other Instructions....................................................... 45

Instruction Set

PIC24FJ16MC101/102

Overview...................................................................226

Summary...................................................................223

Instruction-Based Power-Saving Modes...........................101

Idle............................................................................102

Sleep.........................................................................101

Internal RC Oscillator

Use with WDT...........................................................221

Internet Address................................................................301

Interrupt Control and Status Registers................................66

IECx ............................................................................66

IFSx.............................................................................66

INTCON1 ....................................................................66

INTCON2 ....................................................................66

IPCx ............................................................................66

Interrupt Setup Procedures.................................................91

Initialization.................................................................91

Interrupt Disable..........................................................91

Interrupt Service Routine ............................................91

Trap Service Routine ..................................................91

Interrupt Vector Table (IVT) ................................................63

Interrupts Coincident with Power Save Instructions..........102

Memory Organization..........................................................27

Microchip Internet Web Site..............................................301

Motor Control PWM...........................................................137

Motor Control PWM Module

6-Output Register Map................................................35

MPLAB ASM30 Assembler, Linker, Librarian ...................232

MPLAB Integrated Development Environment Software ..231

MPLAB PM3 Device Programmer.....................................234

MPLAB REAL ICE In-Circuit Emulator System.................233

MPLINK Object Linker/MPLIB Object Librarian ................232

Multi-Bit Data Shifter...........................................................26

NVM Module

Open-Drain Configuration.................................................108

Output Compare................................................................133

Packaging .........................................................................277

Details.......................................................................279

Marking.............................................................277, 278

PAD Configuration

Peripheral Module Disable (PMD).....................................102

Pinout I/O Descriptions (table)............................................13

PMD Module

PORTA

PORTB

Power-on Reset (POR).......................................................59

Power-Saving Features.....................................................101

Clock Frequency and Switching................................101

Program Address Space.....................................................27

Construction................................................................46

Data Access from Program Memory Using

Program Space Visibility.....................................49

Data Access from Program Memory Using

Table Instructions............................................... 48

Data Access from, Address Generation ..................... 47

Memory Map............................................................... 27

Table Read Instructions

TBLRDH............................................................. 48

TBLRDL.............................................................. 48

Visibility Operation...................................................... 49

Program Memory

Interrupt Vector........................................................... 28

Organization ............................................................... 28

Reset Vector............................................................... 28

PWM Time Base............................................................... 141

Reader Response............................................................. 302

Real-Time Clock and Calendar................................... 39

Comparator................................................................. 40

Registers

AD1CHS123 (ADC1 Input Channel 1 , 2, 3 Select)... 181

ADxCHS0 (ADCx Input Channel 0 Select ................ 182

ADxCON1 (ADCx Control 1)..................................... 177

ADxCON2 (ADCx Control 2)..................................... 179

ADxCON3 (ADCx Control 3)..................................... 180

ADxCSSL (ADCx Input Scan Select Low)................ 183

ADxPCFGL (ADCx Port Configuration Low)............. 184

CLKDIV (Clock Divisor) .............................................. 98

CMSTAT (Comparator Status) ................................. 189

CMxCON (Comparator Control) ............................... 190

CMxFLTR (Comparator Filter Control) ..................... 196

CMxMSKCON (Comparator Mask Gating Control) .. 194

CMxMSKSRC (Comparator Mask Source Control).. 192

CORCON (Core Control)...................................... 25, 67

CTMUCON (CTMU Control)............................. 211, 212

CTMUCON1 (CTMU Control Register 1).................. 211

CTMUCON1 (CTMU Control Register 2).................. 212

CTMUICON (CTMU Current Control)....................... 213

CVRCON (Comparator Voltage Reference Control) 197

DEVID (Device ID).................................................... 219

DEVREV (Device Revision)...................................... 219

I2CxCON (I2Cx Control)........................................... 161

I2CxMSK (I2Cx Slave Mode Address Mask)............ 165

I2CxSTAT (I2Cx Status)........................................... 163

IEC0 (Interrupt Enable Control 0)............................... 75

IEC1 (Interrupt Enable Control 1)............................... 77

IEC2 (Interrupt Enable Control 2)............................... 78

IEC3 (Interrupt Enable Control 3)............................... 78

IEC4 (Interrupt Enable Control 4)............................... 79

IFS0 (Interrupt Flag Status 0)..................................... 70

IFS1 (Interrupt Flag Status 1)..................................... 72

IFS2 (Interrupt Flag Status 2)..................................... 73

IFS3 (Interrupt Flag Status 3)..................................... 73

IFS4 (Interrupt Flag Status 4)..................................... 74

INTCON1 (Interrupt Control 1).................................... 68

INTCON2 (Interrupt Control 2).................................... 69

INTTREG Interrupt Control and Status Register ........ 90

IPC0 (Interrupt Priority Control 0)............................... 80

IPC1 (Interrupt Priority Control 1)............................... 81

IPC14 (Interrupt Priority Control 14)........................... 86

IPC15 (Interrupt Priority Control 15)........................... 87

IPC16 (Interrupt Priority Control 16)........................... 88

IPC19 (Interrupt Priority Control 19)........................... 89

IPC2 (Interrupt Priority Control 2)............................... 82

IPC3 (Interrupt Priority Control 3)............................... 83

IPC4 (Interrupt Priority Control 4)............................... 84

PIC24FJ16MC101/102

IPC5 (Interrupt Priority Control 5) .. .............................85

IPC7 (Interrupt Priority Control 7) .. .............................85

IPC9 (Interrupt Priority Control 9) .. .............................86

NVMCON (Flash Memory Control) .............................53

NVMKEY (Nonvolatile Memory Key) ..........................54

OCxCON (Output Compare x Control) .....................135

OSCCON (Oscillator Control).....................................96

OSCTUN (FRC Oscillator Tuning)..............................99

PMD1 (Peripheral Module Disable

Control Register 1)............................................103

PMD2 (Peripheral Module Disable

Control Register 2)............................................104

PMD3 (Peripheral Module Disable

Control Register 3)............................................105

PMD4 (Peripheral Module Disable

Control Register 4)............................................105

PWMxCON1 (PWM Control 1)..................................144

PWMxCON2 (PWM Control 2)..................................145

PWMxKEY (PWM Key Unlock Register) ..................152

PxDC1 (PWM Duty Cycle 1)............................... ......151

PxDC2 (PWM Duty Cycle 2)............................... ......151

PxDC3 (PWM Duty Cycle 3)............................... ......151

PxDTCON1 (Dead-Time Control 1) ..........................146

PxDTCON2 (Dead-Time Control 2) ..........................147

PxFLTACON (Fault A Control)..........................148, 149

PxOVDCON (Override Control)................................150

PxSECMP (Special Event Compare)........................143

PxTCON (PWM Time Base Control).........................141

PxTMR (PWM Timer Count Value)...........................142

PxTPER (PWM Time Base Period) ..........................142

RCON (Reset Control)................................................56

RPINR0 (Peripheral Pin Select Input Register 0) .....112

RPINR1 (Peripheral Pin Select Input Register 1) .....112

RPINR11 (Peripheral Pin Select Input Register 11) .115

RPINR18 (Peripheral Pin Select Input Register 18) .116

RPINR21 (Peripheral Pin Select Input Register 21) .117

RPINR3 (Peripheral Pin Select Input Register 3) .....113

RPINR7 (Peripheral Pin Select Input Register 7) .....114

RPINR8 (Peripheral Pin Select Input Register 8) .....115

RPOR0 (Peripheral Pin Select Output Register 0) ...118

RPOR1 (Peripheral Pin Select Output Register 1) ...118

RPOR2 (Peripheral Pin Select Output Register 2) ...119

RPOR3 (Peripheral Pin Select Output Register 3) ...119

RPOR4 (Peripheral Pin Select Output Register 4) ...120

RPOR5 (Peripheral Pin Select Output Register 5) ...120

RPOR6 (Peripheral Pin Select Output Register 6) ...121

RPOR7 (Peripheral Pin Select Output Register 7) ...121

SPIxCON1 (SPIx Control 1)......................................155

SPIxCON2 (SPIx Control 2)......................................157

SPIxSTAT (SPIx Status and Control) .......................154

SR (CPU Status)...................................................24, 67

T1CON (Timer1 Control)................ ..................... ......124

T2CON Control.........................................................128

T3CON Control.........................................................129

TCxCON (Input Capture x Control)...........................132

UxMODE (UARTx Mode)..........................................168

UxSTA (UARTx Status and Control).........................170

Reset

Illegal Opcode.......................................................55, 61

Trap Conflict................................................................60

Uninitialized W Register........................................55, 61

Reset Sequence .................................................................63

Resets.................................................................................55

Serial Peripheral Interface (SPI) .......................................153

Software Reset Instruction (SWR)...................................... 60

Software Simulator (MPLAB SIM) .................................... 233

Software Stack Pointer, Frame Pointer

CALLL Stack Frame................................................... 44

Special Features of the CPU............................................ 215

Special MCU Features........................................................ 21

SPI Module

SPI1 Register Map ..................................................... 36

Symbols Used in Opcode Descriptions ............................ 224

System Control

Temperature and Voltage Specifications

AC............................................................................. 244

Timer1 .............................................................................. 123

Timer2/3 ........................................................................... 125

Timing Characteristics

CLKO and I/O........................................................... 247

Timing Diagrams

10-bit ADC Conversion (CHPS<1:0> = 01, SIMSAM = 0,

ASAM = 0, SSRC<2:0> = 000)......................... 272

10-bit ADC Conversion (CHPS<1:0> = 01, SIMSAM = 0,

ASAM = 1, SSRC<2:0> = 111,

SAMC<4:0> = 00001)....................................... 273

ADC Conversion Timing Characteristics

(CHPS<1:0> = 01, SIMSAM = 0, ASAM = 1,

SSRC<2:0> = 111, SAMC<4:0> = 00001) ....... 272

Brown-out Situations .................................................. 59

External Clock .......................................................... 245

I2Cx Bus Data (Master Mode).................................. 266

I2Cx Bus Data (Slave Mode).................................... 268

I2Cx Bus Start/Stop Bits (Master Mode)................... 266

I2Cx Bus Start/Stop Bits (Slave Mode)..................... 268

Input Capture (CAPx)............................................... 251

Motor Control PWM.................................................. 253

Motor Control PWM Fault..... .................................... 253

OC/PWM .................................................................. 252

Output Compare (OCx) ............................................ 252

Reset, Watchdog Timer, Oscillator Start-up Timer

and Power-up Timer......................................... 248

Timer1, 2 and 3 External Clock................................ 249

Timing Requirements

CLKO and I/O........................................................... 247

External Clock .......................................................... 245

Input Capture............................................................ 251

Timing Specifications

10-bit ADC Requirements......................................... 273

I2Cx Bus Data Requirements (Master Mode)........... 267

I2Cx Bus Data Requirements (Slave Mode)............. 269

Motor Control PWM Requirements........................... 253

Output Compare Requirements................................ 252

PLL Clock................................................................. 246

Reset, Watchdog Timer, Oscillator Start-up Timer,

Power-up Timer and Brown-out Reset

Requirements................................................... 248

Simple OC/PWM Mode Requirements..................... 252

Timer1 External Clock Requirements....................... 249

Timer2 External Clock Requirements....................... 250

Timer3 External Clock Requirements....................... 250

UART Module

UART1 Register Map ................................................. 36

Universal Asynchronous Receiver Tran smitter (UART ) ... 167

Using the RCON Status Bits............................................... 61

PIC24FJ16MC101/102

Voltage Regulator (On-Chip).............................................220

Watchdog Time-out Reset (WDTR) ....................................60

Watchdog Timer (WDT)............................................215, 221

Programming Considerations ...................................221

WWW Address..................................................................301

WWW, On-Line Support......................................................10

PIC24FJ16MC101/102

THE MICROCHIP WEB SITE

Microchip provides online support via our WWW site at

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PIC24FJ16MC101/102

READER RESPONSE

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DS39997BPIC24FJ16MC101/102

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PIC24FJ16MC101/102

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Architecture: 24 = 16-bit Microcontroller

Flash Memory Family: FJ = Flash program memory, 3.3V

Product Group: MC1 = Motor Control family

Pin Count: 01 = 18-pin and 20-pin

02 = 28-pin and 32-pin

Temperature Range: I = -40°C to+8 5°C (Industrial)

E=-40°C to+125°C (Extended)

Package: P = Plastic Dual In-Line - 300 mil body (PDIP)

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Examples:

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memory, 28-pin, Extended temperature,

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Microchip Trademark

Architecture

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Package

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PIC 24 FJ 16 MC1 02 T E / SP - XXX

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