UTS4ACS 165/UTS4ACTS 165 Radiation-Hardened 8-Bit Parallel Shift Registers FEATURES Complementary outputs Direct overriding load (data) inputs Gated clock inputs Parallel-to-serial data conversions 1.2 radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes e Flexible package - 16-pin DIP - 16-lead flatpack DESCRIPTION The UTS4ACS 165 and the UTS4ACTS165 are 8-bit serial shift regis- ters that, when clocked, shift the data toward serial output Qy. Parallel- in access to each stage is provide by eight individual data inputs that are enabled by a low level at the SH/LD input. The devices feature a clock inhibit function and a complemented serial output Qy . Clocking is accomplished by a low-to-high transition of the CLK input while SH/LD is held high and CLK INH is held low. The functions of the CLK and CLK INH (clock inhibit) inputs are interchangeable. Since a low CLK input and a low-to-high transition of CLK INH will also accomplish clocking, CLK INH should be changed to the high level only while the CLK input is high. Parallel loading is disabled when SH/LD is held high. Parallel inputs to the registers are enabled while SH/LD is low independently of the levels of CLK, CLK INH or SER inputs. The devices are characterized over full military temperature range of - 55C to +125C, FUNCTION TABLE INPUTS INTERNAL]OUTPUTS OUTPUTS io NH onkyeen Te Op | Og | Oy | Oy L]|xX]x]xX a...h a b h h H|LI]LI xX x Qa | Qn | Qu | Gr H|L/]T IH xX H | Qa | Qc | H]LI TIL x L | Qa | Qg | Sc H|H|x|x x Qa | Qp | Qu | Oy Note: 1. Q, = The state of the referenced output one setup time prior to the Low-to- High clock transition. PINOUTS 16-Pin DIP Top View SHID[71 16 [7] Vop cuk (]2 = 15{_) CLK INH EC)s wD FOLJa wie eCls 2[)8 HCJ]6 wLia Gi C]7 10(-) SER Vss (| 8 9] Oy 16-Lead Flatpack Top View 16 18 14 13 12 W 10 9 1 2 3 4 6 7 8 LOGIC SYMBOL sHID ek inn 9) CLK SER A B c D E F G g, H 1D a Note: 1. This symbot is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 107 Rad-Hard MSI Logic UT54ACS165/UT54ACTS 165 LOGIC DIAGRAM A B Cc D E F G H ae [ {" " @) I" I? (6) sup {) cux wn 23) cx & s s s s s s s s [2 a c Lobo c Lac c c c Q x (10) a 5 ) D D ID 1D Q SER CO No Ba q Qe Q On Q a 4 Gr R R R RADIATION HARDNESS SPECIFICATIONS ! PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU & SEL Threshold * 80 MeV-cm?/mg Neutron Fluence 1.0E14 nicm Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects, ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS Vpp Supply voltage -0.3 to 7.0 v Vio Voltage any pin -.3 0 Vpp +3 Vv TstG Storage Temperature range -65 to +150 cc Ty Maximum junction temperature +175 C TLs Lead temperature (soldering 5 seconds) +300 oo Qjc Thermal resistance junction to case 20 C/W i DC input current +10 mA Pp Maximum power dissipation 1 WwW Note; 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rad-Hard MSI Logic 108 UT54ACS165/UTS4ACTS 165 RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL DD IN any pin Cc range DC ELECTRICAL CHARACTERISTICS 7 (Vpp = 5.0V 10%: Vs = OV , -55C < Te < +125C) SYMBOL PARAMETER CONDITION MIN MAX UNIT Vit Low-level input voltage 1 ACTS 0.8 v ACS 3Vpp Vin High-level input voltage ! ACTS 5Vpp Vv ACS Ypp In Input leakage current ACTS/ACS Vin = Vpp or Vsg -l 1 HA Vou Low-level output voltage 3 ACTS Ioy,= 8.0mA 0.40 Vv ACS Io. = 100UA 0.25 Vou High-level output voltage 7 ACTS Ion = -8.0mA Vpp Vv ACS Tog = -1L00HA Vpp - 0.25 los Short-circuit output current * 4 ACTS/ACS Vo = Vpp and Vgs -200 200 mA Protal Power dissipation C, = SOpF 2.9 mW/MHz Ippg Quiescent Supply Current Vpp = 5.5V 10 HA Cin Input capacitance 4 f = IMHz @ 0V 15 pF Cour Output capacitance * f = IMHz @ 0V 15 pF Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: Vjjy = Vj_j(min) + 20%, - 0%; Vj, = Vy (max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to Vj,j(min) and Vj; (max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-M-38510, for current density $ 5.0E5 amps/cm/, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF MHz. 4, Not more than one output may be shorted at a time for maximum duration of one second. 5, Capacitance measured for initial qualification and when design changes may affect the value. Capaci is at frequency of 1MHz and a signal amplitude of 50mV mms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose $ 1 E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. inal and Vcg 109 Rad-Hard MSI Logic AC ELECTRICAL CHARACTERISTICS 2 (Vpp = 5.0V 10%; Vgg = OV}, 85C < Te < +125C) UT54ACS 165/UT54ACTS165 SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tpyL CLK or CLK INH to Qy or Oy 2 21 ns pL CLK or CLK INH to Qy or Oy 2 18 ns tpHL SH/LD to Qy or Ou 2 21 ns tL SH/LD to Qy or Oy 2 18 {PHL HtoQy 2 21 ns toy Hto Qy 2 17 ns tpHL Hwy 2 20 ns tpLH Hto Ou 2 18 ns fax Maximum clock frequency 71 MHz tsy Setup time before CLK T or CLK INH T 7 ns SER SH/LD CLK INH or CLK Data setup time before SH/LD ty SER hold time after CLK or CLK INH T 2 ns CLK INH hold time CLK T Hold time for any input after SH/LD tw Minimum pulse width 7 ns CLK or CLK INH high CLK or CLK INH low SHLD Notes: 1, Maximum allowable relative shift equals SOmV. 2. All specifications valid for radiation dose $ }E6 rads(Si). Rad-Hard MSI Logic 110