2002 Microchip Technology Inc. DS21428B-page 1
TC500/A/510/514
Features
• Precision (up to 17-bits) A/D Converter "Front End"
• 3-Pin Control Interface to Microprocessor
• Flexible: User Can Trade-off Conversion Speed
for Resolution
• Single Supply Operation (TC510/TC514)
• 4 Input, Differential Analog MUX (TC514)
• Automatic Input Voltage Polarity Detection
• Low Power Dissipation:
- (TC500/TC500A): 10mΩ
- (TC510/TC514): 18mΩ
• Wide Analog Input Range: ±4.2V (TC500A/TC510)
• Directly Accepts Bipolar and Differential
Input Signals
Applications
• Precision Analog Signal Processor
• Precision Sensor Interface
• High Accuracy DC Measurements
Device Selection Table
Package Types
Part
Number Package Temperature
Range
TC500ACOE 16-Pin SOIC (Wide) 0°C to +70°C
TC500ACPE 16-Pin PDIP (Narrow) 0°C to +70°C
TC500COE 16-Pin SOIC (Wide) 0°C to +70°C
TC500CPE 16-Pin PDIP (Narrow) 0°C to +70°C
TC510COG 24-Pin SOIC (Wide) 0°C to +70°C
TC510CPF 24-Pin PDIP (Narrow) 0°C to +70°C
TC514COI 28-Pin SOIC (Wide) 0°C to +70°C
TC514CPJ 28-Pin PDIP (Narrow) 0°C to +70°C
V
OUT-1
2
3
4
20
19
18
CAP-
5
6
7
8
17
23
22
21
9
10
11
12
24
25
26
27
28
DGND
A
B
C
REF
-
C
INT
C
AZ
BUF
ACOM
CH4-
CH3-
CH2-
TC514COI
TC514CPJ
C
REF
+
V
REF
-
V
REF
+
VDD
OSC
CMPTR OUT
CAP+
16
15
13
14
CH1-
N/C
CH1+
CH2+
CH3+
CH4+
A0
A1
28-Pin SOIC
28-Pin PDIP
24-Pin SOIC
24-Pin PDIP
1
2
3
4
16
15
14
5
6
7
8
13
19
18
17
9
10
11
12
20
21
22
23
24
TC510COG
TC510CPF
CAP-
DGND
A
B
V
DD
OSC
CMPTR OUT
V
IN
+
V
IN
-
N/C
N/C
CAP+
C
REF
-
C
INT
C
AZ
BUF
ACOM
N/C
N/C
N/C
V
OUT
-
C
REF
+
V
REF
+
V
REF
-
1
2
3
4
16
15
14
13
5
6
7
12
11
10
9
8
CMPTR OUT
A
DGND
B
V
DD
V
IN
+
V
IN
–
V
REF
+
BUF
V
SS
C
INT
ACOM
V
REF
C
REF
+
C
REF
–
C
AZ
TC500/
TC500A
CPE
TC500/
TC500A
COE
16 Pin-PDIP
16-Pin SOIC
Precision Analog Front Ends
TC500/A/510/514
DS21428B-page 2
2002 Microchip Technology Inc.
General Description
TheTC500/A/510/514 family are precision analog front
ends that implement dual slope A/D converters having
a maximum resolution of 17-bits plus sign. As a mini-
mum, each device contains the integrator, zero cross-
ing comparator and processor interface logic. The
TC500 is the base (16-bit max) device and requires
both positive and negative power supplies. The
TC500A is identical to the TC500 with the exception
that it has improved linearity, allowing it to operate to a
maximum resolution of 17-bits. The TC510 adds an on-
board negative power supply converter for single sup-
ply operation. The TC514 adds both a negative power
supply converter and a 4 input differential analog
multiplexer.
Each device has the same processor control interface
consisting of3 wires: control inputs(A and B)and zero-
crossing comparator output (CMPTR). The processor
manipulates A, B to sequence the TC5XX through four
phases of conversion: Auto Zero, Integrate, De-inte-
grate and Integrator Zero. During the Auto Zero phase,
offset voltages in the TC5XX are corrected by a closed
loop feedback mechanism.The input voltage is applied
to the integrator during the Integrate phase. This
causes an integrator output dv/dt directly proportional
to the magnitude of the input voltage. The higher the
input voltage, the greater the magnitude of the voltage
stored on the integrator during this phase. At the start
of the De-integrate phase, an external voltage refer-
ence is applied to the integrator and, at the same time,
the external host processor starts its on-board timer.
The processor maintains this state until a transition
occurs on the CMPTR output, at which time the proces-
sor halts its timer. The resulting timer count is the con-
verted analog data. Integrator Zero (the final phase of
conversion) removes any residue remaining in the
integrator in preparation for the next conversion.
The TC500/A/510/514 offer high resolution (up to 17-
bits), superior 50Hz/60Hz noise rejection, low power
operation, minimum I/O connections, low input bias
currents and lower cost compared to other converter
technologies having similar conversion speeds.
Typical Application
Level
Shift
Control Logic
Analog
Switch
Control
Signals
ACOM
V
REF
+
BUF
C
AZ
Buffer Integrator
SW
R
SW
IZ
CMPTR 1
CMPTR 2
CMPTR
Output
DGND
Control Logic
SW
1
TC500
TC500A
TC510
TC514
C
REF
C
REF
+
SW
R
C
REF
-C
AZ
R
INT
C
INT
C
INT
SW
RI-
SW
RI-
SW
RI
+SW
RI
-
SWZ
SW
I
SW
Z
V
SS
OSC
–
+
+
–
–
+
Phase
Decoding
Logic
Polarity
Detection
DC-TO-DC
Converter
(TC510 & TC514)
-
+
A B
0 0 Zero Integrator Output
0 1 Auto-Zero
1 0 Signal Integrate
1 1 Deintegrate
V
REF
-
V
OUT
-
C
OUT
-
1.0µF
1.0µF
V
SS
SW
I
BA
A0 A1
DIF.
MUX
(TC514)
CH1+
CH2+
CH3+
CH4+
CH1-
CH2-
CH3-
CH4-
CAP- CAP+
(TC500
TC500A
)
Converter Sate
2002 Microchip Technology Inc. DS21428B-page 3
TC500/A/510/514
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings*
TC510/TC514 Positive Supply Voltage
(VDD to GND) .........................................+10.5V
TC500/TC500A Supply Voltage
(VDD to VSS) ..............................................+18V
TC500/TC500A Positive Supply Voltage
(VDD to GND) ............................................+12V
TC500/TC500A Negative Supply Voltage
(VSS to GND)................................................-8V
Analog Input Voltage (VIN+orV
IN-) ............VDD to VSS
Logic Input Voltage...............VDD +0.3V to GND - 0.3V
Voltage on OSC:
........................... -0.3V to (VDD +0.3V) for VDD <5.5V
Ambient Operating Temperature Range:
................................................................0°C to +70°C
Storage Temperature Range:.............-65°C to +150°C
*Stresses above those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to the
device. These are stress ratings only and functional
operation of the device at these or any other conditions
above those indicated in the operation sections of the
specifications is not implied. Exposure to Absolute
Maximum Rating conditions for extended periods may
affect device reliability.
TC500/A/510/514 ELECTRICAL SPECIFICATIONS
Electrical Characteristics: TC510/TC514: VDD = +5V, TC500/TC500A: VSS = ±5V unless otherwise specified.
CAZ =C
REF =0.47µF.
Symbol Parameter TA=+25°C TA=0°Cto70°C Unit Test Conditions
Min Typ Max Min Typ Max
Analog
Resolution 60 — — ——— µVNote1
ZSE Zero Scale Error
with Auto Zero Phase —
——
—0.005
0.003 —
—
0.005
0.003 0.012
0.009 % F.S. TC500/510/514
TC500A
ENL End Point Linearity —
—0.005
—0.015
0.010 —
—0.015
0.010 0.060
0.045 %F.S.
%F.S. TC500/510/514,
Note 1, Note 2,
TC500A
NL Best Case Straight
Line Linearity — 0.003 0.008 —
— — % F.S. TC500/510/514,
Note 1, Note 2
— — 0.005 — — — % F.S. TC500A
ZSTC Zero-Scale Temp.
Coefficient ——— — 12µV/°C Over Operating
Temperature Range
SYE Full-Scale Symmetry
Error (Roll-Over Error) —0.01— — 0.03 — % F.S. Note 3
FSTC Full-Scale Tempera-
ture Coefficient ——— — 10 — ppm/°C Over Operating
Temperature Range;
External Reference
TC = 0 ppm/°C
IIN Input Current — 6 — ——— pAV
IN =0V
Note 1: Integrate time ≥66msec, auto zero time ≥ 66msec, VINT (peak) ≈4V.
2: End point linearity at ±1/4, ±1 /2, ±3/4 F.S. after full-scale adjustment.
3: Roll-over error is related to CINT,C
REF,C
AZ characteristics.
TC500/A/510/514
DS21428B-page 4
2002 Microchip Technology Inc.
Analog (Continued)
VCMR Common Mode
Voltage Range VSS +1.5 — VDD –1.5 V
SS +1.5 — V
DD –1.5 V
Integrator Output
Swing VSS +0.9 — VDD –0.9 V
SS +0.9 —VSS +0.9 V
Analog Input Signal-
Range VSS +1.5 — VDD –1.5 V
SS +1.5 —VSS +1.5 V ACOM = GND = 0V
VREF Voltage Reference
Range VSS +1 — VDD –1 V
SS +1 — VDD –1 V V
REF-V
REF+
Digital
VOH Comparator Logic 1,
Output High 4——4——VI
SOURCE =400µA
VOL Comparator Logic 0,
Output Low ——0.4 — — 0.4 V ISINK =2.1mA
VIH Logic 1, Input High
Voltage 3.5 ——3.5——V
VIL Logic 0, Input Low
Voltage ——1——1V
ILLogic Input Current — ———0.3 µALogic1or0
tDComparator Delay — 2— — 3 — µsec
Multiplexer (TC514 Only)
Maximum Input
Voltage -2.5 —2.5 -2.5 — 2.5 V VDD =5V
RDSON Drain/Source ON
Resistance —610 ———kΩVDD =5V
Power (TC510/TC514 Only)
ISSupply Current — 1.8 2.4 — — 3.5 mA VDD =5V,A=1,B=1
PDPower Dissipation — 18 — — — — mW VDD =5V
VDD Positive Supply Oper-
ating Voltage Range 4.5 — 5.5 4.5 — 5.5 V
ROUT Operating Source
Resistance —6085 — —100 ΩIOUT =10mA
Oscillator Frequency — 100 — — — — kHz (Note 3)
IOUT Maximum Current Out — — -10 — — -10 mA VDD =5V
Power (TC500/TC500A Only)
ISSupply Current — 11.5 — — 2.5 mA VS=±5V,A=B=1
PDPower Dissipation — 10 — — — — mW VDD =5V,V
SS =-5V
VDD Positive Supply Oper-
ating Range 4.5 — 7.5 4.5 — 7.5 V
VSS Negative Supply
Operating Range -4.5 — -7.5 - 4.5 — -7.5 V
TC500/A/510/514 ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: TC510/TC514: VDD = +5V, TC500/TC500A: VSS = ±5V unless otherwise specified.
CAZ =C
REF =0.47µF.
Symbol Parameter TA=+25°C TA=0°Cto70°C Unit Test Conditions
Min Typ Max Min Typ Max
Note 1: Integrate time ≥66msec, auto zero time ≥ 66msec, VINT (peak) ≈4V.
2: End point linearity at ±1/4, ±1 /2, ±3/4 F.S. after full-scale adjustment.
3: Roll-over error is related to CINT,C
REF,C
AZ characteristics.
2002 Microchip Technology Inc. DS21428B-page 5
TC500/A/510/514
2.0 PIN DESCRIPTIONS
ThedescriptionsofthepinsarelistedinTable2-1.
TABLE 2-1: PIN FUNCTION TABLE
Pin Number
(TC500,
TC500A)
Pin
Number
(TC510)
Pin
Number
(TC514) Symbol Description
122C
INT Integrator output. Integrator capacitor connection.
2 Not Used Not Used VSS Negative power supply input (TC500/TC500A only).
333C
AZ Auto Zero input. The Auto Zero capacitor connection.
4 4 4 BUF Buffer output. The Integrator capacitor connection.
5 5 5 ACOM This pin is grounded in most applications. It is recommended that ACOM and the
input common pin (Ven-orCH
n-) be within the analog common mode range (CMR).
666C
REF- Input. Negative reference capacitor connection.
777C
REF+ Input. Positive reference capacitor connection.
888V
REF- Input. External voltage reference (-) connection.
999V
REF+ Input. External voltage reference (+) connection.
10 15 Not Used VIN- Negative analog input.
11 16 Not Used VIN+ Positive analog input.
12 18 22 A Input. Converter phase control MSB. (See input B.)
13 17 21 B Input. Converter phase control LSB. The states of A, B place the TC5XX in one of
four required phases. A conversion is complete when all four phases have been
executed:
Phase control input pins: AB = 00: Integrator Zero
01: Auto Zero
10: Integrate
11: De-integrate
14 19 23 CMPTR
OUT Zero crossing comparator output. CMPTR is HIGH during the Integration phase
when a positive input voltage is being integrated and is LOW when a negative input
voltage is being integrated. A HIGH-to-LOW transition on CMPTR signals the pro-
cessor that the De-integrate phase is completed. CMPTR is undefined during the
Auto Zero phase. It should be monitored to time the Integrator Zero phase.
15 23 27 DGND Input. Digital ground.
16 21 25 VDD Input. Power supply positive connection.
22 26 CAP+ Input. Negative power supply converter capacitor (+) connection.
24 28 CAP- Input. Negative power supply converter capacitor (-) connection.
11V
OUT- Output. Negative power supply converter output and reservoir capacitor connection.
This output can be used to power other devices in the circuit requiring a negative
bias voltage.
20 24 OSC Oscillator control input. The negative power supply converter normally runs at a fre-
quency of 100kHz. The converter oscillator frequency can be slowed down
(to reduce quiescent current) by connecting an external capacitor between this pin
and VDD (see Section 9.0, Typical Characteristics Curves).
18 CH1+ Positive analog input pin. MUX channel 1.
13 CH1- Negative analog input pin. MUX channel 1.
17 CH2+ Positive analog input pin. MUX channel 2.
12 CH2- Negative analog input pin. MUX channel 2.
16 CH3+ Positive analog input pin. MUX channel 3.
11 CH3- Negative analog input pin. MUX channel 3.
15 CH4+ Positive analog input pin. MUX channel 4.
10 CH4- Negative analog input pin. MUX channel 4
20 A0 Multiplexer input channel select input LSB (see A1).
19 A1 Multiplexer input channel select input MSB.
Phase control input pins: A1, A0 = 00 = Channel 1
01 = Channel 2
10 = Channel 3
11 = Channel 4
TC500/A/510/514
DS21428B-page 6
2002 Microchip Technology Inc.
3.0 DETAILED DESCRIPTION
3.1 Dual Slope Conversion Principles
Actual data conversion is accomplished in two phases:
input signal Integration and reference voltage
De-integration.
The integrator outputis initialized to 0V prior to the start
of Integration. During Integration, analog switch S1
connects VIN to the integrator input where it is main-
tained for a fixed time period (TINT). The application of
VIN causes the integrator output to depart 0V at a rate
determined by the magnitude of VIN and a direction
determined by the polarity of VIN. The De-integration
phase is initiated immediately at the expiration of TINT.
During De-integration, S1 connects a reference voltage
(having a polarity opposite that of VIN) to the integrator
input. At the same time, an external precision timer is
started. The De-integration phase is maintained until
the comparator output changes state, indicating the
integrator has returned to its starting point of 0V. When
this occurs, the precision timer is stopped. The De-inte-
gration time period (TDEINT),as measured by the preci-
sion timer, is directly proportional to the magnitude of
the applied input voltage (see Figure 3-3).
A simple mathematical equation relates the Input Sig-
nal, Reference Voltage and Integration time:
EQUATION 3-1:
For a constant VIN:
EQUATION 3-2:
The dual slope converter accuracy is unrelated to the
integrating resistor and capacitor values as long as
they are stable during a measurement cycle.
An inherent benefit is noise immunity. Input noise
spikes are integrated (averaged to zero) during the
integration periods. Integrating ADCs are immune to
the large conversion errors that plague successive
approximation converters in high noise environments.
Integrating converters provide inherent noise rejection
with at least a 20dB/decade attenuation rate. Interfer-
ence signals with frequencies at integral multiples of
the integration period are, theoretically, completely
removed, since the average value of a sine wave of
frequency (1/T) averaged over a period (T) is zero.
Integrating converters often establish the integration
period to reject 50/60Hz line frequency interference
signals. The ability to reject such signals is shown by a
normal mode rejection plot (Figure 3-1). Normal mode
rejection is limited in practice to 50 to 65dB, since the
line frequency can deviate by a few tenths of a percent
(Figure 3-2).
FIGURE 3-1: INTEGRATING
CONVERTER NORMAL
MODE REJECTION
FIGURE 3-2: LINE FREQUENCY
DEVIATION
1
RINTCINT
VREFTDEINT
RINTCINT
TINT
0VIN(T)DT =
∫
Where:
VREF = Reference Voltage
TINT = Signal Integration time (fixed)
tDEINT = Reference Voltage Integration time (variable)
VIN =V
REF TDEINT
TINT
30
20
10
0
0.1/T 1/T 10/
T
Input Frequency
Normal Mode Rejection (dB)
T = Measurment
Period
0.01 0.1 1.0
Normal Mode Rejeciton (dB)
80
70
60
50
40
30
20
t = 0.1 sec
Line Frequency Deviation from 60 Hz (%)
Normal Mode
REJECTION
= 20 LOG
DEV = Deviation from 60Hz
t = Integration Period
SIN 60 t (1 ± )
p
p
DEV
100
DEV
100
60 t (1 ± )
2002 Microchip Technology Inc. DS21428B-page 7
TC500/A/510/514
FIGURE 3-3: BASIC DUAL SLOPE CONVERTER
Phase
Control
Comparator
Integrator
Output
Integrator
CINT
Analog
Input (V
IN
)
Switch Driver
REF
VOLTAGE
Control
Logic
Polarity Control
S1
I/O
Timer
Counter
ROM
RAM
Microcomputer
AB
CMPTR Out
V
SUPPLY
±
T
INT
TC510
V
INT
V
IN
≈ V
REF
V
IN
≈ 1/2 V
REF
T
DEINT
–
+
RINT
VINT
–
+
TC500/A/510/514
DS21428B-page 8
2002 Microchip Technology Inc.
4.0 TC500/A/510/514 CONVERTER
OPERATION
The TC500/A/510/514 incorporates an Auto Zero and
Integrator phase in addition to the input signal Integrate
and reference De-integrate phases. The addition of
these phases reduce system errors, calibration steps
and shorten overrange recovery time. A typical mea-
surement cycle uses all four phases in the following
order:
1. Auto Zero
2. Input signal integration
3. Reference deintegration
4. Integrator output zero
The internal analog switch status for each of these
phases is summarized in Table 4-1. This table
references the Typical Application.
TABLE 4-1: INTERNAL ANALOG GATE STATUS
4.1 Auto Zero Phase (AZ)
During this phase, errors due to buffer, integrator and
comparator offset voltages are nulled out by charging
CAZ (auto zero capacitor) with a compensating error
voltage.
The external inputsignal is disconnected from the inter-
nal circuitry by opening the two SWIswitches. The
internal input points connect to analog common. The
reference capacitor is charged to the reference voltage
potential through SWR. A feedback loop,closed around
the integrator and comparator, charges the CAZ capac-
itor with a voltage to compensate for buffer amplifier,
integrator and comparator offset voltages.
4.2 Analog Input Signal Integration
Phase (INT)
The TC5XX integrates the differential voltage between
the (VIN+) and (VIN–) inputs. The differential voltage
must be within the device's Common mode range
VCMR. The input signal polarity is normally checked via
software at the end of this phase: CMPTR = 1 for
positive polarity; CMPTR = 0 for negative polarity.
4.3 Reference Voltage De-integration
Phase (DINT)
The previously charged reference capacitor is con-
nected with the proper polarity to ramp the integrator
output back to zero. An externally-provided, precision
timer is used to measure the duration of this phase.
The resulting time measurement is proportional to the
magnitude of the applied input voltage.
4.4 Integrator Output Zero Phase (IZ)
This phase ensures the integrator output is at 0V when
the Auto Zero phase is entered and that only system
offset voltages are compensated. This phase is used at
the end of the reference voltage de-integration phase
and MUST be used for ALL TC5XX applications having
resolutions of 12-bits or more. If this phase is not used,
the value of the Auto Zero capacitor (CAZ)mustbe
about 2 to 3 times the value of the Integration capacitor
(CINT) to reduce the effects of charge sharing. The Inte-
grator Output Zero phase should be programmed to
operate until the output of the comparator returns
"HIGH". The overall timing system is shown in
Figure 4-1.
Conversion Phase SWISWR+SW
R-SW
ZSWRSW1SWIZ
Auto Zero (A = 0, B = 1) Closed Closed Closed
Input Signal Integration (A = 1, B = 0) Closed
Reference Voltage De-integration
(A =1, B = 1) Closed* Closed
Integrator Output Zero (A = 0, B = 0) Closed Closed Closed
Note: *Assumes a positive polarity input signal. SW–RI would be closed for a negative input signal.
2002 Microchip Technology Inc. DS21428B-page 9
TC500/A/510/514
FIGURE 4-1: TYPICAL DUAL SLOPE A/D CONVERTER SYSTEM TIMING
Auto-Zero Integrate
Full Scale Input
Reference
De-integrate Overshoot Integrator
Output
Zero
Converter Status
T
TIME
Integrator
Voltage
Comparator
Output
AB Inputs
Controller
Operation
Notes:
Comparator Delay
Begin Conversion with
Auto-Zero Phase
(Positive Input Shown)
Sample Input Polarity
The length of this phase is chosen almost arbitrarily
but needs to be long enough to null out worst case errors
(see text).
Minimizing
Overshoot
will Minimize
I.O.Z. Time
Ready for Next
Conversion
(Auto-Zero is
Idle State)
Time Input
Integration
Phase
Capture
De-integration
Time
I
ntegrator
Output
Zero Phase
Complete
Undefined
A = 0
B = 1
A = 1
0 For Negative Input
1 For Postive Input
B = 0 B = 1 B = 0
A = 1 A = 0
V
INT
Typically = T
INT
T
INT
0
A
B
Comparator Delay +
Processor Latency
TC500/A/510/514
DS21428B-page 10
2002 Microchip Technology Inc.
5.0 ANALOG SECTION
5.1 Differential Inputs (VIN+,V
IN–)
The TC5XX operates with differential voltages within
the input amplifier Common mode range. The amplifier
Common mode range extends from 1.5V below posi-
tive supply to 1.5V above negative supply. Within this
Common mode voltage range, Common mode rejec-
tion is typically 80dB. Full accuracy is maintained, how-
ever, when the inputs are no less than 1.5V from either
supply.
The integrator output also follows the Common mode
voltage. The integrator output must not be allowed to
saturate. A worst case condition exists, for example,
when a large, positive Common mode voltage, with a
near full scale negative differential input voltage, is
applied. The negative input signal drives the integrator
positive when most of its swing has been used up by
the positive Common mode voltage. For these critical
applications, the integrator swing can be reduced. The
integrator outputcan swing within 0.9V of either supply
without loss of linearity.
5.2 Analog Common
Analog common is used as VIN return during system
zero andreference de-integrate. If VIN– is differentfrom
analog common, a Common mode voltage exists in the
system. This signal is rejected by the excellent CMR of
the converter. In most applications, VIN–willbesetata
fixed known voltage (i.e., power supply common). A
Common mode voltage will exist when VIN– is not
connected to analog common.
5.3 Differential Reference
(VREF+,V
REF–)
The reference voltage can be anywhere within 1V of
the power supply voltage of the converter. Rollover
error is caused by the reference capacitor losing or
gaining charge due to stray capacitance on its nodes.
The difference in reference for (+) or (-) input voltages
will cause a rollover error. This error can be minimized
by using a large reference capacitor in comparison to
the stray capacitance.
5.4 Phase Control Inputs (A, B)
The A, B unlatched logic inputs select the TC5XX oper-
ating phase. The A, B inputs are normally driven by a
microprocessor I/O port or external logic.
5.5 Comparator Output
By monitoring the comparator output during the fixed
signal integrate time, the input signal polarity can be
determined by the microprocessor controlling the
conversion. The comparator output is HIGH for positive
signals and LOW for negative signals during the signal
integrate phase (see Figure 5-1).
During the reference de-integrate phase, the compara-
tor output will make a HIGH-to-LOW transition as the
integrator output ramp crosses zero. The transition is
used to signal the processor that the conversion is
complete.
The internal comparator delay is 2µsec, typically.
Figure 5-1 shows the comparator output for large
positive and negative signal inputs. For signal inputs at
or near zero volts, however, the integrator swing is very
small.If Common mode noise is present, the compara-
tor can switch several times during the beginning ofthe
signal integrate period. To ensure that the polarity
reading is correct, the comparator output should be
read and stored at the end of the signal integrate
phase.
The comparator output is undefined during the Auto
Zero phase and is used to time the Integrator Output
Zero phase. (See Section 7.6, Integrator Output Zero
Phase).
FIGURE 5-1: COMPARATOR OUTPUT
Integrator
Output
Zero
Crossing
Comparator
Output
Reference
De-integrate
Signal
Integrate
Integrator
Output
Zero
Crossing
Comparator
Output
Reference
Deintegrate
Signal
Integrate
B. Ne
g
ative Input Si
g
nalA. Positive Input Si
g
nal
2002 Microchip Technology Inc. DS21428B-page 11
TC500/A/510/514
6.0 TYPICAL APPLICATIONS
6.1 Component Value Selection
The procedure outlined below allows the user to arrive
at values for the following TC5XX design variables:
1. Integration Phase Timing
2. Integrator Timing Components (RINT,C
INT)
3. Auto Zero and Reference Capacitors
4. Voltage Reference
6.2 Select Integration Time
Integration time must be picked as a multiple of the
periodof the line frequency. For example, TINT times of
33msec, 66msec and 132msec maximize 60Hz line
rejection.
6.3 DINT and IZ Phase Timing
The duration of the DINT phase is a function of the
amount of voltage stored on the integrator during TINT
and the value of VREF. The DINT phase must be initi-
ated immediately following INT and terminated when
an integrator output zero-crossing is detected. In gen-
eral, the maximum number of counts chosen for DINT
istwicethatofINT(withV
REF chosen at VIN(MAX) /2).
6.4 Calculate Integrating Resistor
(RINT)
The desired full scale input voltage and amplifier output
current capability determine the value of RINT.The
buffer and integrator amplifiers each have a full-scale
currentof20µA.
The value of RINT is therefore directly calculated in the
following equation:
EQUATION 6-1:
6.5 Select Reference (CREF)andAuto
Zero (CAZ) Capacitors
CREF and CAZ must be low leakage capacitors (such as
polypropylene). The slower the conversion rate, the
larger the value CREF must be. Recommended capac-
itors for CREF and CAZ are shown in Table 6-1. Larger
values for CAZ and CREF mayalsobeusedtolimit
rollover errors.
TABLE 6-1: CREF AND CAZ SELECTION
6.6 Calculate Integrating Capacitor
(CINT)
The integrating capacitor must be selected to maximize
integrator output voltage swing. The integrator output
voltage swing is defined as the absolute value of VDD
(or VSS)less0.9V(i.e.,IV
DD - 0.9VI or IVSS +0.9VI).
Using the 20µA buffer maximum output current, the
value ofthe integrating capacitor iscalculated using the
following equation.
EQUATION 6-2:
It is critical that the integrating capacitor has a very low
dielectric absorption. Polypropylene capacitors are an
example ofone such dielectic. Polyester and Polybicar-
bonate capacitors may also be used in less critical
applications. Table 6-2 summarizes recommended
capacitors for CINT.
TABLE 6-2: RECOMMENDED CAPACITOR
FOR CINT
6.7 Calculate VREF
The reference deintegration voltage is calculated using
the following equation:
EQUATION 6-3:
VIN(MAX)
20
RINT(in MΩ)=
Where:
VIN(MAX) = Maximum input voltage (full count voltage)
RINT = Integrating Resistor (in MΩ)
For loop stability, RINT should be ≥ 50kΩ.
Conversions
Per Second Typical Value of
CREF,C
AZ (µF) Suggested* Part
Number
>7 0.1 SMR5 104K50J01L4
2 to 7 0.22 SMR5 224K50J02L4
2 or less 0.47 SMR5 474K50J04L4
Note: Manufactured by Evox-Rifa, Inc.
Value Suggested Part Number*
0.1 SMR5 104K50J01L4
0.22 SMR5 224K50J02L4
0.33 SMR5 334K50J03L4
0.47 SMR5 474K50J04L4
Note: Manufactured by Evox-Rifa, Inc.
CINT =(VS-0.9)
(TINT)(20x10-6)µF
Where:
TINT = Integration Period
VS=IV
DDIorIV
SSI, whichever is less (TC500/A
VS=IV
DDI (TC510, TC514)
(VS–0.9)(C
INT)(R
INT)
VREF =2(RINT)V
TC500/A/510/514
DS21428B-page 12
2002 Microchip Technology Inc.
7.0 DESIGN CONSIDERATIONS
7.1 Noise
The threshold noise (NTH) is the algebraic sum of the
integrator noise and the comparator noise. This value
istypically30µV.Figure 7-1 shows how the value of the
reference voltage can affectthe finalcount.Such errors
can be reduced by increased integration times, in the
same way that 50/60Hz noise is rejected. The signal-
to-noise ratio is related to the integration time (TINT)
and the integration time constant (RINT) (CINT)asfol-
lows:
EQUATION 7-1:
7.2 System Timing
To obtain maximum performance from the TC5XX, the
overshoot at the end of the De-integration phase must
be minimized. Also, the Integrator Output Zero phase
must be terminated as soon as the comparator output
returns high. (See Figure 4-1).
Figure 4-1 shows the overall timing for a typical system
in which a TC5XX is interfaced to a microcontroller. The
microcontroller drives the A, B inputs with I/O lines and
monitors the comparator output, CMPTR, using an I/O
line or dedicated timer capture control pin. It may be
necessary to monitor the state of the CMPTR output in
addition to having it control a timer directly for the Ref-
erence De-integration phase. (This is further explained
below.)
The timing diagram in Figure 4-1 is not to scale, as the
timing in a real system depends on many system
parameters and component value selections. There
are four critical timing events (as shown in Figure 4-1):
sampling the input polarity; capturing the de-integration
time; minimizing overshoot and properly executing the
Integrator Output Zero phase.
7.3 Auto Zero Phase
The length of this phase is usually set to be equal to the
Input Signal Integration time. This decision is virtually
arbitrary since the magnitudes of the various system
errors are not known. Setting the Auto Zero time equal
to the Input Integrate time should be more than
adequate to null out system errors. The system may
remain in this phase indefinitely (i.e., Auto Zero is the
appropriate Idle state for a TC5XX device).
7.4 Input Signal Integrate Phase
The length of this phase is constant from one conver-
sion to the next and depends on system parameters
and component value selections. The calculation of
TINT is shown elsewhere in this data sheet. At some
point near the end of this phase, the microcontroller
should sample CMPTR to determine the input signal
polarity. This value is, in effect, the Sign Bit for the over-
all conversion result. Optimally, CMPTR should be
sampled just before this phase is terminated by chang-
ing AB from 10 to 11. The consideration here is that,
during the initial stage of input integration when the
integrator voltage is low, the comparator may be
affected by noise and its output unreliable. Once inte-
gration is well underway, the comparator will be in a
defined state.
7.5 Reference De-integration
The length of this phase must be precisely measured
from the transition of AB from 10 to 11 to the falling
edge of CMPTR. The comparator delay contributes
some error in timing this phase. The typical delay is
specifiedtobe2µsec. This should be considered in the
context of the length of a single count when
determining overall system performance and possible
single count errors. Additionally, Overshoot willresult in
charge accumulating on the integrator after its output
crosses zero. This charge must be nulled during the
Integrator Output Zero phase.
VIN tINT
30 x 10–6(RINT)•(C
INT)
S/N (dB) = 20 Log •
()
2002 Microchip Technology Inc. DS21428B-page 13
TC500/A/510/514
FIGURE 7-1: NOISE THRESHOLD
7.6 Integrator Output Zero Phase
The comparator delay and the controller's response
latency may result in overshoot, causing charge
buildup on the integrator at the end of a conversion.
This charge must be removed or performance will
degrade. The Integrator Output Zero phase should be
activated (AB = 00) until CMPTR goes high. It is abso-
lutely criticalthat this phase be terminated immediately
so that Overshoot is not allowed to occur in the oppo-
site direction. At this point, it can be assured that the
integrator is near zero. Auto Zero should be entered
(AB = 01) and the TC5XX held in this state untilthe next
cycle is begun (see Figure 7-2).
FIGURE 7-2: OVERSHOOT
7.7 Using the TC510/TC514
7.7.1 NEGATIVE SUPPLY VOLTAGE
CONVERTER (TC510, TC514)
A capacitive chargepump is employed to invert the volt-
age on VDD for negative bias within the TC510/TC514.
Thisvoltage is also available on the VOUT- pin to provide
negative bias elsewhere in the system. Two external
capacitors are required to perform the conversion.
Timing is generated by an internal state machine driven
from an on-board oscillator. During the first phase,
capacitor CFis switched across the power supply and
charged to VS+. This charge is transferred to capacitor
COUT- during the second phase. The oscillator normally
runs at 100kHz to ensure minimum output ripple. This
frequency can be reduced by placing a capacitor from
OSC to VDD. The relationship between the capacitor
value is shown in Section 9.0.
7.7.2 ANALOG INPUT MULTIPLEXER
(TC514)
The TC514 is equipped with a four input differential
analog multiplexer. Input channels are selected using
select inputs (A1, A0). These are high-true control sig-
nals (i.e., channel 0 is selected when (A1, A0 = 00).
LowREF Normal VREF High VREF
S
NTH
S
NTH
30 µV
S
NTH
Slope (S) = NTH = Noise Threshold
VREF
RINT CINT
Integrator
Output
Comparator
Output Comp
Integrate
Phase
De-integrate Phase
Integrator
Zero Phase
Zero
Crossing
Overshoot
TC500/A/510/514
DS21428B-page 14
2002 Microchip Technology Inc.
8.0 DESIGN EXAMPLE
(SEE FIGURES 8-1 TO 8-4)
Given: Required Resolution: (16 Bits (65,536
counts).
Maximum VIN:±2V
Power Supply Voltage: +5V
60Hz System
Step 1: Pickintegration time (tINT) as a multiple of the
line frequency:
1/60Hz = 16.6msec. Use 4x line frequency
=66msec
Step 2: Calculate RINT
RINT =V
IN(MAX) /20µA2/20µA = 100kΩ
Step 3: Calculate CINT for maximum (4V) integrator
output swing:
CINT =(t
INT)(20x10–6)/(V
S-0.9)
= (.066) (20 x 10 –6)/(4.1)
= .32µF (use closest value: 0.33µF)
Note: Microchip recommended capacitor:
Evox-Rifa p/n: 5MR5 334K50J03L4.
Step 4: Choose CREF and CAZ based on conversion
rate:
Conversions/sec:
=1/(T
AZ +T
INT +2T
INT +2msec)
= 1/(66msec +66msec
+132msec +2msec)
= 3.7 conversions/sec
From which CAZ =C
REF =0.22µF
(see Table 6-1)
Note: Microchip recommended capacitor:
Evox-Rifa p/n: 5MR5 224K50J02L4
Step 5: Calculate VREF
EQUATION 8-1:
(VS-0.9)(C
INT)(R
INT)
VREF =2(TINT)
=(4.1)(0.33x1
–6)(10
5) / 2(.066)
= 1.025V
2002 Microchip Technology Inc. DS21428B-page 15
TC500/A/510/514
FIGURE 8-1: TC510 DESIGN SAMPLE
FIGURE 8-2: TC514 DESIGN EXAMPLE
Microcontroller
INPUT+
INPUT–
+5V
+5V
Pin 2
Pin 19
Pin 2
Pin 19
C
INT
0.33µF
V
IN
+
Typical Waveforms
1µF
1µF
C
AZ
0.22µF
CREF
V
IN
-
R
INT
100k
1
2
3
4
16
15
CAP-
5
6
7
9
19
18
17
8
21
22
23
24
DGND
V
REF
-
V
OUT-
A
B
C
REF
-
C
INT
CAZ
BUF
ACOM
TC510
V
REF
+V
IN
+
V
IN
-
CAP+
V
DD
CMPTR
0.22µF
C1
0.01µF
R2
10k
+5V
R3, 10k
MCP1525
1µF
C
REF
+
Microcontroller
+5V
5V
+
PIN 2
PIN 23
PIN 2
PIN 23
CINT
0.33µF
VIN+
Typical Waveforms
1µF 1µF
CAZ
0.22µF
CREF
0.22µF
VIN
RINT
100k
1
2
3
4
CAP-
5
6
7
23
22
21
25
26
27
28
DGND
VOUT-
A
B
CREF-
CINT
CAZ
BUF
ACOM
TC514
CAP+
VDD
CMPTR
Analog
Mux Logic
INPUT 1+
INPUT 1–
INPUT 2+
INPUT 2–
INPUT 3+
INPUT 3–
INPUT4+
INPUT4–
18
13
A1
CH1+
17
12
CH2+
CH2–
16
11
CH3+
CH3–
15
10
CH4+
CH4–
22
19
A0
CH1–
9
8
C1, .01µF
1µF10k
10k
+5V
MCP1525
CREF+
VREF+
VREF-
TC500/A/510/514
DS21428B-page 16
2002 Microchip Technology Inc.
FIGURE 8-3: TC510 TO IBM®COMPATIBLE PRINTER PORT
PC
Printer
Port
PORT
0378
HEX
Input
+
–
+5V
10k
10k
100kΩ
100kΩ
1µF
1µF
121
2
23
3
4
16
15
CAP-
5
6
7
8
19
10
18
17
9
22
23
24
DGND
V
OUT
-V
DD
A
B C
INT
C
AZ
BUF
ACOM
TC510
C
REF
+
V
IN
+
CAP+
CMPTR
0.22µF
0.22µF
0.01µF
0.01µF
1µF
0.33µF
MCP1525
C
REF
-
V
REF
+
V
REF
-
V
IN
-
2002 Microchip Technology Inc. DS21428B-page 17
TC500/A/510/514
FIGURE 8-4: TC514 TO IBM COMPATIBLE PRINTER PORT
IBM
Printer Port
Port
0378
Hex
+5V
10kΩ
100kΩ
1µF
1µF
1
25
2
23
3
4
CAP–
5
6
7
8
23
10
22
21
9
26
27
28
DGND
V
OUT
V
DD
A
B
C
REF+
TC514
–
BUF
0.22µF
10k
10k
0.22µF
0.01µF
0.33µF
CH1+
Input 1
+18
–13
Input 2
+17
–12
Input 3
+16
–11
Input 4
+15
–10
CAP+
C
REF-
V
REF
+
V
REF-
C
AZ
C
INT
ACOM
CH1–
CH2+
CH2–
CH3+
CH3–
CH4+
CH4–
CMPTR
Analog
Mux Control Logic
A0
A1
20
19
MCP1525
TC500/A/510/514
DS21428B-page 18
2002 Microchip Technology Inc.
9.0 TYPICAL CHARACTERISTICS
The graphs and tables following this note are a statistical summary based on a limited number of samples and are
provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed.
In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified
power supply range), and therefore outside the warranted range.
Load Current
(
mA
)
-5
-4
-3
-2
-1
0
1
2
3
4
5
010 20 30 40 50 60 70 80
Output Voltage (V)
Output Voltage vs Load Current
TA = 25˚C
V+ = 5V
Slope 60Ω
Load Current (mA)
0 3 45612 78 910
0
25
50
75
100
125
150
175
200
Output Ripple (mV PK-PK)
Output Ripple vs. Load Current
V+ = 5V, T
A = 25˚C
Osc. Freq. = 100kHz
CAP = 1µF
CAP = 10µF
Oscillator Capacitance (pF)
100
10
1110 100 1000
Oscillator Frequency (kHz)
Oscillator Frequency vs. Capacitance
T
A
= +25˚C
V+ = 5V
Output Current (mA)
068104214161812 20
-0
-1
-3
-2
-4
-5
-7
-6
-8
Output Voltage (V)
Output Voltage vs. Output Current
TA = 25˚C
Temperature (˚C)
70
80
90
100
60
50
40
-50 025
-25 50 75 100
Output Source Resistance (W)
Output Source Resistance vs. Temperature
V+ = 5V
I
OUT
= 10mA
Temperature (˚C)
125
150
100
75
50
-50 025-25 50 75 125100
Oscillator Frequency (kHz)
Oscillator Frequency vs. Temperature
V+ = 5V
2002 Microchip Technology Inc. DS21428B-page 19
TC500/A/510/514
10.0 PACKAGING INFORMATION
10.1 Package Marking Information
Package marking data not available at this time.
10.2 Taping Forms
Component Taping Orientation for 16-Pin SOIC (Wide) Devices
W
PIN 1
User Direction of Feed
Standard Reel Component Orientation
for TR Suffix Device
P
Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size
16-Pin SOIC (W) 16 mm 12 mm 1000 13 in
Carrier Tape, Number of Components Per Reel and Reel Size
Component Taping Orientation for 24-Pin SOIC (Wide) Devices
PIN 1
User Direction of Feed
Standard Reel Component Orientation
for TR Suffix Device
W
P
Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size
24-Pin SOIC (W) 24 mm 12 mm 1000 13 in
Carrier Tape, Number of Components Per Reel and Reel Size
TC500/A/510/514
DS21428B-page 20
2002 Microchip Technology Inc.
10.2 Taping Forms (Continued)
Component Taping Orientation for 28-Pin SOIC (Wide) Devices
PIN 1
User Direction of Feed
Standard Reel Component Orientation
for TR Suffix Device
W
P
Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size
28-Pin SOIC (W) 24 mm 12 mm 1000 13 in
Carrier Tape, Number of Components Per Reel and Reel Size
2002 Microchip Technology Inc. DS21428B-page 21
TC500/A/510/514
10.3 Package Dimensions
.110 (2.79)
.090 (2.29)
.022 (0.56)
.015 (0.38)
.150 (3.81)
.115 (2.92)
.770 (19.56)
.740 (18.80)
.045 (1.14)
.030 (0.76)
.070 (1.78)
.045 (1.14)
.310 (7.87)
.290 (7.37)
.040 (1.02)
.020 (0.51)
.270 (6.86)
.240 (6.10)
.200 (5.08)
.140 (3.56)
.014 (0.36)
.008 (0.20)
.400 (10.16)
.310 (7.87)
16-Pin PDIP (Narrow)
PIN 1
10°
MAX.
Dimensions: inches
(
mm
)
.018 (0.46)
.014 (0.36)
.050 (1.27)
.016 (0.40)
.050 (1.27) TYP
.157 (3.99)
.150 (3.81)
.244 (6.20)
.228 (5.79)
.010 (0.25)
.004 (0.10)
.069 (1.75)
.053 (1.35) 8°
MAX.
PIN 1
.010 (0.25)
.007 (0.18)
.394 (10.00)
.385 (9.78)
16-Pin SOIC (Narrow)
Dimensions: inches (mm)
TC500/A/510/514
DS21428B-page 22
2002 Microchip Technology Inc.
10.3 Packaging Dimensions (Continued)
8°
MAX.
PIN 1
.299 (7.59)
.291 (7.40)
.413 (10.49)
.398 (10.10)
.019 (0.48)
.014 (0.36)
.012 (0.30)
.004 (0.10)
.104 (2.64)
.097 (2.46) .013 (0.33)
.009 (0.23)
.050 (1.27)
.016 (0.40)
.419 (10.65)
.398 (10.10)
.050 (1.27) TYP.
16-Pin SOIC (Wide)
Dimensions: inches (mm)
1.195 (30.35)
1.155 (29.34)
.280 (7.11)
.240 (6.10)
.040 (1.02)
.015 (0.38)
.045 (1.14)
.030 (0.76)
.200 (5.08)
.140 (3.56)
.023 (0.58)
.015 (0.38)
.110 (2.79)
.090 (2.29)
.070 (1.78)
.045 (1.14)
PIN 1
.150 (3.81)
.115 (2.92)
.015 (0.38)
.008 (0.20) 3
˚
MIN.
.400 (10.16)
.310 (7.87)
.310 (7.87)
.290 (7.37)
24-Pin PDIP (Narrow)
Dimensions: inches
(
mm
)
2002 Microchip Technology Inc. DS21428B-page 23
TC500/A/510/514
10.3 Packaging Dimensions (Continued)
8°
MAX.
24-Pin SOIC (Wide)
.299 (7.59)
.291 (7.40)
.012 (0.30)
.004 (0.10)
.013 (0.33)
.009 (0.23)
.615 (15.62)
.597 (15.16)
.019 (0.48)
.014 (0.36)
.050 (1.27)
.016 (0.40)
.050 (1.27) TYP.
.419 (10.65)
.398 (10.10)
.104 (2.64)
.097 (2.46)
PIN 1
Dimensions: inches (mm)
PIN 1
3
˚
MIN.
28-Pin PDIP (Narrow)
1.400 (35.56)
1.345 (34.16)
.022 (0.56)
.015 (0.38)
.110 (2.79)
.090 (2.29)
.070 (1.78)
.045 (1.14)
.150 (3.81)
.115 (2.92)
.045 (1.14)
.030 (0.76)
.288 (7.32)
.240 (6.10)
.200 (5.08)
.140 (3.56)
.015 (0.38)
.008 (0.20)
.400 (10.16)
.310 (7.87)
.310 (7.87)
.290 (7.37)
.040 (1.02)
.015 (0.38)
Dimensions: inches (mm)
TC500/A/510/514
DS21428B-page 24
2002 Microchip Technology Inc.
10.3 Package Dimensions (Continued)
.299 (7.59)
.291 (7.40)
.103 (2.62)
.097 (2.46) 8
˚
MAX.
.713 (18.11)
.697 (17.70)
.019 (0.48)
.014 (0.36)
.419 (10.65)
.398 (10.10)
PIN 1
.050 (1.27)
.016 (0.40)
.013 (0.33)
.009 (0.23)
.012 (0.30)
.004 (0.10)
28-Pin SOIC (Wide)
Dimensions: inches
(
mm
)
2002 Microchip Technology Inc. DS21428B-page 25
TC500/A/510/514
SALES AND SUPPORT
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
TC500/A/510/514
DS21428B-page 26 2002 Microchip Technology Inc.
NOTES:
2002 Microchip Technology Inc. DS21428B-page 27
TC500/A/510/514
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical com-
ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.
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KEELOQ,microID,MPLAB,PIC,PICmicro,PICMASTER,
PICSTART, PRO MATE, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip Tech-
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dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
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MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode
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Serialized Quick Turn Programming (SQTP) is a service mark
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All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
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certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro®8-bit MCUs, KEELOQ®code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
DS21428B-page 28
2002 Microchip Technology Inc.
AMERICAS
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200 Fax: 480-792-7277
Technical Support: 480-792-7627
Web Address: http://www.microchip.com
Rocky Mountain
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7966 Fax: 480-792-7456
Atlanta
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 770-640-0034 Fax: 770-640-0307
Boston
2 Lan Drive, Suite 120
Westford, MA 01886
Tel: 978-692-3848 Fax: 978-692-3821
Chicago
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 630-285-0071 Fax: 630-285-0075
Dallas
4570 Westgrove Drive, Suite 160
Addison, TX 75001
Tel: 972-818-7423 Fax: 972-818-2924
Detroit
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
Kokomo
2767 S. Albright Road
Kokomo, Indiana 46902
Tel: 765-864-8360 Fax: 765-864-8387
Los Angeles
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888 Fax: 949-263-1338
New York
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Tel: 631-273-5305 Fax: 631-273-5335
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
Toronto
6285 Northam Drive, Suite 108
Mississauga, Ontario L4V 1X5, Canada
Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Australia
Microchip Technology Australia Pty Ltd
Suite 22, 41 Rawson Street
Epping 2121, NSW
Australia
Tel: 61-2-9868-6733 Fax: 61-2-9868-6755
China - Beijing
Microchip Technology Consulting (Shanghai)
Co., Ltd., Beijing Liaison Office
Unit 915
Bei Hai Wan Tai Bldg.
No. 6 Chaoyangmen Beidajie
Beijing, 100027, No. China
Tel: 86-10-85282100 Fax: 86-10-85282104
China - Chengdu
Microchip Technology Consulting (Shanghai)
Co., Ltd., Chengdu Liaison Office
Rm. 2401, 24th Floor,
Ming Xing Financial Tower
No. 88 TIDU Street
Chengdu 610016, China
Tel: 86-28-86766200 Fax: 86-28-86766599
China - Fuzhou
Microchip Technology Consulting (Shanghai)
Co., Ltd., Fuzhou Liaison Office
Unit 28F, World Trade Plaza
No. 71 Wusi Road
Fuzhou 350001, China
Tel: 86-591-7503506 Fax: 86-591-7503521
China - Shanghai
Microchip Technology Consulting (Shanghai)
Co., Ltd.
Room 701, Bldg. B
Far East International Plaza
No. 317 Xian Xia Road
Shanghai, 200051
Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
China - Shenzhen
Microchip Technology Consulting (Shanghai)
Co., Ltd., Shenzhen Liaison Office
Rm. 1315, 13/F, Shenzhen Kerry Centre,
Renminnan Lu
Shenzhen 518001, China
Tel: 86-755-2350361 Fax: 86-755-2366086
China - Hong Kong SAR
Microchip Technology Hongkong Ltd.
Unit 901-6, Tower 2, Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2401-1200 Fax: 852-2401-3431
India
Microchip Technology Inc.
India Liaison Office
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-2290061 Fax: 91-80-2290062
Japan
Microchip Technology Japan K.K.
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa, 222-0033, Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Korea
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea 135-882
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Singapore
Microchip Technology Singapore Pte Ltd.
200 Middle Road
#07-02 Prime Centre
Singapore, 188980
Tel: 65-6334-8870 Fax: 65-6334-8850
Taiwan
Microchip Technology Taiwan
11F-3, No. 207
Tung Hua North Road
Taipei, 105, Taiwan
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE
Denmark
Microchip Technology Nordic ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
France
Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Germany
Microchip Technology GmbH
Gustav-Heinemann Ring 125
D-81739 Munich, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Italy
Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
United Kingdom
Microchip Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44 118 921 5869 Fax: 44-118 921-5820
04/20/02
*DS21428B*
WORLDWIDE SALES AND SERVICE
