HV300LG-G - Supertex, Inc. - Datasheet.Directory

HV300/HV310

08/26/02

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HV300

HV310

Applications

❏Central Office Switching

❏Servers

❏POTS Line Cards

❏ISDN Line Cards

❏xDSL Line Cards

❏PBX Systems

❏Powered Ethernet for VoIP

❏Distributed Power Systems

❏Negative Power Supply Control

❏Antenna and Fixed Wireless Systems

General Description

The Supertex HV300 (and HV310),

Hotswap Controller, Negative

Supply

control power supply connection during insertion of

cards or modules into live backplanes. They may be used in

traditional ‘negative 48V’ powered systems or for higher voltage

busses up to negative 90V.

Operation during the initial power up prevents turn-on glitches,

and after complete charging of load capacitors (typically found

in filters at the input of DC-DC converters) the HV300 (and

HV310) issues a power good signal. This signal is typically

used to enable the DC-DC converter.

The only difference between the HV300 and the HV310 is the

polarity of the PWRGD signal line to accommodate different

DC-DC converter models. Once PWRGD signal has been

established the device sleeps in a low power state, important

for large systems with many individual hotswap cards or

modules.

An external power MOSFET is required as the pass element,

plus a ramp capacitor, and resistors to establish current limiting

and over and under voltage lockouts. There is no need for

additional external snubber components.

Features are programmable over voltage and under voltage

detection of the input voltage which locks out the load connection

if the bus (input) voltage is out of range. An internal voltage

regulator creates a stable reference, and maintains accurate

gate drive voltage. The unique control loop scheme provides

full current control and limiting during start up.

Theory of Operation

Initially the external N-channel MOSFET is held off by the gate

signal, preventing an input glitch. After a delay (while internal

circuits are activated) the inrush current to the load is limited by

the gate control output. The current may ramp up and limit at

a maximum value programmed by an external resistor. Initial

time delay, to allow for contact bounce, and charging operation

is determined by the single external ramp capacitor connected

to the RAMP pin. When the load capacitor is fully charged, the

controller emerges from current limit mode, an additional time

delay occurs before the external N-channel MOSFET pass

transistor is switched to full conduction, and the PWRGD

output signal is activated. The controller will then transition to

a low power standby mode.

The HV300LG PWRGD is active high (open drain), while the

HV310LG PWRGD is active low (VEE).

Ordering Information

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Features

❏HV300, PWRGD=Active HIGH

❏HV310, PWRGD=Active LOW

❏-10V to -90V Input Voltage Range

❏Few External Components

❏0.33mA Typical Standby Supply Current

❏Programmable Over/Under Voltage Limits with

Hysteresis

❏Programmable Current Limit

❏Active control during all phases of start-up

❏Programmable timing

❏8 Lead SOIC

Hotswap, Inrush Current Limiter Controllers

(Negative Supply Rail)

Not RecommendedNot Recommended

For New Designs! For New Designs!

HV300/HV310

Electrical Characteristics (VIN=-10V to -90V, -40°C ≤ TA ≤ +85°C unless otherwise noted)

Symbol Parameters Min Typ Max Unit Conditions

Supply (Referenced to VDD pin)

VEE Supply Voltage -90 -10 V

IEE Supply Current 550 650 µAV

EE = -48V, Mode = Limiting

IEE Standby Mode Supply Current 330 400 µAV

EE = -48V, Mode = Standby

OV and UV Control (Referenced to VEE pin)

VUVH UV High Threshold 1.26 V Low to High Transition

VUVL UV Low Threshold 1.16 V High to Low Transition

VUVHY UV Hysteresis 100 mV

IUV UV Input Current 1.0 nA VUV = VEE + 1.9V

VOVH OV High Threshold 1.26 V Low to High Transition

VOVL OV Low Threshold 1.16 V High to Low Transition

VOVHY OV Hysteresis 100 mV

IOV OV Input Current 1.0 nA VOV = VEE + 0.5V

Current Limit (Referenced to VEE pin)

VSENSE Current Limit Threshold Voltage 40 50 60 mV VUV = VEE + 1.9V,

VOV = VEE + 0.5V

Gate Drive Output (Referenced to VEE pin)

VGATE Maximum Gate Drive Voltage 9.0 10 11 V VUV = VEE + 1.9V,

VOV = VEE + 0.5V

IGATEUP Gate Drive Pull-Up Current 500 µAV

UV = VEE + 1.9V,

VOV = VEE + 0.5V,

IGATEDOWN Gate Drive Pull-Down Current 40 mA VUV = VEE, VOV = VEE + 0.5V

Power Good Output (Referenced to VEE pin)

VPWRGD Power Good Pin Breakdown Voltage 90 V

VPWRGD Power Good Pin Output Low Voltage 0.5 0.8 V IPWRGD = 1mA

Dynamic Characterstics

tGATEHLOV OV Delay 500 ns

tGATEHLUV UV Delay 500 ns

Note 1: This timing depends on the threshold voltage of the external N-Channel MOSFET. The higher its threshold is, the longer this timing.

Note 2: This voltage depends on the characteristics of the external N-Channel MOSFET. VGS(th) = 3V for an IRF530.

*IRF530 is a registered trademark of International Rectifier.

Timing Control – Test Conditions: C =100µF, CRAMP=10nF, VUV = VEE+1.9V, VOV= VEE+0.5V, External MOSFET is IRF530*

IRAMP Ramp Pin Output Current 10 µAV

SENSE = 0V

tPOR Time from UV to Gate Turn On 2.0 ms (Note 1)

tRISE Time from Gate Turn On to VSENSE Limit 400 µs

tLIMIT Duration of Current Limit Mode 5.0 ms

tPWRGD Time from Current Limit to PWRGD 5.0 ms

VRAMP Voltage on Ramp Pin in Current Limit Mode 3.6 V (Note 2)

HV300/HV310

Timing Diagrams

Absolute Maximum Ratings

VEE reference to VDD pin +0.3V to -100V

VPWRGD referenced to VEE Voltage -0.3V to +100V

Operating Ambient Temperature Range -40°C to +85°C

Operating Junction Temperature

Range -40°C to +125°C

Storage Temperature Range -65°C to +150°C

UV & OV ref to VEE -0.3V to +12V

VINT is the internally regulated supply voltage and can

range from 9V to 11V.

VGS(th) is the gate threshold voltage of the external pass

transistor and may be obtained from its datasheet.

VGS(lim) is the pass transistor gate-source voltage required

to obtain the limit curent. It is dependent on the pass

transistor ’s characteristics and may be obtained from the

transfer characteristics curves on the transistor datasheet.

gfs is the transconductance of the pass transistor and may

be obtained from its datasheet.

RFB is the internal feedback resistor and is 5kΩ nominal.

tVC

tt t

gIIRR

tVV V

LIM SENSE

SENSE

START RAMP

RAMP

TH GS th RAMP

RAMP

POR START TH

RISE RAMP

fs RAMP

LIM

SENSE

LIM IN LOAD

LIM RISE

PWRGD INT GS RAMP

RAMP

≈

−











≈−

=−−

()

(lim)

GND

-48V

tSTART

contact

bounce

ILIM

PWRGD

VUVL

tRISE tPWRGD

GATE

Initialization Limiting Full On

VGATE

OUT

tLIM

tTH

RAMP V

RAMP

GATE

inactive

active

OUT

VGS(th)

VGS(lim)

VEE

tPOR

90%

HV300/HV310

Pinout

Pin Description

PWRGD – The Power Good Output Pin is held inactive on initial

power application and will go active when the external MOSFET

is fully turned on. This pin may be used as an enable control

when connected directly to a PWM power module.

OV – This Over Voltage sense pin, when raised above its high

threshold will immediately cause the GATE pin to be pulled low .

The GATE pin will remain low until the voltage on this pin falls

below the low threshold limit, initiating a new start-up cycle.

UV – This Under V oltage sense pin, when below its low threshold

limit will ensure that the GATE pin is low. The GATE pin will

remain low until the voltage on this pin rises above the high

threshold, initializing a new start-up cycle.

VEE – This pin is the negative voltage power supply input to the

circuit.

VDD – This pin is the positive voltage power supply input to the

circuit.

RAMP – This pin provides a current output so that a timing

ramp voltage is generated when a capacitor is connected. The

initial portion of the ramp provides a time delay, which in

conjunction with the Under Voltage detection circuit eliminates

circuit card insertion contact bounce. The RAMP pin also controls

the delay between the current limit mode disengaging and the

PWRGD signal activating; as well as the current rise profile

after the initial turn on delay.

GATE – This is the Gate Driver Output for the external N-

Channel MOSFET.

SENSE – The current sense resistor connected from this pin to

VEE pin programs the current limit. Constant current output

mode is established when the voltage drop across this resistor

reaches 50mV.

Functional Block Diagram

PWRGD VDD

OV RAMP

UV GATE

VEE SENSE

PWRGD Logic

Model Condition PWRGD

HV300 NOT READY 0 VEE

READY 1 HI Z

HV310 NOT READY 1 HI Z

READY 0 VEE

Buffer

LOGIC

VINT

SENSE GATERAMP

Vref

UVLO

and

POR

Band Gap

Reference

Internal

Supply

Regulator

VINT

INT –1.2V

Vref

HV300:PWRG

HV310: PWRGD

–

10µA

Trans-

conductor

VREF

5kΩ

HV300/HV310

Functional Description

Insertion Into Hot Backplanes

Telecom, Data Network and some Computer applications require

the ability to insert and remove circuit cards from systems

without powering down the entire system. All circuit cards have

some filter capacitance on the power rails, which is especially

true in circuit cards or network terminal equipment utilizing

distributed power systems. The insertion can result in high

inrush currents that can cause damage to connector and circuit

cards and may result in unacceptable disturbances on the

system backplane power rails.

The HV300/HV310 was designed to allow the insertion of these

circuit cards or connection of terminal equipment by eliminating

these inrush currents and powering up these circuits in a

controlled manner after full connector insertion has been

achieved. The HV300/HV310 is intended to provide this function

on a negative supply rail in the range of -10 to -90 Volts.

Operation

On initial power application an internal regulator seeks to provide

10 Volts for the internal IC circuitry. Until the proper internal

voltage is achieved all circuits are held reset, the open drain

PWRGD signal is inactive to inhibit the start of any load circuitry

and the gate to source voltage of the external N-channel

MOSFET is held low. Once the internal under voltage lock out

(UVLO) has been satisfied, the circuit checks the input supply

voltage under voltage (UV) and over voltage (OV) sense circuits

to ensure that the input voltage is within acceptable programmed

limits. These limits are determined by the selected values of

resistors R1, R2 and R3, which form a voltage divider.

Waveforms

Drain

50V/div

VIN

50V/div

Gate

5.00V/div

Iinrush

500mA/div

5.00ms/div

Assuming the above conditions are satisfied and while continuing

to hold the PWRGD output inactive and the external MOSFET

GATE voltage low, the current source feeding the RAMP pin is

turned on. The external capacitor connected to it begins to

charge, thus starting an initial time delay determined by the

value of the capacitor. If an interruption of the input power

occurs during this time (i.e. caused by contact bounce) or the

OV or UV limits are exceeded, an immediate reset occurs and

the external capacitor connected to the RAMP pin is discharged.

When the voltage on the RAMP pin reaches an internally set

voltage limit, the gate drive circuitry begins to turn on the

external MOSFET; allowing the current to softly rise over a

period of a few hundred micro-seconds to the current limit set

point. While the circuit is limiting current, the voltage on the

RAMP pin will be fixed.

Depending on the value of the load capacitance and the

programmed current limit, charging may continue for some

time. The magnitude of the current limit is programmed by

comparing a voltage developed by a sense resistor connected

between the VEE and SENSE pins to 50mV (Typical). Once the

load capacitor has been charged, the current will drop which

will cause the ramp voltage to continue rising; providing yet

another programmed delay.

When the ramp voltage is within 1.2V of the internally regulated

voltage, the controller will force the GATE full on and will

activate the PWRGD pin and the circuit will transition to a low

power standby mode. The PWRGD pin is often used as an

enable for downstream DC/DC converter loads.

At any time during the start up cycle or thereafter, crossing the

UV and OV limits (including hysteresis) will cause an immediate

reset of all internal circuitry. Thereafter the start up process will

begin again.

HV300/HV310

1235 Bordeaux Drive, Sunnyvale, CA 94089

TEL: (408) 744-0100 • FAX: (408) 222-4895

www.supertex.com

08/26/02rev.10b

Typical Application Circuit

Application Information

Under Voltage and Over Voltage Detection

The UV and OV pins are connected to comparators with nominal

1.21V thresholds and 100mV of hysteresis (1.21V ± 50mV).

They are used to detect under voltage and over voltage

conditions at the input to the circuit. Whenever the OV pin rises

above its threshold or the UV pin falls below its threshold the

GATE voltage is immediately pulled low, the PWRGD signal is

deactivated and the external capacitor connected to the RAMP

pin is discharged.

The under voltage and over voltage trip points can be

programmed by means of the three resistor divider formed by

R1, R2 and R3. Since the input currents on the UV and OV pins

are negligible the resistor values may be calculated as follows:

UVoff = VUVH = 1.16 = |VEEUV| * (R2+R3) / (R1+R2+R3)

OVoff = VOVL = 1.26 = |VEEOV| * R3 / (R1+R2+R3)

Where |VEEUV| and |VEEOV| are Under & Over Voltage Set

points.

If we select a divider current of 100µA at a nominal operating

input voltage of 50 Volts then

(R1+R2+R3) = 50V / 100µA = 500kΩ

From the second equation for an Over voltage set point of 65

Volts the value of R3 may be calculated.

OVoff = 1.26 = 65 * R3 / 500kΩ

R3 = (1.26 * 500K) / 65 = 9.69 kΩ

The closest 1% value is 9.76kΩ.

From the first equation for an Under Voltage set point of 35

Volts the value R2 can be calculated.

UVoff = 1.16 = 35 * (R2 + R3) / 500K

R2 = (1.16 * 500K) / 35 – 9.76kΩ = 6.81kΩ.

The closest 1% value is 6.81kΩ.

Then R1 = 500K – (R2 +R3) = 483kΩ

The closest 1% value is 487kΩ.

Current Limit

The current limit magnitude above which the current will not be

allowed to rise during startup is programmed using a sense

resistor connected from the SENSE pin to VEE pin. For example

to program a current limit of 1A, one would choose a resistor as

follows:

Rsense = 50mV / Isense

Rsense = 50mV / 1A

Rsense = 50mΩ

Undervoltage/Overvoltage Operation

SENSE GATERAMP

GND

-48V

50mΩ

487kΩ

6.81kΩ

9.76kΩ

IRF530

Cload

+5V

HV300LG or

HV310LG

COM

DC/DC

PWM

CONVERTER

GND

Jumper

Long

Short

ENABLE

10nF

PWRGD

NOTES: 1. Undervoltage Lockout (UV) set to 35

2. Overvoltage Lockout (OV) set to 65V

3. Remove Jumper if Short Pin is used

74 5 6

GND

Pass

Transistor OFF

OFF