May 2010 Doc ID 17461 Rev 1 1/26
1
VND830E-E
Double channel high-side driver
Features
■Output current: 9.5 A
■CMOS compatible inputs
■On-state open-load detection
■Off-state open-load detection
■Output stuck to VCC detection
■Open drain status outputs
■Undervoltage shutdown
■Overvoltage clamp
■Thermal shutdown
■Current and power limitation
■Very low standby current
■Protection against loss of ground and loss of
VCC
■Reverse battery protection
■Very low electromagnetic susceptibility
■Optimized electromagnetic emission
Description
The VND830E-E is a monolithic device made by
using STMicroelectronics™ VIPower™ M0-3
technology. It is intended for driving resistive or
inductive loads with one side connected to
ground.
Active VCC pin voltage clamp protects the device
against low energy spikes (see ISO7637 transient
compatibility table).
The device detects open-load condition both in
on-state and off-state. Output shorted to VCC is
detected in the off-state.
Output current limitation protects the device in
overload condition. In case of long duration
overload, the device limits the dissipated power to
safe level up to thermal shutdown intervention.
Thermal shutdown with automatic restart allows
the device to recover normal operation as soon as
fault condition disappears.
Type RDS(on) IOUT VCC
VND830E-E 65 mΩ(1)
1. Per each channel.
9.5 A(1) 36 V
Table 1. Device summary
Package
Order codes
Tube Tape and reel
SO-16L VND830E-E VND830ETR-E
www.st.com
VND830E-E Contents
Doc ID 17461 Rev 1 2/26
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 16
3.1.1 Solution 1: a resistor in the ground line (RGND only) . . . . . . . . . . . . . . 16
3.1.2 Solution 2: a diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . 17
3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3 MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5 Maximum demagnetization energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1 SO-16L thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
List of tables VND830E-E
3/26 Doc ID 17461 Rev 1
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Thermal data (per island) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Power outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 6. Switching (VCC = 13 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 7. Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 8. VCC - output diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 9. Status pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 10. Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 11. Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 12. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 13. Electrical transient requirements on VCC pin (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 14. Electrical transient requirements on VCC pin (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 15. Electrical transient requirements on VCC pin (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 16. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 17. SO-16L mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
VND830E-E List of figures
Doc ID 17461 Rev 1 4/26
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. Switching time waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 9. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 10. Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12. Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 13. On-state resistance vs Tcase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 14. On-state resistance vs VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 15. Open-load on-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 16. Open-load off-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 17. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 18. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 19. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 20. Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 21. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 22. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 23. ILIM vs Tcase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 24. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 25. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 26. Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 27. Maximum turn-off current versus load inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 28. SO-16L PC board(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 29. Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 30. SO-16 L thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 31. Thermal fitting model of a quad channel HSD in SO-16L . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 32. SO-16L package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Block diagram and pin description VND830E-E
5/27 Doc ID 17461 Rev 1
1 Block diagram and pin description
Figure 1. Block diagram
Figure 2. Configuration diagram (top view)
Table 2. Suggested connections for unused and not connected pins
Connection / pin Status N.C. Output Input
Floating X X X X
To ground - X - Through 10 KΩ
resistor
OVERTEMP. 1
Vcc
GND
INPUT1 OUTPUT1
OVERVOLTAGE
LOGIC
DRIVER 1
STATUS1
Vcc
CLAMP
UNDERVOLTAGE
CLAMP 1
OPEN-LOAD ON 1
CURRENT LIMITER 1
OPEN-LOAD OFF 1
OUTPUT2
DRIVER 2
CLAMP 2
OPEN-LOAD ON 2
OPEN-LOAD OFF 2
OVERTEMP. 2
INPUT2
STATUS2
CURRENT LIMITER 2
V
CC
OUTPUT 2
OUTPUT 2
OUTPUT 2
OUTPUT 1
V
CC
OUTPUT 1
OUTPUT 1
V
CC
INPUT 2
STATUS 2
STATUS 1
INPUT 1
V
CC
GND
N.C.
1
89
16
VND830E-E Electrical specifications
Doc ID 17461 Rev 1 6/27
2 Electrical specifications
2.1 Absolute maximum ratings
Stressing the device above the rating listed in Ta bl e 3 may cause permanent damage to the
device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality
document.
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
VCC DC supply voltage 41 V
- VCC Reverse DC supply voltage - 0.3 V
- IGND DC reverse ground pin current - 200 mA
IOUT DC output current Internally limited A
- IOUT Reverse DC output current - 6 A
IIN DC input current +/- 10 mA
ISTAT DC status current +/- 10 mA
VESD
Electrostatic discharge (Human Body Model: R = 1.5 KΩ;
C = 100 pF)
- INPUT
- STATUS
- OUTPUT
- VCC
4000
4000
5000
5000
V
V
V
V
EMAX
Maximum switching energy
(L = 0.45 mH; RL = 0 Ω; Vbat = 13.5 V; Tjstart = 150 °C;
IL = 13.5 A)
57 mJ
Ptot Power dissipation TC=25°C 8.3 W
TjJunction operating temperature Internally limited °C
TcCase operating temperature - 40 to 150 °C
Tstg Storage temperature - 55 to 150 °C
Electrical specifications VND830E-E
7/27 Doc ID 17461 Rev 1
2.2 Thermal data
2.3 Electrical characteristics
Values specified in this section are for 8 V < VCC < 36 V; -40 °C < Tj < 150 °C, unless
otherwise stated.
(Per each channel)
Figure 3. Current and voltage conventions
1. VFn = VCCn - VOUTn during reverse battery condition.
Table 4. Thermal data (per island)
Symbol Parameter Value Unit
Rthj-lead Thermal resistance junction-lead 15 °C/W
Rthj-amb Thermal resistance junction-ambient 65(1)
1. When mounted on a standard single-sided FR-4 board with 0.5 cm2 of Cu (at least 35 µm thick) connected to all VCC pins.
Horizontal mounting and no artificial air flow.
47(2)
2. When mounted on a standard single-sided FR-4 board with 6 cm2 of Cu (at least 35 µm thick) connected to all VCC pins.
Horizontal mounting and no artificial air flow.
°C/W
Table 5. Power outputs
Symbol Parameter Test conditions Min. Typ. Max. Unit
VCC Operating supply voltage 5.5 13 36 V
VUSD Undervoltage shutdown 3 4 5.5 V
VOV Overvoltage shutdown 36 V
RON On-state resistance IOUT = 2 A; Tj = 25°C
IOUT = 2 A; VCC > 8 V
65
130
mΩ
mΩ
I
S
I
GND
OUTPUT 2
V
CC
GND
STATUS 2
INPUT 2 I
OUT2
I
IN2
I
STAT2
V
STAT2
V
IN2
V
CC
V
OUT2
OUTPUT 1
I
OUT1
V
OUT1
INPUT 1
I
IN1
STATUS 1
I
STAT1
V
IN1
V
STAT1
V
F1 (1)
VND830E-E Electrical specifications
Doc ID 17461 Rev 1 8/27
IS Supply current
Off-state; VCC = 13 V;
VIN = VOUT = 0 V
Off-state; VCC = 13 V;
VIN = VOUT = 0 V; Tj = 25°C
On-state; VCC = 13 V;
VIN = 5 V; IOUT = 0 A
12
12
5
40
25
7
µA
µA
mA
IL(off1) Off-state output current VIN = VOUT = 0 V 0 50 µA
IL(off2) Off-state output current VIN = 0 V; VOUT = 3.5 V -75 0 µA
IL(off3) Off-state output current VIN = VOUT = 0 V; VCC = 13 V;
Tj = 125°C 5µA
IL(off4) Off-state output current VIN = VOUT = 0 V; VCC = 13 V;
Tj =25°C 3µA
Table 6. Switching (VCC = 13 V)
Symbol Parameter Test conditions Min. Typ. Max. Unit
td(on) Turn-on delay time RL = 6.5 Ω from VIN rising
edge to VOUT = 1.3 V -50-µs
td(off) Turn-off delay time RL = 6.5 Ω from VIN falling
edge to VOUT = 11.7 V -50-µs
dVOUT/dt(on) Turn-on voltage slope RL = 6.5 Ω from VOUT = 1.3 V
to VOUT = 10.4 V -See
Figure 21 -V/µs
dVOUT/dt(off) Turn-off voltage slope RL = 6.5 Ω from VOUT = 11.7 V
to VOUT = 1.3 V -See
Figure 22 -V/µs
Table 7. Logic input
Symbol Parameter Test conditions Min. Typ. Max. Unit
VIL Input low level 1.25 V
IIL Low level input current VIN = 1.25 V 1 µA
VIH Input high level 3.25 V
IIH High level input current VIN = 3.25 V 10 µA
VI(hyst) Input hysteresis voltage 0.5 V
VICL Input clamp voltage IIN = 1 mA
IIN = -1 mA
66.8
-0.7
8V
V
Table 5. Power outputs (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
Electrical specifications VND830E-E
9/27 Doc ID 17461 Rev 1
Table 8. VCC - output diode
Symbol Parameter Test conditions Min. Typ. Max. Unit
VFForward on voltage -IOUT =1.2A; T
j= 150 °C - - 0.6 V
Table 9. Status pin
Symbol Parameter Test conditions Min. Typ. Max. Unit
VSTAT Status low output voltage ISTAT = 1.6 mA 0.5 V
ILSTAT Status leakage current Normal operation; VSTAT = 5 V 10 µA
CSTAT Status pin Input capacitance Normal operation; VSTAT = 5 V 100 pF
VSCL Status clamp voltage ISTAT = 1 mA
ISTAT = - 1 mA
66.8
- 0.7
8V
V
Table 10. Protections(1)
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.
Symbol Parameter Test conditions Min. Typ. Max. Unit
TTSD Shutdown temperature 150 175 200 °C
TRReset temperature 135 °C
Thyst Thermal hysteresis 7 15 °C
tSDL
Status delay in overload
conditions Tj > TTSD 20 µs
Ilim Current limitation VCC = 13 V
5.5 V < VCC < 36 V
9.5 13.5 18
18
A
A
Vdemag
Turn-off output clamp
voltage IOUT = 2A; L = 6mH V
CC-41 VCC-48 VCC-55 V
Table 11. Open-load detection
Symbol Parameter Test conditions Min. Typ. Max. Unit
IOL
Open-load on-state detection
threshold VIN = 5 V 50 115 200 mA
tDOL(on)
Open-load on-state detection
delay IOUT = 0 A 200 µs
VOL
Open-load off-state voltage
detection threshold VIN = 0 V 1.5 2.9 3.5 V
tDOL(off)
Open-load detection delay at
turn-off 1000 µs
VND830E-E Electrical specifications
Doc ID 17461 Rev 1 10/27
Figure 4. Status timings
Figure 5. Switching time waveforms
Table 12. Truth table
Conditions InputnOutputnStatusn
Normal operation L
H
L
H
H
H
Current limitation
L
H
H
L
X
X
H
(Tj < TTSD) H
(Tj > TTSD) L
Overtemperature L
H
L
L
H
L
Undervoltage L
H
L
L
X
X
V
INn
V
STATn
t
DOL(off)
OPEN- LOAD STATUS TIMING (with external pull-up)
V
INn
V
STATn
OVERTEMP STATUS TIMING
t
SDL
t
SDL
I
OUT
< I
OL
V
OUT
> V
OL
t
DOL(on)
T
j
> T
TSD
Electrical specifications VND830E-E
11/27 Doc ID 17461 Rev 1
Table 15. Electrical transient requirements on VCC pin (part 3)
Overvoltage L
H
L
L
H
H
Output voltage > VOLn
L
H
H
H
L
H
Output current < IOLn
L
H
L
H
H
L
Table 13. Electrical transient requirements on VCC pin (part 1)
ISO T/R
7637/1
test pulse
Test levels
I II III IV Delays and impedance
1 -25 V -50 V -75 V -100 V 2ms, 10Ω
2 +25 V +50 V +75 V +100 V 0.2 ms, 10 Ω
3a -25 V -50 V -100 V -150 V 0.1 µs, 50 Ω
3b +25 V +50 V +75 V +100 V 0.1 µs, 50 Ω
4 -4 V -5 V -6 V -7 V 100 ms, 0.01 Ω
5 +26.5V +46.5V +66.5V +86.5V 400ms, 2Ω
Table 14. Electrical transient requirements on VCC pin (part 2)
ISO T/R
7637/1
test pulse
Test levels results
I II III IV
1 CCCC
2 CCCC
3a CCCC
3b CCCC
4 CCCC
5CEEE
Class Contents
CAll functions of the device are performed as designed after exposure to
disturbance.
E
One or more functions of the device is not performed as designed after
exposure to disturbance and cannot be returned to proper operation without
replacing the device.
Table 12. Truth table (continued)
Conditions InputnOutputnStatusn
VND830E-E Electrical specifications
Doc ID 17461 Rev 1 12/27
Figure 6. Waveforms
OPEN-LOAD without external pull-up
STATUSn
INPUTn
NORMAL OPERATION
UNDERVOLTAGE
VCC
VUSD
VUSDhyst
INPUTn
OVERVOLTAGE
VCC
VCC > VOV
STATUS
INPUTn
STATUSn
STATUSn
INPUTn
STATUSn
INPUTn
OPEN-LOAD with external pull-up
undefined
OVERTEMPERATURE
INPUTn
STATUSn
TTSD
TR
Tj
OUTPUT VOLTAGEn
VCC<VOV
OUTPUT VOLTAGEn
OUTPUT VOLTAGEn
OUTPUT VOLTAGEn
OUTPUT VOLTAGEn
OUTPUT CURRENTn
VOUT > VOL
VOL
Electrical specifications VND830E-E
13/27 Doc ID 17461 Rev 1
2.4 Electrical characteristics curves
Figure 7. Off-state output current Figure 8. High level input current
Figure 9. Input clamp voltage Figure 10. Status leakage current
Figure 11. Status low output voltage Figure 12. Status clamp voltage
-50 -25 0 25 50 75 100 125 150 175
Tc ( ° C )
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
IL(off1) (µA)
Off state
Vcc=13V
Vin=Vout=0V
-50 -25 0 25 50 75 100 125 150 175
Tc ( ° C )
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
lih (µA)
Vin=3.25V
-50 -25 0 25 50 75 100 125 150 175
Tc ( ° C)
2
3
4
5
6
7
8
9
10
11
12
Vicl (V)
Iin=1mA
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0.15
0.155
0.16
0.165
0.17
0.175
0.18
0.185
0.19
0.195
0.2
Ilstat (µA)
Vstat=5V
-50 -25 0 25 50 75 100 125 150 175
Tc ( ° C )
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Vstat (V)
Istat=1.6mA
-50 -25 0 25 50 75 100 125 150 175
Tc ( ° C )
2
3
4
5
6
7
8
9
10
Vscl (V)
Istat=1mA
VND830E-E Electrical specifications
Doc ID 17461 Rev 1 14/27
Figure 13. On-state resistance vs Tcase Figure 14. On-state resistance vs VCC
Figure 15. Open-load on-state detection
threshold
Figure 16. Open-load off-state detection
threshold
Figure 17. Input high level Figure 18. Input low level
-50 -25 0 25 50 75 100 125 150 175
Tc ( ° C )
0
20
40
60
80
100
120
140
160
Ron (mOhm)
Iout=2A
Vcc=8V; 13V & 36V
5 10152025303540
Vcc (V)
0
15
30
45
60
75
90
105
120
Ron (mOhm)
Tc=-40°C
Tc=25°Tc=25°C
Tc=150°C
Iout=2A
-50 -25 0 25 50 75 100 125 150 175
Tc ( ° C )
70
80
90
100
110
120
130
140
150
Iol (mA)
Vcc=13V
Vin=5V
-50 -25 0 25 50 75 100 125 150 175
Tc ( ° C )
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Vol (V)
Vin=0V
-50 -25 0 25 50 75 100 125 150 175
Tc ( ° C )
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Vih (V)
-50 -25 0 25 50 75 100 125 150 175
Tc ( ° C )
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
Vil (V)
Electrical specifications VND830E-E
15/27 Doc ID 17461 Rev 1
Figure 19. Input hysteresis voltage Figure 20. Overvoltage shutdown
Figure 21. Turn-on voltage slope Figure 22. Turn-off voltage slope
Figure 23. ILIM vs Tcase Figure 24. Undervoltage shutdown
-50 -25 0 25 50 75 100 125 150 175
Tc ( ° C )
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
Vhyst (V)
-50 -25 0 25 50 75 100 125 150 175
Tc ( ° C )
10
15
20
25
30
35
40
45
50
55
60
65
70
Vov (V)
-50 -25 0 25 50 75 100 125 150 175
Tc ( ° C )
0
100
200
300
400
500
600
700
800
dVout/dt(on) (Vms)
Vcc=13V
Rl=6.5Ohm
-50 -25 0 25 50 75 100 125 150 175
Tc ( ° C )
0
50
100
150
200
250
300
350
400
450
500
dVout/dt(off) (Vms)
Vcc=13V
Rl=6.5Ohm
-50 -25 0 25 50 75 100 125 150 175
Tc ( ° C )
0
5
10
15
20
25
30
Ilim (A)
Vcc=13V
-50 -25 0 25 50 75 100 125 150 175
Tc ( ° C )
1
2
3
4
5
6
7
8
9
10
Vusd (V)
VND830E-E Application information
Doc ID 17461 Rev 1 16/27
3 Application information
Figure 25. Application schematic
3.1 GND protection network against reverse battery
This section provides two solutions for implementing a ground protection network against
reverse battery.
3.1.1 Solution 1: a resistor in the ground line (RGND only)
This can be used with any type of load.
The following shows how to dimension the RGND resistor:
1. RGND ≤600 mV / (IS(on)max)
2. RGND ≥(-VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device’s datasheet.
Power dissipation in RGND (when VCC < 0 during reverse battery situations) is:
PD = (-VCC)2/ RGND
This resistor can be shared amongst several different HSD. Please note that the value of this
resistor should be calculated with formula (1) where IS(on)max becomes the sum of the
maximum on-state currents of the different devices.
V
CC
OUTPUT2
D
ld
+5V
R
prot
OUTPUT1
STATUS1
INPUT1
+5V
STATUS2
INPUT2
GND
+5V
μ
CR
prot
R
prot
R
prot
D
GND
R
GND
V
GND
Application information VND830E-E
17/27 Doc ID 17461 Rev 1
Please note that, if the microprocessor ground is not common with the device ground, then
the RGND produces a shift (IS(on)max * RGND) in the input thresholds and the status output
values. This shift varies depending on how many devices are ON in the case of several high-
side drivers sharing the same RGND.
If the calculated power dissipation requires the use of a large resistor, or several devices
have to share the same resistor, then ST suggests using Section 3.1.2 described below.
3.1.2 Solution 2: a diode (DGND) in the ground line
A resistor (RGND = 1 kΩ) should be inserted in parallel to DGND if the device is driving an
inductive load. This small signal diode can be safely shared amongst several different HSD.
Also in this case, the presence of the ground network produce a shift (~600 mV) in the input
threshold and the status output values if the microprocessor ground is not common with the
device ground. This shift does not vary if more than one HSD shares the same
diode/resistor network. Series resistor in INPUT and STATUS lines are also required to
prevent that, during battery voltage transient, the current exceeds the absolute maximum
rating. Safest configuration for unused INPUT and STATUS pin is to leave them
unconnected.
3.2 Load dump protection
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
VCC maximum DC rating. The same applies if the device is subjected to transients on the
VCC line that are greater than those shown in Ta bl e 1 3 .
3.3 MCU I/O protection
If a ground protection network is used and negative transients are present on the VCC line,
the control pins are pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent
the microcontroller I/O pins from latching up.
The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
microcontroller I/Os:
- VCCpeak / Ilatchup ≤ Rprot ≤ (VOHμC - VIH - VGND) / IIHmax
Example
For the following conditions:
VCCpeak = -100 V
Ilatchup ≥ 20 mA
VOHμC ≥ 4.5 V
5kΩ ≤ Rprot ≤ 65 kΩ.
The recommended values are:
Rprot = 10 kΩ
VND830E-E Application information
Doc ID 17461 Rev 1 18/27
3.4 Open-load detection in off-state
Off-state open-load detection requires an external pull-up resistor (RPU) connected between
OUTPUT pin and a positive supply voltage (VPU) like the +5 V line used to supply the
microprocessor.
The external resistor has to be selected according to the following requirements:
1. No false open-load indication when load is connected: in this case it needs to avoid
VOUT to be higher than VOlmin; this results in the following condition
VOUT = (VPU / (RL + RPU))RL < VOlmin.
2. No misdetection when load is disconnected: in this case the VOUT has to be higher than
VOLmax; this results in the following condition RPU < (VPU - VOLmax) / IL(off2).
Because Is(OFF) may significantly increase if Vout is pulled high (up to several mA), the pull-
up resistor RPU should be connected to a supply that is switched OFF when the module is in
standby.
The values of VOLmin, VOLmax and IL(off2) are available in Chapter 2: Electrical specifications.
Figure 26. Open-load detection in off-state
VOL
V batt. VPU
RPU
RL
R
DRIVER
+
LOGIC
+
-
IN P U T
STATUS
VCC
OUT
GROUND
IL(o ff2)
Application information VND830E-E
19/27 Doc ID 17461 Rev 1
3.5 Maximum demagnetization energy
Figure 27. Maximum turn-off current versus load inductance
Note: Values are generated with RL = 0
Ω
.
In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse
must not exceed the temperature specified above for curves B and C.
V
IN
, I
L
t
Demagnetization Demagnetization Demagnetization
A = single pulse at TJstart = 150°C
B= repetitive pulse at TJstart = 100°C
C= repetitive pulse at TJstart = 125°C
1
10
100
0,1 1 10 100
L( mH)
ILM AX (A)
A
B
C
Conditions:
VCC= 13.5 V
VND830E-E Package and PCB thermal data
Doc ID 17461 Rev 1 20/27
4 Package and PCB thermal data
4.1 SO-16L thermal data
Figure 28. SO-16L PC board(1)
1. Layout condition of Rth and Zth measurements (PCB FR4 area = 41 mm x 48 mm, PCB thickness = 2 mm,
Cu thickness = 35 µm, Copper areas: 0.5 cm2, 6 cm2).
Figure 29. Rthj-amb vs PCB copper area in open box free air condition
40
45
50
55
60
65
70
01234567
PCB Cu heatsink area (cm^2)
RTH j-amb (°C/W)
Package and PCB thermal data VND830E-E
21/27 Doc ID 17461 Rev 1
Figure 30. SO-16 L thermal impedance junction ambient single pulse
Equation 1: pulse calculation formula
Figure 31. Thermal fitting model of a quad channel HSD in SO-16L
ZTHδRTH δZTHtp 1δ–()+⋅=
where
δtpT⁄=
T_amb
Pd1
C1
R4
C3 C4
R3R1 R6R5R2
C5 C6C2
Pd2
R2
C1 C2
R1
Tj_1
Tj_2
VND830E-E Package and PCB thermal data
Doc ID 17461 Rev 1 22/27
Table 16. Thermal parameters
Area/ island (cm2) Footprint 6
R1 (°C/W) 0.15
R2 (°C/W) 0.7
R3 (°C/W) 2
R4 (°C/W) 10
R5 (°C/W) 15
R6 (°C/W) 37 22
C1 (W.s/°C) 0.0005
C2 (W.s/°C) 0.003
C3 (W.s/°C) 0.015
C4 (W.s/°C) 0.15
C5 (W.s/°C) 1.5
C6 (W.s/°C) 3 5
Package and packing information VND830E-E
23/27 Doc ID 17461 Rev 1
5 Package and packing information
5.1 ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 32. SO-16L package dimensions
VND830E-E Package and packing information
Doc ID 17461 Rev 1 24/27
Table 17. SO-16L mechanical data
DIM.
mm.
Min. Typ. Max.
A2.65
a1 0.1 0.2
a2 2.45
b 0.35 0.49
b1 0.23 0.32
C0.5
c1 45° (typ.)
D 10.1 10.5
E 10.0 10.65
e1.27
e3 8.89
F7.4 7.6
L 0.5 1.27
M0.75
S 8° (max.)
Revision history VND830E-E
25/27 Doc ID 17461 Rev 1
6 Revision history
Table 18. Document revision history
Date Revision Changes
03-May-2010 1 Initial release.
VND830E-E
Doc ID 17461 Rev 1 26/26
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