2009 Microchip Technology Inc. DS41237D-page 1
PIC16F785/HV785
This document includes the
programming specifications for the
following devi ces:
•PIC16F785
•PIC16HV785
• PIC16F785-ICD
1.0 PROGRAMMING THE
PIC16F785/HV785
The PIC16F785/HV785 is programmed using a serial
method. The Serial mode will allow the device to be
programmed while in the user’s system. This allows for
increased design flexibility.
This programming specification applies to the
PIC16F785/HV785 devices in all packages.
1.1 Hardware Requirements
The PIC16F785 requires one power supply for VDD
(5.0V) and one for VPP (12V).
The PIC16HV785 requires one power supply for VDD
(4.5V) and one for VPP (12V). VDD is lower for the
PIC16HV78 5 to avo id pos sible conte ntion b etwee n the
shunt regulator and an unrestricted supply current.
1.2 Program/Verify Mode
The Program/Verify mode for the PIC16F785/HV785
allows programming of user program memory, data
memory, user ID locations and the C onfiguratio n Word
register.
TABLE 1-1: PI N D E S CR IP T I ON S I N PR OG RA M /VER IF Y MO DE : PIC16F785/HV785
Pin Name During Programming
Function Pin Type Pin Description
RA0 ICSPDAT I/O Data Input/Output – Schmitt Trigger input
RA1 ICSPCLK I Clock Input – Schmitt Trigger input
RA3/MCLR Program/Verify mode P(1) Program Mode Select
VDD VDD P Power Supply
VSS VSS P Ground
Legend: I = Input, I/O = Input/Output, P = Power
Note 1: In the PIC16F785/HV785, the programming high voltage is internally generated. To activate the Program/
Verify mode, hi gh voltage needs to be app lie d to M CLR input. Since the MCLR is used for a level source,
MCLR does not draw significant current.
PIC16F785/HV785 Memory Programming Specification
PIC16F785/HV785
DS41237D-page 2 2009 Microchip Technology Inc.
FIGU RE 1-1 : 20-P IN DI AGRAM F OR PIC16F 785/ HV7 85
FIGURE 1-2: 20-PIN DIAGRAM FOR PIC16F785/HV785
PDIP, SOIC, SSOP
1
2
3
4
5
6
7
8
9
10
20
11
12
13
14
15
16
17
18
19
PIC16F785/HV785
VDD
RA5/T1CKI/OSC1/CLKIN
RA4/AN3/T1G/OSC2/CLKOUT
RA3/MCLR/VPP
RC5/CCP1
RC4/C2OUT/PH2
RC3/AN7/C12IN3-/OP1
RC6/AN8/OP1-
RC7/AN9/OP1+
RB7/SYNC
VSS
RA0/AN0/C1IN+/ICSPDAT
RA1/AN1/C12IN0-/VREF/ICSPCLK
RA2/AN2/T0CKI/INT/C1OUT
RC0/AN4/C2IN+
RC1/AN5/C12IN1-/PH1
RC2/AN6/C12IN2-/OP2
RB4/AN10/OP2-
RB5/AN11/OP2+
RB6
QFN
1
2
3
4
511
12
13
14
15
6
7
8
9
10
20
19
18
17
16
PIC16F785/HV785
RA1/AN1/C12IN0-/VREF/ICSPCLK
RA2/AN2/T0CKI/INT/C1OUT
RC0/AN4/C2IN+
RC1/AN5/C12IN1-/PH1
RC2/AN6/C12IN2-/OP2
RA3/MCLR/VPP
RC5/CCP1
RC4/C2OUT/PH2
RC3/AN7/C12IN3-/OP1
RC6/AN8/OP1-
RC7/AN9/OP1+
RB7/SYNC
RB6
RB5/AN11/OP2+
RB4/AN10/OP2-
RA4/AN3/TIG/OSC2/CLKOUT
RA5/T1CKI/OSC1/CLKIN
VDD
GND
RA0/AN0/C1IN+/ICSPDAT
2009 Microchip Technology Inc. DS41237D-page 3
PIC16F785/HV785
FIGURE 1-3: ICD PINOUT
28-Pin PDIP
PIC16F785-ICD
In-Circuit Debug Device
SHNTREG
ICDMCLR/VPP
VDD
RA5
RA4
RA3
ICDCLK
ICDDATA
Vss
RA0
RC6 RB4
RA1
RA2
RC5
RC4
RC3
RC0
RC1
RC2
1
2
3
4
5
6
7
8
9
10
28
27
26
25
24
23
22
21
20
19
NC NC
RC7
RB7
ICD
RB5
RB6
NC
11
12
13
14
18
17
16
15
PIC16F785/HV785
DS41237D-page 4 2009 Microchip Technology Inc.
2.0 MEMORY DESC R IPTI ON
2.1 Program Memory Map
The user memory space extends from 0x0000 to
0x1FFF, with ad dre ss es 0x0000 -0x 07F F im ple me nte d.
In Program/Verify mode, the program memory space
extends from 0x0000 to 0x3FFF, with the first half
(0x0000 -0x1FFF ) being u ser prog ram me mory a nd the
second half (0x2000-0x3FFF) being configuration
memory. The PC will increment from 0x0000-0x1FFF
and wrap to 0x0000. If the PC starts at 0x2000 it will
increment to 0x3FFF and wrap around to 0x2000 (not
to 0x0000). Once in configuration memory, the highest
bit of the PC stays a ‘1’, thus always pointing to the
configuration memory. The only way to point to user
program memory is to reset the part and re-enter
Program/Verify mode as described in Section 3.0
“Program/Verify Mode”.
In the configuration memory space, 0x2000-0x203F
are physically implemented. However, only locations
0x2000 -0x2003 a nd 0x2007 -0x2009 a re availa ble. The
other locations are reserved.
2.2 User ID Locations
A user may store identification information (user ID) in
four designated locations. The user ID locations are
mapped in [0x2000-0x2003]. It is recommended that
the use r use only the seve n Least Sig nificant bits (L Sb)
of each user ID location. The user ID locations read out
normally, even after code protection is enabled. It is
recommended that user ID locations are written as
‘11 1111 1bbb bbbb’ where ‘bbb bbbb’ is user ID
information.
The 14 bits may be programmed, but only the 7 LSbs
are displayed by MPLAB® IDE. The 1111’s are “don’t
care” bits and are not read by MPLAB® IDE.
2.3 Calibration Words
The 8 MHz Intern al Oscillato r (INTOS C), the Power-on
Reset (POR), the Brown-out Reset (BOR) modules an d
band gap voltage reference are factory calibrated.
These values are stored in Calibration Words at
addresses 0x2008 and 0x2009.
The Calibration Word locations are written at the time
of manufacturing and are not erased when a Bulk
Erase is performed. See Section 3.1.5.10 “Bulk
Erase Program Memory” for more information on the
various erase sequences. However, it is possible to
inadvertently write to these locations. The device may
not funct ion pr op erly or may ope rate outs id e of s pe cif i-
cations if the Calib rati on Word loc ati ons do not con t ai n
the correct value. Therefore, it is recommended that
the Calibration Words be read prior to any program-
ming p rocedur e and ve rified af ter progra mming i s com-
plete. See Figure 3-21 for a flowchart of the
recomm end ed ve rifi cation proce dure .
The device should not be used if the verification of the
Calibration Word values fail after the device is
programmed. The 0x3FFF value is a special c ase, it is
a valid calibration value but, it is also the erased state
of the registe r.
2009 Microchip Technology Inc. DS41237D-page 5
PIC16F785/HV785
FIGURE 2-1: PROGRAM MEMORY MAPPING
1FFF
2000
User ID Location
User ID Location
User ID Location
User ID Location
Reserved
Reserved
Device ID
Configuration Word
Calibration Word
Calibration Word
Reserved
2040
3FFF
Implemented
2 K
Implemented
07FF
Maps to
0-7FF
Unimplemented
Program Memory
Configu r ati on Me mo ry
2000
2008
2009
2001
2002
2003
2004
2005
2006
2007
2009-203F
PIC16F785/HV785
DS41237D-page 6 2009 Microchip Technology Inc.
3.0 PROGRAM/VERIFY MODE
Two methods are available to enter Program/Verify
mode. The ‘VPP-first’ method is entered by holding
ICSPDAT and ICSPCLK low while raising MCLR pin
from VIL to VIHH (high voltage), then applying VDD and
data. This method can be used for any Configuration
Word selection and must be u sed if the IN TOSC and
internal MCLR options are selected (FOSC<2:0> = 100
or 101 and MCLRE = 0). The VPP-first entry prevents
the device from executing code prior to entering
Program/Verify mode. See the timing diagram in
Figure 3-1. To prevent the device from executing code
while exiting Program/Verify mode, the ‘VPP-last’ must
also be used if the I NT OSC an d intern al MC LR option s
are selected. See the timin g diagr am in Figure 3-3.
The second entry method, ‘VDD-first’, is entered by
applying VDD, holding ICSPDAT and ICSPCLK low,
then raising MCLR pin from VIL to VIHH (high voltage),
followed by data. This method can be used for any
Configuration Word selection except when INTOSC
and internal MCLR options are selected
(FOSC<2:0> = 100 or 101 and MCLRE = 0). This
technique is useful when programming the device
when VDD is already applied, for it is not necessary to
disconnect VDD to enter or exit Program/Verify mode.
See the timing diagram in Figure 3-2.
Once in this mode, the program memory , data memory ,
and configuration memory can be accessed and
programm ed in s erial fashi on. ICSPDAT and ICSPCLK
are Schmitt Trigger inputs in this mode.
The sequence that enters the device into the
Programm ing/V erify mode mo mentarily places all oth er
logic into the Reset state (the MCLR pin was initia lly at
VIL). Therefore, all I/O’s are in the Reset state (high-
impedance inputs) and the Program Counter (PC) is
cleared.
To prevent a device configured with INTOSC and
internal MCLR from executing after exiting Program/
Verify mode, VDD needs to power-down before VPP.
See Figure 3-3 for the timing.
FIGURE 3-1: VPP-FIRST PROGRAM/
VERIFY MODE ENTRY
FIGURE 3-2: VDD-FIRST PROGRAM/
VERIFY MODE ENTRY
FIGURE 3-3: VPP-LAST PROGRAM/
VERIFY MODE EXIT
VPP
THLD0
ICSPDAT
ICSPCLK
VDD
TPPDP
Note: This method of entry is valid, regardless
of Configuration Word selected.
VPP
TPPDP
ICSPDAT
ICSPCLK
VDD
THLD0
Note: This method of entry is not valid if
INT OSC and inte rnal MCLR are s elected.
VPP
ICSPDAT
ICSPCLK
VDD
THLD0
Note: This method must be used if INTOSC
and internal MCLR are selected.
2009 Microchip Technology Inc. DS41237D-page 7
PIC16F785/HV785
3.1 Program/Erase Algorithms
The PIC16F785/HV785 program memory may be
written in two ways. The fastest method writes four
words at a time. However, one-word writes are also
supported for backward compatibility with previous 8-
pin and 14-pin Flash devices. The four-word algorithm
is us ed to pr ogra m the pro gram m emory and the u ser
ID locatio ns only . The one-word algorithm ca n write any
available memory location (i.e., program memory,
configu r ati on me mo ry and data memory).
After writing the array, the PC may be reset and the
entire array read back to verify the write. It is not
possible to verify immediately following the write
because the PC can only increment, not decrement.
A devic e Rese t wil l clear t he PC and s et the addres s to
‘0’. The Increment Address command will increment
the PC. The Load Configuration command will set the
PC to 0x2000. The available commands are shown in
Table 3-1.
3.1.1 FOUR-WORD PROGRAMMING
Only the program memory can be written using this
algorithm. Data and configuration memory (>0x2003)
must use the one-word programming algorithm
(Section 3.1.2 “One-Word Program ming”).
This algorithm writes four sequential addresses in
program memory. The four addresses must point to a
four-wo rd bloc k with a ddre sses mo dulo 4 of 0, 1, 2 an d
3. For example, programming address 4 through 7 can
be programmed together. Programming addresses 2
through 5 will create an unexpected result.
The sequence for programming four words of program
memory at a time is as follows:
1. Load a word at the current program memory
address using Load Data for Program Memory
command.
2. Issue an Increment Addres s com m and.
3. Load a word at the current program memory
address using Load Data for Program Memory
command.
4. Repeat Steps 2 and 3, two more times.
5. Issue a Begin Programming command, either
internally or externally timed.
6. Wait TPROG1 (internally timed) or TPROG2
(externally tim ed).
7. Issue an End Programming command if externally
timed.
8. Issue an Increment Addres s com m and.
9. Repeat steps 1 through 8 as required to write
program memory .
See Figure 3-17 for more information.
3.1.2 ONE-WORD PROGRAMMING
The program memory may also be written one-word at
a time t o allo w co mp atibil ity w ith oth er 8-pin and 1 4-pin
Flash PIC® devices. Configuration memory (>0x2003)
and dat a memo ry must be written o ne-word (o r byte) at
a time with the exception of the user ID locations.
The sequence for programming one-word of program
memory at a time is as follows:
1. Load a word at the current program memory
address using Load Data for Program Memory
command.
2. Issue a Begin Programming command either
internally or externally timed.
3. Wait TPROG1 (internally timed) or TPROG2
(externally t imed).
4. Issue an End Programming command if
externally timed.
5. Issue an Increment Address command.
6. Repeat this sequence as required to write
program, data or configuration memory.
See Figure 3-16 for more information.
3.1.3 RESETTING WRITE LATCHES
The user ID (0x2000-0x2003) and Configuration Word
(0x2007) are mapped into the configuration memory
but do not physically reside in it. As a result, the write
latches are not reset when programming these
locations and must be reset by the programmer. This
can be don e in two way s, eith er loadi ng all fou r latche s
with ‘1’s or by exiting Program/Verify mode.
The sequence for manually resetting the write latches
is as follows:
1. Load a word using Load Data for Program
Memory command with a data word of all ‘1’s.
2. Issue an Increment Address command.
3. Repeat this sequence three times to all four
write latches to 1’s (Reset state).
Note: The fo ur wr ite lat ches must be rese t afte r
programming the user ID (0x2000-
0x2003) or Configuration Word (0x2007).
See Section 3.1.3 “Resetting Write
Latches”.
PIC16F785/HV785
DS41237D-page 8 2009 Microchip Technology Inc.
3.1. 4 ERASE ALGORITHMS
The PIC16F785/HV785 will erase different memory
locations depending on the Program Counter (PC), CP
and CPD values, and which erase command is
executed. The following sequences can be used to
erase noted memory locations. In each sequence, the
data memory will be erased if the CPD bit in the
Configuration Word is programmed (clear).
To erase the progra m mem ory and C onfig uration Wo rd
(0x2007), the following sequence must be performed.
1. Do a Bulk Erase Program Memory command.
2. Wait TERA to complete erase.
To erase the user ID (0x2000-0x2003), Configuration
Word (0x2007 ) an d prog ram m em ory u se th e foll owin g
sequence. Note that the Calibration Words (0x2008-
0x2009) will not be erased.
1. Perform a Load Configuration command with
dummy data to point the Program Counter (PC)
to 0x2000.
2. Perform a Bulk Erase Program Memory
command.
3. Wait TERA to complete erase.
3.1.5 SERIAL PROGRAM/VERIFY
OPERATION
The ICSPCLK pin is used as a clock input and the
ICSPDAT pin is used for entering command bits and
data input/output during serial operation. To input a
command, ICSPCLK is cycled six times. Each
command bit is latched on the falling edge of the clock
with the LSb of the command being input first. The data
input onto the ICSPDAT pin is required to have a
minimum setup and hold time (see Table 6-1), with
respect to the fal ling edge of the clock. Commands th at
have data associated with them (read and load) are
specif ied to ha ve a mini mum dela y of 1 s between the
comma nd and the d ata. Af ter this de lay, the clock pi n is
cycle d 16 times wit h the first cy cle bei ng a S t art bit and
the last cycle being a Stop bit.
During a read operation, the LSb will be transmitted
onto ICSPDAT pin on the rising edge of the second
cycl e. Fo r a l oad o per atio n, t he L Sb w ill be lat che d on
the falling edge of the second cycle. A minimum 1 s
delay is also specified between consecutive
commands, except for the End Programming
command, which requires a 100 s TDIS.
All commands and data words are transmitted LSb first.
Data is transmitted on the rising edge and latched on
the falling edge of the ICSPCLK. To allow for decoding
of commands and reversal of data pin configuration, a
time separation of at least 1 s is required between a
command and a data word.
The commands that are available are described in
Table 3-1.
TABLE 3-1: COMMAND MAPPING FOR PIC16F785/HV785
Note: The Calibration Words (0x2008-0x2009)
and user ID (0x2000-0x2003) will not be
erased.
Note: See Table 3-2.
Command Mapping (MSb … LSb) Data
Load Configuration xx00000, ones data (14), 0
Load Data for Program Memory xx00100, data (14), 0
Load Data for Data Memory xx00110, data (8), zero (6), 0
Read Data from Program Memory xx01000, data (14), 0
Read Data from Data Memory xx01010, data (8), zero (6), 0
Inc rement Address xx0110
Begin Programming (internally timed) x01000
Begin Programming (externally timed)(1) x11000
End Programming x01010
Bulk Erase Program Memory (internally timed)(2) xx1001
Bulk Erase Data Memory (internally timed)(2) xx1011
Row Erase Program Memory (internally timed)(2) x10001
Note 1: Externally timed Data EE programming is a program-only command. No erase cycle is performed.
2: VDD must be at least 4.0V for this command.
2009 Microchip Technology Inc. DS41237D-page 9
PIC16F785/HV785
3.1.5.1 Load Configuration
The Load Configuration command is used to access
the Configuration Word (0x2007) and the user ID
(0x2000-0x2003). This command sets the Program
Counter (PC) to address 0x2000. The data field must
be loaded with all ones.
After receiving this command, the Configuration Word
is accessed by performing an Increment Address
command 7 times to point the PC to the Configuration
Word . Data can be loa ded using the Load Dat a for Pro-
gram Memory command then be programmed using a
Begin Programming command, either internally or
externally timed.
After the 6-bit command is input, ICSPCLK pin is
cycled an additional 16 times for the S tart bit, 14 bits of
data and a Stop bit (see Figure 3-4).
Aft er the configuratio n memory is ente red, the only w ay
to get back to the program memory is to exit the
Program/Verify mode by taking MCLR low (VIL).
FIGURE 3-4: LOAD CONFIGURATION COMMAND
3.1.5.2 Load Data for Program Memory
After receiving this command, the device will load in a
14-bit ‘data word’ when 16 cycles are applied, as
described previously. A timing diagram for the Load
Data for Program Memory command is shown in
Figure 3-5.
FIGURE 3-5: LOAD DATA FOR PROGRAM MEMORY COMMAND
00TSET1
THLD1
TDLY1
TDLY2
12 34 56
00
0xx
12 34 5 15
16
strt_bit stp_bit
LSb MSb
ICSPCLK
ICSPDAT
TSET1
THLD1
TDLY1
TSET1
THLD1
TDLY2
12 34 56
0100xx
12 34 5 15
16
strt_bit stp_bit
LSb MSb
ICSPDAT
ICSPCLK
PIC16F785/HV785
DS41237D-page 10 2009 Microchip Technology Inc.
3.1.5.3 Load Data for Data Memory
After receiving this command, the device will load in a
14-bit ‘data word’ when 16 cycles are applied.
Howeve r , th e dat a memo ry is only 8 bit s wide a nd thus,
only the first 8 bits of data after the Start bit will be
prog ram me d i nt o the da ta m em ory. It is st il l ne cess ar y
to cycl e the clo ck the fu ll 16 cy cles in order to al low the
internal circuitry to reset properly. The data memory
cont ains 256 bytes.
FIGURE 3-6: LOAD DATA FOR DATA MEMORY COMMAND
3.1.5.4 Read Data from Program Memory
After receiving this command, the device will transmit
data bits out of the program memory (user or
configuration) currently accessed, starting with the
second rising edge of the clock input. The data pin will
go into Output mode on the second rising clock edge,
and it will revert to Input mode (high-impedance) after
the 16th rising edge.
If the program memory is code-protected (CP = 0), the
data i s read as ‘0’s.
FIGURE 3-7: READ DATA FROM PROGRAM MEMORY COMMAND
TDLY1
TDLY2
12 34 56
1100xx
12 34 51516
strt_bit stp_bit
LSb MSb on 9th falling edge
ICSPCLK
ICSPDAT
TDLY1
TSET1
THLD1
TDLY2
12 34 56
010xx
12 34 51516
TDLY3
input output input
strt_bit stp_bit
LSb MSb
0
ICSPCLK
ICSPDAT
2009 Microchip Technology Inc. DS41237D-page 11
PIC16F785/HV785
3.1.5.5 Read Data from Data Memory
After receiving this command, the device will transmit
data bits out of the data memory starting with the
second rising edge of the clo ck input. T he ICSPDA T pin
will go into Output mode on the second rising edge, and
it will revert to Input mode (high-impedance) after the
16th rising edge. As previously stated, the data mem-
ory is 8 bit s wide , and therefore, only the first 8 bi ts that
are output are actual data. If the data memory is code-
prote cted, the data is read as all ‘0’ s . A timing dia gra m
of this command is shown in Figure 3-8.
FIGURE 3-8: READ DATA FROM DATA MEMORY COMMAND
3.1.5.6 Increment Address
The PC is incremented when this command is
received. A timing diagram of this command is shown
in Figure 3-9.
It is not possible to decrement the address counter. To
reset this counter, the user should exit and re-enter
Program/Verify mode.
FIGURE 3-9: INCREMENT ADDRESS COMMAND (PROGRAM/V E RIFY)
TDLY1
TSET1
TDLY2
12 34 56
1010xx
12 34 51516
TDLY3
input output input
strt_bit LSb
stp_bit
MSb on 9th falling edge
THLD1
ICSPCLK
ICSPDAT
TDLY1
TSET1
THLD1
TDLY2
12 3 4 56
011
12
0
Next Command
ICSPCLK
ICSPDAT
PIC16F785/HV785
DS41237D-page 12 2009 Microchip Technology Inc.
3.1.5.7 Beg in Programmi ng (Internally
Timed)
A Load command must be given before every Begin
Programming command. Programming of the
appropriate memory (user program memory,
configuration memory or data memory) will begin after
this command is received and decoded. An internal
timing mechanism executes a write. The user must
allow for program cycle time for programming to
comple te. No End Progra mm ing c om mand is requ ire d.
The addressed location is not erased before
programming.
FIGU RE 3- 1 0: BEGIN P RO GRA MMI NG COMM AN D ( IN TE RN ALL Y TIMED)
3.1.5.8 Begin Programming (Externally
Timed)
A Load command must be given before every Begin
Programming command. Programming of the
appropriate memory (program memory, configuration
or data memory) will begin after this command is
received and decoded. Programming requires
(TPROG2) time and is terminated using an End
Programming command.
The addressed location is not erased before
programming.
FIGURE 3-11: BEGIN PROGRAMMI NG (EXTERNALLY T IM ED)
TSET1
THLD1
TPROG1
12 34 56 12
Next Command
010
00 x
ICSPCLK
ICSPDAT
ICSPCLK
ICSPDAT
TSET1
THLD1
TPROG2
123456
000 1
12
1
End Programming command
x
2009 Microchip Technology Inc. DS41237D-page 13
PIC16F785/HV785
3.1.5.9 End Programming
The End Programming command is executed when
terminating external timing or programming. The End
Programming command requires a 100 s TDIS.
FIGURE 3-12: END PROGRAMMING (SERIAL PR OGRAM/VERIFY)
3.1.5.10 Bulk Erase Program Memory
After this command is performed, the entire program
memory and Configuration Word (0x2007) are erased.
Data memory will also be erased if the CPD bit in the
Configuration Word is programmed (clear). See
Section 3.1.4 “Erase Algorithms” for erase
sequences.
FIGU RE 3-1 3: BUL K E R ASE PR OG RAM ME MORY COM M AN D
TSET1
THLD1
123456
010 0
12
1
Next Command
TDIS
x
ICSPCLK
ICSPDAT
Note: All Bu lk Er as e op e rat i on s mus t tak e pl a ce
between 4.5V and 5.5V VDD for
PIC16F785, 2.0V to 5.5V VDD for
PIC16F785-ICD and 4.5V to 4.9V for
PIC16HV785.
TSET1THLD1
TERA
12 3 4 56 12
Next Command
11x
00 x
ICSPDAT
ICSPCLK
PIC16F785/HV785
DS41237D-page 14 2009 Microchip Technology Inc.
TABLE 3-2: BULK ERASE RESULTS
3.1.5.11 Bulk Erase Data Memory
To perform an erase of the data memory, the following
sequen ce must be perfor me d.
1. Perform a Bulk Erase Data Memory command.
2. Wait TERA to complete Bulk Erase.
Dat a memo ry won’ t erase if co de-prote cted (CPD = 0).
If CPD = 0, a Bulk Erase program memory must be
used.
FIGU RE 3- 1 4: BULK E R ASE D ATA MEMORY CO M MAN D
PC = Programming
Memory Space
(Program Memory)
Configuration Memory Space
Configuration
Word User ID Calibration Word
Configuration Word or
Program Memory Space EEUU
First User ID Location E E E U
Either Calibration Wor d E E E E
Legend: E = Erased, U = Unchanged.
Note: All Bu lk Er as e op e rat i on s mus t tak e pl a ce
between 4.5V and 5.5V VDD for
PIC16F785, 2.0V to 5.5V VDD for
PIC16F785-ICD and 4.5V to 4.9V for
PIC16HV785.
TSET1
THLD1
TERA
12 34 56 12
Next Command
1110 x
ICSPCLK
ICSPDAT x
2009 Microchip Technology Inc. DS41237D-page 15
PIC16F785/HV785
3.1.5.12 Row Erase Program Memory
This command erases the 16-word row of program
memory pointed to by PC<11:4>. If the program
memory a rray i s prot ec ted (CP = 0) or the PC points to
configuration memory (>0x2000), the command is
ignored.
To perform a Row Erase Program Memory, the
following sequence must be performed.
1. Execute a Row Erase Program Memory
command.
2. Wait TERA to complete a row erase.
FIGU RE 3-1 5: ROW E R ASE PR OGR AM M EMO RY CO M MAN D
Note: All row erase operations must take place
between 4.5V and 5.5V VDD for
PIC16F785, 2.0V to 5.5V VDD for
PIC16F785-ICD and 4.5V to 4.9V for
PIC16HV785.
TERA
1234 56 12
Next Command
11
00 x
0
ICSPCLK
ICSPDAT
PIC16F785/HV785
DS41237D-page 16 2009 Microchip Technology Inc.
FIGURE 3-16: ONE-WORD PROGRAMMING FLOWCHART
Start
Program Cycle
Read Data
Program Memory
Data Correct? Report
Programming
Failure
All Locations
Done?
Begin
Programming
Wait TDIS
Program Cycle
No
No
Increment
Address
Command
From
Bulk Erase
Device(1)
Load Data
For
Program Memory
Yes
Command
(internal ly tim ed )
Begin
Programming
Wait TPROG2
Command
(externally timed)
End
Programming
Wait TPROG1
One-word
(Figure 3-20)
Done
Program Data
Memory
(Figure 3-19)
Yes
Note 1: This step is optional if device has already
been erased or has not been previously
programmed.
Program
User ID/Config. bits
(Figure 3-18)
Exit Program
Verify Mode
Re-enter Program
Verify Mode
Read and Store
Calib r ati on Me mo r y
Values
(Figure 3-21)
Read and Verify
Calibration Memory
Values
(Figure 3-21)
2009 Microchip Technology Inc. DS41237D-page 17
PIC16F785/HV785
FIGURE 3-17: FOUR-WORD PROGRAMMING FLOWCHART
Start
All Locations
Done?
Wait TPROG1
Program Cycle
No
Load Data
For
Program Memory
Wait TPROG2
End
Programming
Wait TDIS
Load Data
For
Program Memory
Increment
Address
Command
Load Data
For
Program Memory
Increment
Address
Command
Load Data
For
Program Memory
Increment
Address
Command
Four-word
Program Cycle
Bulk Erase
Device(1)
(Figure 3-20)
Done
Program
User ID/Config. bits
Program Data
Memory
(Figure 3-19)
(Figure 3-18)
Yes
Note 1: This step is optional if device is erased or not previously programmed.
Begin
Programming
Command
(internally timed)
Begin
Programming
Command
(externally timed)
Increment
Address
Command
Re-enter Program
Verify Mode
Exit Program
Verify Mode
Read and Store
Calibration Memory
Values
(Figure 3-21)
Read and Verify
Calibration Memory
Values
(Figure 3-21)
PIC16F785/HV785
DS41237D-page 18 2009 Microchip Technology Inc.
FIGURE 3- 1 8: PROGRAM FLO WCH ART – PIC 16F78 5/ HV7 85 CONFIGURATION MEMORY
Start
Load
Configuration
Data
Program Cycle
Read Data From
Command
Data Correct? Report
Programming
Failure
Address =
0x2004?
Data Correct? Report
Programming
Failure
Yes
No
Yes
Yes
No
Increment
Address
Command
No
Done
One-word
One-word
Program Cycle
(Config. bits)
Wait TDIS
Program Cycle
Load Data
For
Program Memory
Wait TPROG2
End
Programming
Wait TPROG1
(User ID)
Progra m Me mo r y
Read Data From
Command
Program Memory
Begin
Programming
Command
(internally timed)
Begin
Programming
Command
(externally timed)
Increment
Address
Command
Increment
Address
Command
Increment
Address
Command
Note: Ensure that a dev ice Bulk E rase has been
performed or that the device is blank prior
to programming the configuration memory.
2009 Microchip Technology Inc. DS41237D-page 19
PIC16F785/HV785
FIGURE 3-19: PROGRAM FLOWCHART – PIC16F785/ HV7 85 DA TA MEMORY
Start
Program Cycle
Data Correct?
All Locations
Done?
No
No
Yes
Yes
Done
Wait TPROG1
Pro gram Cycle
Load Data
For
Data Memory
Wait TPROG2
End
Programming
Wait TDIS
Begin
Programming
Command
(externally t imed)
Begin
Programming
Command
(internally timed)
Read Dat a From
Command
Program Mem ory
Report
Programming
Failure
Increment
Address
Command
(Data Memory)
5-6 ms
PIC16F785/HV785
DS41237D-page 20 2009 Microchip Technology Inc.
FIGURE 3-20: PROGRAM FLOWCHART – ERASE FLASH DEVICE
Start
Load Configuration
Done
Bulk Erase
Program Memory
Bulk Erase
Data Memory
Read and Verify
Calibration Memory
Values
(Figure 3-21)
Read and Store
Calibration Memory
Values
(Figure 3-21)
2009 Microchip Technology Inc. DS41237D-page 21
PIC16F785/HV785
FIGURE 3-21: CALIBRATION WORD VERIFICATION FLOWCHART
Start
Increment Address
Read and Store
Calibration
No
No
Yes
Yes
Done
Command
Address =
0x2008?
Calibration Word 1
Word 1
is Valid?(1,2) Fail
Increment Address
Read and Store
Command
Calibration Word 2
Calibration No
Yes
Word 2
is Valid?(1,2) Fail
Note 1: This step is not required for the Read and Store Calibration Memory Values proce dure.
2: The device should not be used if verification of the Calibration Word locations fails. This information
should be reported to the user through the user interface of the device programmer.
Load Configuration
PIC16F785/HV785
DS41237D-page 22 2009 Microchip Technology Inc.
4.0 CONFIGURATION WORD
The P IC16F785/H V785 h as several C onfi gur atio n bits .
These bits can be programmed (reads ‘0’) or left
unchanged (reads ‘1’) to select various device
configurations.
REGISTER 4-1: CONFIG: CONFIGURATION WORD (ADDRESS: 2007h)
U-1 U-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
––FCMEN
(5) IESO BOREN1(1) BOREN0(1) CPD(2,3)
bit 13 bit 7
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
CP(2) MCLRE(4) PWRTE WDTE(5) FOSC2 FOSC1 FOSC0
bit 6 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 13-12 Unimplemented: Read as ‘1’
bit 11 FCMEN: Fail-Safe Clock Monitor Enabled bit(5)
1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
bit 10 IESO: Internal External Switchover bit
1 = Internal External Switchover mode is enabled
0 = Internal External Switchover mode is disabled
bit 9-8 BOREN<1:0>: Brown-out Reset Selection bits(1)
11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
01 = BOR controlled by SBOREN bit (PCON<4>)
00 = BOR disabled
bit 7 CPD: Data Code Protection bit(2,3)
1 = Data memory code protection is disabled
0 = Data memory code protection is enabled
bit 6 CP: Code Protection bit(2)
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
bit 5 MCLRE: RA3/MCLR pin function select bit(4)
1 = RA3/MCLR pin function is MCLR
0 = RA3/MCLR pin function is digital input, MCLR internally tied to VDD
bit 4 PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 3 WDTE: Wa tchdog Timer Enable bit(5)
1 = WDT enabled
0 = WDT disabled and can be enabled by SWDTEN bit (WDTCON<0>)
2009 Microchip Technology Inc. DS41237D-page 23
PIC16F785/HV785
4.1 Device ID W ord
The device ID word for the PIC16F785/HV785 is
located at 2006h. This location cannot be erased.
TABLE 4-1: DEVICE ID VALUES
bit 2-0 FOSC<2:0>: Oscillator Selection bits
111 = RC oscillator: CLKOUT function on RA4/AN3/T1G/OSC2/CLKOUT pin, RC on RA5/T1CKI/OSC1/CLKIN
110 = RCIO oscillator: I/O function on RA4/AN3/T1G/OSC2/CLKOUT pin, RC on RA5/T1CKI/OSC1/CLKIN
101 = INTOSC o s c i llat or: C L K O U T f u n c tion o n RA4/AN3/T1G/OSC2/CLK OUT pin, I / O funct i o n o n
RA5/T1CKI/OSC1/CLKIN
100 = INTOSCIO oscillator: I/O function on RA4/AN3/T1G/OSC2/CLKOUT pin, I/O function on
RA5/T1CKI/OSC1/CLKIN
011 = EC: I/O function on RA4/AN3/T1G/OSC2/CLKOUT pin, CLKIN on RA5/T1CKI/OSC1/CLKIN
010 = HS oscillator: High-speed crystal/resonator on RA4/AN3/T1G/OSC2/CLKOUT and RA5/T1CKI/OSC1/
CLKIN(5)
001 = XT oscillator: Crystal/resonator on RA4/AN3/T1G/OSC2/CLKOUT and RA5/T1CKI/OSC1/CLKIN(5)
000 = LP oscillator: Low-power crystal on RA4/AN3/T1G/OSC2/CLK O UT and RA5/T1C KI/OSC1 /CLK IN(5)
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.
2: Program memory Bulk Erase must be performed to turn off code protection.
3: The entire data EEPROM will be erased when the code protection is turned off.
4: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.
5: If the HS, XT, or LP oscillator fails In Fail-Safe mode the Watchdog time-out can occur only once after which it will be
disabled until the oscillator is restored..
REGISTER 4-1: CONFIG: CONFIGURATION WORD (ADDRESS: 2007h) (CONTINUED)
Device Device ID Values
Dev Rev
PIC16HV785 01 0010 001 x xxxx
PIC16F785 01 0010 000 x xxxx
PIC16F785/HV785
DS41237D-page 24 2009 Microchip Technology Inc.
5.0 CODE PROTECTION
For the PIC16F785/HV785, once the CP bit is
program med to ‘0’, all program memory locations read
all ‘0’s. The user ID locations and the Configuration
Word read out in an unprotected fashion. Further
programming is disabled for the entire program
memory.
Data memory is protected with its own code-protect bit
(CPD). When enabled, the data memory can still be
programmed and read using the EECON1 register.
The user ID locations and the Configuration Word can
be programmed regardless of the state of the CP and
CPD bits.
5.1 Disabling Code Protection
It is reco mm en ded to use the proc ed ure i n Fi gure 3-20
to disabl e code protectio n of the device. Thi s sequence
will e rase the prog ram memo ry, data m emory, Configu-
ration Word (0x2007) and user ID locations (0x2000-
0x2003). The Calibration Words (0x2008-0x2009) will
not be erased.
5.2 Embedding Configuration Word
and User ID I nformation in the Hex
File
To allow portability of code, the programmer is required
to read the Configuration Word and user ID locations
from the hex fil e when loading t he hex fi le. If Conf igura-
tion Word info rma tio n w as no t pres en t in th e hex fil e, a
simple warning message may be issued. Similarly,
while saving a hex file, Configuration Word and user ID
information must be included. An option to not include
this information may be provided.
Specifically for the PIC16F785/HV785, the data
memory should also be embedded in the hex file (see
Section 5.3.2 “Embedding Data Memory Contents
in Hex File”).
Microchip Technology Incorporated feels strongly that
this feature is important for the benefit of the end
customer.
5.3 Checksum Comput ation
5.3.1 CHECKSUM
Checksum is calculated by reading the contents of the
PIC16F785/HV785 memory locations and adding up
the opcodes up to the maximum user addressable
location (e.g., 0x7FF for the PIC16F785/HV785). Any
Carry bits exceeding 16 bits are neglected. Finally, the
Config uration W ord (app ropriately masked) is added to
the checksum. Checksum computation for the
PIC16F785/HV785 devices is shown in Table 5-1.
The check s um is cal cu lated by summi ng the follow in g:
• The contents of all program memory locations
• The Configuration Word, appropriately masked
• Masked user ID locations (when applicable)
The 16 LSbs of this sum is the checksum.
The following table describes how to calculate the
checksum for each device. Note that the checksum
calculation differs depending on the code-protect
setting. Since the program memory locations read out
‘0’s when code-protected, the table describes how to
manipulate the actual program memory values to
simulate values that would be read from a protected
device. When calculating a checksum by reading a
device, the ent ire program memory can simply be read
and summed. The Configuration Word and user ID
locations can always be read regardless of code-protect
setting.
Note: To ensure system security, if CPD bit = 0,
Bulk Erase Program Memory command
will also erase data memory.
Note: Some older devices have an additional
value added in the checksum. This is to
maintain compatibility with older device
prog rammer checksums.
2009 Microchip Technology Inc. DS41237D-page 25
PIC16F785/HV785
TABLE 5-1: CHECKSUM COMPUTATIONS
5.3.2 EMBEDDING DATA MEMORY
CONTENTS IN HEX FILE
The programmer should be able to read data memory
information from a hex file and conversely (as an
option), write data memory contents to a hex file along
with program memory information and Configuration
Word (0x2007) and user ID (0x2000-0x2003)
information.
The 256 data memory locations are logically mapped
starting at address 0x2100. The format for data
memory sto rage is one dat a byte pe r add res s lo ca tio n,
LSb aligned.
Device Code-Protect Checksum* Blank
Value
0x25E6 a t 0
and Max.
Address
PIC16F785/HV785 OFF SUM[0x0000:0x7FF] + CFGW & 0FFF 07FF D3CD
ALL CFGW & 0x0FFF + SUM_ID 173E(1) E30C(1)
Legend: CFGW = Configuration Word. Example calculations assume Configuration Word is erased (all 1’s).
SUM[a:b] = [Sum of locations a to b inclusive]
SUM_ID = User ID locations masked by 0xF then made into a 16-bit value with ID0 as the Most Significant
nibble.
For example, ID0 = 0x1, ID1 = 0x2, ID3 = 0x3, ID4 = 0x4, then SUM_ID = 0x1234.
The 4 LSbs of the unprotected checksum is used for the example calculations.
* = Checksum – [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND
Note 1: Checksu m sho wn assu mes th at both t he d ata a nd prog ram mem ory are code-p rote cted and th at SUM _ID
cont ains the unprote cte d chec k sum.
PIC16F785/HV785
DS41237D-page 26 2009 Microchip Technology Inc.
6.0 PROGRAM/VERIFY MODE ELECTRICAL CH ARACTERISTICS
TA BLE 6-1: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY
MODE
AC/DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +85°C
Operating Voltage 4.5V VDD 5.5V
Sym. Characteristics Min. Typ. Max. Units Conditions/Comments
General
VDD
VDD level for read/write operations,
program and data memory 2.0
2.0 —
—5.5
4.9 V
VPIC16F785/PIC16F785-ICD
PS200
VDD level for Bulk Erase operations,
program and data memory 2.0
4.5
4.5
—
—
—
5.5
5.5
4.9(1)
V
V
V
PIC16F785-ICD
PIC16F785
PIC16HV785
VIHH High voltage on MCLR for Program/
Ve rify mode entry 10 — 12 V
TVHHR MCLR rise time (VSS to VHH) for
Program/Verify mode entry ——1.0s
TPPDP Hold time after VPP changes 5 — — s
VIH1 (ICSPCLK, ICSPDAT) input high level 0 .8 VDD ——V
VIL1 (ICSPCLK, ICSPDAT) input low level 0.2 VDD ——V
TSET0ICSPCLK, ICSPDAT setup ti me
before MCLR (Program/V e rify mode
selection pattern setup time) 100 — — ns
THLD0 Hold time after VDD changes 5 — — s
Serial Program/Verify
TSET1 Data in setup time before clock 100 — — ns
THLD1 Data in hold time after clock 100 — — ns
TDLY1
Data input not driven to next clock
input (delay required between
command/data or command/
command)
1.0 — — s
TDLY2Delay between clock to clock of
next command or data 1.0 — — s
TDLY3Clock to data out valid (during a
Read D at a co mm and) —80ns
TERA Erase cycle time — 5 6 ms
TPROG1Programming cy cle time (internally
timed) 2
5—2.5
6ms Program mem ory
Data memory
TPROG2Programming cycle time (externally
timed) 2—2.5ms
10°C TA+40°C
Program memory
TDIS Time delay from program to compare
(HV discharg e time ) 100 — — s
Note 1: Exceeding the maximum voltage may cause the shunt regulator to draw excessive current and damage
the device.
2009 Microchip Technology Inc. DS41237D-page 27
Information contained in this publication regarding device
applications a nd the lik e is p ro vided on ly for yo ur con ve nien ce
and may be supers eded by updates . I t is you r r es ponsibil it y to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPL AB, PIC , PI Cmi cro, PI CSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONIT OR, FanSense, HI- TIDE , In - Circuit Seria l
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Om niscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporat ed in the
U.S.A. and other countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that it s family of products is one of the most secure families of it s kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such act s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS41237D-page 28 2009 Microchip Technology Inc.
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Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08 -91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921- 5820
WORLDWIDE SALES AND SERVICE
03/26/09
