4-Mbit (256K x 16) Static RAM
CY7C1041CV33
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05134 Rev. *H Revised September 1, 2006
Features
• Pin equivalent to CY7C1041BV33
• Temperature Range s
— Commercial: 0°C to 70°C
— Industrial: –40 °C to 85°C
— Automotive-A: –40°C to 85°C
— Automotive-E: –40°C to 125°C
•High speed
—t
AA = 10 ns
• Low active pow er
— 324 mW (max.)
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE featur es
• Available in Pb-free and non Pb-free 44-pin 400-mil-
SOJ, 44-pin TSOP II and 48-ball FB GA packages
Functional Description[1]
The CY7C1041CV33 is a high-performance CMOS Static
RAM organized as 262,144 words by 16 bits.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte LOW Enable
(BLE) is LOW, then data from I/O pins (I/O0–I/O7), is written
into the location specified on the address pins (A0–A17). If Byte
HIGH Enable (BHE) is LOW, then data from I/O pins
(I/O8–I/O15) is written into the location specified on the
address pins (A0–A17).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte LOW Enable (BLE) is LOW,
then data from the memory location specified b y the address
pins will appear on I/O0 – I/O7. If Byte HIGH Enable (BHE) is
LOW , then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of Re ad an d Write mo de s.
The input/output pins (I/O0–I/O15) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a Write operation
(CE LOW, and WE LOW).
The CY7C1041CV33 is available in a standard 44-pin
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground (revolutionary) pinout, as well
as a 48-ball fine-pitch ball grid array (FBGA) package.
Notes:
1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www . cypress.com.
14
15
Logic Block Diagram Pin Configuration
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
256K × 16
ARRAY
A
0
A
11
A
13
A
12
A
A
A
16
A
17
A
9
A
10
I/O
0
–I/O
7
OE
I/O
8
–I/O
15
CE
WE
BLE
BHE
Top View
SOJ/
TSOP II
WE
1
2
3
4
5
6
7
8
9
10
11
14 31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15 29
30
V
CC
A
5
A
6
A
7
A
8
A
0
A
1
OE
V
SS
A
17
I/O
15
A
2
CE
I/O
2
I/O
0
I/O
1
BHE
A
3
A
4
18
17
20
19
I/O
3
27
28
25
26
22
21 23
24
V
SS
I/O
6
I/O
4
I/O
5
I/O
7
A
16
A
15
BLE
V
CC
I/O
14
I/O
13
I/O
12
I/O
11
I/O
10
I/O
9
I/O
8
A
14
A
13
A
12
A
11
A
9
A
10
NC
CY7C1041CV33
Document #: 38-05134 Rev. *H Page 2 of 12
Selection Guide
-10-12-15-20Unit
Maximum Access T ime 10 12 15 20 ns
Maximum Operating Current Commercial 90 85 80 75 mA
Industrial 100 95 90 85 mA
Automotive-A 100 85 mA
Automotive-E 90 mA
Maximum CMOS Standby Current Commercial/
Industrial 10 10 10 10 mA
Automotive-A 10 mA
Automotive-E 15 mA
Pin Configurations
48-ball FBGA
(Top View)
WE
VCC
A11
A10
NC
A6
A0
A3CE
I/O2
I/O0
I/O1
A4
A5
I/O3
I/O5
I/O4
I/O6
I/O7
VSS
A9
A8
OE
VSS
A7
I/O8
BHE
NC
A17
A2
A1
BLE
VCC
I/O9
I/O10
I/O
11
I/O12
I/O13 I/O14
I/O15
A15
A14
A13
A12
NC
NC NC
3
26
5
4
1
D
E
B
A
C
F
G
H
A16
CY7C1041CV33
Document #: 38-05134 Rev. *H Page 3 of 12
Pin Definitions
Pin Name
44-SOJ,
44-TSOP
Pin Number 48-ball FBGA
Pin Number I/O Type Description
A0–A17 1–5, 18–27,
42–44 A3, A4, A5, B3,
B4, C3, C4, D4,
H2, H3, H4, H5,
G3, G4, F3, F4,
E4, D3
Input Address Inputs used to select one of the address
locations.
I/O0–I/O15 7–10,13–16,
29–32, 35–38 B1, C1, C2, D2,
E2, F2, F1, G1,
B6, C6, C5, D5,
E5, F5, F6, G6
Input/Output Bidirectional Data I/O lines. Used as input or output lines
depending on operation
NC 28 A6, E3, G2, H1,
H6 No Connect No Conne cts. This pin is not connected to the die
WE 17 G5 Input/Control Write Enable Input, active LOW. When selected LOW, a
WRITE is conducted. When selected HIGH, a READ is
conducted.
CE 6 B5 Input/Control Chip Enable Input, active LOW. When LOW , selects the chip.
When HIGH, deselects the chip.
BHE, BLE 40, 39 B2, A1 Input/Control Byte Write Select Inputs, active LOW. BHE controls
I/O15–I/O8, BLE controls I/O7–I/O0
OE 41 A2 Input/Control Output Enable, active LOW. Controls the direction of the I/O
pins. When LOW, the I/O pins are allowed to behave as
outputs. When deasserted HIGH, I/O pins are tri-stated, and
act as input data pins.
VSS 12, 34 D1, E6 Ground Ground for the device. Should be connected to ground of the
system.
VCC 11, 33 D6, E1 Power Supply Power Supply inputs to the device.
CY7C1041CV33
Document #: 38-05134 Rev. *H Page 4 of 12
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............. ... ............................–55°C to +125°C
Supply Voltage on VCC to Relative GND[2] ....–0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z S tate[2] ....................................–0.5V to VCC + 0.5V
DC Input V oltage[2].................................–0.5V to VCC + 0.5V
Current into Outputs (LO W).........................................20 mA
Static Discharge Voltage..... .. ...... ............. ... ...............>2001V
(per MIL-STD-883, Method 3015)
Latch-up Current...................................................... >200 mA
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +70°C 3.3V ± 0.3V
Industrial –40°C to +85°C
Automotive-A –40°C to +85°C
Automotive-E –40°C to +125°C
DC Electrical Characteristics Over the Operating Range
Parameter Description Test Co nditions
-10 -12 -15 -20
UnitMin. Max. Min. Max. Min. Max. Min. Max.
VOH Output HIGH V olt age VCC = Min., IOH = –4.0 mA 2.4 2.4 2.4 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 0.4 0.4 V
VIH Input HIGH Voltage 2.0 VCC
+ 0.3 2.0 VCC
+ 0.3 2.0 VCC
+ 0.3 2.0 VCC
+ 0.3 V
VIL[2] Input LOW Voltage –0.3 0.8 –0.3 0.8 –0.3 0.8 –0.3 0.8 V
IIX Input Leakage
Current GND < VI < VCC Com’l/Ind’l–1+1–1+1–1+1–1+1µA
Auto-A –1 +1 –1 +1 µA
Auto-E –20 +20 µA
IOZ Output Leakage
Current GND < VOUT < VCC,
Output Disabled Com’l/Ind’l–1+1–1+1–1+1–1+1µA
Auto-A –1 +1 –1 +1 µA
Auto-E –20 +20 µA
ICC VCC Operating
Supply Current VCC = Max.,
f = fMAX = 1/t RC Com’l 90858075mA
Ind’l 100 95 90 85 mA
Auto-A 100 85 mA
Auto-E 90 mA
ISB1 Automatic CE
Power-down Current
—TTL Inputs
Max. VCC,
CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
Com’l/Ind’l 40 40 40 40 mA
Auto-A 40 40 mA
Auto-E 45 mA
ISB2 Automatic CE
Power-down Current
—CMOS Inputs
Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
Com’l/Ind’l 10 10 10 10 mA
Auto-A 10 10 mA
Auto-E 15 mA
Capacitance[3]
Parameter Description Test Co nditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz, VCC = 3.3V 8 pF
COUT I/O Capa citance 8 pF
Notes:
2. VIL (min.) = –2.0V and VIH(max) = VCC + 0.5V for pulse duratio ns of less than 20 ns.
3. Tested initially and afte r any design or process changes that may affect these parameters.
CY7C1041CV33
Document #: 38-05134 Rev. *H Page 5 of 12
AC Test Loads and Waveforms[4]
Thermal Resistance[3]
Parameter Description Test Conditions TSOP-II FBGA SOJ Unit
ΘJA Thermal Resistance (Junction to Ambient) Test conditions follow standard
test methods and procedures for
measuring therma l impedance,
per EIA / JESD51.
42.96 38.15 25.99 °C/W
ΘJC Thermal Resistance (Junction to Case) 10.75 9.15 18.8 °C/W
AC Switching Characteristics[5] Over the Operating Range
Parameter Description
-10 -12 -15 -20
UnitMin. Max. Min. Max. Min. Max. Min. Max.
Read Cycle
tpower[6] VCC(typical) to the first access 100 100 100 100 µs
tRC Read Cycle Time 10 12 15 20 ns
tAA Address to Data Valid 10 12 15 20 ns
tOHA Data Hold from Address Change 3 3 3 3 ns
tACE CE LOW to Data Valid 10 12 15 20 ns
tDOE OE LOW to Data Valid 5 6 7 8 ns
tLZOE OE LOW to Low-Z 0 0 0 0 ns
tHZOE OE HIGH to High-Z[7, 8] 5678ns
tLZCE CE LOW to Low-Z[8] 3333ns
tHZCE CE HIGH to High-Z[7, 8] 5678ns
tPU CE LOW to Power-Up 0 0 0 0 ns
tPD CE HIGH to Power-Down 10 12 15 20 ns
tDBE Byte Enable to Data Valid 5 6 7 8 ns
tLZBE Byte Enable to Low-Z 0 0 0 0 ns
tHZBE Byte Disable to High-Z 6 6 7 8 ns
Notes:
4. AC characteristics (except High-Z) for 10-ns p art s are tested u sing the load condi tions shown in Figure (a). All other speeds are tested using the Thevenin load
shown in Figure (b). High-Z characteristics are test ed for all speeds using the test load shown in Figure (d).
5. Test conditions assume signal transition time o f 3 ns or l ess, timing reference le vels of 1.5V, input pulse leve ls of 0 to 3.0V.
6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
7. tHZOE, tHZCE, and tHZWE are specified wi th a load capacit ance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-st ate volt age
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is les s than tLZWE for any given device.
9. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and t he transition of
either of these si gnals can termin ate the W rit e. The inpu t dat a set-up an d hold timin g should be refer enced to the lea ding edge of the signal that termin ates t he
Write.
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
3.3V
OUTPUT
30 pF
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT (b)
R 317Ω
R2
351Ω
Rise Time: 1 V/ns Fall Time: 1 V/ns
30 pF*
OUTPUT Z = 50Ω
50Ω
1.5V
(c)
(a)
3.3V
OUTPUT
5 pF
(d)
R 317Ω
R2
351Ω
10-ns Devices 12-, 15-, 20-ns Devices
High-Z Characteristics
CY7C1041CV33
Document #: 38-05134 Rev. *H Page 6 of 12
Write Cycle[9, 10]
tWC Write Cycle Time 10 12 15 20 ns
tSCE CE LOW to Write End 7 8 10 10 ns
tAW Address Set-Up to Write End 7 8 10 10 ns
tHA Address Hold from Write End 0 0 0 0 ns
tSA Address Set-Up to Write Start 0 0 0 0 ns
tPWE WE Pulse Width 7 8 10 10 ns
tSD Data Set-Up to Write End 5 6 7 8 ns
tHD Data Hold from Write End 0 0 0 0 ns
tLZWE WE HIGH to Low-Z[7] 3333ns
tHZWE WE LOW to High-Z[7, 8] 5678ns
tBW Byte Enable to End of Write 7 8 10 10 ns
Switching Waveforms
Read Cycle No. 1[1 1, 12]
Read Cycle No. 2 (OE Controlled)[12, 13]
Notes:
10.The minimum Write cycle time for Writ e Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
11.Device is continuously selected. OE, CE, BHE and/or BH E = VIL.
12.WE is HIGH for Read cycle.
13.Address valid prior to or coincident with CE transition LOW.
AC Switching Characteristics[5] Over the Operating Range (continued)
Parameter Description
-10 -12 -15 -20
UnitMin. Max. Min. Max. Min. Max. Min. Max.
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZBE
tPD
HIGH
OE
CE
ICC
ISB
IMPEDANCE
ADDRESS
DATA OUT
VCC
SUPPLY
tDBE
tLZBE
tHZCE
BHE,BLE
CURRENT
ICC
ISB
CY7C1041CV33
Document #: 38-05134 Rev. *H Page 7 of 12
Write Cycle No. 1 (CE Controlled)[14, 15]
Write Cycle No. 2 (BLE or BHE Contro lle d )
Notes:
14.Data I/O is high-impedance if OE or BHE and/or BLE = VIH.
15.If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Switching Waveforms (continued)
tHD
tSD
tSCE
tSA
tHA
tAW
tPWE
tWC
BW
DATA I/O
ADDRESS
CE
WE
BHE, BLE
t
tHD
tSD
tBW
tSA
tHA
tAW
tPWE
tWC
tSCE
DATA I/O
ADDRESS
BHE, BLE
WE
CE
CY7C1041CV33
Document #: 38-05134 Rev. *H Page 8 of 12
Write Cycle No. 2 (WE Controlled, OE LOW)
Truth Table
CE OE WE BLE BHE I/O0–I/O7I/O8–I/O15 Mode Power
H X X X X High-Z High-Z Power-down Standby (ISB)
L L H L L Data Out Da ta Out Read All Bits Active (ICC)
L L H L H Data Out High-Z Read Lower Bits Only Active (ICC)
L L H H L Hi gh-Z Data Out Read Upper Bits Only Active (ICC)
L X L L L Data In Da ta In Write All Bits Active (ICC)
L X L L H Data In High-Z Write Lower Bits Only Active (ICC)
L X L H L High-Z Data In Write Upper Bits Only Active (ICC)
L H H X X High-Z High-Z Selected, Outputs Disabled Active (ICC)
Switching Waveforms (continued)
tHD
tSD
tSCE
tHA
tAW
tPWE
tWC
tBW
DATA I/O
ADDRESS
CE
WE
BHE, BLE
tSA
tLZWE
tHZWE
CY7C1041CV33
Document #: 38-05134 Rev. *H Page 9 of 12
Ordering Information
Speed
(ns) Ordering Code Package
Diagram Package Type Operating
Range
10 CY7C1041CV33-10BAC 51-85106 48-ball Fine Pitch BGA Commercial
CY7C1041CV33-10BAXC 48-ball Fine Pitch BGA (Pb-Free)
CY7C1041CV33-10VC 51-85082 44-lead (400-mil) Molded SOJ
CY7C1041CV33-10VXC 44-lead (400-mil) Molded SOJ (Pb-Free)
CY7C1041CV33-10ZC 51-85087 44-pin TSOP II
CY7C1041CV33-10ZXC 44-pin TSOP II (Pb-Free)
CY7C1041CV33-10BAI 51-85106 48-ball Fine Pitch BGA Industrial
CY7C1041CV33-10BAXI 48-ball Fine Pitch BGA (Pb-Free)
CY7C1041CV33-10ZI 51-85087 44-pin TSOP II
CY7C1041CV33-10ZXI 44-pin TSOP II (Pb-Free)
CY7C1041CV33-10ZSXA 44-pin TSOP II (Pb-Free) Automotive-A
CY7C1041CV33-10BAXA 51-85106 48-ball Fine Pitch BGA (Pb-Free)
12 CY7C1041CV33-12VC 51-85082 44-lead (400-mil) Molded SOJ Commercial
CY7C1041CV33-12VXC 44-lead (400-mil) Molded SOJ (Pb-Free)
CY7C1041CV33-12ZC 51-85087 44-pin TSOP II
CY7C1041CV33-12ZXC 44-pin TSOP II (Pb-Free)
CY7C1041CV33-12VXI 51-85082 44-lead (400-mil) Molded SOJ (Pb-Free) Industrial
CY7C1041CV33-12ZI 51-85087 44-pin TSOP II
CY7C1041CV33-12ZXI 44-pin TSOP II (Pb-Free)
15 CY7C1041CV33-15VC 51-85082 44-lead (400-mil) Molded SOJ Commercial
CY7C1041CV33-15VXC 44-lead (400-mil) Molded SOJ (Pb-Free)
CY7C1041CV33-15ZC 51-85087 44-pin TSOP II
CY7C1041CV33-15ZXC 44-pin TSOP II (Pb-Free)
CY7C1041CV33-15VI 51-85082 44-lead (400-mil) Molded SOJ Industrial
CY7C1041CV33-15VXI 44-lead (400-mil) Molded SOJ (Pb-Free)
CY7C1041CV33-15ZI 51-85087 44-pin TSOP II
CY7C1041CV33-15ZXI 44-pin TSOP II (Pb-Free)
20 CY7C1041CV33-20ZC 51-85087 44-pin TSOP II Commercial
CY7C1041CV33-20ZXC 44-pin TSOP II (Pb-Free)
CY7C1041CV33-20ZSXA 44-pin TSOP II (Pb-Free) Automotive-A
CY7C1041CV33-20VE 51-85082 44-lead (400-mil) Molded SOJ Automotive-E
CY7C1041CV33-20VXE 44-lead (400-mil) Molded SOJ (Pb-Free)
CY7C1041CV33-20ZE 51-85087 44-pin TSOP II
CY7C1041CV33-20ZSXE 44-pin TSOP II (Pb-Free)
Please contact your local Cypress sales representative for availability of these parts
CY7C1041CV33
Document #: 38-05134 Rev. *H Page 10 of 12
Package Diagrams
A
1
A1 CORNER
0.75
0.75
Ø0.30±0.05(48X)
Ø0.25 M C A B
Ø0.05 M C
B
A
0.15(4X)
0.21±0.05
1.20 MAX.
C
SEATING PLANE
0.53±0.05
0.25 C
0.15 C
A1 CORNER
TOP VIEW BOTTOM VIEW
234
3.75
5.25
B
C
D
E
F
G
H
65
465231
D
H
F
G
E
C
B
A
7.00±0.10
8.50±0.10
A
8.50±0.10
7.00±0.10
B
1.875
2.625
0.36
48-Ball (7.00 mm x 8.5 mm x 1.2 mm) FBGA (51-8510 6)
51-85106-*E
CY7C1041CV33
Document #: 38-05134 Rev. *H Page 11 of 12
© Cypress Semi con duct or Cor po rati on , 20 06 . The information contained he re i n is subject to change without notice. C ypr ess S em ic onductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. F urthermore, Cyp ress does not a uthorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
All products and company names mentioned in this document may be the trademarks of their respective holders.
Package Diagrams (continued)
44-lead (400-mil) Molded SOJ (51-8508 2)
51-85082-*B
44-pin TSOP II (51-85087)
51-85087-*A
CY7C1041CV33
Document #: 38-05134 Rev. *H Page 12 of 12
Document History Page
Document Title: CY7C1041CV33 4-Mbit (256K x 16) Static RAM
Document Number: 38-05134
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 109513 12/13/01 HGK New Data Sheet
*A 112440 12/20/01 BSS Updated 51-85106 from revision *A to *C
*B 112859 03/25/02 DFP Added CY7C1042CV33 in BGA package
Removed 1042 BGA option pin ACC Final Data Sheet
*C 116477 09/16/02 CEA Add applications foot note to data sheet
*D 119797 10/21/02 DFP Added 20-ns speed bin
*E 262949 See ECN RKF 1) Added Lead (Pb)-Free parts in the Ordering info (Page #9)
2) Added Automotive Specs to Datasheet
*F 3 61795 See ECN SYT Added Pb-Free offerings in the Ordering Information
*G 435387 See ECN NXR Removed -8 Speed bin from Product offering.
Corrected typo in description for BHE/BLE in pin definitions table on Page# 3
corrected ther Pin name from OE2 to OE.
Included the Maximum Ratings for Static Discharge Voltage and Latch up
Current.
Changed the description of IIX current from Input Load Current to
Input Leakage Current
Added note# 4 on page# 4
Updated the Ordering Information table
*H 499153 See ECN NXR Added Automotive-A Operating Range
Changed tpower value from 1 µs to 100 µs
Updated Ordering Information table
