2011 Microchip Technology Inc. DS39762F
PIC18F97J60 Family
Data Sheet
64/80/100-Pin, High-Performance,
1-Mbit Flash Microcontrollers
with Ethernet
DS39762F-page 2 2011 Microchip Technology Inc.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
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Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
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Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
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SQTP is a service mark of Microchip Technology Incorporated
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All other trademarks mentioned herein are property of their
respective companies.
© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-069-1
Note the following details of the code protection feature on Microch ip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
2011 Microchip Technology Inc. DS39762F-page 3
PIC18F97J60 FAMILY
Ethernet Features:
• IEEE 802.3™ Compatible Ethernet Controller
• Fully Compatible with 10/100/1000Base-T Networks
• Integrated MAC and 10Base-T PHY
• 8-Kbyte Transmit/Receive Packet Buffer SRAM
• Supports One 10Base-T Port
• Programmable Automatic Retransmit on Collision
• Programmable Padding and CRC Generation
• Programmable Automatic Rejection of Erroneous
Packets
• Activity Outputs for 2 LED Indicators
•Buffer:
- Configurable transmit/receive buffer size
- Hardware-managed circular receive FIFO
- Byte-wide random and sequential access
- Internal DMA for fast memory copying
- Hardware assisted checksum calculation for
various protocols
•MAC:
- Support for Unicast, Multicast and Broadcast
packets
- Programmable Pattern Match of up to 64 bytes
within packet at user-defined offset
- Programmable wake-up on multiple packet
formats
•PHY:
- Wave shaping output filter
Flexible Oscil lator Struc ture:
• Selectable System Clock derived from Single
25 MHz External Source:
- 2.778 to 41.667 MHz
• Internal 31 kHz Oscillator
• Secondary Oscillator using Timer1 @ 32 kHz
• Fail-Safe Clock Monitor:
- Allows for safe shutdown if oscillator stops
• Two-Speed Oscillator Start-up
External Memory Bus
(100-pin devi ces only) :
• Address Capability of up to 2 Mbytes
• 8-Bit or 16-Bit Interface
• 12-Bit, 16-Bit and 20-Bit Addressing modes
Peripheral Highl ight s:
• High-Current Sink/Source: 25 mA/25 mA on PORTB
and PORTC
• Five Timer modules (Timer0 to Timer4)
• Four External Interrupt pins
• Two Capture/Compare/PWM (CCP) modules
• Three Enhanced Capture/Compare/PWM (ECCP)
modules:
- One, two or four PWM outputs
- Selectable polarity
- Programmable dead time
- Auto-shutdown and auto-restart
• Up to Two Master Synchronous Serial Port (MSSP)
modules supporting SPI (all 4 modes) and I2C™
Master and Slave modes
• Up to Two Enhanced USART modules:
- Supports RS-485, RS-232 and LIN/J2602
- Auto-wake-up on Start bit
- Auto-Baud Detect (ABD)
• 10-Bit, Up to 16-Channel Analog-to-Digital Converter
module (A/D):
- Auto-acquisition capability
- Conversion available during Sleep
• Dual Analog Comparators with Input Multiplexing
• Parallel Slave Port (PSP) module
(100-pin devices only)
S pecial Microcontroller Features:
• 5.5V Tolerant Inputs (digital-only pins)
• Low-Power, High-Speed CMOS Flash Technology:
- Self-reprogrammable under software control
• C compiler Optimized Architecture for Reentrant Code
• Power Management Features:
- Run: CPU on, peripherals on
- Idle: CPU off, peripherals on
- Sleep: CPU off, peripherals off
• Priority Levels for Interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 134s
• Single-Supply 3.3V In-Circuit Serial Programming™
(ICSP™) via Two Pins
• In-Circuit Debug (ICD) with 3 Breakpoints via
Two Pins
• Operating Voltage Range of 2.35V to 3.6V (3.1V to
3.6V using Ethernet module)
• On-Chip 2.5V Regulator
64/80/100-Pin High-Performance,
1-Mbit Flash Microcontrollers with Ethernet
PIC18F97J60 FAMILY
DS39762F-page 4 2011 Microchip Technology Inc.
Device
Flash
Program
Memory
(bytes)
SRAM
Dat a
Memory
(bytes)
Ethernet
TX/RX
Buffer
(bytes)
I/O 10-Bit
A/D (ch) CCP/
ECCP
MSSP
EUSART
Comparators
Timers
8/16-Bit PSP
External
Mem or y Bu s
SPI Master
I2C™
PIC18F66J60 64K 3808 8192 39 11 2/3 1 Y Y 1 2 2/3 N N
PIC18F66J65 96K 3808 8192 39 11 2/3 1 Y Y 1 2 2/3 N N
PIC18F67J60 128K 3808 8192 39 11 2/3 1 Y Y 1 2 2/3 N N
PIC18F86J60 64K 3808 8192 55 15 2/3 1 Y Y 2 2 2/3 N N
PIC18F86J65 96K 3808 8192 55 15 2/3 1 Y Y 2 2 2/3 N N
PIC18F87J60 128K 3808 8192 55 15 2/3 1 Y Y 2 2 2/3 N N
PIC18F96J60 64K 3808 8192 70 16 2/3 2 Y Y 2 2 2/3 Y Y
PIC18F96J65 96K 3808 8192 70 16 2/3 2 Y Y 2 2 2/3 Y Y
PIC18F97J60 128K 3808 8192 70 16 2/3 2 Y Y 2 2 2/3 Y Y
2011 Microchip Technology Inc. DS39762F-page 5
PIC18F97J60 FAMILY
Pin Diagrams
PIC18F66J65
1
2
3
4
5
6
7
8
9
10
11
12
13
14
38
37
36
35
34
33
50 49
17 18 19 20 21 22 23 24 25 26
VDD
MCLR
VSS
VDDCORE/VCAP
OSC2/CLKO
OSC1/CLKI
15
16
31
40
39
27 28 29 30 32
48
47
46
45
44
43
42
41
54 53 52 5158 57 56 5560 59
64 63 62 61
64-Pin TQFP
RB4/KBI0
RB5/KBI1
RB6/KBI2/PGC
VSS
VDD
RB7/KBI3/PGD
RC4/SDI1/SDA1
RC3/SCK1/SCL1
RC2/ECCP1/P1A
RC5/SDO1
VDDRX
TPIN+
TPIN-
VSSRX
RE2/P2B
RE3/P3C
RE4/P3B
RE5/P1C
RD0/P1B
RD1/ECCP3/P3A
RD2/CCP4/P3D
VSSPLL
VDDPLL
RBIAS
VSSTX
TPOUT+
TPOUT-
VDDTX
VSS
RE1/P2C
RE0/P2D
RG4/CCP5/P1D
RF7/SS1
RB0/INT0/FLT0
RB1/INT1
RB2/INT2
RB3/INT3
RF5/AN10/CVREF
RF4/AN9
RF3/AN8
RF2/AN7/C1OUT
RF6/AN11
ENVREG
RF1/AN6/C2OUT
AVDD
AVSS
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/LEDB/AN1
RA0/LEDA/AN0
VSS
VDD
RA4/T0CKI
RA5/AN4
RC1/T1OSI/ECCP2/P2A
RC0/T1OSO/T13CKI
RC7/RX1/DT1
RC6/TX1/CK1
PIC18F67J60
PIC18F66J60
PIC18F97J60 FAMILY
DS39762F-page 6 2011 Microchip Technology Inc.
Pin Diagrams (Continued)
PIC18F86J65
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
64 63 62 61
21 22 23 24 25 26 27 28 29 30 31 32
RE2/P2B
RE3/P3C(2)
RE4/P3B(2)
RE5/P1C(2)
RE6/P1B(2)
RE7/ECCP2(1)/P2A(1)
RD0
VDD
VSS
RD1
RD2
RE1/P2C
RE0/P2D
RG0/ECCP3/P3A
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4/P3D
MCLR
RG4/CCP5/P1D
VSS
VDDCORE/VCAP
RF7/SS1
RB0/INT0/FLT0
RB1/INT1
RB2/INT2
RB3/INT3
RB4/KBI0
RB5/KBI1
RB6/KBI2/PGC
VSS
OSC2/CLKO
OSC1/CLKI
VDD
RB7/KBI3/PGD
RC4/SDI1/SDA1
RC3/SCK1/SCL1
RC2/ECCP1/P1A
ENVREG
RF1/AN6/C2OUT
AVDD
AVSS
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/LEDB/AN1
RA0/LEDA/AN0
VSS
VDD
RA4/T0CKI
RA5/AN4
RC1/T1OSI/ECCP2(1)/P2A(1)
RC0/T1OSO/T13CKI
RC7/RX1/DT1
RC6/TX1/CK1
RC5/SDO1
RH1
RH0
1
2
RH2
RH3
17
18
RH7/AN15/P1B(2)
RH6/AN14/P1C(2)
RH5/AN13/P3B(2)
RH4/AN12/P3C(2)
RJ5
RJ4
37
50
49
19
20
33 34 35 36 38
58
57
56
55
54
53
52
51
60
59
68 67 66 6572 71 70 6974 7378 77 76 757980
80-Pin TQFP
Note 1: The ECCP2/P2A pin placement depends on the CCP2MX Configuration bit setting.
2: P1B, P1C, P3B and P3C pin placement depends on the ECCPMX Configuration bit setting.
RF5/AN10/CVREF
RF4/AN9
RF3/AN8
RF2/AN7/C1OUT
RF6/AN11
VSSPLL
VDDPLL
RBIAS
VSSTX
TPOUT+
TPOUT-
VDDTX
VDDRX
TPIN+
TPIN-
VSSRX
PIC18F87J60
PIC18F86J60
2011 Microchip Technology Inc. DS39762F-page 7
PIC18F97J60 FAMILY
Pin Diagrams (Continued)
92
94
93
91
90
89
88
87
86
85
84
83
82
81
80
79
78
20
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
65
64
63
62
61
60
59
26
56
45
44
43
42
41
40
39
28
29
30
31
32
33
34
35
36
37
38
17
18
19
21
22
95
1
76
77
72
71
70
69
68
67
66
75
74
73
58
57
24
23
25
96
98
97
99
27
46
47
48
49
50
55
54
53
52
51
100
10 0 -Pin TQFP
RB0/INT0/FLT0
RB1/INT1
RB2/INT2
RB3/INT3/ECCP2(1)/P2A(1)
RB4/KBI0
RB5/KBI1
RB6/KBI2/PGC
VSS
OSC2/CLKO
OSC1/CLKI
VDD
RB7/KBI3/PGD
RC4/SDI1/SDA1
RC3/SCK1/SCL1
RC2/ECCP1/P1A
RC5/SDO1
RJ7/UB
RJ6/LB
RJ2/WRL
RJ3/WRH
RE1/AD9/WR/P2C
RE0/AD8/RD/P2D
RG0/ECCP3/P3A
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4/P3D
MCLR
RG4/CCP5/P1D
VSS
VDDCORE/VCAP
RF7/SS1
RH2/A18
RH3/A19
RH7/AN15/P1B(2)
RH6/AN14/P1C(2)
RF5/AN10/CVREF
RF4/AN9
RF3/AN8
RF2/AN7/C1OUT
RF6/AN11
RE2/AD10/CS/P2B
RE3/AD11/P3C(2)
RE4/AD12/P3B(2)
RE5/AD13/P1C(2)
RE6/AD14/P1B(2)
RE7/AD15/ECCP2(1)/P2A(1)
RD0/AD0/PSP0
VDD
VSS
RD1/AD1/PSP1
RD2/AD2/PSP2
RD3/AD3/PSP3
RD4/AD4/PSP4/SDO2
RD5/AD5/PSP5/SDI2/SDA2
RD6/AD6/PSP6/SCK2/SCL2
RJ0/ALE
RJ1/OE
RH1/A17
RH0/A16
ENVREG
RF1/AN6/C2OUT
AVDD
AVSS
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/LEDB/AN1
RA0/LEDA/AN0
VSS
VDD
RA4/T0CKI
RA5/AN4
RC1/T1OSI/ECCP2(1)/P2A(1)
RC0/T1OSO/T13CKI
RC7/RX1/DT1
RC6/TX1/CK1
RH5/AN13/P3B(2)
RH4/AN12/P3C(2)
RJ5/CE
RJ4/BA0
VSS
VSSPLL
VDDPLL
RBIAS
VSSTX
TPOUT+
TPOUT-
VDDTX
VDDRX
TPIN+
TPIN-
VSSRX
RG6
RG5
RF0/AN5
VDD
RG7
VSS
RD7/AD7/PSP7/SS2
VDD
PIC18F96J65
PIC18F97J60
Note 1: The ECCP2/P2A pin placement depends on the CCP2MX Configuration bit and Processor mode settings.
2: P1B, P1C, P3B and P3C pin placement depends on the ECCPMX Configuration bit setting.
NC
PIC18F96J60
82
81
80
79
78
76
77
PIC18F97J60 FAMILY
DS39762F-page 8 2011 Microchip Technology Inc.
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 11
2.0 Guidelines for Getting Started with PIC18FJ Microcontrollers ................................................................................................... 43
3.0 Oscillator Configurations ............................................................................................................................................................ 49
4.0 Power-Managed Modes ............................................................................................................................................................. 55
5.0 Reset .......................................................................................................................................................................................... 63
6.0 Memory Organization ................................................................................................................................................................. 77
7.0 Flash Program Memory............................................................................................................................................................ 105
8.0 External Memory Bus ............................................................................................................................................................... 115
9.0 8 x 8 Hardware Multiplier.......................................................................................................................................................... 127
10.0 Interrupts .................................................................................................................................................................................. 129
11.0 I/O Ports ................................................................................................................................................................................... 145
12.0 Timer0 Module ......................................................................................................................................................................... 171
13.0 Timer1 Module ......................................................................................................................................................................... 175
14.0 Timer2 Module ......................................................................................................................................................................... 180
15.0 Timer3 Module ......................................................................................................................................................................... 183
16.0 Timer4 Module ......................................................................................................................................................................... 187
17.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 189
18.0 Enhanced Capture/Compare/PWM (ECCP) Modules .............................................................................................................. 197
19.0 Ethernet Module ....................................................................................................................................................................... 217
20.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 269
21.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 315
22.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 339
23.0 Comparator Module.................................................................................................................................................................. 349
24.0 Comparator Voltage Reference Module ................................................................................................................................... 355
25.0 Special Features of the CPU.................................................................................................................................................... 359
26.0 Instruction Set Summary .......................................................................................................................................................... 375
27.0 Development Support............................................................................................................................................................... 425
28.0 Electrical Characteristics .......................................................................................................................................................... 429
29.0 Packaging Information.............................................................................................................................................................. 465
Appendix A: Revision History............................................................................................................................................................. 475
Appendix B: Device Differences......................................................................................................................................................... 476
Index .................................................................................................................................................................................................. 477
The Microchip Web Site..................................................................................................................................................................... 489
Customer Change Notification Service .............................................................................................................................................. 489
Customer Support .............................................................................................................................................................................. 489
Reader Response .............................................................................................................................................................................. 490
Product Identification System............................................................................................................................................................. 491
2011 Microchip Technology Inc. DS39762F-page 9
PIC18F97J60 FAMILY
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
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welcome your feedback.
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http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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PIC18F97J60 FAMILY
DS39762F-page 10 2011 Microchip Technology Inc.
NOTES:
2011 Microchip Technology Inc. DS39762F-page 11
PIC18F97J60 FAMILY
1.0 DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
This family introduces a new line of low-voltage devices
with the foremost traditional advantage of all PIC18
microcontrollers – namely, high computational per-
formance and a rich feature set at an extremely
competitive price point. These features make the
PIC18F97J60 family a logical choice for many
high-performance applications where cost is a primary
consideration.
1.1 Core Features
1.1.1 OSCILLATOR OPTIONS AND
FEATURES
All of the devices in the PIC18F97J60 family offer five
different oscillator options, allowing users a range of
choices in developing application hardware. These
options include:
• Two Crystal modes, using crystals or ceramic
resonators.
• Two External Clock modes, offering the option of
a divide-by-4 clock output.
• A Phase Lock Loop (PLL) frequency multiplier,
available to the external oscillator modes, which
allows clock speeds of up to 41.667 MHz.
• An internal RC oscillator with a fixed 31 kHz
output which provides an extremely low-power
option for timing-insensitive applications.
The internal oscillator block provides a stable reference
source that gives the family additional features for
robust operation:
•Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a reference
signal provided by the internal oscillator. If a clock
failure occurs, the controller is switched to the
internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.
•Two-Speed Start-up: This option allows the
internal oscillator to serve as the clock source
from Power-on Reset, or wake-up from Sleep
mode, until the primary clock source is available.
1.1.2 EXPANDED MEMORY
The PIC18F97J60 family provides ample room for
application code, from 64 Kbytes to 128 Kbytes of code
space. The Flash cells for program memory are rated
to last 100 erase/write cycles. Data retention without
refresh is conservatively estimated to be greater than
20 years.
The PIC18F97J60 family also provides plenty of room
for dynamic application data with 3808 bytes of data
RAM.
1.1.3 EXTERNAL MEMORY BUS
In the unlikely event that 128 Kbytes of memory are
inadequate for an application, the 100-pin members of
the PIC18F97J60 family also implement an External
Memory Bus (EMB). This allows the controller’s inter-
nal program counter to address a memory space of up
to 2 Mbytes, permitting a level of data access that few
8-bit devices can claim. This allows additional memory
options, including:
• Using combinations of on-chip and external
memory up to the 2-Mbyte limit
• Using external Flash memory for reprogrammable
application code or large data tables
• Using external RAM devices for storing large
amounts of variable data
1.1.4 EXTENDED INSTRUCTION SET
The PIC18F97J60 family implements the optional
extension to the PIC18 instruction set, adding eight
new instructions and an Indexed Addressing mode.
Enabled as a device configuration option, the extension
has been specifically designed to optimize reentrant
application code originally developed in high-level
languages, such as C.
1.1.5 EASY MIGRATION
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve.
• PIC18F66J60 • PIC18F87J60
• PIC18F66J65 • PIC18F96J60
• PIC18F67J60 • PIC18F96J65
• PIC18F86J60 • PIC18F97J60
• PIC18F86J65
PIC18F97J60 FAMILY
DS39762F-page 12 2011 Microchip Technology Inc.
1.2 Other Special Features
•Communications: The PIC18F97J60 family
incorporates a range of serial communication
peripherals, including up to two independent
Enhanced USARTs and up to two Master SSP
modules, capable of both SPI and I2C™ (Master
and Slave) modes of operation. In addition, one of
the general purpose I/O ports can be reconfigured
as an 8-bit Parallel Slave Port for direct
processor-to-processor communications.
•CCP Modules: All devices in the family incorporate
two Capture/Compare/PWM (CCP) modules and
three Enhanced CCP (ECCP) modules to maximize
flexibility in control applications. Up to four different
time bases may be used to perform several
different operations at once. Each of the three
ECCP modules offers up to four PWM outputs,
allowing for a total of twelve PWMs. The ECCP
modules also offer many beneficial features,
including polarity selection, programmable dead
time, auto-shutdown and restart and Half-Bridge
and Full-Bridge Output modes.
•10-Bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period and
thus, reducing code overhead.
•Extended Watchdog Timer (WDT): This
enhanced version incorporates a 16-bit prescaler,
allowing an extended time-out range. See
Section 28.0 “Electrical Characteristics” for
time-out periods.
1.3 Details on Individual Family
Members
Devices in the PIC18F97J60 family are available in
64-pin, 80-pin and 100-pin packages. Block diagrams
for the three groups are shown in Figure 1-1,
Figure 1-2 and Figure 1-3.
The devices are differentiated from each other in four
ways:
1. Flash program memory (three sizes, ranging
from 64 Kbytes for PIC18FX6J60 devices to
128 Kbytes for PIC18FX7J60 devices).
2. A/D channels (eleven for 64-pin devices, fifteen
for 80-pin pin devices and sixteen for 100-pin
devices).
3. Serial communication modules (one EUSART
module and one MSSP module on 64-pin
devices, two EUSART modules and one MSSP
module on 80-pin devices and two EUSART
modules and two MSSP modules on 100-pin
devices).
4. I/O pins (39 on 64-pin devices, 55 on 80-pin
devices and 70 on 100-pin devices).
All other features for devices in this family are identical.
These are summarized in Table 1-1, Tabl e 1 -2 and
Table 1-3.
The pinouts for all devices are listed in Ta b l e 1 - 4 ,
Table 1-5 and Ta b l e 1-6.
2011 Microchip Technology Inc. DS39762F-page 13
PIC18F97J60 FAMILY
TABLE 1-1: DEVICE FEATURES FOR THE PIC18F97J60 FAMILY (64-PIN DEVICES)
TABLE 1-2: DEVICE FEATURES FOR THE PIC18F97J60 FAMILY (80-PIN DEVICES)
Features PIC18F66J60 PIC18F66J65 PIC18F67J60
Operating Frequency DC – 41.667 MHz DC – 41.667 MHz DC – 41.667 MHz
Program Memory (Bytes) 64K 96K 128K
Program Memory (Instructions) 32764 49148 65532
Data Memory (Bytes) 3808
Interrupt Sources 26
I/O Ports Ports A, B, C, D, E, F, G
I/O Pins 39
Timers 5
Capture/Compare/PWM Modules 2
Enhanced Capture/Compare/PWM Modules 3
Serial Communications MSSP (1), Enhanced USART (1)
Ethernet Communications (10Base-T) Yes
Parallel Slave Port Communications (PSP) No
External Memory Bus No
10-Bit Analog-to-Digital Module 11 Input Channels
Resets (and Delays) POR, BOR, RESET Instruction, Stack Full,
Stack Underflow, MCLR , WDT (PWRT, OST)
Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled
Packages 64-Pin TQFP
Features PIC18F86J60 PIC18F86J65 PIC18F87J60
Operating Frequency DC – 41.667 MHz DC – 41.667 MHz DC – 41.667 MHz
Program Memory (Bytes) 64K 96K 128K
Program Memory (Instructions) 32764 49148 65532
Data Memory (Bytes) 3808
Interrupt Sources 27
I/O Ports Ports A, B, C, D, E, F, G, H, J
I/O Pins 55
Timers 5
Capture/Compare/PWM Modules 2
Enhanced Capture/Compare/PWM Modules 3
Serial Communications MSSP (1), Enhanced USART (2)
Ethernet Communications (10Base-T) Yes
Parallel Slave Port Communications (PSP) No
External Memory Bus No
10-Bit Analog-to-Digital Module 15 Input Channels
Resets (and Delays) POR, BOR, RESET Instruction, Stack Full,
Stack Underflow, MCLR , WDT (PWRT, OST)
Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled
Packages 80-Pin TQFP
PIC18F97J60 FAMILY
DS39762F-page 14 2011 Microchip Technology Inc.
TABLE 1-3: DEVICE FEATURES FOR THE PIC18F97J60 FAMILY (100-PIN DEVICES)
Features PIC18F96J60 PIC18F96J65 PIC18F97J60
Operating Frequency DC – 41.667 MHz DC – 41.667 MHz DC – 41.667 MHz
Program Memory (Bytes) 64K 96K 128K
Program Memory (Instructions) 32764 49148 65532
Data Memory (Bytes) 3808
Interrupt Sources 29
I/O Ports Ports A, B, C, D, E, F, G, H, J
I/O Pins 70
Timers 5
Capture/Compare/PWM Modules 2
Enhanced Capture/Compare/PWM Modules 3
Serial Communications MSSP (2), Enhanced USART (2)
Ethernet Communications (10Base-T) Yes
Parallel Slave Port Communications (PSP) Yes
External Memory Bus Yes
10-Bit Analog-to-Digital Module 16 Input Channels
Resets (and Delays) POR, BOR, RESET Instruction, Stack Full,
Stack Underflow, MCLR , WDT (PWRT, OST)
Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled
Packages 100-Pin TQFP
2011 Microchip Technology Inc. DS39762F-page 15
PIC18F97J60 FAMILY
FIGURE 1-1: PIC18F66J60/66J65/67J60 (64-PIN) BLOCK DIAGRAM
Instruction
Decode and
Control
PORTA
Data Latch
Data Memory
(3808 Bytes)
Address Latch
Data Address<12>
12
Access
BSR FSR0
FSR1
FSR2
inc/dec
logic
Address
412 4
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
8
BITOP
8
8
ALU<8>
Address Latch
Program Memory
(64, 96, 128 Kbytes)
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
PCLATU
PCU
Note 1: See Ta b le 1 - 4 for I/O port pin descriptions.
2: BOR functionality is provided when the on-board voltage regulator is enabled.
EUSART1
Comparators
MSSP1
Timer2Timer1 Timer3Timer0
ECCP1
ADC
10-Bit
W
Instruction Bus <16>
STKPTR Bank
8
State Machine
Control Signals
Decode
8
8
ECCP2
ROM Latch
ECCP3 CCP4 CCP5
PORTC
PORTD
PORTE
PORTF
PORTG
RA0:RA5(1)
RC0:RC7(1)
RD0:RD2(1)
RE0:RE5(1)
RF1:RF7(1)
RG4(1)
PORTB
RB0:RB7(1)
Timer4
OSC1/CLKI
OSC2/CLKO
VDD,
Timing
Generation
VSS MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset(2)
Precision
Reference
Band Gap
INTRC
Oscillator
Regulator
Voltage
VDDCORE/VCAP
ENVREG
Ethernet
PIC18F97J60 FAMILY
DS39762F-page 16 2011 Microchip Technology Inc.
FIGURE 1-2: PIC18F86J60/86J65/87J60 (80-PIN) BLOCK DIAGRAM
PRODLPRODH
8 x 8 Multiply
8
BITOP
8
8
ALU<8>
8
8
3
W8
8
8
Instruction
Decode &
Control
State Machine
Control Signals
PORTA
PORTC
PORTD
PORTE
PORTF
PORTG
RA0:RA5(1)
RC0:RC7(1)
RD0:RD2(1)
RE0:RE7(1)
RF1:RF7(1)
RG0:RG4(1)
PORTB
RB0:RB7(1)
PORTH
RH0:RH7(1)
PORTJ
RJ4:RJ5(1)
EUSART1
Comparators
MSSP1
Timer2Timer1 Timer3Timer0
ECCP1
ADC
10-Bit
EUSART2
ECCP2 ECCP3 CCP4 CCP5
Timer4
Note 1: See Ta b l e 1 - 5 for I/O port pin descriptions.
2: BOR functionality is provided when the on-board voltage regulator is enabled.
OSC1/CLKI
OSC2/CLKO
VDD, VSS
Timing
Generation
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset(2)
Precision
Reference
Band Gap
INTRC
Oscillator
Regulator
Voltage
VDDCORE/VCAP
ENVREG
Data Latch
Data Memory
(3808 Bytes)
Address Latch
Data Address<12>
12
Access
BSR FSR0
FSR1
FSR2
inc/dec
logic
Address
412 4
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
20
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
PCLATU
PCU
Instruction Bus <16>
STKPTR Bank
Decode
ROM Latch
Ethernet
Address Latch
Program Memory
(64, 96, 128 Kbytes)
Data Latch
2011 Microchip Technology Inc. DS39762F-page 17
PIC18F97J60 FAMILY
FIGURE 1-3: PIC18F96J60/96J65/97J60 (100-PIN) BLOCK DIAGRAM
PRODLPRODH
8 x 8 Multiply
8
BITOP
8
8
ALU<8>
8
8
3
W8
8
8
Instruction
Decode &
Control
Data Address<12>
12
Access
BSR FSR0
FSR1
FSR2
inc/dec
logic
Address
412 4
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
20
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
ROM Latch
PCLATU
PCU
Instruction Bus <16>
STKPTR Bank
State Machine
Control Signals
Decode
System Bus Interface
AD15:AD0, A19:A16
(Multiplexed with PORTD,
PORTE and PORTH)
PORTA
PORTC
PORTD
PORTE
PORTF
PORTG
RA0:RA5(1)
RC0:RC7(1)
RD0:RD7(1)
RE0:RE7(1)
RF0:RF7(1)
RG0:RG7(1)
PORTB
RB0:RB7(1)
PORTH
RH0:RH7(1)
PORTJ
RJ0:RJ7(1)
EUSART1
Comparators
MSSP1
Timer2Timer1 Timer3Timer0
ECCP1
ADC
10-Bit
EUSART2
ECCP2 ECCP3 MSSP2CCP4 CCP5
Timer4
Note 1: See Ta bl e 1 - 6 for I/O port pin descriptions.
2: BOR functionality is provided when the on-board voltage regulator is enabled.
OSC1/CLKI
OSC2/CLKO
VDD, VSS
Timing
Generation
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset(2)
Precision
Reference
Band Gap
INTRC
Oscillator
Regulator
Voltage
VDDCORE/VCAP
ENVREG
Ethernet
Data Latch
Data Memory
(3808 Bytes)
Address Latch
Address Latch
Program Memory
(64, 96, 128 Kbytes)
Data Latch
PIC18F97J60 FAMILY
DS39762F-page 18 2011 Microchip Technology Inc.
TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS
Pin Name Pin Number Pin
Type Buffer
Type Description
TQFP
MCLR 7 I ST Master Clear (Reset) input. This pin is an active-low Reset
to the device.
OSC1/CLKI
OSC1
CLKI
39
I
I
ST
CMOS
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in internal RC mode; CMOS
otherwise.
External clock source input. Always associated
with pin function, OSC1. (See related OSC2/CLKO pin.)
OSC2/CLKO
OSC2
CLKO
40
O
O
—
—
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In Internal RC mode, OSC2 pin outputs CLKO which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
PORTA is a bidirectional I/O port.
RA0/LEDA/AN0
RA0
LEDA
AN0
24
I/O
O
I
TTL
—
Analog
Digital I/O.
Ethernet LEDA indicator output.
Analog Input 0.
RA1/LEDB/AN1
RA1
LEDB
AN1
23
I/O
O
I
TTL
—
Analog
Digital I/O.
Ethernet LEDB indicator output.
Analog Input 1.
RA2/AN2/VREF-
RA2
AN2
VREF-
22
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog Input 2.
A/D reference voltage (low) input.
RA3/AN3/VREF+
RA3
AN3
VREF+
21
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog Input 3.
A/D reference voltage (high) input.
RA4/T0CKI
RA4
T0CKI
28
I/O
I
ST
ST
Digital I/O.
Timer0 external clock input.
RA5/AN4
RA5
AN4
27
I/O
I
TTL
Analog
Digital I/O.
Analog Input 4.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
2011 Microchip Technology Inc. DS39762F-page 19
PIC18F97J60 FAMILY
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0/FLT0
RB0
INT0
FLT0
3
I/O
I
I
TTL
ST
ST
Digital I/O.
External Interrupt 0.
Enhanced PWM Fault input (ECCP modules); enabled
in software.
RB1/INT1
RB1
INT1
4
I/O
I
TTL
ST
Digital I/O.
External Interrupt 1.
RB2/INT2
RB2
INT2
5
I/O
I
TTL
ST
Digital I/O.
External Interrupt 2.
RB3/INT3
RB3
INT3
6
I/O
I
TTL
ST
Digital I/O.
External Interrupt 3.
RB4/KBI0
RB4
KBI0
44
I/O
I
TTL
TTL
Digital I/O.
Interrupt-on-change pin.
RB5/KBI1
RB5
KBI1
43
I/O
I
TTL
TTL
Digital I/O.
Interrupt-on-change pin.
RB6/KBI2/PGC
RB6
KBI2
PGC
42
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.
RB7/KBI3/PGD
RB7
KBI3
PGD
37
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
PIC18F97J60 FAMILY
DS39762F-page 20 2011 Microchip Technology Inc.
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
30
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
RC1/T1OSI/ECCP2/P2A
RC1
T1OSI
ECCP2
P2A
29
I/O
I
I/O
O
ST
CMOS
ST
—
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
ECCP2 PWM Output A.
RC2/ECCP1/P1A
RC2
ECCP1
P1A
33
I/O
I/O
O
ST
ST
—
Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
ECCP1 PWM Output A.
RC3/SCK1/SCL1
RC3
SCK1
SCL1
34
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
RC4/SDI1/SDA1
RC4
SDI1
SDA1
35
I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI data in.
I2C data I/O.
RC5/SDO1
RC5
SDO1
36
I/O
O
ST
—
Digital I/O.
SPI data out.
RC6/TX1/CK1
RC6
TX1
CK1
31
I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART1 asynchronous transmit.
EUSART1 synchronous clock (see related RX1/DT1 pin).
RC7/RX1/DT1
RC7
RX1
DT1
32
I/O
I
I/O
ST
ST
ST
Digital I/O.
EUSART1 asynchronous receive.
EUSART1 synchronous data (see related TX1/CK1 pin).
TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
2011 Microchip Technology Inc. DS39762F-page 21
PIC18F97J60 FAMILY
PORTD is a bidirectional I/O port.
RD0/P1B
RD0
P1B
60
I/O
O
ST
—
Digital I/O.
ECCP1 PWM Output B.
RD1/ECCP3/P3A
RD1
ECCP3
P3A
59
I/O
I/O
O
ST
ST
—
Digital I/O.
Capture 3 input/Compare 3 output/PWM3 output.
ECCP3 PWM Output A.
RD2/CCP4/P3D
RD2
CCP4
P3D
58
I/O
I/O
O
ST
ST
—
Digital I/O.
Capture 4 input/Compare 4 output/PWM4 output.
CCP4 PWM Output D.
TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
PIC18F97J60 FAMILY
DS39762F-page 22 2011 Microchip Technology Inc.
PORTE is a bidirectional I/O port.
RE0/P2D
RE0
P2D
2
I/O
O
ST
—
Digital I/O.
ECCP2 PWM Output D.
RE1/P2C
RE1
P2C
1
I/O
O
ST
—
Digital I/O.
ECCP2 PWM Output C.
RE2/P2B
RE2
P2B
64
I/O
O
ST
—
Digital I/O.
ECCP2 PWM Output B.
RE3/P3C
RE3
P3C
63
I/O
O
ST
—
Digital I/O.
ECCP3 PWM Output C.
RE4/P3B
RE4
P3B
62
I/O
O
ST
—
Digital I/O.
ECCP3 PWM Output B.
RE5/P1C
RE5
P1C
61
I/O
O
ST
—
Digital I/O.
ECCP1 PWM Output C.
TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
2011 Microchip Technology Inc. DS39762F-page 23
PIC18F97J60 FAMILY
PORTF is a bidirectional I/O port.
RF1/AN6/C2OUT
RF1
AN6
C2OUT
17
I/O
I
O
ST
Analog
—
Digital I/O.
Analog Input 6.
Comparator 2 output.
RF2/AN7/C1OUT
RF2
AN7
C1OUT
16
I/O
I
O
ST
Analog
—
Digital I/O.
Analog Input 7.
Comparator 1 output.
RF3/AN8
RF3
AN8
15
I/O
I
ST
Analog
Digital I/O.
Analog Input 8.
RF4/AN9
RF4
AN9
14
I/O
I
ST
Analog
Digital I/O.
Analog Input 9.
RF5/AN10/CVREF
RF5
AN10
CVREF
13
I/O
I
O
ST
Analog
—
Digital I/O.
Analog Input 10.
Comparator reference voltage output.
RF6/AN11
RF6
AN11
12
I/O
I
ST
Analog
Digital I/O.
Analog Input 11.
RF7/SS1
RF7
SS1
11
I/O
I
ST
TTL
Digital I/O.
SPI slave select input.
TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
PIC18F97J60 FAMILY
DS39762F-page 24 2011 Microchip Technology Inc.
PORTG is a bidirectional I/O port.
RG4/CCP5/P1D
RG4
CCP5
P1D
8
I/O
I/O
O
ST
ST
—
Digital I/O.
Capture 5 input/Compare 5 output/PWM5 output.
ECCP1 PWM Output D.
VSS 9, 25, 41, 56 P — Ground reference for logic and I/O pins.
VDD 26, 38, 57 P — Positive supply for peripheral digital logic and I/O pins.
AVSS 20 P — Ground reference for analog modules.
AVDD 19 P — Positive supply for analog modules.
ENVREG 18 I ST Enable for on-chip voltage regulator.
VDDCORE/VCAP
VDDCORE
VCAP
10
P
P
—
—
Core logic power or external filter capacitor connection.
Positive supply for microcontroller core logic
(regulator disabled).
External filter capacitor connection (regulator enabled).
VSSPLL 55 P — Ground reference for Ethernet PHY PLL.
VDDPLL 54 P — Positive 3.3V supply for Ethernet PHY PLL.
VSSTX 52 P — Ground reference for Ethernet PHY transmit subsystem.
VDDTX 49 P — Positive 3.3V supply for Ethernet PHY transmit subsystem.
VSSRX 45 P — Ground reference for Ethernet PHY receive subsystem.
VDDRX 48 P — Positive 3.3V supply for Ethernet PHY receive subsystem.
RBIAS 53 I Analog Bias current for Ethernet PHY. Must be tied to VSS via a resistor;
see Section 19.0 “Ethernet Module” for specification.
TPOUT+ 51 O — Ethernet differential signal output.
TPOUT- 50 O — Ethernet differential signal output.
TPIN+ 47 I Analog Ethernet differential signal input.
TPIN- 46 I Analog Ethernet differential signal input.
TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
2011 Microchip Technology Inc. DS39762F-page 25
PIC18F97J60 FAMILY
TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS
Pin Name Pin Number Pin
Type Buffer
Type Description
TQFP
MCLR 9 I ST Master Clear (Reset) input. This pin is an active-low Reset to
the device.
OSC1/CLKI
OSC1
CLKI
49
I
I
ST
CMOS
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in internal RC mode; CMOS
otherwise.
External clock source input. Always associated with
pin function, OSC1. (See related OSC2/CLKO pin.)
OSC2/CLKO
OSC2
CLKO
50
O
O
—
—
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In Internal RC mode, OSC2 pin outputs CLKO which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
PORTA is a bidirectional I/O port.
RA0/LEDA/AN0
RA0
LEDA
AN0
30
I/O
O
I
TTL
—
Analog
Digital I/O.
Ethernet LEDA indicator output.
Analog Input 0.
RA1/LEDB/AN1
RA1
LEDB
AN1
29
I/O
O
I
TTL
—
Analog
Digital I/O.
Ethernet LEDB indicator output.
Analog Input 1.
RA2/AN2/VREF-
RA2
AN2
VREF-
28
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog Input 2.
A/D reference voltage (low) input.
RA3/AN3/VREF+
RA3
AN3
VREF+
27
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog Input 3.
A/D reference voltage (high) input.
RA4/T0CKI
RA4
T0CKI
34
I/O
I
ST
ST
Digital I/O.
Timer0 external clock input.
RA5/AN4
RA5
AN4
33
I/O
I
TTL
Analog
Digital I/O.
Analog Input 4.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.
2: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
3: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared.
4: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
PIC18F97J60 FAMILY
DS39762F-page 26 2011 Microchip Technology Inc.
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0/FLT0
RB0
INT0
FLT0
5
I/O
I
I
TTL
ST
ST
Digital I/O.
External Interrupt 0.
Enhanced PWM Fault input (ECCP modules); enabled
in software.
RB1/INT1
RB1
INT1
6
I/O
I
TTL
ST
Digital I/O.
External Interrupt 1.
RB2/INT2
RB2
INT2
7
I/O
I
TTL
ST
Digital I/O.
External Interrupt 2.
RB3/INT3
RB3
INT3
8
I/O
I
TTL
ST
Digital I/O.
External Interrupt 3.
RB4/KBI0
RB4
KBI0
54
I/O
I
TTL
TTL
Digital I/O.
Interrupt-on-change pin.
RB5/KBI1
RB5
KBI1
53
I/O
I
TTL
TTL
Digital I/O.
Interrupt-on-change pin.
RB6/KBI2/PGC
RB6
KBI2
PGC
52
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.
RB7/KBI3/PGD
RB7
KBI3
PGD
47
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.
2: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
3: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared.
4: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
2011 Microchip Technology Inc. DS39762F-page 27
PIC18F97J60 FAMILY
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
36
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
RC1/T1OSI/ECCP2/P2A
RC1
T1OSI
ECCP2(1)
P2A(1)
35
I/O
I
I/O
O
ST
CMOS
ST
—
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
ECCP2 PWM Output A.
RC2/ECCP1/P1A
RC2
ECCP1
P1A
43
I/O
I/O
O
ST
ST
—
Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
ECCP1 PWM Output A.
RC3/SCK1/SCL1
RC3
SCK1
SCL1
44
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
RC4/SDI1/SDA1
RC4
SDI1
SDA1
45
I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI data in.
I2C data I/O.
RC5/SDO1
RC5
SDO1
46
I/O
O
ST
—
Digital I/O.
SPI data out.
RC6/TX1/CK1
RC6
TX1
CK1
37
I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART1 asynchronous transmit.
EUSART1 synchronous clock (see related RX1/DT1 pin).
RC7/RX1/DT1
RC7
RX1
DT1
38
I/O
I
I/O
ST
ST
ST
Digital I/O.
EUSART1 asynchronous receive.
EUSART1 synchronous data (see related TX1/CK1 pin).
TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.
2: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
3: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared.
4: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
PIC18F97J60 FAMILY
DS39762F-page 28 2011 Microchip Technology Inc.
PORTD is a bidirectional I/O port.
RD0 72 I/O ST Digital I/O.
RD1 69 I/O ST Digital I/O.
RD2 68 I/O ST Digital I/O.
PORTE is a bidirectional I/O port.
RE0/P2D
RE0
P2D
4
I/O
O
ST
—
Digital I/O.
ECCP2 PWM Output D.
RE1/P2C
RE1
P2C
3
I/O
O
ST
—
Digital I/O.
ECCP2 PWM Output C.
RE2/P2B
RE2
P2B
78
I/O
O
ST
—
Digital I/O.
ECCP2 PWM Output B.
RE3/P3C
RE3
P3C(2)
77
I/O
O
ST
—
Digital I/O.
ECCP3 PWM Output C.
RE4/P3B
RE4
P3B(2)
76
I/O
O
ST
—
Digital I/O.
ECCP3 PWM Output B.
RE5/P1C
RE5
P1C(2)
75
I/O
O
ST
—
Digital I/O.
ECCP1 PWM Output C.
RE6/P1B
RE6
P1B(2)
74
I/O
O
ST
—
Digital I/O.
ECCP1 PWM Output B.
RE7/ECCP2/P2A
RE7
ECCP2(3)
P2A(3)
73
I/O
I/O
O
ST
ST
—
Digital I/O.
Capture 2 input/Compare 2 output/PWM2 output.
ECCP2 PWM Output A.
TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.
2: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
3: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared.
4: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
2011 Microchip Technology Inc. DS39762F-page 29
PIC18F97J60 FAMILY
PORTF is a bidirectional I/O port.
RF1/AN6/C2OUT
RF1
AN6
C2OUT
23
I/O
I
O
ST
Analog
—
Digital I/O.
Analog Input 6.
Comparator 2 output.
RF2/AN7/C1OUT
RF2
AN7
C1OUT
18
I/O
I
O
ST
Analog
—
Digital I/O.
Analog Input 7.
Comparator 1 output.
RF3/AN8
RF3
AN8
17
I/O
I
ST
Analog
Digital I/O.
Analog Input 8.
RF4/AN9
RF4
AN9
16
I/O
I
ST
Analog
Digital I/O.
Analog Input 9.
RF5/AN10/CVREF
RF5
AN10
CVREF
15
I/O
I
O
ST
Analog
—
Digital I/O.
Analog Input 10.
Comparator reference voltage output.
RF6/AN11
RF6
AN11
14
I/O
I
ST
Analog
Digital I/O.
Analog Input 11.
RF7/SS1
RF7
SS1
13
I/O
I
ST
TTL
Digital I/O.
SPI slave select input.
TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.
2: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
3: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared.
4: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
PIC18F97J60 FAMILY
DS39762F-page 30 2011 Microchip Technology Inc.
PORTG is a bidirectional I/O port.
RG0/ECCP3/P3A
RG0
ECCP3
P3A
56
I/O
I/O
O
ST
ST
—
Digital I/O.
Capture 3 input/Compare 3 output/PWM3 output.
ECCP3 PWM Output A.
RG1/TX2/CK2
RG1
TX2
CK2
55
I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART2 asynchronous transmit.
EUSART2 synchronous clock (see related RX2/DT2 pin).
RG2/RX2/DT2
RG2
RX2
DT2
42
I/O
I
I/O
ST
ST
ST
Digital I/O.
EUSART2 asynchronous receive.
EUSART2 synchronous data (see related TX2/CK2 pin).
RG3/CCP4/P3D
RG3
CCP4
P3D
41
I/O
I/O
O
ST
ST
—
Digital I/O.
Capture 4 input/Compare 4 output/PWM4 output.
ECCP3 PWM Output D.
RG4/CCP5/P1D
RG4
CCP5
P1D
10
I/O
I/O
O
ST
ST
—
Digital I/O.
Capture 5 input/Compare 5 output/PWM5 output.
ECCP1 PWM Output D.
TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.
2: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
3: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared.
4: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
2011 Microchip Technology Inc. DS39762F-page 31
PIC18F97J60 FAMILY
PORTH is a bidirectional I/O port.
RH0 79 I/O ST Digital I/O.
RH1 80 I/O ST Digital I/O.
RH2 1 I/O ST Digital I/O.
RH3 2 I/O ST Digital I/O.
RH4/AN12/P3C
RH4
AN12
P3C(4)
22
I/O
I
O
ST
Analog
—
Digital I/O.
Analog Input 12.
ECCP3 PWM Output C.
RH5/AN13/P3B
RH5
AN13
P3B(4)
21
I/O
I
O
ST
Analog
—
Digital I/O.
Analog Input 13.
ECCP3 PWM Output B.
RH6/AN14/P1C
RH6
AN14
P1C(4)
20
I/O
I
O
ST
Analog
—
Digital I/O.
Analog Input 14.
ECCP1 PWM Output C.
RH7/AN15/P1B
RH7
AN15
P1B(4)
19
I/O
I
O
ST
Analog
—
Digital I/O.
Analog Input 15.
ECCP1 PWM Output B.
TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.
2: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
3: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared.
4: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
PIC18F97J60 FAMILY
DS39762F-page 32 2011 Microchip Technology Inc.
PORTJ is a bidirectional I/O port.
RJ4 39 I/O ST Digital I/O.
RJ5 40 I/O ST Digital I/O
VSS 11, 31, 51, 70 P — Ground reference for logic and I/O pins.
VDD 32, 48, 71 P — Positive supply for peripheral digital logic and I/O pins.
AVSS 26 P — Ground reference for analog modules.
AVDD 25 P — Positive supply for analog modules.
ENVREG 24 I ST Enable for on-chip voltage regulator.
VDDCORE/VCAP
VDDCORE
VCAP
12
P
P
—
—
Core logic power or external filter capacitor connection.
Positive supply for microcontroller core logic
(regulator disabled).
External filter capacitor connection (regulator enabled).
VSSPLL 67 P — Ground reference for Ethernet PHY PLL.
VDDPLL 66 P — Positive 3.3V supply for Ethernet PHY PLL.
VSSTX 64 P — Ground reference for Ethernet PHY transmit subsystem.
VDDTX 61 P — Positive 3.3V supply for Ethernet PHY transmit subsystem.
VSSRX 57 P — Ground reference for Ethernet PHY receive subsystem.
VDDRX 60 P — Positive 3.3V supply for Ethernet PHY receive subsystem.
RBIAS 65 I Analog Bias current for Ethernet PHY. Must be tied to VSS via a resistor;
see Section 19.0 “Ethernet Module” for specification.
TPOUT+ 63 O — Ethernet differential signal output.
TPOUT- 62 O — Ethernet differential signal output.
TPIN+ 59 I Analog Ethernet differential signal input.
TPIN- 58 I Analog Ethernet differential signal input.
TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.
2: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
3: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared.
4: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
2011 Microchip Technology Inc. DS39762F-page 33
PIC18F97J60 FAMILY
TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS
Pin Name Pin Number Pin
Type Buffer
Type Description
TQFP
MCLR 13 I ST Master Clear (Reset) input. This pin is an active-low Reset to
the device.
OSC1/CLKI
OSC1
CLKI
63
I
I
ST
CMOS
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in internal RC mode; CMOS
otherwise.
External clock source input. Always associated with
pin function, OSC1. (See related OSC2/CLKO pin.)
OSC2/CLKO
OSC2
CLKO
64
O
O
—
—
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or resonator
in Crystal Oscillator mode.
In Internal RC mode, OSC2 pin outputs CLKO which has 1/4
the frequency of OSC1 and denotes the instruction cycle rate.
PORTA is a bidirectional I/O port.
RA0/LEDA/AN0
RA0
LEDA
AN0
35
I/O
O
I
TTL
—
Analog
Digital I/O.
Ethernet LEDA indicator output.
Analog Input 0.
RA1/LEDB/AN1
RA1
LEDB
AN1
34
I/O
O
I
TTL
—
Analog
Digital I/O.
Ethernet LEDB indicator output.
Analog Input 1.
RA2/AN2/VREF-
RA2
AN2
VREF-
33
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog Input 2.
A/D reference voltage (low) input.
RA3/AN3/VREF+
RA3
AN3
VREF+
32
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog Input 3.
A/D reference voltage (high) input.
RA4/T0CKI
RA4
T0CKI
42
I/O
I
ST
ST
Digital I/O.
Timer0 external clock input.
RA5/AN4
RA5
AN4
41
I/O
I
TTL
Analog
Digital I/O.
Analog Input 4.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
PIC18F97J60 FAMILY
DS39762F-page 34 2011 Microchip Technology Inc.
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0/FLT0
RB0
INT0
FLT0
5
I/O
I
I
TTL
ST
ST
Digital I/O.
External Interrupt 0.
Enhanced PWM Fault input (ECCP modules); enabled
in software.
RB1/INT1
RB1
INT1
6
I/O
I
TTL
ST
Digital I/O.
External Interrupt 1.
RB2/INT2
RB2
INT2
7
I/O
I
TTL
ST
Digital I/O.
External Interrupt 2.
RB3/INT3/ECCP2/P2A
RB3
INT3
ECCP2(1)
P2A(1)
8
I/O
I
I/O
O
TTL
ST
ST
—
Digital I/O.
External Interrupt 3.
Capture 2 input/Compare 2 output/PWM2 output.
ECCP2 PWM Output A.
RB4/KBI0
RB4
KBI0
69
I/O
I
TTL
TTL
Digital I/O.
Interrupt-on-change pin.
RB5/KBI1
RB5
KBI1
68
I/O
I
TTL
TTL
Digital I/O.
Interrupt-on-change pin.
RB6/KBI2/PGC
RB6
KBI2
PGC
67
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.
RB7/KBI3/PGD
RB7
KBI3
PGD
57
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
2011 Microchip Technology Inc. DS39762F-page 35
PIC18F97J60 FAMILY
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
44
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
RC1/T1OSI/ECCP2/P2A
RC1
T1OSI
ECCP2(2)
P2A(2)
43
I/O
I
I/O
O
ST
CMOS
ST
—
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
ECCP2 PWM Output A.
RC2/ECCP1/P1A
RC2
ECCP1
P1A
53
I/O
I/O
O
ST
ST
—
Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
ECCP1 PWM Output A.
RC3/SCK1/SCL1
RC3
SCK1
SCL1
54
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
RC4/SDI1/SDA1
RC4
SDI1
SDA1
55
I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI data in.
I2C data I/O.
RC5/SDO1
RC5
SDO1
56
I/O
O
ST
—
Digital I/O.
SPI data out.
RC6/TX1/CK1
RC6
TX1
CK1
45
I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART1 asynchronous transmit.
EUSART1 synchronous clock (see related RX1/DT1 pin).
RC7/RX1/DT1
RC7
RX1
DT1
46
I/O
I
I/O
ST
ST
ST
Digital I/O.
EUSART1 asynchronous receive.
EUSART1 synchronous data (see related TX1/CK1 pin).
TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
PIC18F97J60 FAMILY
DS39762F-page 36 2011 Microchip Technology Inc.
PORTD is a bidirectional I/O port.
RD0/AD0/PSP0
RD0
AD0
PSP0
92
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External Memory Address/Data 0.
Parallel Slave Port data.
RD1/AD1/PSP1
RD1
AD1
PSP1
91
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External Memory Address/Data 1.
Parallel Slave Port data.
RD2/AD2/PSP2
RD2
AD2
PSP2
90
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External Memory Address/Data 2.
Parallel Slave Port data.
RD3/AD3/PSP3
RD3
AD3
PSP3
89
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External Memory Address/Data 3.
Parallel Slave Port data.
RD4/AD4/PSP4/SDO2
RD4
AD4
PSP4
SDO2
88
I/O
I/O
I/O
O
ST
TTL
TTL
—
Digital I/O.
External Memory Address/Data 4.
Parallel Slave Port data.
SPI data out.
RD5/AD5/PSP5/
SDI2/SDA2
RD5
AD5
PSP5
SDI2
SDA2
87
I/O
I/O
I/O
I
I/O
ST
TTL
TTL
ST
ST
Digital I/O.
External Memory Address/Data 5.
Parallel Slave Port data.
SPI data in.
I2C™ data I/O.
RD6/AD6/PSP6/
SCK2/SCL2
RD6
AD6
PSP6
SCK2
SCL2
84
I/O
I/O
I/O
I/O
I/O
ST
TTL
TTL
ST
ST
Digital I/O.
External Memory Address/Data 6.
Parallel Slave Port data.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
RD7/AD7/PSP7/SS2
RD7
AD7
PSP7
SS2
83
I/O
I/O
I/O
I
ST
TTL
TTL
TTL
Digital I/O.
External Memory Address/Data 7.
Parallel Slave Port data.
SPI slave select input.
TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
2011 Microchip Technology Inc. DS39762F-page 37
PIC18F97J60 FAMILY
PORTE is a bidirectional I/O port.
RE0/AD8/RD/P2D
RE0
AD8
RD
P2D
4
I/O
I/O
I
O
ST
TTL
TTL
—
Digital I/O.
External Memory Address/Data 8.
Read control for Parallel Slave Port.
ECCP2 PWM Output D.
RE1/AD9/WR/P2C
RE1
AD9
WR
P2C
3
I/O
I/O
I
O
ST
TTL
TTL
—
Digital I/O.
External Memory Address/Data 9.
Write control for Parallel Slave Port.
ECCP2 PWM Output C.
RE2/AD10/CS/P2B
RE2
AD10
CS
P2B
98
I/O
I/O
I
O
ST
TTL
TTL
—
Digital I/O.
External Memory Address/Data 10.
Chip select control for Parallel Slave Port.
ECCP2 PWM Output B.
RE3/AD11/P3C
RE3
AD11
P3C(3)
97
I/O
I/O
O
ST
TTL
—
Digital I/O.
External Memory Address/Data 11.
ECCP3 PWM Output C.
RE4/AD12/P3B
RE4
AD12
P3B(3)
96
I/O
I/O
O
ST
TTL
—
Digital I/O.
External Memory Address/Data 12.
ECCP3 PWM Output B.
RE5/AD13/P1C
RE5
AD13
P1C(3)
95
I/O
I/O
O
ST
TTL
—
Digital I/O.
External Memory Address/Data 13.
ECCP1 PWM Output C.
RE6/AD14/P1B
RE6
AD14
P1B(3)
94
I/O
I/O
O
ST
TTL
—
Digital I/O.
External Memory Address/Data 14.
ECCP1 PWM Output B.
RE7/AD15/ECCP2/P2A
RE7
AD15
ECCP2(4)
P2A(4)
93
I/O
I/O
I/O
O
ST
TTL
ST
—
Digital I/O.
External Memory Address/Data 15.
Capture 2 input/Compare 2 output/PWM2 output.
ECCP2 PWM Output A.
TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
PIC18F97J60 FAMILY
DS39762F-page 38 2011 Microchip Technology Inc.
PORTF is a bidirectional I/O port.
RF0/AN5
RF0
AN5
12
I/O
I
ST
Analog
Digital I/O.
Analog Input 5.
RF1/AN6/C2OUT
RF1
AN6
C2OUT
28
I/O
I
O
ST
Analog
—
Digital I/O.
Analog Input 6.
Comparator 2 output.
RF2/AN7/C1OUT
RF2
AN7
C1OUT
23
I/O
I
O
ST
Analog
—
Digital I/O.
Analog Input 7.
Comparator 1 output.
RF3/AN8
RF3
AN8
22
I/O
I
ST
Analog
Digital I/O.
Analog Input 8.
RF4/AN9
RF4
AN9
21
I/O
I
ST
Analog
Digital I/O.
Analog Input 9.
RF5/AN10/CVREF
RF5
AN10
CVREF
20
I/O
I
O
ST
Analog
—
Digital I/O.
Analog Input 10.
Comparator reference voltage output.
RF6/AN11
RF6
AN11
19
I/O
I
ST
Analog
Digital I/O.
Analog Input 11.
RF7/SS1
RF7
SS1
18
I/O
I
ST
TTL
Digital I/O.
SPI slave select input.
TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
2011 Microchip Technology Inc. DS39762F-page 39
PIC18F97J60 FAMILY
PORTG is a bidirectional I/O port.
RG0/ECCP3/P3A
RG0
ECCP3
P3A
71
I/O
I/O
O
ST
ST
—
Digital I/O.
Capture 3 input/Compare 3 output/PWM3 output.
ECCP3 PWM Output A.
RG1/TX2/CK2
RG1
TX2
CK2
70
I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART2 asynchronous transmit.
EUSART2 synchronous clock (see related RX2/DT2 pin).
RG2/RX2/DT2
RG2
RX2
DT2
52
I/O
I
I/O
ST
ST
ST
Digital I/O.
EUSART2 asynchronous receive.
EUSART2 synchronous data (see related TX2/CK2 pin).
RG3/CCP4/P3D
RG3
CCP4
P3D
51
I/O
I/O
O
ST
ST
—
Digital I/O.
Capture 4 input/Compare 4 output/PWM4 output.
ECCP3 PWM Output D.
RG4/CCP5/P1D
RG4
CCP5
P1D
14
I/O
I/O
O
ST
ST
—
Digital I/O.
Capture 5 input/Compare 5 output/PWM5 output.
ECCP1 PWM Output D.
RG5 11 I/O ST Digital I/O.
RG6 10 I/O ST Digital I/O.
RG7 38 I/O ST Digital I/O.
TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
PIC18F97J60 FAMILY
DS39762F-page 40 2011 Microchip Technology Inc.
PORTH is a bidirectional I/O port.
RH0/A16
RH0
A16
99
I/O
O
ST
—
Digital I/O.
External Memory Address 16.
RH1/A17
RH1
A17
100
I/O
O
ST
—
Digital I/O.
External Memory Address 17.
RH2/A18
RH2
A18
1
I/O
O
ST
—
Digital I/O.
External Memory Address 18.
RH3/A19
RH3
A19
2
I/O
O
ST
—
Digital I/O.
External Memory Address 19.
RH4/AN12/P3C
RH4
AN12
P3C(5)
27
I/O
I
O
ST
Analog
—
Digital I/O.
Analog Input 12.
ECCP3 PWM Output C.
RH5/AN13/P3B
RH5
AN13
P3B(5)
26
I/O
I
O
ST
Analog
—
Digital I/O.
Analog Input 13.
ECCP3 PWM Output B.
RH6/AN14/P1C
RH6
AN14
P1C(5)
25
I/O
I
O
ST
Analog
—
Digital I/O.
Analog Input 14.
ECCP1 PWM Output C.
RH7/AN15/P1B
RH7
AN15
P1B(5)
24
I/O
I
O
ST
Analog
—
Digital I/O.
Analog Input 15.
ECCP1 PWM Output B.
TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
2011 Microchip Technology Inc. DS39762F-page 41
PIC18F97J60 FAMILY
PORTJ is a bidirectional I/O port.
RJ0/ALE
RJ0
ALE
49
I/O
O
ST
—
Digital I/O.
External memory address latch enable.
RJ1/OE
RJ1
OE
50
I/O
O
ST
—
Digital I/O.
External memory output enable.
RJ2/WRL
RJ2
WRL
66
I/O
O
ST
—
Digital I/O.
External memory write low control.
RJ3/WRH
RJ3
WRH
61
I/O
O
ST
—
Digital I/O.
External memory write high control.
RJ4/BA0
RJ4
BA0
47
I/O
O
ST
—
Digital I/O.
External Memory Byte Address 0 control.
RJ5/CE
RJ5
CE
48
I/O
O
ST
—
Digital I/O
External memory chip enable control.
RJ6/LB
RJ6
LB
58
I/O
O
ST
—
Digital I/O.
External memory low byte control.
RJ7/UB
RJ7
UB
39
I/O
O
ST
—
Digital I/O.
External memory high byte control.
TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
PIC18F97J60 FAMILY
DS39762F-page 42 2011 Microchip Technology Inc.
NC 9 — — No connect.
VSS 15, 36, 40,
60, 65, 85
P — Ground reference for logic and I/O pins.
VDD 17, 37, 59,
62, 86
P — Positive supply for peripheral digital logic and I/O pins.
AVSS 31 P — Ground reference for analog modules.
AVDD 30 P — Positive supply for analog modules.
ENVREG 29 I ST Enable for on-chip voltage regulator.
VDDCORE/VCAP
VDDCORE
VCAP
16
P
P
—
—
Core logic power or external filter capacitor connection.
Positive supply for microcontroller core logic
(regulator disabled).
External filter capacitor connection (regulator enabled).
VSSPLL 82 P — Ground reference for Ethernet PHY PLL.
VDDPLL 81 P — Positive 3.3V supply for Ethernet PHY PLL.
VSSTX 79 P — Ground reference for Ethernet PHY transmit subsystem.
VDDTX 76 P — Positive 3.3V supply for Ethernet PHY transmit subsystem.
VSSRX 72 P — Ground reference for Ethernet PHY receive subsystem.
VDDRX 75 P — Positive 3.3V supply for Ethernet PHY receive subsystem.
RBIAS 80 I Analog Bias current for Ethernet PHY. Must be tied to VSS via a resistor;
see Section 19.0 “Ethernet Module” for specification.
TPOUT+ 78 O — Ethernet differential signal output.
TPOUT- 77 O — Ethernet differential signal output.
TPIN+ 74 I Analog Ethernet differential signal input.
TPIN- 73 I Analog Ethernet differential signal input.
TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
2011 Microchip Technology Inc. DS39762F-page 43
PIC18F97J60 FAMILY
2.0 GUIDELINES FOR GETTING
STARTED WITH PIC18FJ
MICROCONTROLLERS
2.1 Basic Connection Requirements
Getting started with the PIC18F97J60 family family of
8-bit microcontrollers requires attention to a minimal
set of device pin connections before proceeding with
development.
The following pins must always be connected:
•All V
DD and VSS pins
(see Section 2.2 “Power Supply Pins”)
•All AV
DD and AVSS pins, regardless of whether or
not the analog device features are used
(see Section 2.2 “Power Supply Pins”)
•MCLR
pin
(see Section 2.3 “Master Clear (MCLR) Pin”)
• ENVREG (if implemented) and VCAP/VDDCORE pins
(see Section 2.4 “Voltage Regulator Pins
(ENVREG and VCAP/VDDCORE)”)
These pins must also be connected if they are being
used in the end application:
• PGC/PGD pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
• OSCI and OSCO pins when an external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
Additionally, the following pins may be required:
•V
REF+/VREF- pins are used when external voltage
reference for analog modules is implemented
The minimum mandatory connections are shown in
Figure 2-1.
FIGURE 2-1: RECOMMENDED
MINIMUM CONNECTIONS
Note: The AVDD and AVSS pins must always be
connected, regardless of whether any of
the analog modules are being used.
PIC18FXXJXX
VDD
VSS
VDD
VSS
VSS
VDD
AVDD
AVSS
VDD
VSS
C1
R1
VDD
MCLR
VCAP/VDDCORE
R2 ENVREG
(1)
C7
C2(2)
C3(2)
C4(2)
C5(2)
C6(2)
Key (all values are recommendations):
C1 through C6: 0.1 F, 20V ceramic
C7: 10 F, 6.3V or greater, tantalum or ceramic
R1: 10 kΩ
R2: 100Ω to 470Ω
Note 1: See Section 2.4 “Voltage Regulator Pins
(ENVREG and VCAP/VDDCORE)” for
explanation of ENVREG pin connections.
2: The example shown is for a PIC18F device
with five VDD/VSS and AVDD/AVSS pairs.
Other devices may have more or less pairs;
adjust the number of decoupling capacitors
appropriately.
(1)
PIC18F97J60 FAMILY
DS39762F-page 44 2011 Microchip Technology Inc.
2.2 Power Suppl y Pins
2.2.1 DECOUPLING CAPACITORS
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS, is required.
Consider the following criteria when using decoupling
capacitors:
•Value and type of capacitor: A 0.1 F (100 nF),
10-20V capacitor is recommended. The capacitor
should be a low-ESR device, with a resonance
frequency in the range of 200 MHz and higher.
Ceramic capacitors are recommended.
•Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is no greater
than 0.25 inch (6 mm).
•Handling high-frequency noise: If the board is
experiencing high-frequency noise (upward of
tens of MHz), add a second ceramic type capaci-
tor in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 F to 0.001 F. Place this
second capacitor next to each primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible
(e.g., 0.1 F in parallel with 0.001 F).
•Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB trace
inductance.
2.2.2 TANK CAPACITORS
On boards with power traces running longer than
six inches in length, it is suggested to use a tank capac-
itor for integrated circuits, including microcontrollers, to
supply a local power source. The value of the tank
capacitor should be determined based on the trace
resistance that connects the power supply source to
the device, and the maximum current drawn by the
device in the application. In other words, select the tank
capacitor so that it meets the acceptable voltage sag at
the device. Typical values range from 4.7 F to 47 F.
2.3 Master Clear (MCLR) Pin
The MCLR pin provides two specific device
functions: Device Reset, and Device Programming
and Debugging. If programming and debugging are
not required in the end application, a direct
connection to VDD may be all that is required. The
addition of other components, to help increase the
application’s resistance to spurious Resets from
voltage sags, may be beneficial. A typical
configuration is shown in Figure 2-1. Other circuit
designs may be implemented, depending on the
application’s requirements.
During programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR pin. Consequently, specific voltage
levels (VIH and VIL) and fast signal transitions must
not be adversely affected. Therefore, specific values
of R1 and C1 will need to be adjusted based on the
application and PCB requirements. For example, it is
recommended that the capacitor, C1, be isolated
from the MCLR pin during programming and
debugging operations by using a jumper (Figure 2-2).
The jumper is replaced for normal run-time
operations.
Any components associated with the MCLR pin
should be placed within 0.25 inch (6 mm) of the pin.
FIGURE 2-2: EXAMPLE OF MCLR PIN
CONNECTIONS
Note 1: R1 10 k is recommended. A suggested
starting value is 10 k. Ensure that the
MCLR pin VIH and VIL specifications are met.
2: R2 470 will limit any current flowing into
MCLR from the external capacitor, C, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
C1
R2
R1
VDD
MCLR
PIC18FXXJXX
JP
2011 Microchip Technology Inc. DS39762F-page 45
PIC18F97J60 FAMILY
2.4 Voltage Regulator Pins (ENVREG
and VCAP/VDDCORE)
The on-chip voltage regulator enable pin, ENVREG,
must always be connected directly to either a supply
voltage or to ground. Tying ENVREG to VDD enables
the regulator, while tying it to ground disables the
regulator. Refer to Section 25.3 “On-Chip Voltage
Regulator” for details on connecting and using the
on-chip regulator.
When the regulator is enabled, a low-ESR (< 5Ω)
capacitor is required on the VCAP/VDDCORE pin to
stabilize the voltage regulator output voltage. The
VCAP/VDDCORE pin must not be connected to VDD and
must use a capacitor of 10 µF connected to ground. The
type can be ceramic or tantalum. Suitable examples of
capacitors are shown in Ta bl e 2-1 . Capacitors with
equivalent specifications can be used.
Designers may use Figure 2-3 to evaluate ESR
equivalence of candidate devices.
It is recommended that the trace length not exceed
0.25 inch (6 mm). Refer to 28.0 “Electrical
Characteristics” for additional information.
When the regulator is disabled, the VCAP/VDDCORE pin
must be tied to a voltage supply at the VDDCORE level.
Refer to 28.0 “Electrical Characteristics” for
information on VDD and VDDCORE.
Note that the “LF” versions of some low pin count
PIC18FJ parts (e.g., the PIC18LF45J10) do not have
the ENVREG pin. These devices are provided with the
voltage regulator permanently disabled; they must
always be provided with a supply voltage on the
VDDCORE pin.
FIGURE 2-3: FREQUENCY vs. ESR
PERFORMANCE FOR
SUGGESTED VCAP
.
10
1
0.1
0.01
0.001 0.01 0.1 1 10 100 1000 10,000
Frequ en cy (MH z)
ESR ()
Note: Typical data measurement at 25°C, 0V DC bias.
TABLE 2-1: SUITABLE CAPACITOR EQUIVALENTS
Make Part # Nominal
Capacitance Base Tolerance Rated Voltage Temp. Range
TDK C3216X7R1C106K 10 µF ±10% 16V -55 to 125ºC
TDK C3216X5R1C106K 10 µF ±10% 16V -55 to 85ºC
Panasonic ECJ-3YX1C106K 10 µF ±10% 16V -55 to 125ºC
Panasonic ECJ-4YB1C106K 10 µF ±10% 16V -55 to 85ºC
Murata GRM32DR71C106KA01L 10 µF ±10% 16V -55 to 125ºC
Murata GRM31CR61C106KC31L 10 µF ±10% 16V -55 to 85ºC
PIC18F97J60 FAMILY
DS39762F-page 46 2011 Microchip Technology Inc.
2.4.1 CONSIDERATIONS FOR CERAMIC
CAPACITORS
In recent years, large value, low-voltage, surface-mount
ceramic capacitors have become very cost effective in
sizes up to a few tens of microfarad. The low-ESR, small
physical size and other properties make ceramic
capacitors very attractive in many types of applications.
Ceramic capacitors are suitable for use with the
VDDCORE voltage regulator of this microcontroller.
However, some care is needed in selecting the capac-
itor to ensure that it maintains sufficient capacitance
over the intended operating range of the application.
Typical low-cost, 10 µF ceramic capacitors are available
in X5R, X7R and Y5V dielectric ratings (other types are
also available, but are less common). The initial toler-
ance specifications for these types of capacitors are
often specified as ±10% to ±20% (X5R and X7R), or
-20%/+80% (Y5V). However, the effective capacitance
that these capacitors provide in an application circuit will
also vary based on additional factors, such as the
applied DC bias voltage and the temperature. The total
in-circuit tolerance is, therefore, much wider than the
initial tolerance specification.
The X5R and X7R capacitors typically exhibit satisfac-
tory temperature stability (ex: ±15% over a wide
temperature range, but consult the manufacturer's data
sheets for exact specifications). However, Y5V capaci-
tors typically have extreme temperature tolerance
specifications of +22%/-82%. Due to the extreme
temperature tolerance, a 10 µF nominal rated Y5V type
capacitor may not deliver enough total capacitance to
meet minimum VDDCORE voltage regulator stability and
transient response requirements. Therefore, Y5V
capacitors are not recommended for use with the
VDDCORE regulator if the application must operate over
a wide temperature range.
In addition to temperature tolerance, the effective
capacitance of large value ceramic capacitors can vary
substantially, based on the amount of DC voltage
applied to the capacitor. This effect can be very signifi-
cant, but is often overlooked or is not always
documented.
A typical DC bias voltage vs. capacitance graph for
X7R type and Y5V type capacitors is shown in
Figure 2-4.
FIGURE 2-4: DC BIAS VOLTAGE vs.
CAPACITANCE
CHARACTERISTICS
When selecting a ceramic capacitor to be used with the
VDDCORE voltage regulator, it is suggested to select a
high-voltage rating, so that the operating voltage is a
small percentage of the maximum rated capacitor volt-
age. For example, choose a ceramic capacitor rated at
16V for the 2.5V VDDCORE voltage. Suggested
capacitors are shown in Table 2-1.
2.5 ICSP Pin s
The PGC and PGD pins are used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes. It
is recommended to keep the trace length between the
ICSP connector and the ICSP pins on the device as
short as possible. If the ICSP connector is expected to
experience an ESD event, a series resistor is recom-
mended, with the value in the range of a few tens of
ohms, not to exceed 100Ω.
Pull-up resistors, series diodes, and capacitors on the
PGC and PGD pins are not recommended as they will
interfere with the programmer/debugger communica-
tions to the device. If such discrete components are an
application requirement, they should be removed from
the circuit during programming and debugging. Alter-
natively, refer to the AC/DC characteristics and timing
requirements information in the respective device
Flash programming specification for information on
capacitive loading limits, and pin input voltage high
(VIH) and input low (VIL) requirements.
For device emulation, ensure that the “Communication
Channel Select” (i.e., PGCx/PGDx pins), programmed
into the device, matches the physical connections for
the ICSP to the Microchip debugger/emulator tool.
For more information on available Microchip
development tools connection requirements, refer to
Section 27.0 “Development Support”.
-80
-70
-60
-50
-40
-30
-20
-10
0
10
5 1011121314151617
DC Bias Voltage (VDC)
Capacitance Change (%)
01234 67 89
16V Capacitor
10V Capacitor
6.3V Capacitor
2011 Microchip Technology Inc. DS39762F-page 47
PIC18F97J60 FAMILY
2.6 External Oscillator Pins
Many microcontrollers have options for at least two
oscillators: a high-frequency primary oscillator and a
low-frequency secondary oscillator (refer to
Section 3.0 “Oscillator Configurations” for details).
The oscillator circuit should be placed on the same
side of the board as the device. Place the oscillator
circuit close to the respective oscillator pins with no
more than 0.5 inch (12 mm) between the circuit
components and the pins. The load capacitors should
be placed next to the oscillator itself, on the same side
of the board.
Use a grounded copper pour around the oscillator cir-
cuit to isolate it from surrounding circuits. The
grounded copper pour should be routed directly to the
MCU ground. Do not run any signal traces or power
traces inside the ground pour. Also, if using a two-sided
board, avoid any traces on the other side of the board
where the crystal is placed.
Layout suggestions are shown in Figure 2-5. In-line
packages may be handled with a single-sided layout
that completely encompasses the oscillator pins. With
fine-pitch packages, it is not always possible to com-
pletely surround the pins and components. A suitable
solution is to tie the broken guard sections to a mirrored
ground layer. In all cases, the guard trace(s) must be
returned to ground.
In planning the application’s routing and I/O assign-
ments, ensure that adjacent port pins, and other
signals in close proximity to the oscillator, are benign
(i.e., free of high frequencies, short rise and fall times,
and other similar noise).
For additional information and design guidance on
oscillator circuits, please refer to these Microchip
Application Notes, available at the corporate web site
(www.microchip.com):
•AN826, “Crystal Oscillator Ba sics and Crystal
Selection for rfPIC™ and PICmicro® Devices”
• AN849, “Basic PICmicro® Oscillator Design”
• AN943, “Practical PICmicro® Oscillator Analysis
and Design”
•AN949, “Ma king Your Oscillator Work ”
2.7 Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic low state. Alternatively, connect a 1 kΩ
to 10 kΩ resistor to VSS on unused pins and drive the
output to logic low.
FIGURE 2-5: SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
GND
`
`
`
OSC1
OSC2
T1OSO
T1OS I
Copper Pour Primary Oscillator
Crystal
Timer1 Oscillator
Crystal
DEVICE PINS
Primary
Oscillator
C1
C2
T1 Oscillator: C1 T1 Oscillator: C2
(tied to ground)
Single-Sided and In-Line Layouts:
Fine-Pitch (Dual-Sided) Layouts:
GND
OSCO
OSCI
Bottom Layer
Copper Pour
Oscillator
Crystal
Top Layer Copper Pour
C2
C1
DEVICE PINS
(tied to ground)
(tied to ground)
PIC18F97J60 FAMILY
DS39762F-page 48 2011 Microchip Technology Inc.
NOTES:
2011 Microchip Technology Inc. DS39762F-page 49
PIC18F97J60 FAMILY
3.0 OSCILLATOR
CONFIGURATIONS
3.1 Overview
Devices in the PIC18F97J60 family incorporate an
oscillator and microcontroller clock system that differs
from standard PIC18FXXJXX devices. The addition of
the Ethernet module, with its requirement for a stable
25 MHz clock source, makes it necessary to provide a
primary oscillator that can provide this frequency as
well as a range of different microcontroller clock
speeds. An overview of the oscillator structure is shown
in Figure 3-1.
Other oscillator features used in PIC18FXXJXX
enhanced microcontrollers, such as the internal RC
oscillator and clock switching, remain the same. They
are discussed later in this chapter.
3.2 Oscillator Types
The PIC18F97J60 family of devices can be operated in
five different oscillator modes:
1. HS High-Speed Crystal/Resonator
2. HSPLL High-Speed Crystal/Resonator
with Software PLL Control
3. EC External Clock with FOSC/4 Output
4. ECPLL External Clock with Software PLL
Control
5. INTRC Internal 31 kHz Oscillator
3.2.1 OSCILLATOR CONTROL
The oscillator mode is selected by programming the
FOSC<2:0> Configuration bits. FOSC<1:0> bits select
the default primary oscillator modes, while FOSC2
selects when INTRC may be invoked.
The OSCCON register (Register 3-2) selects the Active
Clock mode. It is primarily used in controlling clock
switching in power-managed modes. Its use is discussed
in Section 3.7.1 “O s ci lla tor Co ntro l Re gi ste r”.
The OSCTUNE register (Register 3-1) is used to select
the system clock frequency from the primary oscillator
source by selecting combinations of prescaler/postscaler
settings and enabling the PLL. Its use is described in
Section 3.6.1 “PL L Bl oc k” .
FIGURE 3-1: PIC18F97J60 FAMILY CLOCK DIAGRAM
PIC18F97J60 Family
5x PLL
FOSC<2:0>
Secondary Oscillator
T1OSCEN
Enable
Oscillator
T1OSO
T1OSI
Clock Source Option
for Other Modules
OSC1
OSC2
Sleep
Primary Oscillator
T1OSC
CPU
Peripherals
IDLEN
MUX
INTRC
Source
WDT, PWRT, FSCM
Internal Oscillator
Clock
Control
OSCCON<1:0>
and Two-Speed Start-up
Ethernet Clock
Prescaler Postscaler
PLL/Prescaler/Postscaler
PLL
OSCTUNE<7:5>(1)
PLL
EC, HS, ECPLL, HSPLL
Note 1: See Table 3-2 for OSCTUNE register configurations and their corresponding frequencies.
PIC18F97J60 FAMILY
DS39762F-page 50 2011 Microchip Technology Inc.
3.3 Cryst al Oscillator/Ceramic
Resonators (HS Modes)
In HS or HSPLL Oscillator modes, a crystal is
connected to the OSC1 and OSC2 pins to establish
oscillation. Figure 3-2 shows the pin connections.
The oscillator design requires the use of a crystal that
is rated for parallel resonant operation.
FIGURE 3-2: CRYSTAL OSCILLATOR
OPERATION (HS OR
HSPLL CONFIGURATION)
TABLE 3-1: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
3.4 External Clock Input (EC Modes)
The EC and ECPLL Oscillator modes require an exter-
nal clock source to be connected to the OSC1 pin.
There is no oscillator start-up time required after a
Power-on Reset or after an exit from Sleep mode.
In the EC Oscillator mode, the oscillator frequency,
divided by 4, is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 3-3 shows the pin connections for the EC
Oscillator mode.
FIGURE 3-3: EXTERNAL CLOCK
INPUT OPERATION
(EC CONFIGURATION)
An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in Figure 3-4. In
this configuration, the OSC2 pin is left open. Current
consumption in this configuration will be somewhat
higher than EC mode, as the internal oscillator’s
feedback circuitry will be enabled (in EC mode, the
feedback circuit is disabled).
FIGURE 3-4: EXTERNAL CLOCK
INPUT OPERATION
(HS CONFIGURATION)
Note: Use of a crystal rated for series resonant
operation may give a frequency out of the
crystal manufacturer’s specifications.
Osc Type Crystal
Freq.
Typical Cap acitor V alu es
Tested:
C1 C2
HS 25 MHz 33 pF 33 pF
Capacitor values are for design guidance only.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application. Refer
to the following application notes for oscillator specific
information:
• AN 5 88, “PIC® Microcontroller Osci llator Design
Guide”
• AN826, “Crystal Oscillator Basics and Crystal
Selection for rfPIC® and PIC® Devices”
• AN 8 49, “Bas ic PIC® Oscillator Design”
• AN 9 43, “Prac tic al PIC® Oscillator Analysis and
Design”
• A N9 49, “Ma ki ng Your Oscillator Work ”
See the notes following this table for additional
information.
Note 1: See Table 3-1 for initial values of C1 and C2.
2: A series resistor (RS) may be required for
crystals with a low drive specification.
3: RF varies with the oscillator mode chosen.
C1(1)
C2(1)
XTAL
OSC2
OSC1
RF(3)
Sleep
To
Logic
PIC18FXXJ6X
RS(2)
Internal
Note 1: Higher capacitance increases the stabil-
ity of the oscillator but also increases the
start-up time.
2: Since each crystal has its own character-
istics, the user should consult the crystal
manufacturer for appropriate values of
external components.
3: Rs may be required to avoid overdriving
crystals with low drive level specifications.
4: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
OSC1/CLKI
OSC2/CLKO
FOSC/4
Clock from
Ext. System PIC18FXXJ6X
OSC1
OSC2
Open
Clock from
Ext. System PIC18FXXJ6X
(HS Mode)
2011 Microchip Technology Inc. DS39762F-page 51
PIC18F97J60 FAMILY
3.5 Internal Oscillator Block
The PIC18F97J60 family of devices includes an internal
oscillator source (INTRC) which provides a nominal
31 kHz output. The INTRC is enabled on device
power-up and clocks the device during its configuration
cycle until it enters operating mode. INTRC is also
enabled if it is selected as the device clock source or if
any of the following are enabled:
• Fail-Safe Clock Monitor
• Watchdog Timer
• Two-Speed Start-up
These features are discussed in greater detail in
Section 25.0 “Special Features of the CPU”.
The INTRC can also be optionally configured as the
default clock source on device start-up by setting the
FOSC2 Configuration bit. This is discussed in
Section 3.7.1 “Oscillator Control Register”.
3.6 Ethernet Operation and the
Microcontroller Clock
Although devices of the PIC18F97J60 family can accept
a wide range of crystals and external oscillator inputs,
they must always have a 25 MHz clock source when
used for Ethernet applications. No provision is made for
internally generating the required Ethernet clock from a
primary oscillator source of a different frequency. A
frequency tolerance is specified, likely excluding the use
of ceramic resonators. See Section 28.0 “Electrical
Characteristics”, Table 28-6, Parameter 5, for more
details.
3.6.1 PLL BLOCK
To accommodate a range of applications and micro-
controller clock speeds, a separate PLL block is
incorporated into the clock system. It consists of three
components:
• A configurable prescaler (1:2 or 1:3)
• A 5x PLL frequency multiplier
• A configurable postscaler (1:1, 1:2, or 1:3)
The operation of the PLL block’s components is
controlled by the OSCTUNE register (Register 3-1).
The use of the PLL block’s prescaler and postscaler,
with or without the PLL itself, provides a range of
system clock frequencies to choose from, including the
unaltered 25 MHz of the primary oscillator. The full
range of possible oscillator configurations compatible
with Ethernet operation is shown in Ta b le 3 -2.
REGISTER 3-1: OSCTUNE: PLL BLOCK CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
PPST1 PLLEN(1) PPST0 PPRE — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 PPST1: PLL Postscaler Configuration bit
1 = Divide-by-2
0 = Divide-by-3
bit 6 PLLEN: 5x Frequency Multiplier PLL Enable bit(1)
1 = PLL is enabled
0 = PLL is disabled
bit 5 PPST0: PLL Postscaler Enable bit
1 = Postscaler is enabled
0 = Postscaler is disabled
bit 4 PPRE: PLL Prescaler Configuration bit
1 = Divide-by-2
0 = Divide-by-3
bit 3-0 Unimplemented: Read as ‘0’
Note 1: Available only for ECPLL and HSPLL oscillator configurations; otherwise, this bit is unavailable and is read
as ‘0’.
PIC18F97J60 FAMILY
DS39762F-page 52 2011 Microchip Technology Inc.
TABLE 3-2: DEVICE CLOCK SPEEDS FOR VARIOUS PLL BLOCK CONFIGURATIONS
3.7 Clock Sources and Oscillator
Switching
The PIC18F97J60 family of devices includes a feature
that allows the device clock source to be switched from
the main oscillator to an alternate clock source. These
devices also offer two alternate clock sources. When
an alternate clock source is enabled, the various
power-managed operating modes are available.
Essentially, there are three clock sources for these
devices:
• Primary oscillators
• Secondary oscillators
• Internal oscillator block
The primary oscillators include the External Crystal
and Resonator modes and the External Clock modes.
The particular mode is defined by the FOSC<2:0>
Configuration bits. The details of these modes are
covered earlier in this chapter.
The secondary oscillators are those external sources
not connected to the OSC1 or OSC2 pins. These
sources may continue to operate even after the controller
is placed in a power-managed mode. The PIC18F97J60
family of devices offers the Timer1 oscillator as a second-
ary oscillator. In all power-managed modes, this oscillator
is often the time base for functions such as a Real-Time
Clock (RTC).
Most often, a 32.768 kHz watch crystal is connected
between the RC0/T1OSO/T13CKI and RC1/T1OSI
pins. Loading capacitors are also connected from each
pin to ground. The Timer1 oscillator is discussed in
greater detail in Section 13.3 “Timer1 Oscillator”.
In addition to being a primary clock source, the internal
oscillator is available as a power-managed mode
clock source. The INTRC source is also used as the
clock source for several special features, such as the
WDT and Fail-Safe Clock Monitor.
The clock sources for the PIC18F97J60 family devices
are shown in Figure 3-1. See Section 25.0 “Special
Features of the CPU” for Configuration register details.
5x PLL PLL Prescaler PLL Postscaler PLL Block
Configuration
(OSCTUNE<7:4>)
Clock Frequency
(MHz)
Enabled
2
Disabled x101 (Note 1)
21111 31.2500
30111 20.8333
3
Disabled x100 41.6667
21110 20.8333
30110 13.8889
Disabled
Disabled(2) Disabled x00x 25 (Default)
221011 6.2500
30011 4.1667
321010 4.1667
30010 2.7778
Legend: x = Don’t care
Note 1: Reserved configuration; represents a clock frequency beyond the microcontroller’s operating range.
2: The prescaler is automatically disabled when the PLL and postscaler are both disabled.
2011 Microchip Technology Inc. DS39762F-page 53
PIC18F97J60 FAMILY
3.7.1 OSCILLATOR CONTROL REGISTER
The OSCCON register (Register 3-2) controls several
aspects of the device clock’s operation, both in
full-power operation and in power-managed modes.
The System Clock Select bits, SCS<1:0>, select the
clock source. The available clock sources are the
primary clock (defined by the FOSC<2:0> Configura-
tion bits), the secondary clock (Timer1 oscillator) and
the internal oscillator. The clock source changes after
one or more of the bits are changed, following a brief
clock transition interval.
The OSTS (OSCCON<3>) and T1RUN (T1CON<6>)
bits indicate which clock source is currently providing
the device clock. The T1RUN bit indicates when the
Timer1 oscillator is providing the device clock in
secondary clock modes. In power-managed modes,
only one of these bits will be set at any time. If neither
bit is set, the INTRC source is providing the clock, or
the internal oscillator has just started and is not yet
stable.
The IDLEN bit determines if the device goes into Sleep
mode or one of the Idle modes when the SLEEP
instruction is executed.
The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 4.0
“Power-M ana ged Modes”.
Note 1: The Timer1 oscillator must be enabled to
select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control reg-
ister (T1CON<3>). If the Timer1 oscillator
is not enabled, then any attempt to select
a secondary clock source will be ignored.
2: It is recommended that the Timer1
oscillator be operating and stable before
executing the SLEEP instruction or a very
long delay may occur while the Timer1
oscillator starts.
REGISTER 3-2: OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0 U-0 U-0 U-0 R-q U-0 R/W-0 R/W-0
IDLEN — — —OSTS
(1) —SCS1SCS0
bit 7 bit 0
Legend: q = Value determined by configuration
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IDLEN: Idle Enable bit
1 = Device enters Idle mode on SLEEP instruction
0 = Device enters Sleep mode on SLEEP instruction
bit 6-4 Unimplemented: Read as ‘0’
bit 3 OSTS: Oscillator Status bit(1)
1 = Device is running from oscillator source defined when SCS<1:0> = 00
0 = Device is running from oscillator source defined when SCS<1:0> = 01, 10 or 11
bit 2 Unimplemented: Read as ‘0’
bit 1-0 SCS<1:0>: System Clock Select bits
11 = Internal oscillator
10 = Primary oscillator
01 = Timer1 oscillator
When FOSC2 = 1;
00 = Primary oscillator
When FOSC2 = 0;
00 = Internal oscillator
Note 1: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
PIC18F97J60 FAMILY
DS39762F-page 54 2011 Microchip Technology Inc.
3.7.1.1 System Clock Selection and the
FOSC2 Configuration Bit
The SCS bits are cleared on all forms of Reset. In the
device’s default configuration, this means the primary
oscillator, defined by FOSC<1:0> (that is, one of the
HC or EC modes), is used as the primary clock source
on device Resets.
The default clock configuration on Reset can be changed
with the FOSC2 Configuration bit. This bit affects the
clock source selection setting when SCS<1:0> = 00.
When FOSC2 = 1 (default), the oscillator source
defined by FOSC<1:0> is selected whenever
SCS<1:0> = 00. When FOSC2 = 0, the INTRC oscillator
is selected whenever SCS<1:0> = 00. Because the SCS
bits are cleared on Reset, the FOSC2 setting also
changes the default oscillator mode on Reset.
Regardless of the setting of FOSC2, INTRC will always
be enabled on device power-up. It will serve as the
clock source until the device has loaded its configura-
tion values from memory. It is at this point that the
FOSC Configuration bits are read and the oscillator
selection of operational mode is made.
Note that either the primary clock or the internal
oscillator will have two bit setting options, at any given
time, depending on the setting of FOSC2.
3.7.2 OSCILLATOR TRANSITIONS
PIC18F97J60 family devices contain circuitry to
prevent clock “glitches” when switching between clock
sources. A short pause in the device clock occurs
during the clock switch. The length of this pause is the
sum of two cycles of the old clock source and three to
four cycles of the new clock source. This formula
assumes that the new clock source is stable.
Clock transitions are discussed in greater detail in
Section 4.1.2 “Entering Power-Managed Modes”.
3.8 Effects of Power-Managed Modes
on the Various Clock Sources
When PRI_IDLE mode is selected, the designated
primary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin if used by the oscillator) will stop oscillating.
In secondary clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and
providing the device clock. The Timer1 oscillator may
also run in all power-managed modes if required to
clock Timer1 or Timer3.
In RC_RUN and RC_IDLE modes, the internal oscilla-
tor provides the device clock source. The 31 kHz
INTRC output can be used directly to provide the clock
and may be enabled to support various special
features, regardless of the power-managed mode (see
Section 25.2 “Watchdog Timer (WDT)” through
Section 25.5 “Fail-Safe Clock Monitor” for more
information on WDT, Fail-Safe Clock Monitor and
Two-Speed Start-up).
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents have
been stopped, Sleep mode achieves the lowest current
consumption of the device (only leakage currents).
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a
Real-Time Clock. Other features may be operating that
do not require a device clock source (i.e., MSSP slave,
PSP, INTx pins and others). Peripherals that may add
significant current consumption are listed in
Section 28.2 “DC Characteristics: Power-Down and
Supply Current PIC18F97J60 Family (Industrial)”
3.9 Power- up De lays
Power-up delays are controlled by two timers, so that
no external Reset circuitry is required for most applica-
tions. The delays ensure that the device is kept in
Reset until the device power supply is stable under nor-
mal circumstances, and the primary clock is operating
and stable. For additional information on power-up
delays, see Section 5.6 “Power-up Timer (PWRT)”.
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (Parameter 33,
Table 28-12); it is always enabled.
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (HS modes). The OST does
this by counting 1024 oscillator cycles before allowing
the oscillator to clock the device.
There is a delay of interval, T
CSD (Parameter 38,
Table 28-12), following POR, while the controller
becomes ready to execute instructions.
TABLE 3-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE
Oscillator Mode OSC1 Pin OSC2 Pin
EC, ECPLL Floating, pulled by external clock At logic low (clock/4 output)
HS, HSPLL Feedback inverter is disabled at quiescent
voltage level
Feedback inverter is disabled at quiescent
voltage level
Note: See Table 5-2 in Section 5.0 “Reset” for time-outs due to Sleep and MCLR Reset.
2011 Microchip Technology Inc. DS39762F-page 55
PIC18F97J60 FAMILY
4.0 POWER-MANAGED MODE S
The PIC18F97J60 family devices provide the ability to
manage power consumption by simply managing clock-
ing to the CPU and the peripherals. In general, a lower
clock frequency and a reduction in the number of circuits
being clocked constitutes lower consumed power. For
the sake of managing power in an application, there are
three primary modes of operation:
• Run mode
• Idle mode
• Sleep mode
These modes define which portions of the device are
clocked and at what speed. The Run and Idle modes
may use any of the three available clock sources
(primary, secondary or internal oscillator block); the
Sleep mode does not use a clock source.
The power-managed modes include several
power-saving features offered on previous PIC® MCU
devices. One is the clock switching feature, offered in
other PIC18 devices, allowing the controller to use the
Timer1 oscillator in place of the primary oscillator. Also
included is the Sleep mode, offered by all PIC MCU
devices, where all device clocks are stopped.
4.1 Sel ecting Power-Managed Modes
Selecting a power-managed mode requires two
decisions: if the CPU is to be clocked or not and which
clock source is to be used. The IDLEN bit
(OSCCON<7>) controls CPU clocking, while the
SCS<1:0> bits (OSCCON<1:0>) select the clock
source. The individual modes, bit settings, clock sources
and affected modules are summarized in Table 4-1.
4.1.1 CLOCK SOURCES
The SCS<1:0> bits allow the selection of one of three
clock sources for power-managed modes. They are:
• The primary clock, as defined by the FOSC<2:0>
Configuration bits
• The secondary clock (Timer1 oscillator)
• The internal oscillator
4.1.2 ENTERING POWER-MANAGED
MODES
Switching from one power-managed mode to another
begins by loading the OSCCON register. The
SCS<1:0> bits select the clock source and determine
which Run or Idle mode is to be used. Changing these
bits causes an immediate switch to the new clock
source, assuming that it is running. The switch may
also be subject to clock transition delays. These are
discussed in Section 4.1.3 “Clock Transitions and
Status Indicators” and subsequent sections.
Entry to the power-managed Idle or Sleep modes is
triggered by the execution of a SLEEP instruction. The
actual mode that results depends on the status of the
IDLEN bit.
Depending on the current mode and the mode being
switched to, a change to a power-managed mode does
not always require setting all of these bits. Many
transitions may be done by changing the oscillator
select bits, or changing the IDLEN bit, prior to issuing a
SLEEP instruction. If the IDLEN bit is already
configured correctly, it may only be necessary to
perform a SLEEP instruction to switch to the desired
mode.
TABLE 4-1: POWER-M ANAGED MODES
Mode OSCCON<7,1:0> Module Clocking Available Clock and Oscillator Source
IDLEN(1) SCS<1:0> CPU Peripherals
Sleep 0N/A Off Off None – All clocks are disabled
PRI_RUN N/A 10 Clocked Clocked Primary – HS, EC, HSPLL, ECPLL;
this is the normal, full-power execution mode
SEC_RUN N/A 01 Clocked Clocked Secondary – Timer1 Oscillator
RC_RUN N/A 11 Clocked Clocked Internal Oscillator
PRI_IDLE 110Off Clocked Primary – HS, EC, HSPLL, ECPLL
SEC_IDLE 101Off Clocked Secondary – Timer1 Oscillator
RC_IDLE 111Off Clocked Internal Oscillator
Note 1: IDLEN reflects its value when the SLEEP instruction is executed.
PIC18F97J60 FAMILY
DS39762F-page 56 2011 Microchip Technology Inc.
4.1.3 CLOCK TRANSITIONS AND STATUS
INDICATORS
The length of the transition between clock sources is
the sum of two cycles of the old clock source and three
to four cycles of the new clock source. This formula
assumes that the new clock source is stable.
Two bits indicate the current clock source and its
status: OSTS (OSCCON<3>) and T1RUN
(T1CON<6>). In general, only one of these bits will be
set while in a given power-managed mode. When the
OSTS bit is set, the primary clock is providing the
device clock. When the T1RUN bit is set, the Timer1
oscillator is providing the clock. If neither of these bits
is set, INTRC is clocking the device.
4.1.4 MULTIPLE SLEEP COMMANDS
The power-managed mode that is invoked with the
SLEEP instruction is determined by the setting of the
IDLEN bit at the time the instruction is executed. If
another SLEEP instruction is executed, the device will
enter the power-managed mode specified by IDLEN at
that time. If IDLEN has changed, the device will enter the
new power-managed mode specified by the new setting.
4.2 Run Modes
In the Run modes, clocks to both the core and
peripherals are active. The difference between these
modes is the clock source.
4.2.1 PRI_RUN MODE
The PRI_RUN mode is the normal, full-power execu-
tion mode of the microcontroller. This is also the default
mode upon a device Reset unless Two-Speed Start-up
is enabled (see Section 25.4 “Two-Speed Start-up”
for details). In this mode, the OSTS bit is set. (see
Section 3.7.1 “Oscillator Control Register”).
4.2.2 SEC_RUN MODE
The SEC_RUN mode is the compatible mode to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the Timer1 oscillator. This gives users the
option of lower power consumption while still using a
high accuracy clock source.
SEC_RUN mode is entered by setting the SCS<1:0>
bits to ‘01’. The device clock source is switched to the
Timer1 oscillator (see Figure 4-1), the primary
oscillator is shut down, the T1RUN bit (T1CON<6>) is
set and the OSTS bit is cleared.
On transitions from SEC_RUN mode to PRI_RUN, the
peripherals and CPU continue to be clocked from the
Timer1 oscillator while the primary clock is started.
When the primary clock becomes ready, a clock switch
back to the primary clock occurs (see Figure 4-2).
When the clock switch is complete, the T1RUN bit is
cleared, the OSTS bit is set and the primary clock is
providing the clock. The IDLEN and SCS bits are not
affected by the wake-up; the Timer1 oscillator
continues to run.
Note: Executing a SLEEP instruction does not
necessarily place the device into Sleep
mode. It acts as the trigger to place the
controller into either the Sleep mode, or
one of the Idle modes, depending on the
setting of the IDLEN bit.
Note: The Timer1 oscillator should already be
running prior to entering SEC_RUN
mode. If the T1OSCEN bit is not set when
the SCS<1:0> bits are set to ‘01’, entry to
SEC_RUN mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, device clocks will be delayed until
the oscillator has started. In such
situations, initial oscillator operation is far
from stable and unpredictable operation
may result.
2011 Microchip Technology Inc. DS39762F-page 57
PIC18F97J60 FAMILY
FIGURE 4-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
FIGURE 4-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Q4Q3Q2
OSC1
Peripheral
Program
Q1
T1OSI
Q1
Counter
Clock
CPU
Clock
PC + 2PC
123
n-1
n
Clock Transition
Q4Q3Q2 Q1 Q3Q2
PC + 4
Q1 Q3 Q4
OSC1
Peripheral
Program PC
T1OSI
PLL Clock
Q1
PC + 4
Q2
Output
Q3 Q4 Q1
CPU Clock
PC + 2
Clock
Counter
Q2 Q2 Q3
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
SCS<1:0> bits Changed
TPLL(1)
12 n-1n
Clock
OSTS bit Set
Transition
TOST(1)
PIC18F97J60 FAMILY
DS39762F-page 58 2011 Microchip Technology Inc.
4.2.3 RC_RUN MODE
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator; the primary clock is
shut down. This mode provides the best power conser-
vation of all the Run modes while still executing code.
It works well for user applications which are not highly
timing-sensitive or do not require high-speed clocks at
all times.
This mode is entered by setting SCS<1:0> to ‘11’.
When the clock source is switched to the INTRC (see
Figure 4-3), the primary oscillator is shut down and the
OSTS bit is cleared.
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTRC
while the primary clock is started. When the primary
clock becomes ready, a clock switch to the primary
clock occurs (see Figure 4-4). When the clock switch is
complete, the OSTS bit is set and the primary clock is
providing the device clock. The IDLEN and SCS bits
are not affected by the switch. The INTRC source will
continue to run if either the WDT or Fail-Safe Clock
Monitor is enabled.
FIGURE 4-3: TRANSITION TIMING TO RC_RUN MODE
FIGURE 4-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
Q4Q3Q2
OSC1
Peripheral
Program
Q1
INTRC
Q1
Counter
Clock
CPU
Clock
PC + 2PC
123 n-1n
Clock Transition
Q4Q3Q2 Q1 Q3Q2
PC + 4
Q1 Q3 Q4
OSC1
Peripheral
Program PC
INTRC
PLL Clock
Q1
PC + 4
Q2
Output
Q3 Q4 Q1
CPU Clock
PC + 2
Clock
Counter
Q2 Q2 Q3
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
SCS<1:0> bits Changed
TPLL(1)
12 n-1n
Clock
OSTS bit Set
Transition
TOST(1)
2011 Microchip Technology Inc. DS39762F-page 59
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4.3 Sleep Mode
The power-managed Sleep mode is identical to the
legacy Sleep mode offered in all other PIC MCU
devices. It is entered by clearing the IDLEN bit (the
default state on device Reset) and executing the
SLEEP instruction. This shuts down the selected
oscillator (Figure 4-5). All clock source status bits are
cleared.
Entering the Sleep mode from any other mode does not
require a clock switch. This is because no clocks are
needed once the controller has entered Sleep. If the
WDT is selected, the INTRC source will continue to
operate. If the Timer1 oscillator is enabled, it will also
continue to run.
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the device will not be clocked
until the clock source selected by the SCS<1:0> bits
becomes ready (see Figure 4-6), or it will be clocked
from the internal oscillator if either the Two-Speed
Start-up or the Fail-Safe Clock Monitor is enabled (see
Section 25.0 “Special Features of the CPU”). In
either case, the OSTS bit is set when the primary clock
is providing the device clocks. The IDLEN and SCS bits
are not affected by the wake-up.
4.4 I dle Modes
The Idle modes allow the controller’s CPU to be
selectively shut down while the peripherals continue to
operate. Selecting a particular Idle mode allows users
to further manage power consumption.
If the IDLEN bit is set to ‘1’ when a SLEEP instruction is
executed, the peripherals will be clocked from the clock
source selected using the SCS<1:0> bits; however, the
CPU will not be clocked. The clock source status bits are
not affected. Setting IDLEN and executing a SLEEP
instruction provides a quick method of switching from a
given Run mode to its corresponding Idle mode.
If the WDT is selected, the INTRC source will continue
to operate. If the Timer1 oscillator is enabled, it will also
continue to run.
Since the CPU is not executing instructions, the only exits
from any of the Idle modes are by interrupt, WDT
time-out or a Reset. When a wake event occurs, CPU
execution is delayed by an interval of TCSD
(Parameter 38, Table 28-12) while it becomes ready to
execute code. When the CPU begins executing code, it
resumes with the same clock source for the current Idle
mode. For example, when waking from RC_IDLE mode,
the internal oscillator block will clock the CPU and periph-
erals (in other words, RC_RUN mode). The IDLEN and
SCS bits are not affected by the wake-up.
While in any Idle mode or Sleep mode, a WDT time-out
will result in a WDT wake-up to the Run mode currently
specified by the SCS<1:0> bits.
FIGURE 4-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE
FIGURE 4-6: TRANSITION TIMING FOR WAKE FROM SLEEP MODE (HSPLL)
Q4Q3Q2
OSC1
Peripheral
Sleep
Program
Q1Q1
Counter
Clock
CPU
Clock
PC + 2PC
Q3 Q4 Q1 Q2
OSC1
Peripheral
Program PC
PLL Clock
Q3 Q4
Output
CPU Clock
Q1 Q2 Q3 Q4 Q1 Q2
Clock
Counter PC + 6PC + 4
Q1 Q2 Q3 Q4
Wake Event
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
TOST(1) TPLL(1)
OSTS bit Set
PC + 2
PIC18F97J60 FAMILY
DS39762F-page 60 2011 Microchip Technology Inc.
4.4.1 PRI_IDLE MODE
This mode is unique among the three low-power Idle
modes in that it does not disable the primary device
clock. For timing-sensitive applications, this allows for
the fastest resumption of device operation with its more
accurate primary clock source, since the clock source
does not have to “warm up” or transition from another
oscillator.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEP instruc-
tion. If the device is in another Run mode, set IDLEN
first, then set the SCS<1:0> bits to ‘10’ and execute
SLEEP. Although the CPU is disabled, the peripherals
continue to be clocked from the primary clock source
specified by the FOSC<1:0> Configuration bits. The
OSTS bit remains set (see Figure 4-7).
When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval, TCSD, is
required between the wake event and when code
execution starts. This is required to allow the CPU to
become ready to execute instructions. After the
wake-up, the OSTS bit remains set. The IDLEN and
SCS bits are not affected by the wake-up (see
Figure 4-8).
4.4.2 SEC_IDLE MODE
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered from SEC_RUN by set-
ting the IDLEN bit and executing a SLEEP instruction. If
the device is in another Run mode, set IDLEN first, then
set SCS<1:0> to ‘01’ and execute SLEEP. When the
clock source is switched to the Timer1 oscillator, the
primary oscillator is shut down, the OSTS bit is cleared
and the T1RUN bit is set.
When a wake event occurs, the peripherals continue to
be clocked from the Timer1 oscillator. After an interval
of TCSD, following the wake event, the CPU begins exe-
cuting code being clocked by the Timer1 oscillator. The
IDLEN and SCS bits are not affected by the wake-up;
the Timer1 oscillator continues to run (see Figure 4-8).
FIGURE 4-7: TRANSITION TIM ING FOR ENTRY TO IDLE MODE
FIGURE 4-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Note: The Timer1 oscillator should already be
running prior to entering SEC_IDLE mode.
If the T1OSCEN bit is not set when the
SLEEP instruction is executed, the SLEEP
instruction will be ignored and entry to
SEC_IDLE mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, peripheral clocks will be delayed
until the oscillator has started. In such
situations, initial oscillator operation is far
from stable and unpredictable operation
may result.
Q1
Peripheral
Program PC PC + 2
OSC1
Q3 Q4 Q1
CPU Clock
Clock
Counter
Q2
OSC1
Peripheral
Program PC
CPU Clock
Q1 Q3 Q4
Clock
Counter
Q2
Wake Event
TCSD
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4.4.3 RC_IDLE MODE
In RC_IDLE mode, the CPU is disabled but the periph-
erals continue to be clocked from the internal oscillator.
This mode allows for controllable power conservation
during Idle periods.
From RC_RUN mode, RC_IDLE mode is entered by
setting the IDLEN bit and executing a SLEEP instruction.
If the device is in another Run mode, first set IDLEN,
then clear the SCS bits and execute SLEEP. When the
clock source is switched to the INTRC, the primary
oscillator is shut down and the OSTS bit is cleared.
When a wake event occurs, the peripherals continue to
be clocked from the INTRC. After a delay of TCSD
following the wake event, the CPU begins executing
code being clocked by the INTRC. The IDLEN and
SCS bits are not affected by the wake-up. The INTRC
source will continue to run if either the WDT or the
Fail-Safe Clock Monitor is enabled.
4.5 Exiting Idle and Sleep Modes
An exit from Sleep mode, or any of the Idle modes, is
triggered by an interrupt, a Reset or a WDT time-out.
This section discusses the triggers that cause exits
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
modes sections (see Section 4.2 “Run Modes”,
Section 4.3 “Sleep Mode” and Section 4.4 “Idle
Modes”).
4.5.1 EXIT BY INTERRUPT
Any of the available interrupt sources can cause the
device to exit from an Idle mode, or the Sleep mode, to
a Run mode. To enable this functionality, an interrupt
source must be enabled by setting its enable bit in one
of the INTCON or PIE registers. The exit sequence is
initiated when the corresponding interrupt flag bit is set.
On all exits from Idle or Sleep modes by interrupt, code
execution branches to the interrupt vector if the
GIE/GIEH bit (INTCON<7>) is set. Otherwise, code
execution continues or resumes without branching
(see Section 10.0 “Interrupts”).
A fixed delay of interval, TCSD, following the wake event
is required when leaving the Sleep and Idle modes.
This delay is required for the CPU to prepare for execu-
tion. Instruction execution resumes on the first clock
cycle following this delay.
4.5.2 EXIT BY WDT TIME-OUT
A WDT time-out will cause different actions depending
on which power-managed mode the device is in when
the time-out occurs.
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in an exit from the
power-managed mode (see Section 4.2 “Run
Modes” and Section 4.3 “Sleep Mode”). If the device
is executing code (all Run modes), the time-out will
result in a WDT Reset (see Section 25.2 “Watchdog
Timer (WDT)”).
The WDT timer and postscaler are cleared by one of
the following events:
• Executing a SLEEP or CLRWDT instruction
• The loss of a currently selected clock source (if
the Fail-Safe Clock Monitor is enabled)
4.5.3 EXIT BY RESET
Exiting an Idle or Sleep mode by Reset automatically
forces the device to run from the INTRC.
4.5.4 EXIT WITHOUT AN OSCILLATOR
START-UP TIMER DELAY
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock source
is not stopped
• The primary clock source is either the EC or
ECPLL mode
In these instances, the primary clock source either
does not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (EC). However, a
fixed delay of interval, T
CSD, following the wake event
is still required when leaving the Sleep and Idle modes
to allow the CPU to prepare for execution. Instruction
execution resumes on the first clock cycle following this
delay.
PIC18F97J60 FAMILY
DS39762F-page 62 2011 Microchip Technology Inc.
NOTES:
2011 Microchip Technology Inc. DS39762F-page 63
PIC18F97J60 FAMILY
5.0 RESET
The PIC18F97J60 family of devices differentiates
between various kinds of Reset:
a) MCLR Reset during normal operation
b) MCLR Reset during power-managed modes
c) Power-on Reset (POR)
d) Brown-out Reset (BOR)
e) Configuration Mismatch (CM)
f) RESET Instruction
g) Stack Full Reset
h) Stack Underflow Reset
i) Watchdog Timer (WDT) Reset during execution
This section discusses Resets generated by hard
events (MCLR), power events (POR and BOR) and
Configuration Mismatches (CM). It also covers the
operation of the various start-up timers. Stack Reset
events are covered in Section 6.1.6.4 “S t ack Full and
Underflow Resets”. WDT Resets are covered in
Section 25.2 “Watchdog Timer (WDT)”.
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 5-1.
5.1 RCON Register
Device Reset events are tracked through the RCON
register (Register 5-1). The lower six bits of the register
indicate that a specific Reset event has occurred. In
most cases, these bits can only be set by the event and
must be cleared by the application after the event. The
state of these flag bits, taken together, can be read to
indicate the type of Reset that just occurred. This is
described in more detail in Section 5.7 “Reset State
of Registers”.
The RCON register also has a control bit for setting
interrupt priority (IPEN). Interrupt priority is discussed
in Section 10.0 “Interrupts”.
FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset
MCLR
VDD
WDT
Time-out
VDD Rise
Detect
PWRT
INTRC
POR Pulse
Chip_Reset
Brown-out
Reset(1)
RESET Instruction
Stack
Pointer
Stack Full/Underflow Reset
Sleep
( )_IDLE
32 s
Note 1: The ENVREG pin must be tied high to enable Brown-out Reset. The Brown-out Reset is provided by the on-chip
voltage regulator when there is insufficient source voltage to maintain regulation.
PWRT
11-Bit Ripple Counter
66 ms
S
RQ
Configuration Word Mismatch
PIC18F97J60 FAMILY
DS39762F-page 64 2011 Microchip Technology Inc.
REGISTER 5-1: RCON: RESET CONTROL REGISTER
R/W-0 U-0 R/W-1 R/W-1 R-1 R-1 R/W-0 R/W-0
IPEN —CMRI TO PD POR BOR
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6 Unimplemented: Read as ‘0’
bit 5 CM: Configuration Mismatch Flag bit
1 = A Configuration Mismatch Reset has not occurred
0 = A Configuration Mismatch Reset has occurred (must be set in software after a Configuration
Mismatch Reset occurs)
bit 4 RI: RESET Instruction Flag bit
1 = The RESET instruction was not executed (set by firmware only)
0 = The RESET instruction was executed causing a device Reset (must be set in software after a
Brown-out Reset occurs)
bit 3 TO: Watchdog Timer Time-out Flag bit
1 = Set by power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 2 PD: Power-Down Detection Flag bit
1 = Set by power-up or by the CLRWDT instruction
0 = Set by execution of the SLEEP instruction
bit 1 POR: Power-on Reset Status bit
1 = A Power-on Reset has not occurred (set by firmware only)
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = A Brown-out Reset has not occurred (set by firmware only)
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent
Power-on Resets may be detected.
2: If the on-chip voltage regulator is disabled, BOR remains ‘0’ at all times. See Section 5.4.1 “Detecting
BOR” for more information.
3: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to
‘1’ by software immediately after a Power-on Reset).
2011 Microchip Technology Inc. DS39762F-page 65
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5.2 Master Clear (MCLR)
The MCLR pin provides a method for triggering a hard
external Reset of the device. A Reset is generated by
holding the pin low. PIC18 extended microcontroller
devices have a noise filter in the MCLR Reset path
which detects and ignores small pulses.
The MCLR pin is not driven low by any internal Resets,
including the WDT.
5.3 Power- on Reset (POR)
A Power-on Reset condition is generated on-chip
whenever VDD rises above a certain threshold. This
allows the device to start in the initialized state when
VDD is adequate for operation.
To take advantage of the POR circuitry, tie the MCLR
pin through a resistor (1 k to 10 k) to VDD. This will
eliminate external RC components usually needed to
create a Power-on Reset delay. A minimum rise rate for
VDD is specified (Parameter D004). For a slow rise
time, see Figure 5-2.
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters
(voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
POR events are captured by the POR bit (RCON<1>).
The state of the bit is set to ‘0’ whenever a Power-on
Reset occurs; it does not change for any other Reset
event. POR is not reset to ‘1’ by any hardware event.
To capture multiple events, the user manually resets
the bit to ‘1’ in software following any Power-on Reset.
5.4 Brown-out Reset (BOR)
The PIC18F97J60 family of devices incorporates a
simple BOR function when the internal regulator is
enabled (ENVREG pin is tied to VDD). Any drop of VDD
below VBOR (Parameter D005), for greater than time,
TBOR (Parameter 35), will reset the device. A Reset
may or may not occur if VDD falls below VBOR for less
than TBOR. The chip will remain in Brown-out Reset
until VDD rises above VBOR.
Once a BOR has occurred, the Power-up Timer will
keep the chip in Reset for TPWRT (Parameter 33). If
VDD drops below VBOR while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power-up Timer will be initialized. Once VDD
rises above VBOR, the Power-up Timer will execute the
additional time delay.
FIGURE 5-2: EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
5.4.1 DETECTING BOR
The BOR bit always resets to ‘0’ on any Brown-out
Reset or Power-on Reset event. This makes it difficult
to determine if a Brown-out Reset event has occurred
just by reading the state of BOR alone. A more reliable
method is to simultaneously check the state of both
POR and BOR. This assumes that the POR bit is reset
to ‘1’ in software immediately after any Power-on Reset
event. If BOR is ‘0’ while POR is ‘1’, it can be reliably
assumed that a Brown-out Reset event has occurred.
If the voltage regulator is disabled, Brown-out Reset
functionality is disabled. In this case, the BOR bit
cannot be used to determine a Brown-out Reset event.
The BOR bit is still cleared by a Power-on Reset event.
5.5 Conf iguration Mismatch (CM)
The Configuration Mismatch (CM) Reset is designed to
detect and attempt to recover from random, memory
corrupting events. These include Electrostatic
Discharge (ESD) events which can cause widespread
single-bit changes throughout the device and result in
catastrophic failure.
In PIC18FXXJ Flash devices, the device Configuration
registers (located in the configuration memory space)
are continuously monitored during operation by com-
paring their values to complimentary shadow registers.
If a mismatch is detected between the two sets of
registers, a CM Reset automatically occurs. These
events are captured by the CM bit (RCON<5>). The
state of the bit is set to ‘0’ whenever a CM event occurs;
it does not change for any other Reset event.
Note 1: External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode, D, helps discharge the capacitor
quickly when VDD powers down.
2: R < 40 k is recommended to make sure that
the voltage drop across R does not violate
the device’s electrical specification.
3: R1 1 k will limit any current flowing into
MCLR from external capacitor, C, in the event
of MCLR/VPP pin breakdown, due to
Electrostatic Discharge (ESD), or Electrical
Overstress (EOS).
C
R1(3)
R(2)
D(1)
VDD
MCLR
PIC18FXXJ6X
VDD
PIC18F97J60 FAMILY
DS39762F-page 66 2011 Microchip Technology Inc.
A CM Reset behaves similarly to a Master Clear Reset,
RESET instruction, WDT time-out or Stack Event Reset.
As with all hard and power Reset events, the device
Configuration Words are reloaded from the Flash Con-
figuration Words in program memory as the device
restarts.
5.6 Power- up Timer (PWRT)
PIC18F97J60 family of devices incorporates an
on-chip Power-up Timer (PWRT) to help regulate the
Power-on Reset process. The PWRT is always
enabled. The main function is to ensure that the device
voltage is stable before code is executed.
The Power-up Timer (PWRT) of the PIC18F97J60 fam-
ily devices is an 11-bit counter which uses the INTRC
source as the clock input. This yields an approximate
time interval of 2048 x 32 s = 66 ms. While the PWRT
is counting, the device is held in Reset.
The power-up time delay depends on the INTRC clock
and will vary from chip-to-chip due to temperature and
process variation. See DC Parameter 33 for details.
5.6.1 TIME-OUT SEQUENCE
The PWRT time-out is invoked after the POR pulse has
cleared. The total time-out will vary based on the status
of the PWRT. Figure 5-3, Figure 5-4, Figure 5-5 and
Figure 5-6 all depict time-out sequences on power-up.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the PWRT will expire. Bringing
MCLR high will begin execution immediately
(Figure 5-5). This is useful for testing purposes or to
synchronize more than one PIC18FXXJ6X device
operating in parallel.
FIGURE 5-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
FIGURE 5-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
TPWRT
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
INTERNAL RESET
TPWRT
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
INTERNAL RESET
2011 Microchip Technology Inc. DS39762F-page 67
PIC18F97J60 FAMILY
FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
FIGURE 5-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
INTERNAL RESET
TPWRT
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
INTERNAL RESET
0V 1V
3.3V
TPWRT
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DS39762F-page 68 2011 Microchip Technology Inc.
5.7 Reset State of Registers
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up
since this is viewed as the resumption of normal
operation. Status bits from the RCON register (CM, RI,
TO, PD, POR and BOR) are set or cleared differently in
different Reset situations, as indicated in Tab le 5 -1 .
These bits are used in software to determine the nature
of the Reset.
Table 5-2 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets, and WDT wake-ups.
TABLE 5-1: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Condition Program
Counter(1) RCON Register STKPTR Register
CM RI TO PD POR BOR STKFUL STKUNF
Power-on Reset 0000h 111100 0 0
RESET Instruction 0000h u0uuuu u u
Brown-out Reset 0000h 1111u0 u u
Configuration Mismatch Reset 0000h 0uuuuu u u
MCLR during power-managed
Run modes
0000h uu1uuu u u
MCLR during power-managed
Idle modes and Sleep mode
0000h uu10uu u u
MCLR during full-power
execution
0000h uuuuuu u u
Stack Full Reset (STVREN = 1) 0000h uuuuuu 1 u
Stack Underflow Reset
(STVREN = 1)
0000h uuuuuu u 1
Stack Underflow Error (not an
actual Reset, STVREN = 0)
0000h uuuuuu u 1
WDT time-out during full power
or power-managed Run modes
0000h uu0uuu u u
WDT time-out during
power-managed Idle or Sleep
modes
PC + 2 uu00uu u u
Interrupt exit from
power-managed modes
PC + 2 uuu0uu u u
Legend: u = unchanged
Note 1: When the wake-up is due to an interrupt, and the GIEH or GIEL bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
2011 Microchip Technology Inc. DS39762F-page 69
PIC18F97J60 FAMILY
TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register Applicable Devices Power-on Reset,
Brown-out Reset
MCLR Reset,
WDT Reset,
RESET Instruction,
Stack Resets,
CM Reset
Wake-up via WDT
or Interrupt
TOSU PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---0 uuuu(1)
TOSH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu(1)
TOSL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu(1)
STKPTR PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 00-0 0000 uu-0 0000 uu-u uuuu(1)
PCLATU PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu
PCLATH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
PCL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 PC + 2(2)
TBLPTRU PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X --00 0000 --00 0000 --uu uuuu
TBLPTRH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
TBLPTRL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
TABLAT PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
PRODH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
PRODL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
INTCON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 000x 0000 000u uuuu uuuu(3)
INTCON2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu(3)
INTCON3 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1100 0000 1100 0000 uuuu uuuu(3)
INDF0 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A
POSTINC0 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A
POSTDEC0 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A
PREINC0 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A
PLUSW0 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A
FSR0H PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- xxxx ---- uuuu ---- uuuu
FSR0L PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
WREG PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
INDF1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A
POSTINC1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A
POSTDEC1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A
PREINC1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A
PLUSW1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A
FSR1H PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- xxxx ---- uuuu ---- uuuu
FSR1L PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
BSR PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- 0000 ---- 0000 ---- uuuu
INDF2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A
POSTINC2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A
POSTDEC2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A
PREINC2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A
PLUSW2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A
FSR2H PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- xxxx ---- uuuu ---- uuuu
FSR2L PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific condition.
PIC18F97J60 FAMILY
DS39762F-page 70 2011 Microchip Technology Inc.
STATUS PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---x xxxx ---u uuuu ---u uuuu
TMR0H PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
TMR0L PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
T0CON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu
OSCCON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0--- q-00 0--- q-00 u--- q-uu
ECON1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 00-- 0000 00-- uuuu uu--
WDTCON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- ---0 ---- ---0 ---- ---u
RCON(4) PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0-q1 1100 0-uq qquu u-uu qquu
TMR1H PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
TMR1L PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
T1CON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 u0uu uuuu uuuu uuuu
TMR2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
PR2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 1111 1111
T2CON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X -000 0000 -000 0000 -uuu uuuu
SSP1BUF PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
SSP1ADD PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
SSP1STAT PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
SSP1CON1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
SSP1CON2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
ADRESH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
ADRESL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0-00 0000 0-00 0000 u-uu uuuu
ADCON1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X --00 0000 --00 0000 --uu uuuu
ADCON2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0-00 0000 0-00 0000 u-uu uuuu
CCPR1H PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1L PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
CCPR2H PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
CCPR2L PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
CCP2CON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
CCPR3H PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
CCPR3L PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
CCP3CON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
ECCP1AS PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
CVRCON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
CMCON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0111 0000 0111 uuuu uuuu
TMR3H PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
TMR3L PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices Power-on R eset,
Brown-ou t Re set
MCLR Reset,
WDT Reset,
RESET Instruction,
Stack Resets,
CM Reset
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific condition.
2011 Microchip Technology Inc. DS39762F-page 71
PIC18F97J60 FAMILY
T3CON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 uuuu uuuu uuuu uuuu
PSPCON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 ---- 0000 ---- uuuu ----
SPBRG1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
RCREG1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
TXREG1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
TXSTA1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0010 0000 0010 uuuu uuuu
RCSTA1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 000x 0000 000x uuuu uuuu
EECON2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- ---- ---- ---- ---- ----
EECON1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 x00- ---0 x00- ---u uuu-
IPR3 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu
PIR3 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu(3)
PIE3 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
IPR2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1-11 1111 1-11 uuuu u-uu
PIR2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0-00 0000 0-00 uuuu u-uu(3)
PIE2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0-00 0000 0-00 uuuu u-uu
IPR1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu
PIR1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu(3)
PIE1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
MEMCON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0-00 --00 0-00 --00 u-uu --uu
OSCTUNE PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 ---- 0000 ---- uuuu ----
TRISJ PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X --11 ---- --11 ---- --uu ----
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu
TRISH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu
TRISG PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---1 ---- ---1 ---- ---u ----
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---1 1111 ---1 1111 ---u uuuu
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu
TRISF PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 111- 1111 111- uuuu uuu-
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu
TRISE PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X --11 1111 --11 1111 --uu uuuu
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu
TRISD PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- -111 ---- -111 ---- -uuu
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu
TRISC PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu
TRISB PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu
TRISA PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X --11 1111 --11 1111 --uu uuuu
LATJ PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X --xx ---- --uu ---- --uu ----
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
LATH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices Power-on Reset,
Brown-out Reset
MCLR Reset,
WDT Reset,
RESET Instruction,
Stack Resets,
CM Reset
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific condition.
PIC18F97J60 FAMILY
DS39762F-page 72 2011 Microchip Technology Inc.
LATG PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---x ---- ---u ---- ---u ----
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---x xxxx ---u uuuu ---u uuuu
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
LATF PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxx- uuuu uuu- uuuu uuu-
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
LATE PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X --xx xxxx --uu uuuu --uu uuuu
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
LATD PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- -xxx ---- -uuu ---- -uuu
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
LATC PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
LATB PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
LATA PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 00xx xxxx 00uu uuuu uuuu uuuu
PORTJ PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X --xx ---- --uu ---- --uu ----
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
PORTH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
PORTG PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---x ---- ---u ---- ---u ----
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---x xxxx ---u uuuu ---u uuuu
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 111x xxxx 111u uuuu uuuu uuuu
PORTF PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X x000 000- x000 000- uuuu uuu-
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X x000 000- x000 000- uuuu uuu-
PORTE PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X --xx xxxx --uu uuuu --uu uuuu
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
PORTD PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- -xxx ---- -uuu ---- -uuu
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
PORTC PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
PORTB PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
PORTA PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0-0x 0000 0-0u 0000 u-uu uuuu
SPBRGH1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
BAUDCON1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0100 0-00 0100 0-00 uuuu u-uu
SPBRGH2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
BAUDCON2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0100 0-00 0100 0-00 uuuu u-uu
ERDPTH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 1010 ---0 1010 ---u uuuu
ERDPTL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 0101 1111 0101 uuuu uuuu
ECCP1DEL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
TMR4 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
PR4 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 1111 1111
T4CON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X -000 0000 -000 0000 -uuu uuuu
CCPR4H PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
CCPR4L PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices Power-on R eset,
Brown-ou t Re set
MCLR Reset,
WDT Reset,
RESET Instruction,
Stack Resets,
CM Reset
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific condition.
2011 Microchip Technology Inc. DS39762F-page 73
PIC18F97J60 FAMILY
CCP4CON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X --00 0000 --00 0000 --uu uuuu
CCPR5H PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
CCPR5L PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
CCP5CON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X --00 0000 --00 0000 --uu uuuu
SPBRG2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
RCREG2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
TXREG2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
TXSTA2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0010 0000 0010 uuuu uuuu
RCSTA2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 000x 0000 000x uuuu uuuu
ECCP3AS PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
ECCP3DEL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
ECCP2AS PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
ECCP2DEL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
SSP2BUF PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
SSP2ADD PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
SSP2STAT PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
SSP2CON1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
SSP2CON2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
EDATA PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu
EIR PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X -000 0-00 -000 0-00 -uuu u-uu
ECON2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 100- ---- 100- ---- uuu- ----
ESTAT PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X -0-0 -000 -0-0 -000 -u-u -uuu
EIE PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X -000 0-00 -000 0-00 -uuu u-uu
EDMACSH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
EDMACSL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
EDMADSTH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu
EDMADSTL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
EDMANDH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu
EDMANDL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
EDMASTH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu
EDMASTL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
ERXWRPTH
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu
ERXWRPTL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
ERXRDPTH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0101 ---0 0101 ---u uuuu
ERXRDPTL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1010 1111 1010 uuuu uuuu
ERXNDH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---1 1111 ---1 1111 ---u uuuu
ERXNDL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu
ERXSTH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0101 ---0 0101 ---u uuuu
ERXSTL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1010 1111 1010 uuuu uuuu
TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices Power-on Reset,
Brown-out Reset
MCLR Reset,
WDT Reset,
RESET Instruction,
Stack Resets,
CM Reset
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific condition.
PIC18F97J60 FAMILY
DS39762F-page 74 2011 Microchip Technology Inc.
ETXNDH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu
ETXNDL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
ETXSTH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu
ETXSTL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
EWRPTH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu
EWRPTL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
EPKTCNT PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
ERXFCON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1010 0001 1010 0001 uuuu uuuu
EPMOH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu
EPMOL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
EPMCSH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
EPMCSL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
EPMM7 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
EPMM6 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
EPMM5 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
EPMM4 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
EPMM3 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
EPMM2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
EPMM1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
EPMM0 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
EHT7 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
EHT6 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
EHT5 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
EHT4 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
EHT3 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
EHT2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
EHT1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
EHT0 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
MIRDH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
MIRDL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
MIWRH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
MIWRL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
MIREGADR PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu
MICMD PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- --00 ---- --00 ---- --uu
MAMXFLH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0110 0000 0110 uuuu uuuu
MAMXFLL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices Power-on R eset,
Brown-ou t Re set
MCLR Reset,
WDT Reset,
RESET Instruction,
Stack Resets,
CM Reset
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific condition.
2011 Microchip Technology Inc. DS39762F-page 75
PIC18F97J60 FAMILY
MAIPGH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X -000 0000 -000 0000 -uuu uuuu
MAIPGL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X -000 0000 -000 0000 -uuu uuuu
MABBIPG PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X -000 0000 -000 0000 -uuu uuuu
MACON4 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X -000 --00 -000 --00 -uuu --uu
MACON3 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
MACON1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu
EPAUSH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0001 0000 0001 0000 000u uuuu
EPAUSL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
EFLOCON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- -000 ---- -000 ---- -uuu
MISTAT PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- 0000 ---- 0000 ---- uuuu
MAADR2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
MAADR1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
MAADR4 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
MAADR3 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
MAADR6 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
MAADR5 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices Power-on Reset,
Brown-out Reset
MCLR Reset,
WDT Reset,
RESET Instruction,
Stack Resets,
CM Reset
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific condition.
PIC18F97J60 FAMILY
DS39762F-page 76 2011 Microchip Technology Inc.
NOTES:
2011 Microchip Technology Inc. DS39762F-page 77
PIC18F97J60 FAMILY
6.0 MEMORY ORGANIZATION
There are two types of memory in PIC18 Flash
microcontroller devices:
• Program Memory
• Data RAM
As Harvard architecture devices, the data and program
memories use separate busses. This allows for
concurrent access of the two memory spaces.
Additional detailed information on the operation of the
Flash program memory is provided in Section 7.0
“Flash Program Memory”.
6.1 Program Memory Organization
PIC18 microcontrollers implement a 21-bit program
counter which is capable of addressing a 2-Mbyte
program memory space. Accessing a location between
the upper boundary of the physically implemented
memory and the 2-Mbyte address will return all ‘0’s (a
NOP instruction).
The entire PIC18F97J60 family offers three sizes of
on-chip Flash program memory, from 64 Kbytes (up
to 32,764 single-word instructions) to 128 Kbytes
(65,532 single-word instructions). The program mem-
ory maps for individual family members are shown in
Figure 6-1.
FIGURE 6-1: MEMORY MAPS FOR PIC18F97J60 FAMILY DEVICES
Note: Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail.
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
000000h
1FFFFFh
01FFFFh
PIC18FX6J60 PIC18FX6J65 PIC18FX7J60
00FFFFh
017FFFh
PC<20:0>
Stack Level 1
Stack Level 31
CALL, CALLW , RCAL L,
RETURN, RETFIE, RETLW,
21
User Memory Space
On-Chip
Memory
On-Chip
Memory
On-Chip
Memory
ADDULNK, SU BUL NK
Config. Words
Config. Words
Config. Words
PIC18F97J60 FAMILY
DS39762F-page 78 2011 Microchip Technology Inc.
6.1.1 HARD MEMORY VECTORS
All PIC18 devices have a total of three hard-coded
return vectors in their program memory space. The
Reset vector address is the default value to which the
program counter returns on all device Resets; it is
located at 0000h.
PIC18 devices also have two interrupt vector
addresses for the handling of high-priority and
low-priority interrupts. The high-priority interrupt vector
is located at 0008h and the low-priority interrupt vector
is at 0018h. Their locations in relation to the program
memory map are shown in Figure 6-2.
FIGURE 6-2: HARD VECTOR AND
CONFIGURATION WORD
LOCATIONS FOR
PIC18F97J60 FAMILY
DEVICES
6.1.2 FLASH CONFIGURATION WORDS
Because the PIC18F97J60 family devices do not have
persistent configuration memory, the top four words of
on-chip program memory are reserved for configuration
information. On Reset, the configuration information is
copied into the Configuration registers.
The Configuration Words are stored in their program
memory location in numerical order, starting with the
lower byte of CONFIG1 at the lowest address and end-
ing with the upper byte of CONFIG4. For these devices,
only Configuration Words, CONFIG1 through
CONFIG3, are used; CONFIG4 is reserved. The actual
addresses of the Flash Configuration Words for
devices in the PIC18F97J60 family are shown in
Table 6-1. Their location in the memory map is shown
with the other memory vectors in Figure 6-2.
Additional details on the device Configuration Words
are provided in Secti on 25.1 “Configuration Bits”.
TABLE 6-1: FLASH CONFIGURATION
WORDS FOR PIC18F97J60
FAMILY DEVICES
Reset Vector
Low-Priority Interrupt Vector
0000h
0018h
On-Chip
Program Memory
High-Priority Interrupt Vector 0008h
1FFFFFh
(Top of Memory)
(Top of Memory-7)
Flash Configuration Words
Read as ‘0’
Legend: (Top of Memory) represents upper boundary
of on-chip program memory space (see
Figure 6-1 for device-specific values).
Shaded area represents unimplemented
memory. Areas are not shown to scale.
Device Program
Memory
(Kbytes)
Configuration
Word Addresses
PIC18F66J60
64 FFF8h to FFFFhPIC18F86J60
PIC18F96J60
PIC18F66J65
96 17FF8h to
17FFFh
PIC18F86J65
PIC18F96J65
PIC18F67J60
128 1FFF8h to
1FFFFh
PIC18F87J60
PIC18F97J60
2011 Microchip Technology Inc. DS39762F-page 79
PIC18F97J60 FAMILY
6.1.3 PIC18F9XJ60/9XJ65 PROGRAM
MEMORY MODES
The 100-pin devices in this family can address up to a
total of 2 Mbytes of program memory. This is achieved
through the external memory bus. There are two
distinct operating modes available to the controllers:
• Microcontroller (MC)
• Extended Microcontroller (EMC)
The program memory mode is determined by setting
the EMB Configuration bits (CONFIG3L<5:4>), as
shown in Register 6-1. (Also see Section 25.1
“Configuration Bits” for additional details on the
device Configuration bits).
The program memory modes operate as follows:
•The Microcontroller Mode accesses only on-chip
Flash memory. Attempts to read above the top of
on-chip memory causes a read of all ‘0’s (a NOP
instruction).
The Microcontroller mode is also the only operating
mode available to 64-pin and 80-pin devices.
•The Extended Microcontroller Mode allows
access to both internal and external program
memories as a single block. The device can
access its entire on-chip program memory. Above
this, the device accesses external program
memory up to the 2-Mbyte program space limit.
Execution automatically switches between the
two memories as required.
The setting of the EMB Configuration bits also controls
the address bus width of the external memory bus. This
is covered in more detail in Section 8.0 “External
Memory Bus”.
In all modes, the microcontroller has complete access
to data RAM.
Figure 6-3 compares the memory maps of the different
program memory modes. The differences between
on-chip and external memory access limitations are
more fully explained in Table 6-2.
REGISTER 6-1: CONFIG3L: CONFIGURATION REGISTER 3 LOW
R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 U-0 U-0 U-0
WAIT(1) BW(1) EMB1(1) EMB0(1) EASHFT(1) — — —
bit 7 bit 0
Legend:
R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 WAIT: External Bus Wait Enable bit(1)
1 = Wait states for operations on external memory bus are disabled
0 = Wait states for operations on external memory bus are enabled and selected by MEMCON<5:4>
bit 6 BW: Data Bus Width Select bit(1)
1 = 16-Bit Data Width mode
0 = 8-Bit Data Width mode
bit 5-4 EMB<1:0>: External Memory Bus Configuration bits(1)
11 = Microcontroller mode, external bus disabled
10 = Extended Microcontroller mode,12-Bit Addressing mode
01 = Extended Microcontroller mode,16-Bit Addressing mode
00 = Extended Microcontroller mode, 20-Bit Addressing mode
bit 3 EASHFT: External Address Bus Shift Enable bit(1)
1 = Address shifting is enabled; address on external bus is offset to start at 000000h
0 = Address shifting is disabled; address on external bus reflects the PC value
bit 2-0 Unimplemented: Read as ‘0’
Note 1: Implemented on 100-pin devices only.
PIC18F97J60 FAMILY
DS39762F-page 80 2011 Microchip Technology Inc.
6.1.4 EXTENDED MICROCONTROLLER
MODE AND ADDRESS SHIFTING
By default, devices in Extended Microcontroller mode
directly present the program counter value on the
external address bus for those addresses in the range
of the external memory space. In practical terms, this
means addresses in the external memory device below
the top of on-chip memory are unavailable.
To avoid this, the Extended Microcontroller mode
implements an address shifting option to enable auto-
matic address translation. In this mode, addresses
presented on the external bus are shifted down by the
size of the on-chip program memory and are remapped
to start at 0000h. This allows the complete use of the
external memory device’s memory space.
FIGURE 6-3: MEMORY MAPS FOR PIC18F97J60 FAMILY PROGRAM MEMORY MODES
TABLE 6-2: MEMORY ACCESS FOR PIC18F9XJ60/9XJ65 PROGRAM MEMORY MODES
Operating Mod e
Internal Program Memory External Program Memory
Execution
From Table Read
From Table Write
To Execution
From Table Read
From Table Write
To
Microcontroller Yes Yes Yes No Access No Access No Access
Extended Microcontroller Yes Yes Yes Yes Yes Yes
External
Memory
On-Chip
Program
Memory
Microcontroller Mode(1)
000000h
On-Chip
Program
Memory
1FFFFFh
Reads
‘0’s
External On-Chip
Memory Memory
(Top of Memory)
(Top of Memory) + 1
Legend: (Top of Memory) represents upper boundary of on-chip program memory space (see Figure 6-1 for device-specific
values). Shaded areas represent unimplemented or inaccessible areas depending on the mode.
Note 1: This mode is the only available mode on 64-pin and 80-pin devices and the default on 100-pin devices.
2: These modes are only available in 100-pin devices.
Extended Microcontroller Mode(2)
000000h
1FFFFFh
(Top of Memory)
(Top of Memory) + 1 External
Memory
On-Chip
Program
Memory
000000h
1FFFFFh
(Top of Memory)
(Top of Memory) + 1
No
Access
Space
On-Chip
Memory
Space
External On-Chip
Memory Memory
Space
Mapped
to
External
Memory
Space
Space Space
Mapped
to
External
Memory
Space (Top of Memory)
Extended Microcontroller Mode
with Address Shifting(2)
1FFFFFh –
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6.1.5 PROGRAM COUNTER
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits wide
and is contained in three separate 8-bit registers. The
low byte, known as the PCL register, is both readable
and writable. The high byte, or PCH register, contains
the PC<15:8> bits; it is not directly readable or writable.
Updates to the PCH register are performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits; it is also not
directly readable or writable. Updates to the PCU
register are performed through the PCLATU register.
The contents of PCLATH and PCLATU are transferred
to the program counter by any operation that writes to
the PCL. Similarly, the upper two bytes of the program
counter are transferred to PCLATH and PCLATU by an
operation that reads PCL. This is useful for computed
offsets to the PC (see Section 6.1.8.1 “Computed
GOTO”).
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit of PCL is fixed to
a value of ‘0’. The PC increments by 2 to address
sequential instructions in the program memory.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
6.1.6 RETURN ADDRESS STACK
The return address stack allows any combination of up to
31 program calls and interrupts to occur. The PC is
pushed onto the stack when a CALL or RCALL instruction
is executed, or an interrupt is Acknowledged. The PC
value is pulled off the stack on a RETURN, RETLW or a
RETFIE instruction (and on ADDULNK and SUBULNK
instructions if the extended instruction set is enabled).
PCLATU and PCLATH are not affected by any of the
RETURN or CALL instructions.
The stack operates as a 31-word by 21-bit RAM and a
5-bit Stack Pointer, STKPTR. The stack space is not
part of either program or data space. The Stack Pointer
is readable and writable and the address on the top of
the stack is readable and writable through the
Top-of-Stack Special Function Registers. Data can also
be pushed to, or popped from the stack, using these
registers.
A CALL type instruction causes a push onto the stack.
The Stack Pointer is first incremented and the location
pointed to by the Stack Pointer is written with the
contents of the PC (already pointing to the instruction
following the CALL). A RETURN type instruction causes
a pop from the stack. The contents of the location
pointed to by the STKPTR are transferred to the PC
and then the Stack Pointer is decremented.
The Stack Pointer is initialized to ‘00000’ after all
Resets. There is no RAM associated with the location
corresponding to a Stack Pointer value of ‘00000’; this
is only a Reset value. Status bits indicate if the stack is
full, has overflowed or has underflowed.
6.1.6.1 Top-of-Stack Access
Only the top of the return address stack (TOS) is read-
able and writable. A set of three registers,
TOSU:TOSH:TOSL, holds the contents of the stack
location pointed to by the STKPTR register
(Figure 6-4). This allows users to implement a software
stack if necessary. After a CALL, RCALL or interrupt
(and ADDULNK and SUBULNK instructions if the
extended instruction set is enabled), the software can
read the pushed value by reading the
TOSU:TOSH:TOSL registers. These values can be
placed on a user-defined software stack. At return time,
the software can return these values to
TOSU:TOSH:TOSL and do a return.
The user must disable the Global Interrupt Enable bits
while accessing the stack to prevent inadvertent stack
corruption.
FIGURE 6-4: RETURN ADDRESS STACK A ND AS SOC IAT ED RE GIS T ERS
00011
001A34h
11111
11110
11101
00010
00001
00000
00010
Return Address Stack <20:0>
Top-o f-Stac k
000D58h
TOSLTOSHTOSU
34h1Ah00h
STKPTR<4:0>
Top-of-Stack Registers Stack Pointer
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DS39762F-page 82 2011 Microchip Technology Inc.
6.1.6.2 Return Stack Pointer (STKPTR)
The STKPTR register (Register 6-2) contains the Stack
Pointer value, the STKFUL (Stack Full) status bit and
the STKUNF (Stack Underflow) status bit. The value of
the Stack Pointer can be 0 through 31. The Stack
Pointer increments before values are pushed onto the
stack and decrements after values are popped off the
stack. On Reset, the Stack Pointer value will be zero.
The user may read and write the Stack Pointer value.
This feature can be used by a Real-Time Operating
System (RTOS) for return stack maintenance.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit is cleared by software or by a
POR.
The action that takes place when the stack becomes
full depends on the state of the STVREN (Stack Over-
flow Reset Enable) Configuration bit. (Refer to
Section 25.1 “Configuration Bit s” for a description of
the device Configuration bits.) If STVREN is set
(default), the 31st push will push the (PC + 2) value
onto the stack, set the STKFUL bit and reset the
device. The STKFUL bit will remain set and the Stack
Pointer will be set to zero.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the Stack Pointer will increment to 31.
Any additional pushes will not overwrite the 31st push
and the STKPTR will remain at 31.
When the stack has been popped enough times to
unload the stack, the next pop returns a value of zero
to the PC, and sets the STKUNF bit, while the Stack
Pointer remains at zero. The STKUNF bit will remain
set until cleared by software or until a POR occurs.
6.1.6.3 PUSH and POP Instructions
Since the Top-of-Stack is readable and writable, the
ability to push values onto the stack and pull values off
the stack, without disturbing normal program execu-
tion, is a desirable feature. The PIC18 instruction set
includes two instructions, PUSH and POP, that permit
the TOS to be manipulated under software control.
TOSU, TOSH and TOSL can be modified to place data
or a return address on the stack.
The PUSH instruction places the current PC value onto
the stack. This increments the Stack Pointer and loads
the current PC value onto the stack.
The POP instruction discards the current TOS by
decrementing the Stack Pointer. The previous value
pushed onto the stack then becomes the TOS value.
Note: Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken. This is
not the same as a Reset, as the contents
of the SFRs are not affected.
REGISTER 6-2: STKPTR: STACK POINTER REGISTER
R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0
bit 7 bit 0
Legend: C = Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 STKFUL: Stack Full Flag bit(1)
1 = Stack became full or overflowed
0 = Stack has not become full or overflowed
bit 6 STKUNF: Stack Underflow Flag bit(1)
1 = Stack underflow occurred
0 = Stack underflow did not occur
bit 5 Unimplemented: Read as ‘0’
bit 4-0 SP<4:0>: Stack Pointer Location bits
Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.
2011 Microchip Technology Inc. DS39762F-page 83
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6.1.6.4 Stack Full and Underflow Resets
Device Resets on stack overflow and stack underflow
conditions are enabled by setting the STVREN bit in
Configuration Register 1L. When STVREN is set, a full
or underflow condition will set the appropriate STKFUL
or STKUNF bit and then cause a device Reset. When
STVREN is cleared, a full or underflow condition will set
the appropriate STKFUL or STKUNF bit, but not cause
a device Reset. The STKFUL or STKUNF bit is cleared
by user software or a Power-on Reset.
6.1.7 FAST REGISTER STACK
A Fast Register Stack (FSR) is provided for the
STATUS, WREG and BSR registers to provide a “fast
return” option for interrupts. This stack is only one level
deep and is neither readable nor writable. It is loaded
with the current value of the corresponding register
when the processor vectors for an interrupt. All inter-
rupt sources will push values into the Stack registers.
The values in the registers are then loaded back into
the working registers if the RETFIE, FAST instruction
is used to return from the interrupt.
If both low and high-priority interrupts are enabled, the
Stack registers cannot be used reliably to return from
low-priority interrupts. If a high-priority interrupt occurs
while servicing a low-priority interrupt, the Stack
register values stored by the low-priority interrupt will
be overwritten. In these cases, users must save the key
registers in software during a low-priority interrupt.
If interrupt priority is not used, all interrupts may use the
Fast Register Stack for returns from interrupt. If no
interrupts are used, the Fast Register Stack can be
used to restore the STATUS, WREG and BSR registers
at the end of a subroutine call. To use the Fast Register
Stack for a subroutine call, a CALL label, FAST
instruction must be executed to save the STATUS,
WREG and BSR registers to the Fast Register Stack. A
RETURN, FAST instruction is then executed to restore
these registers from the Fast Register Stack.
Example 6-1 shows a source code example that uses
the Fast Register Stack during a subroutine call and
return.
EXAMPLE 6-1: FAST REGISTER STACK
CODE EXAMPLE
6.1.8 LOOK-UP TABLES IN PROGRAM
MEMORY
There may be programming situations that require the
creation of data structures, or look-up tables, in
program memory. For PIC18 devices, look-up tables
can be implemented in two ways:
• Computed GOTO
• Table Reads
6.1.8.1 Computed GOTO
A computed GOTO is accomplished by adding an offset
to the program counter. An example is shown in
Example 6-2.
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW nn instructions. The
W register is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW nn
instructions, that returns the value ‘nn’ to the calling
function.
The offset value (in WREG) specifies the number of
bytes that the program counter should advance and
should be multiples of 2 (LSb = 0).
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
EXAMPLE 6-2: COMPUTED GOTO USING
AN OFFSET VALUE
6.1.8.2 Table Reads
A better method of storing data in program memory
allows two bytes of data to be stored in each instruction
location.
Look-up table data may be stored, two bytes per
program word, while programming. The Table Pointer
(TBLPTR) specifies the byte address and the Table
Latch (TABLAT) contains the data that is read from the
program memory. Data is transferred from program
memory, one byte at a time.
Table read operation is discussed further in
Section 7.1 “Table Reads and Table Writes”.
CALL SUB1, FAST ;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
SUB1
RETURN FAST ;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
MOVF OFFSET, W
CALL TABLE
ORG nn00h
TABLE ADDWF PCL
RETLW nnh
RETLW nnh
RETLW nnh
.
.
.
PIC18F97J60 FAMILY
DS39762F-page 84 2011 Microchip Technology Inc.
6.2 PIC18 Instruction Cycle
6.2.1 CLOCKING SCHEME
The microcontroller clock input, whether from an
internal or external source, is internally divided by four
to generate four non-overlapping quadrature clocks
(Q1, Q2, Q3 and Q4). Internally, the program counter is
incremented on every Q1. The instruction is fetched
from the program memory and latched into the
Instruction Register (IR) during Q4. The instruction is
decoded and executed during the following Q1 through
Q4. The clocks and instruction execution flow are
shown in Figure 6-5.
6.2.2 INSTRUCTION FLOW/PIPELINING
An “Instruction Cycle” consists of four Q cycles, Q1
through Q4. The instruction fetch and execute are
pipelined in such a manner that a fetch takes one
instruction cycle, while the decode and execute take
another instruction cycle. However, due to the pipelining,
each instruction effectively executes in one cycle. If an
instruction causes the program counter to change
(e.g., GOTO), then two cycles are required to complete
the instruction (Example 6-3).
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the Q2,
Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination write).
FIGURE 6-5: CLOCK/INSTRUCTION CYCLE
EXAMPLE 6-3: INSTRUCTION PIPELINE FLOW
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKO
(RC mode)
PC PC + 2 PC + 4
Fetch INST (PC)
Execute INST (PC – 2)
Fetch INST (PC + 2)
Execute INST (PC)
Fetch INST (PC + 4)
Execute INST (PC + 2)
Internal
Phase
Clock
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
TCY0TCY1TCY2TCY3TCY4TCY5
1. MOVLW 55h Fetch 1 Execute 1
2. MOVWF PORTB Fetch 2 Execute 2
3. BRA SUB_1 Fetch 3 Execute 3
4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP)
5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1
2011 Microchip Technology Inc. DS39762F-page 85
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6.2.3 INSTRUCTIONS IN PROGRAM
MEMORY
The program memory is addressed in bytes. Instruc-
tions are stored as two bytes or four bytes in program
memory. The Least Significant Byte (LSB) of an
instruction word is always stored in a program memory
location with an even address (LSb = 0). To maintain
alignment with instruction boundaries, the PC incre-
ments in steps of 2 and the LSb will always read ‘0’ (see
Section 6.1.5 “Program Counter”).
Figure 6-6 shows an example of how instruction words
are stored in the program memory.
The CALL and GOTO instructions have the absolute
program memory address embedded into the instruction.
Since instructions are always stored on word boundaries,
the data contained in the instruction is a word address.
The word address is written to PC<20:1> which
accesses the desired byte address in program memory.
Instruction #2 in Figure 6-6 shows how the instruction,
GOTO 0006h, is encoded in the program memory.
Program branch instructions, which encode a relative
address offset, operate in the same manner. The offset
value stored in a branch instruction represents the
number of single-word instructions that the PC will be
offset by. Section 26.0 “Instruction Set Summary”
provides further details of the instruction set.
FIGURE 6-6: INSTRUCTIONS IN PROGRAM MEMORY
6.2.4 TWO-WORD INSTRUCTIONS
The standard PIC18 instruction set has four, two-word
instructions: CALL, MOVFF, GOTO and LSFR. In all
cases, the second word of the instructions always has
‘1111’ as its four Most Significant bits (MSbs); the other
12 bits are literal data, usually a data memory address.
The use of ‘1111’ in the 4 MSbs of an instruction
specifies a special form of NOP. If the instruction is
executed in proper sequence, immediately after the
first word, the data in the second word is accessed and
used by the instruction sequence. If the first word is
skipped, for some reason, and the second word is
executed by itself, a NOP is executed instead. This is
necessary for cases when the two-word instruction is
preceded by a conditional instruction that changes the
PC. Example 6-4 shows how this works.
EXAMPLE 6-4: TWO-WORD INSTRUCTIONS
Word Address
LSB = 1LSB = 0
Program Memory
Byte Locations
000000h
000002h
000004h
000006h
Instruction 1: MOVLW 055h 0Fh 55h 000008h
Instruction 2: GOTO 0006h EFh 03h 00000Ah
F0h 00h 00000Ch
Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh
F4h 56h 000010h
000012h
000014h
Note: See Section 6.5 “Program Memory and
the Extended Instruction Set” for
information on two-word instructions in
the extended instruction set.
CASE 1:
Object Code Source Code
0110 01 10 000 0 00 00 TSTFS Z R EG 1 ; is RAM lo ca ti on 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word
1111 0100 0101 0110 ; Execute this word as a NOP
0010 0100 0000 0000 ADDWF REG3 ; continue code
CASE 2:
Object Code Source Code
0110 01 10 000 0 00 00 TSTFSZ REG1 ; is RAM lo ca ti on 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes , ex ec ut e th is wor d
1111 0100 0101 0110 ; 2nd word of instruction
0010 01 00 000 0 00 00 ADDWF REG3 ; con ti nu e co de
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6.3 Data Memory Organiz ation
The data memory in PIC18 devices is implemented as
static RAM. Each register in the data memory has a
12-bit address, allowing up to 4096 bytes of addressable
memory. The memory space is divided into 16 banks
that contain 256 bytes each. All of the PIC18F97J60
family devices implement all available banks and pro-
vide 3808 bytes of data memory available to the user.
Figure 6-7 shows the data memory organization for the
devices.
The data memory contains Special Function Registers
(SFRs) and General Purpose Registers (GPRs). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratchpad operations in the user’s
application. Any read of an unimplemented location will
read as ‘0’s.
The instruction set and architecture allow operations
across all banks. The entire data memory may be
accessed by Direct, Indirect or Indexed Addressing
modes. Addressing modes are discussed later in this
section.
To ensure that commonly used registers (most SFRs
and select GPRs) can be accessed in a single cycle,
PIC18 devices implement an Access Bank. This is a
256-byte memory space that provides fast access to
the majority of SFRs and the lower portion of GPR
Bank 0 without using the BSR. Sect ion 6.3.2 “Access
Bank” provides a detailed description of the Access
RAM.
6.3.1 BANK SELECT REGISTER
Large areas of data memory require an efficient
addressing scheme to make rapid access to any
address possible. Ideally, this means that an entire
address does not need to be provided for each read or
write operation. For PIC18 devices, this is accom-
plished with a RAM banking scheme. This divides the
memory space into 16 contiguous banks of 256 bytes.
Depending on the instruction, each location can be
addressed directly by its full 12-bit address, or an 8-bit
low-order address and a 4-bit Bank Pointer.
Most instructions in the PIC18 instruction set make use
of the Bank Pointer, known as the Bank Select Register
(BSR). This SFR holds the 4 Most Significant bits of a
location’s address; the instruction itself includes the
8 Least Significant bits (LSbs). Only the four lower bits
of the BSR are implemented (BSR3:BSR0). The upper
four bits are unused; they will always read ‘0’ and can-
not be written to. The BSR can be loaded directly by
using the MOVLB instruction.
The value of the BSR indicates the bank in data memory.
The 8 bits in the instruction show the location in the bank
and can be thought of as an offset from the bank’s lower
boundary. The relationship between the BSR’s value
and the bank division in data memory is shown in
Figure 6-8.
Since up to 16 registers may share the same low-order
address, the user must always be careful to ensure that
the proper bank is selected before performing a data
read or write. For example, writing what should be
program data to an 8-bit address of F9h, while the BSR
is 0Fh, will end up resetting the program counter.
While any bank can be selected, only those banks that
are actually implemented can be read or written to.
Writes to unimplemented banks are ignored, while
reads from unimplemented banks will return ‘0’s. Even
so, the STATUS register will still be affected as if the
operation was successful. The data memory map in
Figure 6-7 indicates which banks are implemented.
In the core PIC18 instruction set, only the MOVFF
instruction fully specifies the 12-bit address of the
source and target registers. This instruction ignores the
BSR completely when it executes. All other instructions
include only the low-order address as an operand and
must use either the BSR or the Access Bank to locate
their target registers.
Note: The operation of some aspects of data
memory is changed when the PIC18
extended instruction set is enabled. See
Section 6.6 “Data Memory and the
Extended Instruction Set” for more
information.
2011 Microchip Technology Inc. DS39762F-page 87
PIC18F97J60 FAMILY
FIGURE 6-7: DATA MEMORY MAP FOR PIC18F97J60 FAMILY DEVICES
Bank 0
Bank 1
Bank 14
Bank 15
Data Memory Map
BSR<3:0>
= 0000
= 0001
= 1111
060h
05Fh
F60h
FFFh
00h
5Fh
60h
FFh
Access Bank
When a = 0:
The BSR is ignored and the
Access Bank is used.
The first 96 bytes are general
purpose RAM (from Bank 0).
The remaining 160 bytes are
Special Function Registers
(from Bank 15).
When a = 1:
The BSR specifies the bank
used by the instruction.
F5Fh
F00h
EFFh
1FFh
100h
0FFh
000h
Access RAM
FFh
00h
FFh
00h
FFh
00h
GPR
GPR
SFR
Access RAM High
Access RAM Low
Bank 2
= 0010
(SFRs)
2FFh
200h
Bank 3
FFh
00h
GPR
FFh
= 0011
= 1101
GPR
GPR
GPR
GPR
GPR
GPR
GPR
GPR
GPR
GPR
GPR
4FFh
400h
5FFh
500h
3FFh
300h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
00h
GPR
GPR
= 0110
= 0111
= 1010
= 1100
= 1000
= 0101
= 1001
= 1011
= 0100 Bank 4
Bank 5
Bank 6
Bank 7
Bank 8
Bank 9
Bank 10
Bank 11
Bank 12
Bank 13
= 1110
6FFh
600h
7FFh
700h
8FFh
800h
9FFh
900h
AFFh
A00h
BFFh
B00h
CFFh
C00h
DFFh
D00h
E00h
Ethernet SFR
E7Fh
E80h
PIC18F97J60 FAMILY
DS39762F-page 88 2011 Microchip Technology Inc.
FIGURE 6-8: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)
6.3.2 ACCESS BANK
While the use of the BSR with an embedded 8-bit
address allows users to address the entire range of
data memory, it also means that the user must always
ensure that the correct bank is selected. Otherwise,
data may be read from or written to the wrong location.
This can be disastrous if a GPR is the intended target
of an operation but an SFR is written to instead.
Verifying and/or changing the BSR for each read or
write to data memory can become very inefficient.
To streamline access for the most commonly used data
memory locations, the data memory is configured with
an Access Bank, which allows users to access a
mapped block of memory without specifying a BSR.
The Access Bank consists of the first 96 bytes of
memory (00h-5Fh) in Bank 0 and the last 160 bytes of
memory (60h-FFh) in Bank 15. The lower block is
known as the “Access RAM” and is composed of
GPRs. The upper block is where the device’s SFRs are
mapped. These two areas are mapped contiguously in
the Access Bank and can be addressed in a linear
fashion by an 8-bit address (Figure 6-7).
The Access Bank is used by core PIC18 instructions
that include the Access RAM bit (the ‘a’ parameter in
the instruction). When ‘a’ is equal to ‘1’, the instruction
uses the BSR and the 8-bit address included in the
opcode for the data memory address. When ‘a’ is ‘0’,
however, the instruction is forced to use the Access
Bank address map; the current value of the BSR is
ignored entirely.
Using this “forced” addressing allows the instruction to
operate on a data address in a single cycle without
updating the BSR first. For 8-bit addresses of 60h and
above, this means that users can evaluate and operate
on SFRs more efficiently. The Access RAM below 60h
is a good place for data values that the user might need
to access rapidly, such as immediate computational
results or common program variables. Access RAM
also allows for faster and more code efficient context
saving and switching of variables.
The mapping of the Access Bank is slightly different
when the extended instruction set is enabled (XINST
Configuration bit = 1). This is discussed in more detail
in Section 6.6.3 “Mapping the Access Bank in
Indexed Literal Offset Mode”.
6.3.3 GENERAL PURPOSE
REGISTER FILE
PIC18 devices may have banked memory in the GPR
area. This is data RAM which is available for use by all
instructions. GPRs start at the bottom of Bank 0
(address 000h) and grow upwards towards the bottom
of the SFR area. GPRs are not initialized by a
Power-on Reset and are unchanged on all other
Resets.
Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR3:BSR0)
to the registers of the Access Bank.
2: The MOVFF instruction embeds the entire 12-bit address in the instruction.
Data Memory
Bank Select(2)
70
From Opcode(2)
0000
000h
100h
200h
300h
F00h
E00h
FFFh
Bank 0
Bank 1
Bank 2
Bank 14
Bank 15
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
Bank 3
through
Bank 13
0010 11111111
70
BSR(1)
11111111
2011 Microchip Technology Inc. DS39762F-page 89
PIC18F97J60 FAMILY
6.3.4 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM.
The main group of SFRs start at the top of data memory
(FFFh) and extend downward to occupy more than the
top half of Bank 15 (F60h to FFFh). These SFRs can
be classified into two sets: those associated with the
“core” device functionality (ALU, Resets and interrupts)
and those related to the peripheral functions. The
Reset and Interrupt registers are described in their
respective chapters, while the ALU’s STATUS register
is described later in this section. Registers related to
the operation of the peripheral features are described
in the chapter for that peripheral.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s. A list of
SFRs is given in Table 6-3; a full description is provided
in Table 6-5.
TABLE 6-3: SPECIAL FUNCTION REGISTER MAP FOR PIC18F97J 60 FAMILY DEVICES
Address Name Address Name Address Name Address Name Address Name
FFFh TOSU FDFh INDF2(1) FBFh CCPR1H F9Fh IPR1 F7Fh SPBRGH1
FFEh TOSH FDEh POSTINC2(1) FBEh CCPR1L F9Eh PIR1 F7Eh BAUDCON1
FFDh TOSL FDDh POSTDEC2(1) FBDh CCP1CON F9Dh PIE1 F7Dh SPBRGH2
FFCh STKPTR FDCh PREINC2(1) FBCh CCPR2H F9Ch MEMCON(4) F7Ch BAUDCON2
FFBh PCLATU FDBh PLUSW2(1) FBBh CCPR2L F9Bh OSCTUNE F7Bh ERDPTH
FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah TRISJ(3) F7Ah ERDPTL
FF9h PCL FD9h FSR2L FB9h CCPR3H F99h TRISH(3) F79h ECCP1DEL
FF8h TBLPTRU FD8h STATUS FB8h CCPR3L F98h TRISG F78h TMR4
FF7h TBLPTRH FD7h TMR0H FB7h CCP3CON F97h TRISF F77h PR4
FF6h TBLPTRL FD6h TMR0L FB6h ECCP1AS F96h TRISE F76h T4CON
FF5h TABLAT FD5h T0CON FB5h CVRCON F95h TRISD F75h CCPR4H
FF4h PRODH FD4h —(2) FB4h CMCON F94h TRISC F74h CCPR4L
FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB F73h CCP4CON
FF2h INTCON FD2h ECON1 FB2h TMR3L F92h TRISA F72h CCPR5H
FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h LATJ(3) F71h CCPR5L
FF0h INTCON3 FD0h RCON FB0h PSPCON F90h LATH(3) F70h CCP5CON
FEFh INDF0(1) FCFh TMR1H FAFh SPBRG1 F8Fh LATG F6Fh SPBRG2
FEEh POSTINC0(1) FCEh TMR1L FAEh RCREG1 F8Eh LATF F6Eh RCREG2
FEDh POSTDEC0(1) FCDh T1CON FADh TXREG1 F8Dh LATE F6Dh TXREG2
FECh PREINC0(1) FCCh TMR2 FACh TXSTA1 F8Ch LATD F6Ch TXSTA2
FEBh PLUSW0(1) FCBh PR2 FABh RCSTA1 F8Bh LATC F6Bh RCSTA2
FEAh FSR0H FCAh T2CON FAAh —(2) F8Ah LATB F6Ah ECCP3AS
FE9h FSR0L FC9h SSP1BUF FA9h —(2) F89h LATA F69h ECCP3DEL
FE8h WREG FC8h SSP1ADD FA8h —(2) F88h PORTJ(3) F68h ECCP2AS
FE7h INDF1(1) FC7h SSP1STAT FA7h EECON2(1) F87h PORTH(3) F67h ECCP2DEL
FE6h POSTINC1(1) FC6h SSP1CON1 FA6h EECON1 F86h PORTG F66h SSP2BUF
FE5h POSTDEC1(1) FC5h SSP1CON2 FA5h IPR3 F85h PORTF F65h SSP2ADD
FE4h PREINC1(1) FC4h ADRESH FA4h PIR3 F84h PORTE F64h SSP2STAT
FE3h PLUSW1(1) FC3h ADRESL FA3h PIE3 F83h PORTD F63h SSP2CON1
FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC F62h SSP2CON2
FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB F61h EDATA
FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA F60h EIR
Note 1: This is not a physical register.
2: Unimplemented registers are read as ‘0’.
3: This register is not available in 64-pin devices.
4: This register is not available in 64 and 80-pin devices.
PIC18F97J60 FAMILY
DS39762F-page 90 2011 Microchip Technology Inc.
6.3.5 ETHERNET SFRs
In addition to the standard SFR set in Bank 15,
members of the PIC18F97J60 family have a second
set of SFRs. This group, associated exclusively with
the Ethernet module, occupies the top half of Bank 14
(E80h to EFFh). A complete list of Ethernet SFRs is given in Ta b le 6 - 4 .
All SFRs are fully described in Ta bl e 6 - 5 .
Note: To improve performance, frequently
accessed Ethernet registers are located in
the standard SFR bank (F60h through
FFFh).
TABLE 6-4: ETHERNET SFR MAP FOR PIC18F97J60 FAMILY DEVICES
Address Name Address Name Address Name Address Name
EFFh —(1) EDFh —(1) EBFh —(1) E9Fh —(1)
EFEh ECON2 EDEh —(1) EBEh —(1) E9Eh —(1)
EFDh ESTAT EDDh —(1) EBDh —(1) E9Dh —(1)
EFCh —(1) EDCh —(1) EBCh —(1) E9Ch —(1)
EFBh EIE EDBh —(1) EBBh —(1) E9Bh —(1)
EFAh —(1) EDAh —(1) EBAh —(1) E9Ah —(1)
EF9h —(2) ED9h EPKTCNT EB9h MIRDH E99h EPAUSH
EF8h —(2) ED8h ERXFCON EB8h MIRDL E98h EPAUSL
EF7h EDMACSH ED7h —(1) EB7h MIWRH E97h EFLOCON
EF6h EDMACSL ED6h —(1) EB6h MIWRL E96h —(2)
EF5h EDMADSTH ED5h EPMOH EB5h —(1) E95h —(2)
EF4h EDMADSTL ED4h EPMOL EB4h MIREGADR E94h —(2)
EF3h EDMANDH ED3h —(2) EB3h —(2) E93h —(2)
EF2h EDMANDL ED2h —(2) EB2h MICMD E92h —(2)
EF1h EDMASTH ED1h EPMCSH EB1h —(1) E91h —(2)
EF0h EDMASTL ED0h EPMCSL EB0h —(1) E90h —(2)
EEFh ERXWRPTH ECFh EPMM7 EAFh —(2) E8Fh —(2)
EEEh ERXWRPTL ECEh EPMM6 EAEh —(1) E8Eh —(2)
EEDh ERXRDPTH ECDh EPMM5 EADh —(1) E8Dh —(2)
EECh ERXRDPTL ECCh EPMM4 EACh —(1) E8Ch —(2)
EEBh ERXNDH ECBh EPMM3 EABh MAMXFLH E8Bh —(2)
EEAh ERXNDL ECAh EPMM2 EAAh MAMXFLL E8Ah MISTAT
EE9h ERXSTH EC9h EPMM1 EA9h —(1) E89h —(1)
EE8h ERXSTL EC8h EPMM0 EA8h —(1) E88h —(1)
EE7h ETXNDH EC7h EHT7 EA7h MAIPGH E87h —(1)
EE6h ETXNDL EC6h EHT6 EA6h MAIPGL E86h —(1)
EE5h ETXSTH EC5h EHT5 EA5h —(2) E85h MAADR2
EE4h ETXSTL EC4h EHT4 EA4h MABBIPG E84h MAADR1
EE3h EWRPTH EC3h EHT3 EA3h MACON4 E83h MAADR4
EE2h EWRPTL EC2h EHT2 EA2h MACON3 E82h MAADR3
EE1h —(1) EC1h EHT1 EA1h —(1) E81h MAADR6
EE0h —(1) EC0h EHT0 EA0h MACON1 E80h MAADR5
Note 1: Reserved register location; do not modify.
2: Unimplemented registers are read as ‘0’.
2011 Microchip Technology Inc. DS39762F-page 91
PIC18F97J60 FAMILY
TABLE 6-5: REGISTER FILE SUMMARY (PIC18F97J60 FAMILY)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 V alues on
POR, BOR Details on
Page:
TOSU — — — Top-of-Stack Register Upper Byte (TOS<20:16>) ---0 0000 69, 81
TOSH Top-of-Stack Register High Byte (TOS<15:8>) 0000 0000 69, 81
TOSL Top-of-Stack Register Low Byte (TOS<7:0>) 0000 0000 69, 81
STKPTR STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0 00-0 0000 69, 82
PCLATU ——bit 21
(2) Holding Register for PC<20:16> ---0 0000 69, 81
PCLATH Holding Register for PC<15:8> 0000 0000 69, 81
PCL PC Low Byte (PC<7:0>) 0000 0000 69, 81
TBLPTRU —— bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 69, 108
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 69, 108
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 69, 108
TABLAT Program Memory Table Latch 0000 0000 69, 108
PRODH Product Register High Byte xxxx xxxx 69, 127
PRODL Product Register Low Byte xxxx xxxx 69, 127
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 69, 131
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 1111 1111 69, 132
INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 1100 0000 69, 133
INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 69, 99
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 69, 100
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 69, 100
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 69, 100
PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
N/A 69, 100
FSR0H — — — — Indirect Data Memory Address Pointer 0 High Byte ---- xxxx 69, 99
FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 69, 100
WREG Working Register xxxx xxxx 69
INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 69, 99
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 69, 100
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 69, 100
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 69, 100
PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A 69, 100
FSR1H — — — — Indirect Data Memory Address Pointer 1 High Byte ---- xxxx 69, 99
FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 69, 99
BSR — — — — Bank Select Register ---- 0000 69, 99
INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 69, 99
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 69, 100
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 69, 100
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 69, 100
PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
N/A 69, 100
FSR2H — — — — Indirect Data Memory Address Pointer 2 High Byte ---- xxxx 69, 99
FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 69, 99
Legend: x = unknown; u = unchanged; - = unimplemented, read as ‘0’; q = value depends on condition; r = reserved bit, do not modify. Shaded cells
are unimplemented, read as ‘0’.
Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.
2: Bit 21 of the PC is only available in Serial Programming modes.
3: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
4: Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode.
5: These bits and/or registers are only available in 100-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values shown
apply only to 100-pin devices.
6: These bits and/or registers are only available in 80-pin and 100-pin devices. In 64-pin devices, they are unimplemented and read as ‘0’. Reset
values are shown for 100-pin devices.
7: In Microcontroller mode, the bits in this register are unwritable and read as ‘0’.
8: PLLEN is only available when either ECPLL or HSPLL Oscillator mode is selected; otherwise, read as ‘0’.
9: Implemented in 100-pin devices in Microcontroller mode only.
PIC18F97J60 FAMILY
DS39762F-page 92 2011 Microchip Technology Inc.
STATUS — — —NOVZDCC---x xxxx 70, 97
TMR0H Timer0 Register High Byte 0000 0000 70, 171
TMR0L Timer0 Register Low Byte xxxx xxxx 70, 171
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 70, 171
OSCCON IDLEN — — —OSTS
(3) — SCS1 SCS0 0--- q-00 70, 53
ECON1 TXRST RXRST DMAST CSUMEN TXRTS RXEN — — 0000 00-- 70, 227
WDTCON — — — — — — —SWDTEN--- ---0 70, 368
RCON IPEN —CMRI TO PD POR BOR 0-q1 1100 70, 64, 143
TMR1H Timer1 Register High Byte xxxx xxxx 70, 175
TMR1L Timer1 Register Low Byte xxxx xxxx 70, 175
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 70, 175
TMR2 Timer2 Register 0000 0000 70, 180
PR2 Timer2 Period Register 1111 1111 70, 180
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 70, 180
SSP1BUF MSSP1 Receive Buffer/Transmit Register xxxx xxxx 70, 279
SSP1ADD MSSP1 Address Register (I2C™ Slave mode), MSSP1 Baud Rate Reload Register (I2C Master mode) 0000 0000 70, 279
SSP1STAT SMP CKE D/A PSR/WUA BF 0000 0000 70, 270,
280
SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 70, 271,
281
SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 70, 282
GCEN ACKSTAT ADMSK5(4) ADMSK4(4) ADMSK3(4) ADMSK2(4) ADMSK1(4) SEN
ADRESH A/D Result Register High Byte xxxx xxxx 70, 347
ADRESL A/D Result Register Low Byte xxxx xxxx 70, 347
ADCON0 ADCAL — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0-00 0000 70, 339
ADCON1 —— VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 70, 340
ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 70, 341
CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 70, 193
CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 70, 193
CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 70, 198
CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx 70, 193
CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 70, 193
CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 0000 0000 70, 198
CCPR3H Capture/Compare/PWM Register 3 High Byte xxxx xxxx 70, 193
CCPR3L Capture/Compare/PWM Register 3 Low Byte xxxx xxxx 70, 193
CCP3CON P3M1 P3M0 DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 0000 0000 70, 198
ECCP1AS ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 0000 0000 70, 212
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 70, 355
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 70, 349
TMR3H Timer3 Register High Byte xxxx xxxx 70, 183
TMR3L Timer3 Register Low Byte xxxx xxxx 70, 183
TABLE 6-5: REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 V alues on
POR, BOR Details on
Page:
Legend: x = unknown; u = unchanged; - = unimplemented, read as ‘0’; q = value depends on condition; r = reserved bit, do not modify. Shaded cells
are unimplemented, read as ‘0’.
Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.
2: Bit 21 of the PC is only available in Serial Programming modes.
3: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
4: Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode.
5: These bits and/or registers are only available in 100-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values shown
apply only to 100-pin devices.
6: These bits and/or registers are only available in 80-pin and 100-pin devices. In 64-pin devices, they are unimplemented and read as ‘0’. Reset
values are shown for 100-pin devices.
7: In Microcontroller mode, the bits in this register are unwritable and read as ‘0’.
8: PLLEN is only available when either ECPLL or HSPLL Oscillator mode is selected; otherwise, read as ‘0’.
9: Implemented in 100-pin devices in Microcontroller mode only.
2011 Microchip Technology Inc. DS39762F-page 93
PIC18F97J60 FAMILY
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 71, 183
PSPCON(5) IBF OBF IBOV PSPMODE — — — — 0000 ---- 71, 169
SPBRG1 EUSART1 Baud Rate Generator Register Low Byte 0000 0000 71, 320
RCREG1 EUSART1 Receive Register 0000 0000 71, 327
TXREG1 EUSART1 Transmit Register xxxx xxxx 71, 329
TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 71, 320
RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 71, 320
EECON2 Program Memory Control Register (not a physical register) ---- ---- 71, 106
EECON1 — — — FREE WRERR WREN WR —---0 x00- 71, 107
IPR3 SSP2IP(5) BCL2IP(5) RC2IP(6) TX2IP(6) TMR4IP CCP5IP CCP4IP CCP3IP 1111 1111 71, 142
PIR3 SSP2IF(5) BCL2IF(5) RC2IF(6) TX2IF(6) TMR4IF CCP5IF CCP4IF CCP3IF 0000 0000 71, 136
PIE3 SSP2IE(5) BCL2IE(5) RC2IE(6) TX2IE(6) TMR4IE CCP5IE CCP4IE CCP3IE 0000 0000 71, 139
IPR2 OSCFIP CMIP ETHIP rBCL1IP— TMR3IP CCP2IP 1111 1-11 71, 141
PIR2 OSCFIF CMIF ETHIF rBCL1IF— TMR3IF CCP2IF 0000 0-00 71, 135
PIE2 OSCFIE CMIE ETHIE rBCL1IE— TMR3IE CCP2IE 0000 0-00 71, 138
IPR1 PSPIP(9) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 1111 1111 71, 140
PIR1 PSPIF(9) ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 71, 134
PIE1 PSPIE(9) ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 71, 137
MEMCON(5,7) EBDIS —WAIT1WAIT0——WM1WM00-00 --00 71, 116
OSCTUNE PPST1 PLLEN(8) PPST0 PPRE — — — — 0000 ---- 71, 51
TRISJ(6) TRISJ7(5) TRISJ6(5) TRISJ5(6) TRISJ4(6) TRISJ3(5) TRISJ2(5) TRISJ1(5) TRISJ0(5) 1111 1111 71, 167
TRISH(6) TRISH7(6) TRISH6(6) TRISH5(6) TRISH4(6) TRISH3(6) TRISH2(6) TRISH1(6) TRISH0(6) 1111 1111 71, 165
TRISG TRISG7(5) TRISG6(5) TRISG5(5) TRISG4 TRISG3(6) TRISG2(6) TRISG1(6) TRISG0(6) 1111 1111 71, 163
TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0(5) 1111 1111 71, 161
TRISE TRISE7(6) TRISE6(6) TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 1111 1111 71, 159
TRISD TRISD7(5) TRISD6(5) TRISD5(5) TRISD4(5) TRISD3(5) TRISD2 TRISD1 TRISD0 1111 1111 71, 156
TRISC TRISC7 TRISC6 TRISC5 TRISC4TRISC3TRISC2TRISC1TRISC01111 1111 71, 153
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 71, 150
TRISA —— TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 71, 147
LATJ(6) LATJ7(5) LATJ6(5) LATJ5(6) LATJ4(6) LATJ3(5) LATJ2(5) LATJ1(5) LATJ0(5) xxxx xxxx 71, 167
LATH(6) LATH7(6) LATH6(6) LATH5(6) LATH4(6) LATH3(6) LATH2(6) LATH1(6) LATH0(6) xxxx xxxx 71, 165
LATG LATG7(5) LATG6(5) LATG5(5) LATG4 LATG3(6) LATG2(6) LATG1(6) LATG0(6) xxxx xxxx 72, 163
LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0(5) xxxx xxxx 72, 161
LATE LATE7(6) LATE6(6) LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx xxxx 72, 159
LATD LATD7(5) LATD6(5) LATD5(5) LATD4(5) LATD3(5) LATD2 LATD1 LATD0 xxxx xxxx 72, 156
LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx 72, 153
LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx 72, 150
LATA RDPU REPU LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 00xx xxxx 72, 147
PORTJ(6) RJ7(5) RJ6(5) RJ5(6) RJ4(6) RJ3(5) RJ2(5) RJ1(5) RJ0(5) xxxx xxxx 72, 167
PORTH(6) RH7(6) RH6(6) RH5(6) RH4(6) RH3(6) RH2(6) RH1(6) RH0(6) 0000 xxxx 72, 165
PORTG RG7(5) RG6(5) RG5(5) RG4 RG3(6) RG2(6) RG1(6) RG0(6) 111x xxxx 72, 163
TABLE 6-5: REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 V alues on
POR, BOR Details on
Page:
Legend: x = unknown; u = unchanged; - = unimplemented, read as ‘0’; q = value depends on condition; r = reserved bit, do not modify. Shaded cells
are unimplemented, read as ‘0’.
Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.
2: Bit 21 of the PC is only available in Serial Programming modes.
3: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
4: Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode.
5: These bits and/or registers are only available in 100-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values shown
apply only to 100-pin devices.
6: These bits and/or registers are only available in 80-pin and 100-pin devices. In 64-pin devices, they are unimplemented and read as ‘0’. Reset
values are shown for 100-pin devices.
7: In Microcontroller mode, the bits in this register are unwritable and read as ‘0’.
8: PLLEN is only available when either ECPLL or HSPLL Oscillator mode is selected; otherwise, read as ‘0’.
9: Implemented in 100-pin devices in Microcontroller mode only.
PIC18F97J60 FAMILY
DS39762F-page 94 2011 Microchip Technology Inc.
PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0(5) 0000 0000 72, 161
PORTE RE7(6) RE6(6) RE5 RE4 RE3 RE2 RE1 RE0 xxxx xxxx 72, 159
PORTD RD7(5) RD6(5) RD5(5) RD4(5) RD3(5) RD2 RD1 RD0 xxxx xxxx 72, 156
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 72, 153
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 72, 150
PORTA RJPU(6) — RA5 RA4 RA3 RA2 RA1 RA0 0-0x 0000 72, 147
SPBRGH1 EUSART1 Baud Rate Generator Register High Byte 0000 0000 72, 320
BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 0100 0-00 72, 318
SPBRGH2 EUSART2 Baud Rate Generator Register High Byte 0000 0000 72, 320
BAUDCON2 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 0100 0-00 72, 318
ERDPTH — — — Buffer Read Pointer High Byte ---0 0101 72, 223
ERDPTL Buffer Read Pointer Low Byte 1111 1010 72, 223
ECCP1DEL P1RSEN P1DC6 P1DC5 P1DC4 P1DC3 P1DC2 P1DC1 P1DC0 0000 0000 72, 211
TMR4 Timer4 Register 0000 0000 72, 187
PR4 Timer4 Period Register 1111 1111 72, 187
T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 72, 187
CCPR4H Capture/Compare/PWM Register 4 High Byte xxxx xxxx 72, 193
CCPR4L Capture/Compare/PWM Register 4 Low Byte xxxx xxxx 72, 193
CCP4CON —— DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 --00 0000 73, 189
CCPR5H Capture/Compare/PWM Register 5 High Byte xxxx xxxx 73, 193
CCPR5L Capture/Compare/PWM Register 5 Low Byte xxxx xxxx 73, 193
CCP5CON —— DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 --00 0000 73, 189
SPBRG2 EUSART2 Baud Rate Generator Register Low Byte 0000 0000 73, 320
RCREG2 EUSART2 Receive Register 0000 0000 73, 327
TXREG2 EUSART2 Transmit Register 0000 0000 73, 329
TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 73, 316
RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 73, 317
ECCP3AS ECCP3ASE ECCP3AS2 ECCP3AS1 ECCP3AS0 PSS3AC1 PSS3AC0 PSS3BD1 PSS3BD0 0000 0000 73, 212
ECCP3DEL P3RSEN P3DC6 P3DC5 P3DC4 P3DC3 P3DC2 P3DC1 P3DC0 0000 0000 73, 211
ECCP2AS ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 73, 212
ECCP2DEL P2RSEN P2DC6 P2DC5 P2DC4 P2DC3 P2DC2 P2DC1 P2DC0 0000 0000 73, 211
SSP2BUF MSSP2 Receive Buffer/Transmit Register xxxx xxxx 73, 279
SSP2ADD MSSP2 Address Register (I2C™ Slave mode), MSSP2 Baud Rate Reload Register (I2C Master mode) 0000 0000 73, 279
SSP2STAT SMP CKE D/A PSR/WUA BF 0000 0000 73, 270
SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 73, 271,
281
SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 73, 282
GCEN ACKSTAT ADMSK5(4) ADMSK4(4) ADMSK3(4) ADMSK2(4) ADMSK1(4) SEN
EDATA Ethernet Transmit/Receive Buffer Register (EDATA<7:0>) xxxx xxxx 73, 223
EIR — PKTIF DMAIF LINKIF TXIF — TXERIF RXERIF -000 0-00 73, 241
ECON2 AUTOINC PKTDEC ETHEN — — — — — 100- ---- 73, 228
TABLE 6-5: REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 V alues on
POR, BOR Details on
Page:
Legend: x = unknown; u = unchanged; - = unimplemented, read as ‘0’; q = value depends on condition; r = reserved bit, do not modify. Shaded cells
are unimplemented, read as ‘0’.
Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.
2: Bit 21 of the PC is only available in Serial Programming modes.
3: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
4: Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode.
5: These bits and/or registers are only available in 100-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values shown
apply only to 100-pin devices.
6: These bits and/or registers are only available in 80-pin and 100-pin devices. In 64-pin devices, they are unimplemented and read as ‘0’. Reset
values are shown for 100-pin devices.
7: In Microcontroller mode, the bits in this register are unwritable and read as ‘0’.
8: PLLEN is only available when either ECPLL or HSPLL Oscillator mode is selected; otherwise, read as ‘0’.
9: Implemented in 100-pin devices in Microcontroller mode only.
2011 Microchip Technology Inc. DS39762F-page 95
PIC18F97J60 FAMILY
ESTAT —BUFER — r — RXBUSY TXABRT PHYRDY -0-0 -000 73, 228
EIE — PKTIE DMAIE LINKIE TXIE — TXERIE RXERIE -000 0-00 73, 240
EDMACSH DMA Checksum Register High Byte 0000 0000 73, 265
EDMACSL DMA Checksum Register Low Byte 0000 0000 73, 265
EDMADSTH — — — DMA Destination Register High Byte ---0 0000 73, 265
EDMADSTL DMA Destination Register Low Byte 0000 0000 73, 265
EDMANDH — — — DMA End Register High Byte ---0 0000 73, 265
EDMANDL DMA End Register Low Byte 0000 0000 73, 265
EDMASTH — — — DMA Start Register High Byte ---0 0000 73, 265
EDMASTL DMA Start Register Low Byte 0000 0000 73, 265
ERXWRPTH — — — Receive Buffer Write Pointer High Byte ---0 0000 73, 225
ERXWRPTL Receive Buffer Write Pointer Low Byte 0000 0000 73, 225
ERXRDPTH — — — Receive Buffer Read Pointer High Byte ---0 0101 73, 225
ERXRDPTL Receive Buffer Read Pointer Low Byte 1111 1010 73, 225
ERXNDH — — — Receive End Register High Byte ---1 1111 73, 225
ERXNDL Receive End Register Low Byte 1111 1111 73, 225
ERXSTH — — — Receive Start Register High Byte ---0 0101 73, 225
ERXSTL Receive Start Register Low Byte 1111 1010 73, 225
ETXNDH — — — Transmit End Register High Byte ---0 0000 74, 226
ETXNDL Transmit End Register Low Byte 0000 0000 74, 226
ETXSTH — — — Transmit Start Register High Byte ---0 0000 74, 226
ETXSTL Transmit Start Register Low Byte 0000 0000 74, 226
EWRPTH — — — Buffer Write Pointer High Byte ---0 0000 74, 223
EWRPTL Buffer Write Pointer Low Byte 0000 0000 74, 223
EPKTCNT Ethernet Packet Count Register 0000 0000 74, 252
ERXFCON UCEN ANDOR CRCEN PMEN MPEN HTEN MCEN BCEN 1010 0001 74, 260
EPMOH — — — Pattern Match Offset Register High Byte ---0 0000 74, 263
EPMOL Pattern Match Offset Register Low Byte 0000 0000 74, 263
EPMCSH Pattern Match Checksum Register High Byte 0000 0000 74, 263
EPMCSL Pattern Match Checksum Register Low Byte 0000 0000 74, 263
EPMM7 Pattern Match Mask Register Byte 7 0000 0000 74, 263
EPMM6 Pattern Match Mask Register Byte 6 0000 0000 74, 263
EPMM5 Pattern Match Mask Register Byte 5 0000 0000 74, 263
EPMM4 Pattern Match Mask Register Byte 4 0000 0000 74, 263
EPMM3 Pattern Match Mask Register Byte 3 0000 0000 74, 263
EPMM2 Pattern Match Mask Register Byte 2 0000 0000 74, 263
EPMM1 Pattern Match Mask Register Byte 1 0000 0000 74, 263
EPMM0 Pattern Match Mask Register Byte 0 0000 0000 74, 263
TABLE 6-5: REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 V alues on
POR, BOR Details on
Page:
Legend: x = unknown; u = unchanged; - = unimplemented, read as ‘0’; q = value depends on condition; r = reserved bit, do not modify. Shaded cells
are unimplemented, read as ‘0’.
Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.
2: Bit 21 of the PC is only available in Serial Programming modes.
3: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
4: Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode.
5: These bits and/or registers are only available in 100-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values shown
apply only to 100-pin devices.
6: These bits and/or registers are only available in 80-pin and 100-pin devices. In 64-pin devices, they are unimplemented and read as ‘0’. Reset
values are shown for 100-pin devices.
7: In Microcontroller mode, the bits in this register are unwritable and read as ‘0’.
8: PLLEN is only available when either ECPLL or HSPLL Oscillator mode is selected; otherwise, read as ‘0’.
9: Implemented in 100-pin devices in Microcontroller mode only.
PIC18F97J60 FAMILY
DS39762F-page 96 2011 Microchip Technology Inc.
EHT7 Hash Table Register Byte 7 0000 0000 74, 259
EHT6 Hash Table Register Byte 6 0000 0000 74, 259
EHT5 Hash Table Register Byte 5 0000 0000 74, 259
EHT4 Hash Table Register Byte 4 0000 0000 74, 259
EHT3 Hash Table Register Byte 3 0000 0000 74, 259
EHT2 Hash Table Register Byte 2 0000 0000 74, 259
EHT1 Hash Table Register Byte 1 0000 0000 74, 259
EHT0 Hash Table Register Byte 0 0000 0000 74, 259
MIRDH MII Read Data Register High Byte 0000 0000 74, 232
MIRDL MII Read Data Register Low Byte 0000 0000 74, 232
MIWRH MII Write Data Register High Byte 0000 0000 74, 232
MIWRL MII Write Data Register Low Byte 0000 0000 74, 232
MIREGADR — — — MII Address Register ---0 0000 74, 232
MICMD — — — — — — MIISCAN MIIRD ---- --00 74, 231
MAMXFLH Maximum Frame Length Register High Byte 0000 0110 74, 245
MAMXFLL Maximum Frame Length Register Low Byte 0000 0000 74, 245
MAIPGH — MAC Non Back-to-Back Inter-Packet Gap Register High Byte -000 0000 75, 245
MAIPGL — MAC Non Back-to-Back Inter-Packet Gap Register Low Byte -000 0000 75, 245
MABBIPG — BBIPG6 BBIPG5 BBIPG4 BBIPG3 BBIPG2 BBIPG1 BBIPG0 -000 0000 75, 246
MACON4 — DEFER r r — — r r -000 --00 75, 231
MACON3 PADCFG2 PADCFG1 PADCFG0 TXCRCEN PHDREN HFRMEN FRMLNEN FULDPX 0000 0000 75, 230
MACON1 — — — r TXPAUS RXPAUS PASSALL MARXEN ---0 0000 75, 229
EPAUSH Pause Timer Value Register High Byte 0001 0000 75, 258
EPAUSL Pause Timer Value Register Low Byte 0000 0000 75, 258
EFLOCON — — — — — r FCEN1 FCEN0 ---- -000 75, 258
MISTAT